diff options
Diffstat (limited to 'drivers/pinctrl')
| -rw-r--r-- | drivers/pinctrl/Kconfig | 9 | ||||
| -rw-r--r-- | drivers/pinctrl/Makefile | 1 | ||||
| -rw-r--r-- | drivers/pinctrl/aspeed/Makefile | 1 | ||||
| -rw-r--r-- | drivers/pinctrl/aspeed/pinctrl_ast2500.c | 127 | ||||
| -rw-r--r-- | drivers/pinctrl/pinctrl_stm32.c | 50 |
5 files changed, 184 insertions, 4 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 9cea6f202c..f6616c5329 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -248,6 +248,15 @@ config PINCTRL_STM32 the GPIO definitions and pin control functions for each available multiplex function. +config ASPEED_AST2500_PINCTRL + bool "Aspeed AST2500 pin control driver" + depends on DM && PINCTRL_GENERIC && ASPEED_AST2500 + default y + help + Support pin multiplexing control on Aspeed ast2500 SoC. The driver uses + Generic Pinctrl framework and is compatible with the Linux driver, + i.e. it uses the same device tree configuration. + endif source "drivers/pinctrl/meson/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 17a7173d35..1e5c4257c4 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC) += pinctrl-generic.o obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o obj-y += nxp/ +obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_ATH79) += ath79/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o diff --git a/drivers/pinctrl/aspeed/Makefile b/drivers/pinctrl/aspeed/Makefile new file mode 100644 index 0000000000..2e6ed604c8 --- /dev/null +++ b/drivers/pinctrl/aspeed/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_ASPEED_AST2500_PINCTRL) += pinctrl_ast2500.o diff --git a/drivers/pinctrl/aspeed/pinctrl_ast2500.c b/drivers/pinctrl/aspeed/pinctrl_ast2500.c new file mode 100644 index 0000000000..01f97c1b48 --- /dev/null +++ b/drivers/pinctrl/aspeed/pinctrl_ast2500.c @@ -0,0 +1,127 @@ +/* + * Copyright 2017 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/pinctrl.h> +#include <asm/arch/scu_ast2500.h> +#include <dm/pinctrl.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * This driver works with very simple configuration that has the same name + * for group and function. This way it is compatible with the Linux Kernel + * driver. + */ + +struct ast2500_pinctrl_priv { + struct ast2500_scu *scu; +}; + +static int ast2500_pinctrl_probe(struct udevice *dev) +{ + struct ast2500_pinctrl_priv *priv = dev_get_priv(dev); + + priv->scu = ast_get_scu(); + + return 0; +} + +struct ast2500_group_config { + char *group_name; + /* Control register number (1-10) */ + unsigned reg_num; + /* The mask of control bits in the register */ + u32 ctrl_bit_mask; +}; + +static const struct ast2500_group_config ast2500_groups[] = { + { "I2C1", 8, (1 << 13) | (1 << 12) }, + { "I2C2", 8, (1 << 15) | (1 << 14) }, + { "I2C3", 8, (1 << 16) }, + { "I2C4", 5, (1 << 17) }, + { "I2C4", 5, (1 << 17) }, + { "I2C5", 5, (1 << 18) }, + { "I2C6", 5, (1 << 19) }, + { "I2C7", 5, (1 << 20) }, + { "I2C8", 5, (1 << 21) }, + { "I2C9", 5, (1 << 22) }, + { "I2C10", 5, (1 << 23) }, + { "I2C11", 5, (1 << 24) }, + { "I2C12", 5, (1 << 25) }, + { "I2C13", 5, (1 << 26) }, + { "I2C14", 5, (1 << 27) }, + { "MAC1LINK", 1, (1 << 0) }, + { "MDIO1", 3, (1 << 31) | (1 << 30) }, + { "MAC2LINK", 1, (1 << 1) }, + { "MDIO2", 5, (1 << 2) }, +}; + +static int ast2500_pinctrl_get_groups_count(struct udevice *dev) +{ + debug("PINCTRL: get_(functions/groups)_count\n"); + + return ARRAY_SIZE(ast2500_groups); +} + +static const char *ast2500_pinctrl_get_group_name(struct udevice *dev, + unsigned selector) +{ + debug("PINCTRL: get_(function/group)_name %u\n", selector); + + return ast2500_groups[selector].group_name; +} + +static int ast2500_pinctrl_group_set(struct udevice *dev, unsigned selector, + unsigned func_selector) +{ + struct ast2500_pinctrl_priv *priv = dev_get_priv(dev); + const struct ast2500_group_config *config; + u32 *ctrl_reg; + + debug("PINCTRL: group_set <%u, %u>\n", selector, func_selector); + if (selector >= ARRAY_SIZE(ast2500_groups)) + return -EINVAL; + + config = &ast2500_groups[selector]; + if (config->reg_num > 6) + ctrl_reg = &priv->scu->pinmux_ctrl1[config->reg_num - 7]; + else + ctrl_reg = &priv->scu->pinmux_ctrl[config->reg_num - 1]; + + ast_scu_unlock(priv->scu); + setbits_le32(ctrl_reg, config->ctrl_bit_mask); + ast_scu_lock(priv->scu); + + return 0; +} + +static struct pinctrl_ops ast2500_pinctrl_ops = { + .set_state = pinctrl_generic_set_state, + .get_groups_count = ast2500_pinctrl_get_groups_count, + .get_group_name = ast2500_pinctrl_get_group_name, + .get_functions_count = ast2500_pinctrl_get_groups_count, + .get_function_name = ast2500_pinctrl_get_group_name, + .pinmux_group_set = ast2500_pinctrl_group_set, +}; + +static const struct udevice_id ast2500_pinctrl_ids[] = { + { .compatible = "aspeed,ast2500-pinctrl" }, + { .compatible = "aspeed,g5-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(pinctrl_ast2500) = { + .name = "aspeed_ast2500_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = ast2500_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct ast2500_pinctrl_priv), + .ops = &ast2500_pinctrl_ops, + .probe = ast2500_pinctrl_probe, +}; diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index aa2c440b14..d7b5ea3e1c 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -1,10 +1,46 @@ #include <common.h> -#include <asm/arch/gpio.h> #include <dm.h> #include <dm/pinctrl.h> +#include <asm/arch/gpio.h> +#include <asm/gpio.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; +#define MAX_PINS_ONE_IP 70 +#define MODE_BITS_MASK 3 +#define OSPEED_MASK 3 +#define PUPD_MASK 3 +#define OTYPE_MSK 1 +#define AFR_MASK 0xF + +static int stm32_gpio_config(struct gpio_desc *desc, + const struct stm32_gpio_ctl *ctl) +{ + struct stm32_gpio_priv *priv = dev_get_priv(desc->dev); + struct stm32_gpio_regs *regs = priv->regs; + u32 index; + + if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 || + ctl->pupd > 2 || ctl->speed > 3) + return -EINVAL; + + index = (desc->offset & 0x07) * 4; + clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index, + ctl->af << index); + + index = desc->offset * 2; + clrsetbits_le32(®s->moder, MODE_BITS_MASK << index, + ctl->mode << index); + clrsetbits_le32(®s->ospeedr, OSPEED_MASK << index, + ctl->speed << index); + clrsetbits_le32(®s->pupdr, PUPD_MASK << index, ctl->pupd << index); + + index = desc->offset; + clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index); + + return 0; +} static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin) { gpio_dsc->port = (port_pin & 0xF000) >> 12; @@ -18,6 +54,7 @@ static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin) static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node) { gpio_fn &= 0x00FF; + gpio_ctl->af = 0; switch (gpio_fn) { case 0: @@ -59,7 +96,7 @@ static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node) static int stm32_pinctrl_set_state_simple(struct udevice *dev, struct udevice *periph) { - u32 pin_mux[50]; + u32 pin_mux[MAX_PINS_ONE_IP]; struct fdtdec_phandle_args args; int rv, len; @@ -85,11 +122,16 @@ static int stm32_pinctrl_set_state_simple(struct udevice *dev, if (len < 0) return -EINVAL; for (i = 0; i < len; i++) { + struct gpio_desc desc; debug("%s: pinmux = %x\n", __func__, *(pin_mux + i)); prep_gpio_dsc(&gpio_dsc, *(pin_mux + i)); prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), args.node); - - rv = stm32_gpio_config(&gpio_dsc, &gpio_ctl); + rv = uclass_get_device_by_seq(UCLASS_GPIO, + gpio_dsc.port, &desc.dev); + if (rv) + return rv; + desc.offset = gpio_dsc.pin; + rv = stm32_gpio_config(&desc, &gpio_ctl); debug("%s: rv = %d\n\n", __func__, rv); if (rv) return rv; |