4 files changed, 67 insertions, 9 deletions

diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index 55f37cb55c..d34430c659 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -417,6 +417,7 @@ static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode)
 			maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
 			upsmr |= (UPSMR_RPM | UPSMR_TBIM);
 			break;
+		case ENET_1000_RGMII_RXID:
 		case ENET_1000_RGMII:
 			maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
 			upsmr |= UPSMR_RPM;
diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h
index c384055ceb..7762de6a8d 100644
--- a/drivers/qe/uec.h
+++ b/drivers/qe/uec.h
@@ -642,6 +642,7 @@ typedef enum enet_interface {
 	ENET_100_RGMII,
 	ENET_1000_GMII,
 	ENET_1000_RGMII,
+	ENET_1000_RGMII_RXID,
 	ENET_1000_TBI,
 	ENET_1000_RTBI
 } enet_interface_e;
diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
index a42701c59b..423ba789e9 100644
--- a/drivers/qe/uec_phy.c
+++ b/drivers/qe/uec_phy.c
@@ -318,16 +318,26 @@ static int genmii_read_status (struct uec_mii_info *mii_info)
 		return err;
 
 	if (mii_info->autoneg) {
-		status = phy_read (mii_info, PHY_ANLPAR);
+		status = phy_read(mii_info, MII_1000BASETSTATUS);
 
-		if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))
-			mii_info->duplex = DUPLEX_FULL;
-		else
-			mii_info->duplex = DUPLEX_HALF;
-		if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX))
-			mii_info->speed = SPEED_100;
-		else
-			mii_info->speed = SPEED_10;
+		if (status & (LPA_1000FULL | LPA_1000HALF)) {
+			mii_info->speed = SPEED_1000;
+			if (status & LPA_1000FULL)
+				mii_info->duplex = DUPLEX_FULL;
+			else
+				mii_info->duplex = DUPLEX_HALF;
+		} else {
+			status = phy_read(mii_info, PHY_ANLPAR);
+
+			if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))
+				mii_info->duplex = DUPLEX_FULL;
+			else
+				mii_info->duplex = DUPLEX_HALF;
+			if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX))
+				mii_info->speed = SPEED_100;
+			else
+				mii_info->speed = SPEED_10;
+		}
 		mii_info->pause = 0;
 	}
 	/* On non-aneg, we assume what we put in BMCR is the speed,
@@ -337,6 +347,37 @@ static int genmii_read_status (struct uec_mii_info *mii_info)
 	return 0;
 }
 
+static int bcm_init(struct uec_mii_info *mii_info)
+{
+	struct eth_device *edev = mii_info->dev;
+	uec_private_t *uec = edev->priv;
+
+	gbit_config_aneg(mii_info);
+
+	if (uec->uec_info->enet_interface == ENET_1000_RGMII_RXID) {
+		u16 val;
+		int cnt = 50;
+
+		/* Wait for aneg to complete. */
+		do
+			val = phy_read(mii_info, PHY_BMSR);
+		while (--cnt && !(val & PHY_BMSR_AUTN_COMP));
+
+		/* Set RDX clk delay. */
+		phy_write(mii_info, 0x18, 0x7 | (7 << 12));
+
+		val = phy_read(mii_info, 0x18);
+		/* Set RDX-RXC skew. */
+		val |= (1 << 8);
+		val |= (7 | (7 << 12));
+		/* Write bits 14:0. */
+		val |= (1 << 15);
+		phy_write(mii_info, 0x18, val);
+	}
+
+	 return 0;
+}
+
 static int marvell_read_status (struct uec_mii_info *mii_info)
 {
 	u16 status;
@@ -505,6 +546,15 @@ static struct phy_info phy_info_marvell = {
 	.config_intr = &marvell_config_intr,
 };
 
+static struct phy_info phy_info_bcm5481 = {
+	.phy_id = 0x0143bca0,
+	.phy_id_mask = 0xffffff0,
+	.name = "Broadcom 5481",
+	.features = MII_GBIT_FEATURES,
+	.read_status = genmii_read_status,
+	.init = bcm_init,
+};
+
 static struct phy_info phy_info_genmii = {
 	.phy_id = 0x00000000,
 	.phy_id_mask = 0x00000000,
@@ -518,6 +568,7 @@ static struct phy_info *phy_info[] = {
 	&phy_info_dm9161,
 	&phy_info_dm9161a,
 	&phy_info_marvell,
+	&phy_info_bcm5481,
 	&phy_info_genmii,
 	NULL
 };
diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h
index e59a940e0d..6f769fb50b 100644
--- a/drivers/qe/uec_phy.h
+++ b/drivers/qe/uec_phy.h
@@ -29,6 +29,11 @@
 #define MII_1000BASETCONTROL_FULLDUPLEXCAP    0x0200
 #define MII_1000BASETCONTROL_HALFDUPLEXCAP    0x0100
 
+/* 1000BT status */
+#define MII_1000BASETSTATUS	0x0a
+#define LPA_1000FULL		0x0400
+#define LPA_1000HALF		0x0200
+
 /* Cicada Extended Control Register 1 */
 #define MII_CIS8201_EXT_CON1	    0x17
 #define MII_CIS8201_EXTCON1_INIT    0x0000