summaryrefslogtreecommitdiff
path: root/drivers/serial
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/serial')
-rw-r--r--drivers/serial/Kconfig25
-rw-r--r--drivers/serial/serial_arc.c26
-rw-r--r--drivers/serial/serial_msm.c32
-rw-r--r--drivers/serial/serial_stm32.c158
-rw-r--r--drivers/serial/serial_stm32.h16
5 files changed, 218 insertions, 39 deletions
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 5937910e5b..2940bd05dc 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -197,6 +197,15 @@ config DEBUG_UART_AR933X
driver will be available until the real driver model serial is
running.
+config DEBUG_ARC_SERIAL
+ bool "ARC UART"
+ depends on ARC_SERIAL
+ help
+ Select this to enable a debug UART using the ARC UART driver.
+ You will need to provide parameters to make this work. The
+ driver will be available until the real driver model serial is
+ running.
+
config DEBUG_UART_ATMEL
bool "Atmel USART"
help
@@ -315,6 +324,15 @@ config DEBUG_UART_MXC
will need to provide parameters to make this work. The driver will
be available until the real driver model serial is running.
+config DEBUG_UART_STM32
+ bool "STMicroelectronics STM32"
+ depends on STM32_SERIAL
+ help
+ Select this to enable a debug UART using the serial_stm32 driver
+ You will need to provide parameters to make this work.
+ The driver will be available until the real driver model
+ serial is running.
+
config DEBUG_UART_UNIPHIER
bool "UniPhier on-chip UART"
depends on ARCH_UNIPHIER
@@ -425,6 +443,13 @@ config AR933X_UART
tree binding to operate, please refer to the document at
doc/device-tree-bindings/serial/qca,ar9330-uart.txt.
+config ARC_SERIAL
+ bool "ARC UART support"
+ depends on DM_SERIAL
+ help
+ Select this to enable support for ARC UART now typically
+ only used in Synopsys DesignWare ARC simulators like nSIM.
+
config ATMEL_USART
bool "Atmel USART support"
help
diff --git a/drivers/serial/serial_arc.c b/drivers/serial/serial_arc.c
index da4a07ab2f..925f0c2555 100644
--- a/drivers/serial/serial_arc.c
+++ b/drivers/serial/serial_arc.c
@@ -130,3 +130,29 @@ U_BOOT_DRIVER(serial_arc) = {
.ops = &arc_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
};
+
+#ifdef CONFIG_DEBUG_ARC_SERIAL
+#include <debug_uart.h>
+
+static inline void _debug_uart_init(void)
+{
+ struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_DEBUG_UART_BASE;
+ int arc_console_baud = CONFIG_DEBUG_UART_CLOCK / (CONFIG_BAUDRATE * 4) - 1;
+
+ writeb(arc_console_baud & 0xff, &regs->baudl);
+ writeb((arc_console_baud & 0xff00) >> 8, &regs->baudh);
+}
+
+static inline void _debug_uart_putc(int c)
+{
+ struct arc_serial_regs *regs = (struct arc_serial_regs *)CONFIG_DEBUG_UART_BASE;
+
+ while (!(readb(&regs->status) & UART_TXEMPTY))
+ ;
+
+ writeb(c, &regs->data);
+}
+
+DEBUG_UART_FUNCS
+
+#endif
diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index 119e6b9846..c462394dbd 100644
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -16,6 +16,7 @@
#include <watchdog.h>
#include <asm/io.h>
#include <linux/compiler.h>
+#include <dm/pinctrl.h>
/* Serial registers - this driver works in uartdm mode*/
@@ -25,6 +26,9 @@
#define UARTDM_RXFS 0x50 /* RX channel status register */
#define UARTDM_RXFS_BUF_SHIFT 0x7 /* Number of bytes in the packing buffer */
#define UARTDM_RXFS_BUF_MASK 0x7
+#define UARTDM_MR1 0x00
+#define UARTDM_MR2 0x04
+#define UARTDM_CSR 0xA0
#define UARTDM_SR 0xA4 /* Status register */
#define UARTDM_SR_RX_READY (1 << 0) /* Word is the receiver FIFO */
@@ -45,6 +49,10 @@
#define UARTDM_TF 0x100 /* UART Transmit FIFO register */
#define UARTDM_RF 0x140 /* UART Receive FIFO register */
+#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
+#define MSM_BOOT_UART_DM_8_N_1_MODE 0x34
+#define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10
+#define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20
DECLARE_GLOBAL_DATA_PTR;
@@ -179,19 +187,29 @@ static int msm_uart_clk_init(struct udevice *dev)
return 0;
}
+static void uart_dm_init(struct msm_serial_data *priv)
+{
+ writel(UART_DM_CLK_RX_TX_BIT_RATE, priv->base + UARTDM_CSR);
+ writel(0x0, priv->base + UARTDM_MR1);
+ writel(MSM_BOOT_UART_DM_8_N_1_MODE, priv->base + UARTDM_MR2);
+ writel(MSM_BOOT_UART_DM_CMD_RESET_RX, priv->base + UARTDM_CR);
+ writel(MSM_BOOT_UART_DM_CMD_RESET_TX, priv->base + UARTDM_CR);
+}
static int msm_serial_probe(struct udevice *dev)
{
+ int ret;
struct msm_serial_data *priv = dev_get_priv(dev);
- msm_uart_clk_init(dev); /* Ignore return value and hope clock was
- properly initialized by earlier loaders */
+ /* No need to reinitialize the UART after relocation */
+ if (gd->flags & GD_FLG_RELOC)
+ return 0;
- if (readl(priv->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN)
- writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR);
+ ret = msm_uart_clk_init(dev);
+ if (ret)
+ return ret;
- writel(0, priv->base + UARTDM_IMR);
- writel(UARTDM_CR_CMD_STALE_EVENT_DISABLE, priv->base + UARTDM_CR);
- msm_serial_fetch(dev);
+ pinctrl_select_state(dev, "uart");
+ uart_dm_init(priv);
return 0;
}
diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c
index 6717ffaaa5..f26234549c 100644
--- a/drivers/serial/serial_stm32.c
+++ b/drivers/serial/serial_stm32.c
@@ -7,19 +7,21 @@
#include <common.h>
#include <clk.h>
#include <dm.h>
-#include <asm/io.h>
#include <serial.h>
+#include <watchdog.h>
+#include <asm/io.h>
#include <asm/arch/stm32.h>
#include "serial_stm32.h"
-static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
+static void _stm32_serial_setbrg(fdt_addr_t base,
+ struct stm32_uart_info *uart_info,
+ u32 clock_rate,
+ int baudrate)
{
- struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
- bool stm32f4 = plat->uart_info->stm32f4;
- fdt_addr_t base = plat->base;
+ bool stm32f4 = uart_info->stm32f4;
u32 int_div, mantissa, fraction, oversampling;
- int_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate);
+ int_div = DIV_ROUND_CLOSEST(clock_rate, baudrate);
if (int_div < 16) {
oversampling = 8;
@@ -33,6 +35,53 @@ static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
fraction = int_div % oversampling;
writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
+}
+
+static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
+{
+ struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+
+ _stm32_serial_setbrg(plat->base, plat->uart_info,
+ plat->clock_rate, baudrate);
+
+ return 0;
+}
+
+static int stm32_serial_setparity(struct udevice *dev, enum serial_par parity)
+{
+ struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+ bool stm32f4 = plat->uart_info->stm32f4;
+ u8 uart_enable_bit = plat->uart_info->uart_enable_bit;
+ u32 cr1 = plat->base + CR1_OFFSET(stm32f4);
+ u32 config = 0;
+
+ if (stm32f4)
+ return -EINVAL; /* not supported in driver*/
+
+ clrbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));
+ /* update usart configuration (uart need to be disable)
+ * PCE: parity check control
+ * PS : '0' : Even / '1' : Odd
+ * M[1:0] = '00' : 8 Data bits
+ * M[1:0] = '01' : 9 Data bits with parity
+ */
+ switch (parity) {
+ default:
+ case SERIAL_PAR_NONE:
+ config = 0;
+ break;
+ case SERIAL_PAR_ODD:
+ config = USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0;
+ break;
+ case SERIAL_PAR_EVEN:
+ config = USART_CR1_PCE | USART_CR1_M0;
+ break;
+ }
+ clrsetbits_le32(cr1,
+ USART_CR1_PCE | USART_CR1_PS | USART_CR1_M1 |
+ USART_CR1_M0,
+ config);
+ setbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));
return 0;
}
@@ -44,12 +93,13 @@ static int stm32_serial_getc(struct udevice *dev)
fdt_addr_t base = plat->base;
u32 isr = readl(base + ISR_OFFSET(stm32f4));
- if ((isr & USART_ISR_FLAG_RXNE) == 0)
+ if ((isr & USART_ISR_RXNE) == 0)
return -EAGAIN;
- if (isr & USART_ISR_FLAG_ORE) {
+ if (isr & (USART_ISR_PE | USART_ISR_ORE)) {
if (!stm32f4)
- setbits_le32(base + ICR_OFFSET, USART_ICR_OREF);
+ setbits_le32(base + ICR_OFFSET,
+ USART_ICR_PCECF | USART_ICR_ORECF);
else
readl(base + RDR_OFFSET(stm32f4));
return -EIO;
@@ -58,13 +108,13 @@ static int stm32_serial_getc(struct udevice *dev)
return readl(base + RDR_OFFSET(stm32f4));
}
-static int stm32_serial_putc(struct udevice *dev, const char c)
+static int _stm32_serial_putc(fdt_addr_t base,
+ struct stm32_uart_info *uart_info,
+ const char c)
{
- struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
- bool stm32f4 = plat->uart_info->stm32f4;
- fdt_addr_t base = plat->base;
+ bool stm32f4 = uart_info->stm32f4;
- if ((readl(base + ISR_OFFSET(stm32f4)) & USART_ISR_FLAG_TXE) == 0)
+ if ((readl(base + ISR_OFFSET(stm32f4)) & USART_ISR_TXE) == 0)
return -EAGAIN;
writel(c, base + TDR_OFFSET(stm32f4));
@@ -72,6 +122,13 @@ static int stm32_serial_putc(struct udevice *dev, const char c)
return 0;
}
+static int stm32_serial_putc(struct udevice *dev, const char c)
+{
+ struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
+
+ return _stm32_serial_putc(plat->base, plat->uart_info, c);
+}
+
static int stm32_serial_pending(struct udevice *dev, bool input)
{
struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
@@ -80,24 +137,34 @@ static int stm32_serial_pending(struct udevice *dev, bool input)
if (input)
return readl(base + ISR_OFFSET(stm32f4)) &
- USART_ISR_FLAG_RXNE ? 1 : 0;
+ USART_ISR_RXNE ? 1 : 0;
else
return readl(base + ISR_OFFSET(stm32f4)) &
- USART_ISR_FLAG_TXE ? 0 : 1;
+ USART_ISR_TXE ? 0 : 1;
+}
+
+static void _stm32_serial_init(fdt_addr_t base,
+ struct stm32_uart_info *uart_info)
+{
+ bool stm32f4 = uart_info->stm32f4;
+ u8 uart_enable_bit = uart_info->uart_enable_bit;
+
+ /* Disable uart-> enable fifo -> enable uart */
+ clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
+ BIT(uart_enable_bit));
+ if (uart_info->has_fifo)
+ setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
+ setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
+ BIT(uart_enable_bit));
}
static int stm32_serial_probe(struct udevice *dev)
{
struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
struct clk clk;
- fdt_addr_t base = plat->base;
int ret;
- bool stm32f4;
- u8 uart_enable_bit;
plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
- stm32f4 = plat->uart_info->stm32f4;
- uart_enable_bit = plat->uart_info->uart_enable_bit;
ret = clk_get_by_index(dev, 0, &clk);
if (ret < 0)
@@ -115,13 +182,7 @@ static int stm32_serial_probe(struct udevice *dev)
return plat->clock_rate;
};
- /* Disable uart-> enable fifo-> enable uart */
- clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
- BIT(uart_enable_bit));
- if (plat->uart_info->has_fifo)
- setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
- setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
- BIT(uart_enable_bit));
+ _stm32_serial_init(plat->base, plat->uart_info);
return 0;
}
@@ -149,6 +210,7 @@ static const struct dm_serial_ops stm32_serial_ops = {
.pending = stm32_serial_pending,
.getc = stm32_serial_getc,
.setbrg = stm32_serial_setbrg,
+ .setparity = stm32_serial_setparity
};
U_BOOT_DRIVER(serial_stm32) = {
@@ -161,3 +223,43 @@ U_BOOT_DRIVER(serial_stm32) = {
.probe = stm32_serial_probe,
.flags = DM_FLAG_PRE_RELOC,
};
+
+#ifdef CONFIG_DEBUG_UART_STM32
+#include <debug_uart.h>
+static inline struct stm32_uart_info *_debug_uart_info(void)
+{
+ struct stm32_uart_info *uart_info;
+
+#if defined(CONFIG_STM32F4)
+ uart_info = &stm32f4_info;
+#elif defined(CONFIG_STM32F7)
+ uart_info = &stm32f7_info;
+#else
+ uart_info = &stm32h7_info;
+#endif
+ return uart_info;
+}
+
+static inline void _debug_uart_init(void)
+{
+ fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
+ struct stm32_uart_info *uart_info = _debug_uart_info();
+
+ _stm32_serial_init(base, uart_info);
+ _stm32_serial_setbrg(base, uart_info,
+ CONFIG_DEBUG_UART_CLOCK,
+ CONFIG_BAUDRATE);
+ printf("DEBUG done\n");
+}
+
+static inline void _debug_uart_putc(int c)
+{
+ fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
+ struct stm32_uart_info *uart_info = _debug_uart_info();
+
+ while (_stm32_serial_putc(base, uart_info, c) == -EAGAIN)
+ WATCHDOG_RESET();
+}
+
+DEBUG_UART_FUNCS
+#endif
diff --git a/drivers/serial/serial_stm32.h b/drivers/serial/serial_stm32.h
index 8a1a24fda8..ccafa31219 100644
--- a/drivers/serial/serial_stm32.h
+++ b/drivers/serial/serial_stm32.h
@@ -13,6 +13,7 @@
#define ISR_OFFSET(x) (x ? 0x00 : 0x1c)
#define ICR_OFFSET 0x20
+
/*
* STM32F4 has one Data Register (DR) for received or transmitted
* data, so map Receive Data Register (RDR) and Transmit Data
@@ -53,19 +54,26 @@ struct stm32x7_serial_platdata {
};
#define USART_CR1_FIFOEN BIT(29)
+#define USART_CR1_M1 BIT(28)
#define USART_CR1_OVER8 BIT(15)
+#define USART_CR1_M0 BIT(12)
+#define USART_CR1_PCE BIT(10)
+#define USART_CR1_PS BIT(9)
#define USART_CR1_TE BIT(3)
#define USART_CR1_RE BIT(2)
#define USART_CR3_OVRDIS BIT(12)
-#define USART_ISR_FLAG_ORE BIT(3)
-#define USART_ISR_FLAG_RXNE BIT(5)
-#define USART_ISR_FLAG_TXE BIT(7)
+#define USART_ISR_TXE BIT(7)
+#define USART_ISR_RXNE BIT(5)
+#define USART_ISR_ORE BIT(3)
+#define USART_ISR_PE BIT(0)
#define USART_BRR_F_MASK GENMASK(7, 0)
#define USART_BRR_M_SHIFT 4
#define USART_BRR_M_MASK GENMASK(15, 4)
-#define USART_ICR_OREF BIT(3)
+#define USART_ICR_ORECF BIT(3)
+#define USART_ICR_PCECF BIT(0)
+
#endif
generated by cgit (git 2.34.1) at 2025-01-21 06:57:46 +0000