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-rw-r--r--drivers/usb/eth/mcs7830.c6
-rw-r--r--drivers/usb/host/Kconfig27
-rw-r--r--drivers/usb/host/Makefile3
-rw-r--r--drivers/usb/host/ehci-rcar_gen3.c106
-rw-r--r--drivers/usb/host/ohci-lpc32xx.c64
-rw-r--r--drivers/usb/musb-new/linux-compat.h2
-rw-r--r--drivers/usb/musb-new/omap2430.c2
-rw-r--r--drivers/usb/musb/omap3.c6
-rw-r--r--drivers/usb/musb/omap3.h2
9 files changed, 183 insertions, 35 deletions
diff --git a/drivers/usb/eth/mcs7830.c b/drivers/usb/eth/mcs7830.c
index 9d6cf8ce7b..4abef5d5c8 100644
--- a/drivers/usb/eth/mcs7830.c
+++ b/drivers/usb/eth/mcs7830.c
@@ -622,10 +622,12 @@ static int mcs7830_recv(struct eth_device *eth)
int len;
len = mcs7830_recv_common(ueth, buf);
- if (len <= 0)
+ if (len >= 0) {
net_process_received_packet(buf, len);
+ return 0;
+ }
- return 0;
+ return len;
}
/*
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index fb5aa6f889..b824eec41d 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -57,6 +57,7 @@ endif # USB_XHCI_HCD
config USB_EHCI_HCD
bool "EHCI HCD (USB 2.0) support"
+ default y if ARCH_MX5 || ARCH_MX6
select USB_HOST
---help---
The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0
@@ -74,12 +75,6 @@ config USB_EHCI_HCD
You may want to read <file:Documentation/usb/ehci.txt>.
-config USB_EHCI
- bool
- default USB_EHCI_HCD
- ---help---
- TODO: rename after most boards switch to Kconfig
-
if USB_EHCI_HCD
config USB_EHCI_ATMEL
@@ -90,8 +85,8 @@ config USB_EHCI_ATMEL
Enables support for the on-chip EHCI controller on Atmel chips.
config USB_EHCI_MARVELL
- bool "Support for MVEBU (AXP / A38x) on-chip EHCI USB controller"
- depends on ARCH_MVEBU
+ bool "Support for Marvell on-chip EHCI USB controller"
+ depends on ARCH_MVEBU || KIRKWOOD || ORION5X
default y
---help---
Enables support for the on-chip EHCI controller on MVEBU SoCs.
@@ -110,6 +105,14 @@ config USB_EHCI_MX7
---help---
Enables support for the on-chip EHCI controller on i.MX7 SoCs.
+config USB_EHCI_OMAP
+ bool "Support for OMAP3+ on-chip EHCI USB controller"
+ depends on ARCH_OMAP2PLUS
+ default y
+ ---help---
+ Enables support for the on-chip EHCI controller on OMAP3 and later
+ SoCs.
+
if USB_EHCI_MX7
config MXC_USB_OTG_HACTIVE
@@ -130,6 +133,14 @@ config USB_EHCI_MSM
This driver supports combination of Chipidea USB controller
and Synapsys USB PHY in host mode only.
+config USB_EHCI_RCAR_GEN3
+ bool "Support for Renesas RCar M3/H3 EHCI USB controller"
+ depends on RCAR_GEN3
+ default y
+ ---help---
+ Enables support for the on-chip EHCI controller on Renesas
+ R8A7795 and R8A7796 SoCs.
+
config USB_EHCI_ZYNQ
bool "Support for Xilinx Zynq on-chip EHCI USB controller"
depends on ARCH_ZYNQ
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 58c0cf54c2..4ece0a2e4b 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -24,7 +24,7 @@ obj-$(CONFIG_USB_OHCI_LPC32XX) += ohci-lpc32xx.o
obj-$(CONFIG_USB_OHCI_GENERIC) += ohci-generic.o
# echi
-obj-$(CONFIG_USB_EHCI) += ehci-hcd.o
+obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
obj-$(CONFIG_USB_EHCI_ARMADA100) += ehci-armada100.o utmi-armada100.o
obj-$(CONFIG_USB_EHCI_ATMEL) += ehci-atmel.o
ifdef CONFIG_MPC512X
@@ -51,6 +51,7 @@ obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o
obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
+obj-$(CONFIG_USB_EHCI_RCAR_GEN3) += ehci-rcar_gen3.o
obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
# xhci
diff --git a/drivers/usb/host/ehci-rcar_gen3.c b/drivers/usb/host/ehci-rcar_gen3.c
new file mode 100644
index 0000000000..525e7f3573
--- /dev/null
+++ b/drivers/usb/host/ehci-rcar_gen3.c
@@ -0,0 +1,106 @@
+/*
+ * drivers/usb/host/ehci-rcar_gen3.
+ * This file is EHCI HCD (Host Controller Driver) for USB.
+ *
+ * Copyright (C) 2015-2017 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <wait_bit.h>
+#include <asm/io.h>
+#include <usb/ehci-ci.h>
+#include "ehci.h"
+
+#define RCAR_GEN3_USB_BASE(n) (0xEE080000 + ((n) * 0x20000))
+
+#define EHCI_USBCMD 0x120
+
+#define CORE_SPD_RSM_TIMSET 0x30c
+#define CORE_OC_TIMSET 0x310
+
+/* Register offset */
+#define AHB_OFFSET 0x200
+
+#define BASE_HSUSB 0xE6590000
+#define REG_LPSTS (BASE_HSUSB + 0x0102) /* 16bit */
+#define SUSPM 0x4000
+#define SUSPM_NORMAL BIT(14)
+#define REG_UGCTRL2 (BASE_HSUSB + 0x0184) /* 32bit */
+#define USB0SEL 0x00000030
+#define USB0SEL_EHCI 0x00000010
+
+#define SMSTPCR7 0xE615014C
+#define SMSTPCR700 BIT(0) /* EHCI3 */
+#define SMSTPCR701 BIT(1) /* EHCI2 */
+#define SMSTPCR702 BIT(2) /* EHCI1 */
+#define SMSTPCR703 BIT(3) /* EHCI0 */
+#define SMSTPCR704 BIT(4) /* HSUSB */
+
+#define AHB_PLL_RST BIT(1)
+
+#define USBH_INTBEN BIT(2)
+#define USBH_INTAEN BIT(1)
+
+#define AHB_INT_ENABLE 0x200
+#define AHB_USBCTR 0x20c
+
+int ehci_hcd_stop(int index)
+{
+#if defined(CONFIG_R8A7795)
+ const u32 mask = SMSTPCR703 | SMSTPCR702 | SMSTPCR701 | SMSTPCR700;
+#else
+ const u32 mask = SMSTPCR703 | SMSTPCR702;
+#endif
+ const u32 base = RCAR_GEN3_USB_BASE(index);
+ int ret;
+
+ /* Reset EHCI */
+ setbits_le32((uintptr_t)(base + EHCI_USBCMD), CMD_RESET);
+ ret = wait_for_bit("ehci-rcar", (void *)(uintptr_t)base + EHCI_USBCMD,
+ CMD_RESET, false, 10, true);
+ if (ret) {
+ printf("ehci-rcar: reset failed (index=%i, ret=%i).\n",
+ index, ret);
+ }
+
+ setbits_le32(SMSTPCR7, BIT(3 - index));
+
+ if ((readl(SMSTPCR7) & mask) == mask)
+ setbits_le32(SMSTPCR7, SMSTPCR704);
+
+ return 0;
+}
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ const void __iomem *base =
+ (void __iomem *)(uintptr_t)RCAR_GEN3_USB_BASE(index);
+ struct usb_ehci *ehci = (struct usb_ehci *)(uintptr_t)base;
+
+ clrbits_le32(SMSTPCR7, BIT(3 - index));
+ clrbits_le32(SMSTPCR7, SMSTPCR704);
+
+ *hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
+ *hcor = (struct ehci_hcor *)((uintptr_t)*hccr +
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
+
+ /* Enable interrupt */
+ setbits_le32(base + AHB_INT_ENABLE, USBH_INTBEN | USBH_INTAEN);
+ writel(0x014e029b, base + CORE_SPD_RSM_TIMSET);
+ writel(0x000209ab, base + CORE_OC_TIMSET);
+
+ /* Choice USB0SEL */
+ clrsetbits_le32(REG_UGCTRL2, USB0SEL, USB0SEL_EHCI);
+
+ /* Clock & Reset */
+ clrbits_le32(base + AHB_USBCTR, AHB_PLL_RST);
+
+ /* low power status */
+ clrsetbits_le16(REG_LPSTS, SUSPM, SUSPM_NORMAL);
+
+ return 0;
+}
diff --git a/drivers/usb/host/ohci-lpc32xx.c b/drivers/usb/host/ohci-lpc32xx.c
index 9245126ed6..2f2b4b90de 100644
--- a/drivers/usb/host/ohci-lpc32xx.c
+++ b/drivers/usb/host/ohci-lpc32xx.c
@@ -9,11 +9,13 @@
*/
#include <common.h>
+#include <dm.h>
#include <errno.h>
#include <wait_bit.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clk.h>
+#include <asm/arch/i2c.h>
#include <usb.h>
#include <i2c.h>
@@ -81,14 +83,20 @@ struct otg_regs {
static struct otg_regs *otg = (struct otg_regs *)USB_BASE;
static struct clk_pm_regs *clk_pwr = (struct clk_pm_regs *)CLK_PM_BASE;
-static int isp1301_set_value(int reg, u8 value)
+static int isp1301_set_value(struct udevice *dev, int reg, u8 value)
{
+#ifndef CONFIG_DM_I2C
return i2c_write(ISP1301_I2C_ADDR, reg, 1, &value, 1);
+#else
+ return dm_i2c_write(dev, reg, &value, 1);
+#endif
}
-static void isp1301_configure(void)
+static void isp1301_configure(struct udevice *dev)
{
+#ifndef CONFIG_DM_I2C
i2c_set_bus_num(I2C_2);
+#endif
/*
* LPC32XX only supports DAT_SE0 USB mode
@@ -96,23 +104,23 @@ static void isp1301_configure(void)
*/
/* Disable transparent UART mode first */
- isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_CLR, MC1_UART_EN);
+ isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_CLR, MC1_UART_EN);
- isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_CLR, ~MC1_SPEED_REG);
- isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_SET, MC1_SPEED_REG);
- isp1301_set_value(ISP1301_I2C_MODE_CONTROL_2_CLR, ~0);
- isp1301_set_value(ISP1301_I2C_MODE_CONTROL_2_SET,
+ isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_CLR, ~MC1_SPEED_REG);
+ isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_SET, MC1_SPEED_REG);
+ isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_2_CLR, ~0);
+ isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_2_SET,
MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL);
- isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_CLR, ~0);
- isp1301_set_value(ISP1301_I2C_MODE_CONTROL_1_SET, MC1_DAT_SE0);
- isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_SET,
+ isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_CLR, ~0);
+ isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_SET, MC1_DAT_SE0);
+ isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_SET,
OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN);
- isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_CLR,
+ isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_CLR,
OTG1_DM_PULLUP | OTG1_DP_PULLUP);
- isp1301_set_value(ISP1301_I2C_INTERRUPT_LATCH_CLR, ~0);
- isp1301_set_value(ISP1301_I2C_INTERRUPT_FALLING_CLR, ~0);
- isp1301_set_value(ISP1301_I2C_INTERRUPT_RISING_CLR, ~0);
+ isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_LATCH_CLR, ~0);
+ isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_FALLING_CLR, ~0);
+ isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_RISING_CLR, ~0);
/* Enable usb_need_clk clock after transceiver is initialized */
setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBDVND_EN);
@@ -149,6 +157,15 @@ static int usbpll_setup(void)
int usb_cpu_init(void)
{
u32 ret;
+ struct udevice *dev = NULL;
+
+#ifdef CONFIG_DM_I2C
+ ret = i2c_get_chip_for_busnum(I2C_2, ISP1301_I2C_ADDR, 1, &dev);
+ if (ret) {
+ debug("%s: No bus %d\n", __func__, I2C_2);
+ return ret;
+ }
+#endif
/*
* USB pins routing setup is done by "lpc32xx_usb_init()" and should
@@ -167,7 +184,7 @@ int usb_cpu_init(void)
return ret;
/* Configure ISP1301 */
- isp1301_configure();
+ isp1301_configure(dev);
/* setup USB clocks and PLL */
ret = usbpll_setup();
@@ -188,21 +205,32 @@ int usb_cpu_init(void)
return ret;
setbits_le32(&otg->otg_sts_ctrl, OTG_HOST_EN);
- isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_VBUS_DRV);
+ isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_VBUS_DRV);
return 0;
}
int usb_cpu_stop(void)
{
+ struct udevice *dev = NULL;
+ int ret = 0;
+
+#ifdef CONFIG_DM_I2C
+ ret = i2c_get_chip_for_busnum(I2C_2, ISP1301_I2C_ADDR, 1, &dev);
+ if (ret) {
+ debug("%s: No bus %d\n", __func__, I2C_2);
+ return ret;
+ }
+#endif
+
/* vbus off */
- isp1301_set_value(ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_VBUS_DRV);
+ isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_VBUS_DRV);
clrbits_le32(&otg->otg_sts_ctrl, OTG_HOST_EN);
clrbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_HCLK_EN);
- return 0;
+ return ret;
}
int usb_cpu_init_fail(void)
diff --git a/drivers/usb/musb-new/linux-compat.h b/drivers/usb/musb-new/linux-compat.h
index 9244977579..4dae83ed68 100644
--- a/drivers/usb/musb-new/linux-compat.h
+++ b/drivers/usb/musb-new/linux-compat.h
@@ -30,7 +30,7 @@
#define CONFIG_SOC_OMAP3430
#endif
-#ifdef CONFIG_OMAP4430
+#ifdef CONFIG_OMAP44XX
#define CONFIG_ARCH_OMAP4
#endif
diff --git a/drivers/usb/musb-new/omap2430.c b/drivers/usb/musb-new/omap2430.c
index 684ad9539a..ba22dfe6cb 100644
--- a/drivers/usb/musb-new/omap2430.c
+++ b/drivers/usb/musb-new/omap2430.c
@@ -441,7 +441,7 @@ static int omap2430_musb_enable(struct musb *musb)
twl6030_usb_device_settings();
#endif
-#ifdef CONFIG_OMAP4430
+#ifdef CONFIG_OMAP44XX
u32 *usbotghs_control = (u32 *)((*ctrl)->control_usbotghs_ctrl);
*usbotghs_control = USBOTGHS_CONTROL_AVALID |
USBOTGHS_CONTROL_VBUSVALID | USBOTGHS_CONTROL_IDDIG;
diff --git a/drivers/usb/musb/omap3.c b/drivers/usb/musb/omap3.c
index 97da529b44..57889ef0e7 100644
--- a/drivers/usb/musb/omap3.c
+++ b/drivers/usb/musb/omap3.c
@@ -55,7 +55,7 @@ static struct omap3_otg_regs *otg;
#define OMAP3_OTG_SYSSTATUS_RESETDONE 0x0001
/* OMAP4430 has an internal PHY, use it */
-#ifdef CONFIG_OMAP4430
+#ifdef CONFIG_OMAP44XX
#define OMAP3_OTG_INTERFSEL_OMAP 0x0000
#else
#define OMAP3_OTG_INTERFSEL_OMAP 0x0001
@@ -118,11 +118,11 @@ int musb_platform_init(void)
stdby &= ~OMAP3_OTG_FORCESTDBY_STANDBY;
writel(stdby, &otg->forcestdby);
-#ifdef CONFIG_OMAP3_EVM
+#ifdef CONFIG_TARGET_OMAP3_EVM
musb_cfg.extvbus = omap3_evm_need_extvbus();
#endif
-#ifdef CONFIG_OMAP4430
+#ifdef CONFIG_OMAP44XX
u32 *usbotghs_control =
(u32 *)((*ctrl)->control_usbotghs_ctrl);
*usbotghs_control = 0x15;
diff --git a/drivers/usb/musb/omap3.h b/drivers/usb/musb/omap3.h
index ae645c72de..d91ad0a85b 100644
--- a/drivers/usb/musb/omap3.h
+++ b/drivers/usb/musb/omap3.h
@@ -32,7 +32,7 @@
int musb_platform_init(void);
-#ifdef CONFIG_OMAP3_EVM
+#ifdef CONFIG_TARGET_OMAP3_EVM
extern u8 omap3_evm_need_extvbus(void);
#endif
generated by cgit (git 2.34.1) at 2024-12-29 11:48:09 +0000