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-rw-r--r--drivers/usb/host/xhci-omap.c1
-rw-r--r--drivers/usb/host/xhci.h6
-rw-r--r--drivers/usb/phy/omap_usb_phy.c17
3 files changed, 19 insertions, 5 deletions
diff --git a/drivers/usb/host/xhci-omap.c b/drivers/usb/host/xhci-omap.c
index e667810bb3..912b2bd8d5 100644
--- a/drivers/usb/host/xhci-omap.c
+++ b/drivers/usb/host/xhci-omap.c
@@ -98,6 +98,7 @@ static int omap_xhci_core_init(struct omap_xhci *omap)
{
int ret = 0;
+ usb_phy_power(1);
omap_enable_phy(omap);
ret = dwc3_core_init(omap->dwc3_reg);
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index ceb1573d86..6685ed23de 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -20,9 +20,7 @@
#include <asm/cache.h>
#include <asm/io.h>
#include <linux/list.h>
-
-#define upper_32_bits(n) (u32)((n) >> 32)
-#define lower_32_bits(n) (u32)(n)
+#include <linux/compat.h>
#define MAX_EP_CTX_NUM 31
#define XHCI_ALIGNMENT 64
@@ -1121,7 +1119,7 @@ static inline void xhci_writeq(__le64 volatile *regs, const u64 val)
__u32 *ptr = (__u32 *)regs;
u32 val_lo = lower_32_bits(val);
/* FIXME */
- u32 val_hi = 0;
+ u32 val_hi = upper_32_bits(val);
writel(val_lo, ptr);
writel(val_hi, ptr + 1);
}
diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c
index af46db2edd..f78d532966 100644
--- a/drivers/usb/phy/omap_usb_phy.c
+++ b/drivers/usb/phy/omap_usb_phy.c
@@ -222,7 +222,22 @@ static void am437x_enable_usb2_phy2(struct omap_xhci *omap)
void usb_phy_power(int on)
{
- return;
+ u32 val;
+
+ /* USB1_CTRL */
+ val = readl(USB1_CTRL);
+ if (on) {
+ /*
+ * these bits are re-used on AM437x to power up/down the USB
+ * CM and OTG PHYs, if we don't toggle them, USB will not be
+ * functional on newer silicon revisions
+ */
+ val &= ~(USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN);
+ } else {
+ val |= USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN;
+ }
+
+ writel(val, USB1_CTRL);
}
#endif /* CONFIG_AM437X_USB2PHY2_HOST */