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-rw-r--r--drivers/video/Kconfig20
-rw-r--r--drivers/video/Makefile4
-rwxr-xr-xdrivers/video/anx9804.c188
-rw-r--r--drivers/video/anx9804.h25
-rw-r--r--drivers/video/bcm2835.c4
-rw-r--r--drivers/video/bridge/Kconfig27
-rw-r--r--drivers/video/bridge/Makefile9
-rw-r--r--drivers/video/bridge/ps862x.c134
-rw-r--r--drivers/video/bridge/ptn3460.c38
-rw-r--r--drivers/video/bridge/video-bridge-uclass.c119
-rw-r--r--drivers/video/cfb_console.c100
-rw-r--r--drivers/video/coreboot_fb.c24
-rw-r--r--drivers/video/ct69000.c21
-rw-r--r--drivers/video/exynos_dp.c24
-rw-r--r--drivers/video/exynos_dp_lowlevel.c4
-rw-r--r--drivers/video/exynos_fb.c8
-rw-r--r--drivers/video/exynos_fimd.c4
-rw-r--r--drivers/video/exynos_mipi_dsi.c4
-rw-r--r--drivers/video/parade.c231
-rw-r--r--drivers/video/pxa_lcd.c9
-rw-r--r--drivers/video/sunxi_display.c450
-rw-r--r--drivers/video/tegra.c4
-rw-r--r--drivers/video/vesa_fb.c8
23 files changed, 1022 insertions, 437 deletions
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 9ae23e8dd0..caf1efcbb3 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1,3 +1,9 @@
+#
+# Video configuration
+#
+
+menu "Graphics support"
+
config VIDEO_VESA
bool "Enable VESA video driver support"
default n
@@ -38,7 +44,7 @@ config FRAMEBUFFER_VESA_MODE_104
bool "1024x768 16-color"
config FRAMEBUFFER_VESA_MODE_105
- bool "1024x7686 256-color"
+ bool "1024x768 256-color"
config FRAMEBUFFER_VESA_MODE_106
bool "1280x1024 16-color"
@@ -145,6 +151,14 @@ config FRAMEBUFFER_VESA_MODE
default 0x11B if FRAMEBUFFER_VESA_MODE_11B
default 0x117 if FRAMEBUFFER_VESA_MODE_USER
+config VIDEO_LCD_ANX9804
+ bool "ANX9804 bridge chip"
+ default n
+ ---help---
+ Support for the ANX9804 bridge chip, which can take pixel data coming
+ from a parallel LCD interface and translate it on the fy into a DP
+ interface for driving eDP TFT displays. It uses I2C for configuration.
+
config VIDEO_LCD_SSD2828
bool "SSD2828 bridge chip"
default n
@@ -240,3 +254,7 @@ config VIDEO_TEGRA124
HDMI. At present only eDP is supported by U-Boot. This option
enables this support which can be used on devices which
have an eDP display connected.
+
+source "drivers/video/bridge/Kconfig"
+
+endmenu
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 2ead7f192c..e85fd8a677 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_VIDEO_COREBOOT) += coreboot_fb.o
obj-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o
obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
obj-$(CONFIG_VIDEO_IMX25LCDC) += imx25lcdc.o videomodes.o
+obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
@@ -51,6 +52,7 @@ obj-$(CONFIG_VIDEO_VESA) += vesa_fb.o
obj-$(CONFIG_FORMIKE) += formike.o
obj-$(CONFIG_LG4573) += lg4573.o
obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
-obj-$(CONFIG_VIDEO_PARADE) += parade.o
obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
+
+obj-y += bridge/
diff --git a/drivers/video/anx9804.c b/drivers/video/anx9804.c
new file mode 100755
index 0000000000..83d60d672d
--- /dev/null
+++ b/drivers/video/anx9804.c
@@ -0,0 +1,188 @@
+/*
+ * (C) 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Support for the ANX9804 bridge chip, which can take pixel data coming
+ * from a parallel LCD interface and translate it on the flight into a DP
+ * interface for driving eDP TFT displays.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include "anx9804.h"
+
+#define BIT(x) (1 << (x))
+
+/* Registers at i2c address 0x38 */
+
+#define ANX9804_HDCP_CONTROL_0_REG 0x01
+
+#define ANX9804_SYS_CTRL2_REG 0x81
+#define ANX9804_SYS_CTRL2_CHA_STA 0x04
+
+#define ANX9804_SYS_CTRL3_REG 0x82
+#define ANX9804_SYS_CTRL3_VALID_CTRL BIT(0)
+#define ANX9804_SYS_CTRL3_F_VALID BIT(1)
+#define ANX9804_SYS_CTRL3_HPD_CTRL BIT(4)
+#define ANX9804_SYS_CTRL3_F_HPD BIT(5)
+
+#define ANX9804_LINK_BW_SET_REG 0xa0
+#define ANX9804_LANE_COUNT_SET_REG 0xa1
+#define ANX9804_TRAINING_PTN_SET_REG 0xa2
+#define ANX9804_TRAINING_LANE0_SET_REG 0xa3
+#define ANX9804_TRAINING_LANE1_SET_REG 0xa4
+#define ANX9804_TRAINING_LANE2_SET_REG 0xa5
+#define ANX9804_TRAINING_LANE3_SET_REG 0xa6
+
+#define ANX9804_LINK_TRAINING_CTRL_REG 0xa8
+#define ANX9804_LINK_TRAINING_CTRL_EN BIT(0)
+
+#define ANX9804_LINK_DEBUG_REG 0xb8
+#define ANX9804_PLL_CTRL_REG 0xc7
+#define ANX9804_ANALOG_POWER_DOWN_REG 0xc8
+
+/* Registers at i2c address 0x39 */
+
+#define ANX9804_DEV_IDH_REG 0x03
+
+#define ANX9804_POWERD_CTRL_REG 0x05
+#define ANX9804_POWERD_AUDIO BIT(4)
+
+#define ANX9804_RST_CTRL_REG 0x06
+
+#define ANX9804_RST_CTRL2_REG 0x07
+#define ANX9804_RST_CTRL2_AUX BIT(2)
+#define ANX9804_RST_CTRL2_AC_MODE BIT(6)
+
+#define ANX9804_VID_CTRL1_REG 0x08
+#define ANX9804_VID_CTRL1_VID_EN BIT(7)
+#define ANX9804_VID_CTRL1_EDGE BIT(0)
+
+#define ANX9804_VID_CTRL2_REG 0x09
+#define ANX9804_ANALOG_DEBUG_REG1 0xdc
+#define ANX9804_ANALOG_DEBUG_REG3 0xde
+#define ANX9804_PLL_FILTER_CTRL1 0xdf
+#define ANX9804_PLL_FILTER_CTRL3 0xe1
+#define ANX9804_PLL_FILTER_CTRL 0xe2
+#define ANX9804_PLL_CTRL3 0xe6
+
+/**
+ * anx9804_init() - Init anx9804 parallel lcd to edp bridge chip
+ *
+ * This function will init an anx9804 parallel lcd to dp bridge chip
+ * using the passed in parameters.
+ *
+ * @i2c_bus: Number of the i2c bus to which the anx9804 is connected.
+ * @lanes: Number of displayport lanes to use
+ * @data_rate: Register value for the bandwidth reg 0x06: 1.62G, 0x0a: 2.7G
+ * @bpp: Bits per pixel, must be 18 or 24
+ */
+void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp)
+{
+ unsigned int orig_i2c_bus = i2c_get_bus_num();
+ u8 c, colordepth;
+ int i;
+
+ i2c_set_bus_num(i2c_bus);
+
+ if (bpp == 18)
+ colordepth = 0x00; /* 6 bit */
+ else
+ colordepth = 0x10; /* 8 bit */
+
+ /* Reset */
+ i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 1);
+ mdelay(100);
+ i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 0);
+
+ /* Write 0 to the powerdown reg (powerup everything) */
+ i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, 0);
+
+ c = i2c_reg_read(0x39, ANX9804_DEV_IDH_REG);
+ if (c != 0x98) {
+ printf("Error anx9804 chipid mismatch\n");
+ i2c_set_bus_num(orig_i2c_bus);
+ return;
+ }
+
+ for (i = 0; i < 100; i++) {
+ c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);
+ i2c_reg_write(0x38, ANX9804_SYS_CTRL2_REG, c);
+ c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);
+ if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0)
+ break;
+
+ mdelay(5);
+ }
+ if (i == 100)
+ printf("Error anx9804 clock is not stable\n");
+
+ i2c_reg_write(0x39, ANX9804_VID_CTRL2_REG, colordepth);
+
+ /* Set a bunch of analog related register values */
+ i2c_reg_write(0x38, ANX9804_PLL_CTRL_REG, 0x07);
+ i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL3, 0x19);
+ i2c_reg_write(0x39, ANX9804_PLL_CTRL3, 0xd9);
+ i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE);
+ i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG1, 0xf0);
+ i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG3, 0x99);
+ i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL1, 0x7b);
+ i2c_reg_write(0x38, ANX9804_LINK_DEBUG_REG, 0x30);
+ i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL, 0x06);
+
+ /* Force HPD */
+ i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,
+ ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL);
+
+ /* Power up and configure lanes */
+ i2c_reg_write(0x38, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
+ i2c_reg_write(0x38, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
+ i2c_reg_write(0x38, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
+ i2c_reg_write(0x38, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
+ i2c_reg_write(0x38, ANX9804_TRAINING_LANE3_SET_REG, 0x00);
+
+ /* Reset AUX CH */
+ i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,
+ ANX9804_RST_CTRL2_AC_MODE | ANX9804_RST_CTRL2_AUX);
+ i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,
+ ANX9804_RST_CTRL2_AC_MODE);
+
+ /* Powerdown audio and some other unused bits */
+ i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
+ i2c_reg_write(0x38, ANX9804_HDCP_CONTROL_0_REG, 0x00);
+ i2c_reg_write(0x38, 0xa7, 0x00);
+
+ /* Set data-rate / lanes */
+ i2c_reg_write(0x38, ANX9804_LINK_BW_SET_REG, data_rate);
+ i2c_reg_write(0x38, ANX9804_LANE_COUNT_SET_REG, lanes);
+
+ /* Link training */
+ i2c_reg_write(0x38, ANX9804_LINK_TRAINING_CTRL_REG,
+ ANX9804_LINK_TRAINING_CTRL_EN);
+ mdelay(5);
+ for (i = 0; i < 100; i++) {
+ c = i2c_reg_read(0x38, ANX9804_LINK_TRAINING_CTRL_REG);
+ if ((c & 0x01) == 0)
+ break;
+
+ mdelay(5);
+ }
+ if(i == 100) {
+ printf("Error anx9804 link training timeout\n");
+ i2c_set_bus_num(orig_i2c_bus);
+ return;
+ }
+
+ /* Enable */
+ i2c_reg_write(0x39, ANX9804_VID_CTRL1_REG,
+ ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE);
+ /* Force stream valid */
+ i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,
+ ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL |
+ ANX9804_SYS_CTRL3_F_VALID | ANX9804_SYS_CTRL3_VALID_CTRL);
+
+ i2c_set_bus_num(orig_i2c_bus);
+}
diff --git a/drivers/video/anx9804.h b/drivers/video/anx9804.h
new file mode 100644
index 0000000000..6c5daf92ea
--- /dev/null
+++ b/drivers/video/anx9804.h
@@ -0,0 +1,25 @@
+/*
+ * (C) 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Support for the ANX9804 bridge chip, which can take pixel data coming
+ * from a parallel LCD interface and translate it on the flight into a DP
+ * interface for driving eDP TFT displays.
+ */
+
+#ifndef _ANX9804_H
+#define _ANX9804_H
+
+#define ANX9804_DATA_RATE_1620M 0x06
+#define ANX9804_DATA_RATE_2700M 0x0a
+
+#ifdef CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
+void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp);
+#else
+static inline void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate,
+ int bpp) {}
+#endif
+#endif
diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c
index 1f18231ac6..61d054dd89 100644
--- a/drivers/video/bcm2835.c
+++ b/drivers/video/bcm2835.c
@@ -38,8 +38,8 @@ struct msg_setup {
void lcd_ctrl_init(void *lcdbase)
{
- ALLOC_ALIGN_BUFFER(struct msg_query, msg_query, 1, 16);
- ALLOC_ALIGN_BUFFER(struct msg_setup, msg_setup, 1, 16);
+ ALLOC_CACHE_ALIGN_BUFFER(struct msg_query, msg_query, 1);
+ ALLOC_CACHE_ALIGN_BUFFER(struct msg_setup, msg_setup, 1);
int ret;
u32 w, h;
diff --git a/drivers/video/bridge/Kconfig b/drivers/video/bridge/Kconfig
new file mode 100644
index 0000000000..2a3b6c4bee
--- /dev/null
+++ b/drivers/video/bridge/Kconfig
@@ -0,0 +1,27 @@
+config VIDEO_BRIDGE
+ bool "Support video bridges"
+ depends on DM
+ help
+ Some platforms use video bridges to convert from one output to
+ another. For example, where the SoC only supports eDP and the LCD
+ requires LVDS, an eDP->LVDS bridge chip can be used to provide the
+ necessary conversion. This option enables support for these devices.
+
+config VIDEO_BRIDGE_PARADE_PS862X
+ bool "Support Parade PS862X DP->LVDS bridge"
+ depends on VIDEO_BRIDGE
+ help
+ The Parade PS8622 and PS8625 are DisplayPort-to-LVDS (Low voltage
+ differential signalling) converters. They enable an LVDS LCD panel
+ to be connected to an eDP output device such as an SoC that lacks
+ LVDS capability, or where LVDS requires too many signals to route
+ on the PCB. Setup parameters are provided in the device tree.
+
+config VIDEO_BRIDGE_NXP_PTN3460
+ bool "Support NXP PTN3460 DP->LVDS bridge"
+ depends on VIDEO_BRIDGE
+ help
+ The NXP PTN3460 is a DisplayPort-to-LVDS (Low voltage differential
+ signalling) converter. It enables an LVDS LCD panel to be connected
+ to an eDP output device such as an SoC that lacks LVDS capability,
+ or where LVDS requires too many signals to route on the PCB.
diff --git a/drivers/video/bridge/Makefile b/drivers/video/bridge/Makefile
new file mode 100644
index 0000000000..ce731fa4ca
--- /dev/null
+++ b/drivers/video/bridge/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2015 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_VIDEO_BRIDGE) += video-bridge-uclass.o
+obj-$(CONFIG_VIDEO_BRIDGE_PARADE_PS862X) += ps862x.o
+obj-$(CONFIG_VIDEO_BRIDGE_NXP_PTN3460) += ptn3460.o
diff --git a/drivers/video/bridge/ps862x.c b/drivers/video/bridge/ps862x.c
new file mode 100644
index 0000000000..80f63e3eb5
--- /dev/null
+++ b/drivers/video/bridge/ps862x.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <i2c.h>
+#include <video_bridge.h>
+#include <power/regulator.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Initialisation of the chip is a process of writing certain values into
+ * certain registers over i2c bus. The chip in fact responds to a range of
+ * addresses on the i2c bus, so for each written value three parameters are
+ * required: i2c address, register address and the actual value.
+ *
+ * The base address is derived from the device tree, but oddly the chip
+ * responds on several addresses with different register sets for each.
+ */
+
+/**
+ * ps8622_write() Write a PS8622 eDP bridge i2c register
+ *
+ * @param dev I2C device
+ * @param addr_off offset from the i2c base address for ps8622
+ * @param reg_addr register address to write
+ * @param value value to be written
+ * @return 0 on success, non-0 on failure
+ */
+static int ps8622_write(struct udevice *dev, unsigned addr_off,
+ unsigned char reg_addr, unsigned char value)
+{
+ struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
+ uint8_t buf[2];
+ struct i2c_msg msg;
+ int ret;
+
+ msg.addr = chip->chip_addr + addr_off;
+ msg.flags = 0;
+ buf[0] = reg_addr;
+ buf[1] = value;
+ msg.buf = buf;
+ msg.len = 2;
+ ret = dm_i2c_xfer(dev, &msg, 1);
+ if (ret) {
+ debug("%s: write failed, reg=%#x, value=%#x, ret=%d\n",
+ __func__, reg_addr, value, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ps8622_set_backlight(struct udevice *dev, int percent)
+{
+ int level = percent * 255 / 100;
+
+ debug("%s: level=%d\n", __func__, level);
+ return ps8622_write(dev, 0x01, 0xa7, level);
+}
+
+static int ps8622_attach(struct udevice *dev)
+{
+ const uint8_t *params;
+ struct udevice *reg;
+ int ret, i, len;
+
+ debug("%s: %s\n", __func__, dev->name);
+ /* set the LDO providing the 1.2V rail to the Parade bridge */
+ ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
+ "power-supply", &reg);
+ if (!ret) {
+ ret = regulator_autoset(reg);
+ } else if (ret != -ENOENT) {
+ debug("%s: Failed to enable power: ret=%d\n", __func__, ret);
+ return ret;
+ }
+
+ ret = video_bridge_set_active(dev, true);
+ if (ret)
+ return ret;
+
+ params = fdt_getprop(gd->fdt_blob, dev->of_offset, "parade,regs", &len);
+ if (!params || len % 3) {
+ debug("%s: missing/invalid params=%p, len=%x\n", __func__,
+ params, len);
+ return -EINVAL;
+ }
+
+ /* need to wait 20ms after power on before doing I2C writes */
+ mdelay(20);
+ for (i = 0; i < len; i += 3) {
+ ret = ps8622_write(dev, params[i + 0], params[i + 1],
+ params[i + 2]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ps8622_probe(struct udevice *dev)
+{
+ debug("%s\n", __func__);
+ if (device_get_uclass_id(dev->parent) != UCLASS_I2C)
+ return -EPROTONOSUPPORT;
+
+ return 0;
+}
+
+struct video_bridge_ops ps8622_ops = {
+ .attach = ps8622_attach,
+ .set_backlight = ps8622_set_backlight,
+};
+
+static const struct udevice_id ps8622_ids[] = {
+ { .compatible = "parade,ps8622", },
+ { .compatible = "parade,ps8625", },
+ { }
+};
+
+U_BOOT_DRIVER(parade_ps8622) = {
+ .name = "parade_ps8622",
+ .id = UCLASS_VIDEO_BRIDGE,
+ .of_match = ps8622_ids,
+ .probe = ps8622_probe,
+ .ops = &ps8622_ops,
+};
diff --git a/drivers/video/bridge/ptn3460.c b/drivers/video/bridge/ptn3460.c
new file mode 100644
index 0000000000..2e2ae7c5a6
--- /dev/null
+++ b/drivers/video/bridge/ptn3460.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <video_bridge.h>
+
+static int ptn3460_attach(struct udevice *dev)
+{
+ int ret;
+
+ debug("%s: %s\n", __func__, dev->name);
+ ret = video_bridge_set_active(dev, true);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+struct video_bridge_ops ptn3460_ops = {
+ .attach = ptn3460_attach,
+};
+
+static const struct udevice_id ptn3460_ids[] = {
+ { .compatible = "nxp,ptn3460", },
+ { }
+};
+
+U_BOOT_DRIVER(parade_ptn3460) = {
+ .name = "nmp_ptn3460",
+ .id = UCLASS_VIDEO_BRIDGE,
+ .of_match = ptn3460_ids,
+ .ops = &ptn3460_ops,
+};
diff --git a/drivers/video/bridge/video-bridge-uclass.c b/drivers/video/bridge/video-bridge-uclass.c
new file mode 100644
index 0000000000..6c5990f54c
--- /dev/null
+++ b/drivers/video/bridge/video-bridge-uclass.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <video_bridge.h>
+
+int video_bridge_set_backlight(struct udevice *dev, int percent)
+{
+ struct video_bridge_ops *ops = video_bridge_get_ops(dev);
+
+ if (!ops->set_backlight)
+ return -ENOSYS;
+
+ return ops->set_backlight(dev, percent);
+}
+
+int video_bridge_attach(struct udevice *dev)
+{
+ struct video_bridge_ops *ops = video_bridge_get_ops(dev);
+
+ if (!ops->attach)
+ return -ENOSYS;
+
+ return ops->attach(dev);
+}
+
+int video_bridge_check_attached(struct udevice *dev)
+{
+ struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct video_bridge_ops *ops = video_bridge_get_ops(dev);
+ int ret;
+
+ if (!ops->check_attached) {
+ ret = dm_gpio_get_value(&uc_priv->hotplug);
+
+ return ret > 0 ? 0 : ret == 0 ? -ENOTCONN : ret;
+ }
+
+ return ops->check_attached(dev);
+}
+
+static int video_bridge_pre_probe(struct udevice *dev)
+{
+ struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev);
+ int ret;
+
+ debug("%s\n", __func__);
+ ret = gpio_request_by_name(dev, "sleep-gpios", 0,
+ &uc_priv->sleep, GPIOD_IS_OUT);
+ if (ret) {
+ debug("%s: Could not decode sleep-gpios (%d)\n", __func__, ret);
+ return ret;
+ }
+ /*
+ * Drop this for now as we do not have driver model pinctrl support
+ *
+ * ret = dm_gpio_set_pull(&uc_priv->sleep, GPIO_PULL_NONE);
+ * if (ret) {
+ * debug("%s: Could not set sleep pull value\n", __func__);
+ * return ret;
+ * }
+ */
+ ret = gpio_request_by_name(dev, "reset-gpios", 0, &uc_priv->reset,
+ GPIOD_IS_OUT);
+ if (ret) {
+ debug("%s: Could not decode reset-gpios (%d)\n", __func__, ret);
+ return ret;
+ }
+ /*
+ * Drop this for now as we do not have driver model pinctrl support
+ *
+ * ret = dm_gpio_set_pull(&uc_priv->reset, GPIO_PULL_NONE);
+ * if (ret) {
+ * debug("%s: Could not set reset pull value\n", __func__);
+ * return ret;
+ * }
+ */
+ ret = gpio_request_by_name(dev, "hotplug-gpios", 0, &uc_priv->hotplug,
+ GPIOD_IS_IN);
+ if (ret && ret != -ENOENT) {
+ debug("%s: Could not decode hotplug (%d)\n", __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+int video_bridge_set_active(struct udevice *dev, bool active)
+{
+ struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev);
+ int ret;
+
+ debug("%s: %d\n", __func__, active);
+ ret = dm_gpio_set_value(&uc_priv->sleep, !active);
+ if (ret)
+ return ret;
+ if (active) {
+ ret = dm_gpio_set_value(&uc_priv->reset, true);
+ if (ret)
+ return ret;
+ udelay(10);
+ ret = dm_gpio_set_value(&uc_priv->reset, false);
+ }
+
+ return ret;
+}
+
+UCLASS_DRIVER(video_bridge) = {
+ .id = UCLASS_VIDEO_BRIDGE,
+ .name = "video_bridge",
+ .per_device_auto_alloc_size = sizeof(struct video_bridge_priv),
+ .pre_probe = video_bridge_pre_probe,
+};
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index 7f2ddc10c6..aa7ca8646d 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -283,9 +283,10 @@ void console_cursor(int state);
#define VIDEO_COLS VIDEO_VISIBLE_COLS
#define VIDEO_ROWS VIDEO_VISIBLE_ROWS
-#define VIDEO_SIZE (VIDEO_ROWS*VIDEO_COLS*VIDEO_PIXEL_SIZE)
-#define VIDEO_PIX_BLOCKS (VIDEO_SIZE >> 2)
-#define VIDEO_LINE_LEN (VIDEO_COLS*VIDEO_PIXEL_SIZE)
+#ifndef VIDEO_LINE_LEN
+#define VIDEO_LINE_LEN (VIDEO_COLS * VIDEO_PIXEL_SIZE)
+#endif
+#define VIDEO_SIZE (VIDEO_ROWS * VIDEO_LINE_LEN)
#define VIDEO_BURST_LEN (VIDEO_COLS/8)
#ifdef CONFIG_VIDEO_LOGO
@@ -1306,7 +1307,7 @@ static int display_rle8_bitmap(struct bmp_image *img, int xoff, int yoff,
struct palette p[256];
struct bmp_color_table_entry cte;
int green_shift, red_off;
- int limit = VIDEO_COLS * VIDEO_ROWS;
+ int limit = (VIDEO_LINE_LEN / VIDEO_PIXEL_SIZE) * VIDEO_ROWS;
int pixels = 0;
x = 0;
@@ -1314,7 +1315,8 @@ static int display_rle8_bitmap(struct bmp_image *img, int xoff, int yoff,
ncolors = __le32_to_cpu(img->header.colors_used);
bpp = VIDEO_PIXEL_SIZE;
fbp = (unsigned char *) ((unsigned int) video_fb_address +
- (((y + yoff) * VIDEO_COLS) + xoff) * bpp);
+ (y + yoff) * VIDEO_LINE_LEN +
+ xoff * bpp);
bm = (uchar *) img + __le32_to_cpu(img->header.data_offset);
@@ -1368,8 +1370,8 @@ static int display_rle8_bitmap(struct bmp_image *img, int xoff, int yoff,
y--;
fbp = (unsigned char *)
((unsigned int) video_fb_address +
- (((y + yoff) * VIDEO_COLS) +
- xoff) * bpp);
+ (y + yoff) * VIDEO_LINE_LEN +
+ xoff * bpp);
continue;
case 1:
/* end of bitmap data marker */
@@ -1381,8 +1383,8 @@ static int display_rle8_bitmap(struct bmp_image *img, int xoff, int yoff,
y -= bm[3];
fbp = (unsigned char *)
((unsigned int) video_fb_address +
- (((y + yoff) * VIDEO_COLS) +
- x + xoff) * bpp);
+ (y + yoff) * VIDEO_LINE_LEN +
+ xoff * bpp);
bm += 4;
break;
default:
@@ -1561,7 +1563,7 @@ int video_display_bitmap(ulong bmp_image, int x, int y)
bmap = (uchar *) bmp + le32_to_cpu(bmp->header.data_offset);
fb = (uchar *) (video_fb_address +
- ((y + height - 1) * VIDEO_COLS * VIDEO_PIXEL_SIZE) +
+ ((y + height - 1) * VIDEO_LINE_LEN) +
x * VIDEO_PIXEL_SIZE);
#ifdef CONFIG_VIDEO_BMP_RLE8
@@ -1597,7 +1599,7 @@ int video_display_bitmap(ulong bmp_image, int x, int y)
cte.blue);
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) *
+ fb -= VIDEO_LINE_LEN + width *
VIDEO_PIXEL_SIZE;
}
break;
@@ -1628,8 +1630,8 @@ int video_display_bitmap(ulong bmp_image, int x, int y)
*fb++ = *bmap++;
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) *
- VIDEO_PIXEL_SIZE;
+ fb -= VIDEO_LINE_LEN + width *
+ VIDEO_PIXEL_SIZE;
}
break;
case GDF__8BIT_332RGB:
@@ -1642,8 +1644,8 @@ int video_display_bitmap(ulong bmp_image, int x, int y)
cte.blue);
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) *
- VIDEO_PIXEL_SIZE;
+ fb -= VIDEO_LINE_LEN + width *
+ VIDEO_PIXEL_SIZE;
}
break;
case GDF_15BIT_555RGB:
@@ -1666,8 +1668,8 @@ int video_display_bitmap(ulong bmp_image, int x, int y)
#endif
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) *
- VIDEO_PIXEL_SIZE;
+ fb -= VIDEO_LINE_LEN + width *
+ VIDEO_PIXEL_SIZE;
}
break;
case GDF_16BIT_565RGB:
@@ -1680,8 +1682,8 @@ int video_display_bitmap(ulong bmp_image, int x, int y)
cte.blue);
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) *
- VIDEO_PIXEL_SIZE;
+ fb -= VIDEO_LINE_LEN + width *
+ VIDEO_PIXEL_SIZE;
}
break;
case GDF_32BIT_X888RGB:
@@ -1694,8 +1696,8 @@ int video_display_bitmap(ulong bmp_image, int x, int y)
cte.blue);
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) *
- VIDEO_PIXEL_SIZE;
+ fb -= VIDEO_LINE_LEN + width *
+ VIDEO_PIXEL_SIZE;
}
break;
case GDF_24BIT_888RGB:
@@ -1708,8 +1710,8 @@ int video_display_bitmap(ulong bmp_image, int x, int y)
cte.blue);
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) *
- VIDEO_PIXEL_SIZE;
+ fb -= VIDEO_LINE_LEN + width *
+ VIDEO_PIXEL_SIZE;
}
break;
}
@@ -1728,8 +1730,8 @@ int video_display_bitmap(ulong bmp_image, int x, int y)
bmap += 3;
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) *
- VIDEO_PIXEL_SIZE;
+ fb -= VIDEO_LINE_LEN + width *
+ VIDEO_PIXEL_SIZE;
}
break;
case GDF_15BIT_555RGB:
@@ -1751,8 +1753,8 @@ int video_display_bitmap(ulong bmp_image, int x, int y)
bmap += 3;
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) *
- VIDEO_PIXEL_SIZE;
+ fb -= VIDEO_LINE_LEN + width *
+ VIDEO_PIXEL_SIZE;
}
break;
case GDF_16BIT_565RGB:
@@ -1765,8 +1767,8 @@ int video_display_bitmap(ulong bmp_image, int x, int y)
bmap += 3;
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) *
- VIDEO_PIXEL_SIZE;
+ fb -= VIDEO_LINE_LEN + width *
+ VIDEO_PIXEL_SIZE;
}
break;
case GDF_32BIT_X888RGB:
@@ -1779,8 +1781,8 @@ int video_display_bitmap(ulong bmp_image, int x, int y)
bmap += 3;
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) *
- VIDEO_PIXEL_SIZE;
+ fb -= VIDEO_LINE_LEN + width *
+ VIDEO_PIXEL_SIZE;
}
break;
case GDF_24BIT_888RGB:
@@ -1793,8 +1795,8 @@ int video_display_bitmap(ulong bmp_image, int x, int y)
bmap += 3;
}
bmap += padded_line;
- fb -= (VIDEO_VISIBLE_COLS + width) *
- VIDEO_PIXEL_SIZE;
+ fb -= VIDEO_LINE_LEN + width *
+ VIDEO_PIXEL_SIZE;
}
break;
default:
@@ -1826,20 +1828,16 @@ int video_display_bitmap(ulong bmp_image, int x, int y)
static int video_logo_xpos;
static int video_logo_ypos;
-static void plot_logo_or_black(void *screen, int width, int x, int y, \
- int black);
+static void plot_logo_or_black(void *screen, int x, int y, int black);
-static void logo_plot(void *screen, int width, int x, int y)
+static void logo_plot(void *screen, int x, int y)
{
- plot_logo_or_black(screen, width, x, y, 0);
+ plot_logo_or_black(screen, x, y, 0);
}
static void logo_black(void)
{
- plot_logo_or_black(video_fb_address, \
- VIDEO_COLS, \
- video_logo_xpos, \
- video_logo_ypos, \
+ plot_logo_or_black(video_fb_address, video_logo_xpos, video_logo_ypos,
1);
}
@@ -1858,11 +1856,11 @@ U_BOOT_CMD(
" "
);
-static void plot_logo_or_black(void *screen, int width, int x, int y, int black)
+static void plot_logo_or_black(void *screen, int x, int y, int black)
{
int xcount, i;
- int skip = (width - VIDEO_LOGO_WIDTH) * VIDEO_PIXEL_SIZE;
+ int skip = VIDEO_LINE_LEN - VIDEO_LOGO_WIDTH * VIDEO_PIXEL_SIZE;
int ycount = video_logo_height;
unsigned char r, g, b, *logo_red, *logo_blue, *logo_green;
unsigned char *source;
@@ -1880,7 +1878,7 @@ static void plot_logo_or_black(void *screen, int width, int x, int y, int black)
y = max(0, (int)(VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT + y + 1));
#endif /* CONFIG_SPLASH_SCREEN_ALIGN */
- dest = (unsigned char *)screen + (y * width + x) * VIDEO_PIXEL_SIZE;
+ dest = (unsigned char *)screen + y * VIDEO_LINE_LEN + x * VIDEO_PIXEL_SIZE;
#ifdef CONFIG_VIDEO_BMP_LOGO
source = bmp_logo_bitmap;
@@ -2009,8 +2007,7 @@ static void *video_logo(void)
}
#endif /* CONFIG_SPLASH_SCREEN */
- logo_plot(video_fb_address, VIDEO_COLS,
- video_logo_xpos, video_logo_ypos);
+ logo_plot(video_fb_address, video_logo_xpos, video_logo_ypos);
#ifdef CONFIG_SPLASH_SCREEN_ALIGN
/*
@@ -2250,16 +2247,17 @@ __weak int board_video_skip(void)
int drv_video_init(void)
{
- int skip_dev_init;
struct stdio_dev console_dev;
bool have_keyboard;
+ bool __maybe_unused keyboard_ok = false;
/* Check if video initialization should be skipped */
if (board_video_skip())
return 0;
/* Init video chip - returns with framebuffer cleared */
- skip_dev_init = (video_init() == -1);
+ if (video_init() == -1)
+ return 0;
if (board_cfb_skip())
return 0;
@@ -2275,11 +2273,9 @@ int drv_video_init(void)
if (have_keyboard) {
debug("KBD: Keyboard init ...\n");
#if !defined(CONFIG_VGA_AS_SINGLE_DEVICE)
- skip_dev_init |= (VIDEO_KBD_INIT_FCT == -1);
+ keyboard_ok = !(VIDEO_KBD_INIT_FCT == -1);
#endif
}
- if (skip_dev_init)
- return 0;
/* Init vga device */
memset(&console_dev, 0, sizeof(console_dev));
@@ -2290,7 +2286,7 @@ int drv_video_init(void)
console_dev.puts = video_puts; /* 'puts' function */
#if !defined(CONFIG_VGA_AS_SINGLE_DEVICE)
- if (have_keyboard) {
+ if (have_keyboard && keyboard_ok) {
/* Also init console device */
console_dev.flags |= DEV_FLAGS_INPUT;
console_dev.tstc = VIDEO_TSTC_FCT; /* 'tstc' function */
diff --git a/drivers/video/coreboot_fb.c b/drivers/video/coreboot_fb.c
index 56c35c18fe..4790ef1fdc 100644
--- a/drivers/video/coreboot_fb.c
+++ b/drivers/video/coreboot_fb.c
@@ -9,6 +9,7 @@
#include <common.h>
#include <asm/arch/tables.h>
#include <asm/arch/sysinfo.h>
+#include <vbe.h>
#include <video_fb.h>
#include "videomodes.h"
@@ -17,6 +18,26 @@
*/
GraphicDevice ctfb;
+static void save_vesa_mode(void)
+{
+ struct vesa_mode_info *vesa = &mode_info.vesa;
+ struct cb_framebuffer *fb = lib_sysinfo.framebuffer;
+
+ vesa->x_resolution = fb->x_resolution;
+ vesa->y_resolution = fb->y_resolution;
+ vesa->bits_per_pixel = fb->bits_per_pixel;
+ vesa->bytes_per_scanline = fb->bytes_per_line;
+ vesa->phys_base_ptr = fb->physical_address;
+ vesa->red_mask_size = fb->red_mask_size;
+ vesa->red_mask_pos = fb->red_mask_pos;
+ vesa->green_mask_size = fb->green_mask_size;
+ vesa->green_mask_pos = fb->green_mask_pos;
+ vesa->blue_mask_size = fb->blue_mask_size;
+ vesa->blue_mask_pos = fb->blue_mask_pos;
+ vesa->reserved_mask_size = fb->reserved_mask_size;
+ vesa->reserved_mask_pos = fb->reserved_mask_pos;
+}
+
static int parse_coreboot_table_fb(GraphicDevice *gdev)
{
struct cb_framebuffer *fb = lib_sysinfo.framebuffer;
@@ -81,5 +102,8 @@ void *video_hw_init(void)
memset((void *)gdev->pciBase, 0,
gdev->winSizeX * gdev->winSizeY * gdev->gdfBytesPP);
+ /* Initialize vesa_mode_info structure */
+ save_vesa_mode();
+
return (void *)gdev;
}
diff --git a/drivers/video/ct69000.c b/drivers/video/ct69000.c
index 168b9bad98..22b34418e5 100644
--- a/drivers/video/ct69000.c
+++ b/drivers/video/ct69000.c
@@ -256,9 +256,6 @@ struct ctfb_chips_properties {
static const struct ctfb_chips_properties chips[] = {
{PCI_DEVICE_ID_CT_69000, 0x200000, 1, 4, -2, 3, 257, 100, 220},
-#ifdef CONFIG_USE_CPCIDVI
- {PCI_DEVICE_ID_CT_69030, 0x400000, 1, 4, -2, 3, 257, 100, 220},
-#endif
{PCI_DEVICE_ID_CT_65555, 0x100000, 16, 4, 0, 1, 255, 48, 220}, /* NOT TESTED */
{0, 0, 0, 0, 0, 0, 0, 0, 0} /* Terminator */
};
@@ -944,9 +941,6 @@ SetDrawingEngine (int bits_per_pixel)
*/
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69000},
-#ifdef CONFIG_USE_CPCIDVI
- {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030},
-#endif
{}
};
@@ -1111,22 +1105,7 @@ video_hw_init (void)
pGD->cprBase = pci_mem_base; /* Dummy */
/* set up Hardware */
-#ifdef CONFIG_USE_CPCIDVI
- if (device_id == PCI_DEVICE_ID_CT_69030) {
- ctWrite (CT_MSR_W_O, 0x0b);
- ctWrite (0x3cd, 0x13);
- ctWrite_i (CT_FP_O, 0x02, 0x00);
- ctWrite_i (CT_FP_O, 0x05, 0x00);
- ctWrite_i (CT_FP_O, 0x06, 0x00);
- ctWrite (0x3c2, 0x0b);
- ctWrite_i (CT_FP_O, 0x02, 0x10);
- ctWrite_i (CT_FP_O, 0x01, 0x09);
- } else {
- ctWrite (CT_MSR_W_O, 0x01);
- }
-#else
ctWrite (CT_MSR_W_O, 0x01);
-#endif
/* set the extended Registers */
ctLoadRegs (CT_XR_O, xreg);
diff --git a/drivers/video/exynos_dp.c b/drivers/video/exynos_dp.c
index f60b060ec1..5b6fc140e0 100644
--- a/drivers/video/exynos_dp.c
+++ b/drivers/video/exynos_dp.c
@@ -22,8 +22,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static struct exynos_dp_platform_data *dp_pd;
-
void __exynos_set_dp_phy(unsigned int onoff)
{
}
@@ -851,7 +849,6 @@ static unsigned int exynos_dp_config_video(struct edp_device_info *edp_info)
return ret;
}
-#ifdef CONFIG_OF_CONTROL
int exynos_dp_parse_dt(const void *blob, struct edp_device_info *edp_info)
{
unsigned int node = fdtdec_next_compatible(blob, 0,
@@ -905,7 +902,6 @@ int exynos_dp_parse_dt(const void *blob, struct edp_device_info *edp_info)
"samsung,color-depth", 0);
return 0;
}
-#endif
unsigned int exynos_init_dp(void)
{
@@ -918,16 +914,8 @@ unsigned int exynos_init_dp(void)
return -EFAULT;
}
-#ifdef CONFIG_OF_CONTROL
if (exynos_dp_parse_dt(gd->fdt_blob, edp_info))
debug("unable to parse DP DT node\n");
-#else
- edp_info = dp_pd->edp_dev_info;
- if (edp_info == NULL) {
- debug("failed to get edp_info data.\n");
- return -EFAULT;
- }
-#endif
exynos_dp_set_base_addr();
@@ -967,17 +955,7 @@ unsigned int exynos_init_dp(void)
return ret;
}
- printf("Exynos DP init done\n");
+ debug("Exynos DP init done\n");
return ret;
}
-
-void exynos_set_dp_platform_data(struct exynos_dp_platform_data *pd)
-{
- if (pd == NULL) {
- debug("pd is NULL\n");
- return;
- }
-
- dp_pd = pd;
-}
diff --git a/drivers/video/exynos_dp_lowlevel.c b/drivers/video/exynos_dp_lowlevel.c
index bf0ea108e8..e9b461a99a 100644
--- a/drivers/video/exynos_dp_lowlevel.c
+++ b/drivers/video/exynos_dp_lowlevel.c
@@ -22,7 +22,7 @@ struct exynos_dp *dp_regs;
void exynos_dp_set_base_addr(void)
{
-#ifdef CONFIG_OF_CONTROL
+#if CONFIG_IS_ENABLED(OF_CONTROL)
unsigned int node = fdtdec_next_compatible(gd->fdt_blob,
0, COMPAT_SAMSUNG_EXYNOS5_DP);
if (node <= 0)
@@ -823,7 +823,7 @@ int exynos_dp_read_bytes_from_i2c(unsigned int device_addr,
reg = readl(&dp_regs->aux_rx_comm);
if (reg == AUX_RX_COMM_AUX_DEFER ||
reg == AUX_RX_COMM_I2C_DEFER) {
- printf("DP Defer: %d\n\n", reg);
+ printf("DP Defer: %d\n", reg);
defer = 1;
}
}
diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c
index 8f3b8263da..69edc3a3a4 100644
--- a/drivers/video/exynos_fb.c
+++ b/drivers/video/exynos_fb.c
@@ -28,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR;
static unsigned int panel_width, panel_height;
-#ifdef CONFIG_OF_CONTROL
+#if CONFIG_IS_ENABLED(OF_CONTROL)
vidinfo_t panel_info = {
/*
* Insert a value here so that we don't end up in the BSS
@@ -126,7 +126,7 @@ static void lcd_panel_on(vidinfo_t *vid)
exynos_backlight_on(1);
-#ifdef CONFIG_OF_CONTROL
+#if CONFIG_IS_ENABLED(OF_CONTROL)
node = fdtdec_next_compatible(gd->fdt_blob, 0,
COMPAT_SAMSUNG_EXYNOS_FIMD);
if (node <= 0) {
@@ -150,7 +150,7 @@ static void lcd_panel_on(vidinfo_t *vid)
exynos_mipi_dsi_init();
}
-#ifdef CONFIG_OF_CONTROL
+#if CONFIG_IS_ENABLED(OF_CONTROL)
int exynos_lcd_early_init(const void *blob)
{
unsigned int node;
@@ -295,7 +295,7 @@ void lcd_ctrl_init(void *lcdbase)
set_system_display_ctrl();
set_lcd_clk();
-#ifdef CONFIG_OF_CONTROL
+#if CONFIG_IS_ENABLED(OF_CONTROL)
#ifdef CONFIG_EXYNOS_MIPI_DSIM
exynos_init_dsim_platform_data(&panel_info);
#endif
diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c
index f67fa817ed..ac001a801e 100644
--- a/drivers/video/exynos_fimd.c
+++ b/drivers/video/exynos_fimd.c
@@ -251,7 +251,7 @@ void exynos_fimd_window_off(unsigned int win_id)
writel(cfg, &fimd_ctrl->winshmap);
}
-#ifdef CONFIG_OF_CONTROL
+#if CONFIG_IS_ENABLED(OF_CONTROL)
/*
* The reset value for FIMD SYSMMU register MMU_CTRL is 3
* on Exynos5420 and newer versions.
@@ -295,7 +295,7 @@ void exynos_fimd_lcd_init(vidinfo_t *vid)
{
unsigned int cfg = 0, rgb_mode;
unsigned int offset;
-#ifdef CONFIG_OF_CONTROL
+#if CONFIG_IS_ENABLED(OF_CONTROL)
unsigned int node;
node = fdtdec_next_compatible(gd->fdt_blob,
diff --git a/drivers/video/exynos_mipi_dsi.c b/drivers/video/exynos_mipi_dsi.c
index c68ebd6f7b..b597accf3d 100644
--- a/drivers/video/exynos_mipi_dsi.c
+++ b/drivers/video/exynos_mipi_dsi.c
@@ -28,7 +28,7 @@
DECLARE_GLOBAL_DATA_PTR;
static struct exynos_platform_mipi_dsim *dsim_pd;
-#ifdef CONFIG_OF_CONTROL
+#if CONFIG_IS_ENABLED(OF_CONTROL)
static struct mipi_dsim_config dsim_config_dt;
static struct exynos_platform_mipi_dsim dsim_platform_data_dt;
static struct mipi_dsim_lcd_device mipi_lcd_device_dt;
@@ -249,7 +249,7 @@ void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd)
dsim_pd = pd;
}
-#ifdef CONFIG_OF_CONTROL
+#if CONFIG_IS_ENABLED(OF_CONTROL)
int exynos_dsim_config_parse_dt(const void *blob)
{
int node;
diff --git a/drivers/video/parade.c b/drivers/video/parade.c
deleted file mode 100644
index ae5097160f..0000000000
--- a/drivers/video/parade.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * This file is a driver for Parade dP<->LVDS bridges. The original submission
- * is for the ps8625 chip.
- */
-#include <config.h>
-#include <common.h>
-#include <i2c.h>
-#include <fdtdec.h>
-#include <asm/gpio.h>
-
-/*
- * Initialization of the chip is a process of writing certaing values into
- * certain registers over i2c bus. The chip in fact responds to a range of
- * addresses on the i2c bus, so for each written value three parameters are
- * required: i2c address, register address and the actual value.
- *
- * The base address is derived from the device tree, only address offset is
- * stored in the table below.
- */
-/**
- * struct reg_data() - data for a parade register write
- *
- * @addr_off offset from the i2c base address for parade
- * @reg_addr register address to write
- * @value value to be written
- */
-struct reg_data {
- uint8_t addr_off;
- uint8_t reg;
- uint8_t value;
-} _packed;
-
-#define END_OF_TABLE 0xff /* Ficticious offset */
-
-static const struct reg_data parade_values[] = {
- {0x02, 0xa1, 0x01}, /* HPD low */
- /*
- * SW setting
- * [1:0] SW output 1.2V voltage is lower to 96%
- */
- {0x04, 0x14, 0x01},
- /*
- * RCO SS setting
- * [5:4] = b01 0.5%, b10 1%, b11 1.5%
- */
- {0x04, 0xe3, 0x20},
- {0x04, 0xe2, 0x80}, /* [7] RCO SS enable */
- /*
- * RPHY Setting
- * [3:2] CDR tune wait cycle before
- * measure for fine tune b00: 1us,
- * 01: 0.5us, 10:2us, 11:4us.
- */
- {0x04, 0x8a, 0x0c},
- {0x04, 0x89, 0x08}, /* [3] RFD always on */
- /*
- * CTN lock in/out:
- * 20000ppm/80000ppm. Lock out 2
- * times.
- */
- {0x04, 0x71, 0x2d},
- /*
- * 2.7G CDR settings
- * NOF=40LSB for HBR CDR setting
- */
- {0x04, 0x7d, 0x07},
- {0x04, 0x7b, 0x00}, /* [1:0] Fmin=+4bands */
- {0x04, 0x7a, 0xfd}, /* [7:5] DCO_FTRNG=+-40% */
- /*
- * 1.62G CDR settings
- * [5:2]NOF=64LSB [1:0]DCO scale is 2/5
- */
- {0x04, 0xc0, 0x12},
- {0x04, 0xc1, 0x92}, /* Gitune=-37% */
- {0x04, 0xc2, 0x1c}, /* Fbstep=100% */
- {0x04, 0x32, 0x80}, /* [7] LOS signal disable */
- /*
- * RPIO Setting
- * [7:4] LVDS driver bias current :
- * 75% (250mV swing)
- */
- {0x04, 0x00, 0xb0},
- /*
- * [7:6] Right-bar GPIO output strength is 8mA
- */
- {0x04, 0x15, 0x40},
- /* EQ Training State Machine Setting */
- {0x04, 0x54, 0x10}, /* RCO calibration start */
- /* [4:0] MAX_LANE_COUNT set to one lane */
- {0x01, 0x02, 0x81},
- /* [4:0] LANE_COUNT_SET set to one lane */
- {0x01, 0x21, 0x81},
- {0x00, 0x52, 0x20},
- {0x00, 0xf1, 0x03}, /* HPD CP toggle enable */
- {0x00, 0x62, 0x41},
- /* Counter number, add 1ms counter delay */
- {0x00, 0xf6, 0x01},
- /*
- * [6]PWM function control by
- * DPCD0040f[7], default is PWM
- * block always works.
- */
- {0x00, 0x77, 0x06},
- /*
- * 04h Adjust VTotal tolerance to
- * fix the 30Hz no display issue
- */
- {0x00, 0x4c, 0x04},
- /* DPCD00400='h00, Parade OUI = 'h001cf8 */
- {0x01, 0xc0, 0x00},
- {0x01, 0xc1, 0x1c}, /* DPCD00401='h1c */
- {0x01, 0xc2, 0xf8}, /* DPCD00402='hf8 */
- /*
- * DPCD403~408 = ASCII code
- * D2SLV5='h4432534c5635
- */
- {0x01, 0xc3, 0x44},
- {0x01, 0xc4, 0x32}, /* DPCD404 */
- {0x01, 0xc5, 0x53}, /* DPCD405 */
- {0x01, 0xc6, 0x4c}, /* DPCD406 */
- {0x01, 0xc7, 0x56}, /* DPCD407 */
- {0x01, 0xc8, 0x35}, /* DPCD408 */
- /*
- * DPCD40A, Initial Code major revision
- * '01'
- */
- {0x01, 0xca, 0x01},
- /* DPCD40B, Initial Code minor revision '05' */
- {0x01, 0xcb, 0x05},
- /* DPCD720, Select internal PWM */
- {0x01, 0xa5, 0xa0},
- /*
- * FFh for 100% PWM of brightness, 0h for 0%
- * brightness
- */
- {0x01, 0xa7, 0xff},
- /*
- * Set LVDS output as 6bit-VESA mapping,
- * single LVDS channel
- */
- {0x01, 0xcc, 0x13},
- /* Enable SSC set by register */
- {0x02, 0xb1, 0x20},
- /*
- * Set SSC enabled and +/-1% central
- * spreading
- */
- {0x04, 0x10, 0x16},
- /* MPU Clock source: LC => RCO */
- {0x04, 0x59, 0x60},
- {0x04, 0x54, 0x14}, /* LC -> RCO */
- {0x02, 0xa1, 0x91}, /* HPD high */
- {END_OF_TABLE}
-};
-
-/**
- * Write values table into the Parade eDP bridge
- *
- * @return 0 on success, non-0 on failure
- */
-
-static int parade_write_regs(int base_addr, const struct reg_data *table)
-{
- int ret = 0;
-
- while (!ret && (table->addr_off != END_OF_TABLE)) {
- ret = i2c_write(base_addr + table->addr_off,
- table->reg, 1,
- (uint8_t *)&table->value,
- sizeof(table->value));
- table++;
- }
- return ret;
-}
-
-int parade_init(const void *blob)
-{
- struct gpio_desc rst_gpio;
- struct gpio_desc slp_gpio;
- int bus, old_bus;
- int parent;
- int node;
- int addr;
- int ret;
-
- node = fdtdec_next_compatible(blob, 0, COMPAT_PARADE_PS8625);
- if (node < 0)
- return 0;
-
- parent = fdt_parent_offset(blob, node);
- if (parent < 0) {
- debug("%s: Could not find parent i2c node\n", __func__);
- return -1;
- }
- addr = fdtdec_get_int(blob, node, "reg", -1);
- if (addr < 0) {
- debug("%s: Could not find i2c address\n", __func__);
- return -1;
- }
-
- gpio_request_by_name_nodev(blob, node, "sleep-gpio", 0, &slp_gpio,
- GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
-
- mdelay(10);
-
- gpio_request_by_name_nodev(blob, node, "reset-gpio", 0, &rst_gpio,
- GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
-
- bus = i2c_get_bus_num_fdt(parent);
- old_bus = i2c_get_bus_num();
-
- debug("%s: Using i2c bus %d\n", __func__, bus);
-
- /*
- * TODO(sjg@chromium.org): Hmmm we seem to need some sort of delay
- * here.
- */
- mdelay(40);
- i2c_set_bus_num(bus);
- ret = parade_write_regs(addr, parade_values);
-
- i2c_set_bus_num(old_bus);
-
- return ret;
-}
diff --git a/drivers/video/pxa_lcd.c b/drivers/video/pxa_lcd.c
index 64cef37bc9..2799425a63 100644
--- a/drivers/video/pxa_lcd.c
+++ b/drivers/video/pxa_lcd.c
@@ -11,14 +11,13 @@
/* ** HEADER FILES */
/************************************************************************/
-#include <config.h>
#include <common.h>
-#include <stdarg.h>
-#include <linux/types.h>
-#include <stdio_dev.h>
-#include <lcd.h>
#include <asm/arch/pxa-regs.h>
#include <asm/io.h>
+#include <lcd.h>
+#include <linux/types.h>
+#include <stdarg.h>
+#include <stdio_dev.h>
/* #define DEBUG */
diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c
index 269083b666..fc1aea3f06 100644
--- a/drivers/video/sunxi_display.c
+++ b/drivers/video/sunxi_display.c
@@ -2,7 +2,7 @@
* Display driver for Allwinner SoCs.
*
* (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
- * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -15,12 +15,15 @@
#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
+#include <axp221.h>
#include <errno.h>
#include <fdtdec.h>
#include <fdt_support.h>
#include <i2c.h>
+#include <malloc.h>
#include <video_fb.h>
#include "videomodes.h"
+#include "anx9804.h"
#include "hitachi_tx18d42vm_lcd.h"
#include "ssd2828.h"
@@ -40,16 +43,27 @@ enum sunxi_monitor {
sunxi_monitor_hdmi,
sunxi_monitor_lcd,
sunxi_monitor_vga,
+ sunxi_monitor_composite_pal,
+ sunxi_monitor_composite_ntsc,
+ sunxi_monitor_composite_pal_m,
+ sunxi_monitor_composite_pal_nc,
};
-#define SUNXI_MONITOR_LAST sunxi_monitor_vga
+#define SUNXI_MONITOR_LAST sunxi_monitor_composite_pal_nc
struct sunxi_display {
GraphicDevice graphic_device;
enum sunxi_monitor monitor;
unsigned int depth;
+ unsigned int fb_addr;
unsigned int fb_size;
} sunxi_display;
+const struct ctfb_res_modes composite_video_modes[2] = {
+ /* x y hz pixclk ps/kHz le ri up lo hs vs s vmode */
+ { 720, 576, 50, 37037, 27000, 137, 5, 20, 27, 2, 2, 0, FB_VMODE_INTERLACED },
+ { 720, 480, 60, 37037, 27000, 116, 20, 16, 27, 2, 2, 0, FB_VMODE_INTERLACED },
+};
+
#ifdef CONFIG_VIDEO_HDMI
/*
@@ -390,6 +404,25 @@ static void sunxi_frontend_mode_set(const struct ctfb_res_modes *mode,
static void sunxi_frontend_enable(void) {}
#endif
+static bool sunxi_is_composite(void)
+{
+ switch (sunxi_display.monitor) {
+ case sunxi_monitor_none:
+ case sunxi_monitor_dvi:
+ case sunxi_monitor_hdmi:
+ case sunxi_monitor_lcd:
+ case sunxi_monitor_vga:
+ return false;
+ case sunxi_monitor_composite_pal:
+ case sunxi_monitor_composite_ntsc:
+ case sunxi_monitor_composite_pal_m:
+ case sunxi_monitor_composite_pal_nc:
+ return true;
+ }
+
+ return false; /* Never reached */
+}
+
/*
* This is the entity that mixes and matches the different layers and inputs.
* Allwinner calls it the back-end, but i like composer better.
@@ -423,11 +456,18 @@ static void sunxi_composer_init(void)
setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE);
}
+static u32 sunxi_rgb2yuv_coef[12] = {
+ 0x00000107, 0x00000204, 0x00000064, 0x00000108,
+ 0x00003f69, 0x00003ed6, 0x000001c1, 0x00000808,
+ 0x000001c1, 0x00003e88, 0x00003fb8, 0x00000808
+};
+
static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode,
unsigned int address)
{
struct sunxi_de_be_reg * const de_be =
(struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
+ int i;
sunxi_frontend_mode_set(mode, address);
@@ -445,6 +485,20 @@ static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode,
writel(SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888, &de_be->layer0_attr1_ctrl);
setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE);
+ if (mode->vmode == FB_VMODE_INTERLACED)
+ setbits_le32(&de_be->mode,
+#ifndef CONFIG_MACH_SUN5I
+ SUNXI_DE_BE_MODE_DEFLICKER_ENABLE |
+#endif
+ SUNXI_DE_BE_MODE_INTERLACE_ENABLE);
+
+ if (sunxi_is_composite()) {
+ writel(SUNXI_DE_BE_OUTPUT_COLOR_CTRL_ENABLE,
+ &de_be->output_color_ctrl);
+ for (i = 0; i < 12; i++)
+ writel(sunxi_rgb2yuv_coef[i],
+ &de_be->output_color_coef[i]);
+ }
}
static void sunxi_composer_enable(void)
@@ -469,6 +523,7 @@ static void sunxi_lcdc_pll_set(int tcon, int dotclock,
int value, n, m, min_m, max_m, diff;
int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
int best_double = 0;
+ bool use_mipi_pll = false;
if (tcon == 0) {
#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
@@ -519,22 +574,51 @@ static void sunxi_lcdc_pll_set(int tcon, int dotclock,
}
}
- debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n",
- dotclock, (best_double + 1) * 3000 * best_n / best_m,
- best_double + 1, best_n, best_m);
+#ifdef CONFIG_MACH_SUN6I
+ /*
+ * Use the MIPI pll if we've been unable to find any matching setting
+ * for PLL3, this happens with high dotclocks because of min_m = 6.
+ */
+ if (tcon == 0 && best_n == 0) {
+ use_mipi_pll = true;
+ best_m = 6; /* Minimum m for tcon0 */
+ }
- clock_set_pll3(best_n * 3000000);
+ if (use_mipi_pll) {
+ clock_set_pll3(297000000); /* Fix the video pll at 297 MHz */
+ clock_set_mipi_pll(best_m * dotclock * 1000);
+ debug("dotclock: %dkHz = %dkHz via mipi pll\n",
+ dotclock, clock_get_mipi_pll() / best_m / 1000);
+ } else
+#endif
+ {
+ clock_set_pll3(best_n * 3000000);
+ debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n",
+ dotclock,
+ (best_double + 1) * clock_get_pll3() / best_m / 1000,
+ best_double + 1, best_n, best_m);
+ }
if (tcon == 0) {
- writel(CCM_LCD_CH0_CTRL_GATE | CCM_LCD_CH0_CTRL_RST |
- (best_double ? CCM_LCD_CH0_CTRL_PLL3_2X :
- CCM_LCD_CH0_CTRL_PLL3),
+ u32 pll;
+
+ if (use_mipi_pll)
+ pll = CCM_LCD_CH0_CTRL_MIPI_PLL;
+ else if (best_double)
+ pll = CCM_LCD_CH0_CTRL_PLL3_2X;
+ else
+ pll = CCM_LCD_CH0_CTRL_PLL3;
+
+ writel(CCM_LCD_CH0_CTRL_GATE | CCM_LCD_CH0_CTRL_RST | pll,
&ccm->lcd0_ch0_clk_cfg);
} else {
writel(CCM_LCD_CH1_CTRL_GATE |
(best_double ? CCM_LCD_CH1_CTRL_PLL3_2X :
CCM_LCD_CH1_CTRL_PLL3) |
CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
+ if (sunxi_is_composite())
+ setbits_le32(&ccm->lcd0_ch1_clk_cfg,
+ CCM_LCD_CH1_CTRL_HALF_SCLK1);
}
*clk_div = best_m;
@@ -663,11 +747,16 @@ static void sunxi_lcdc_backlight_enable(void)
gpio_direction_output(pin, PWM_ON);
}
-static int sunxi_lcdc_get_clk_delay(const struct ctfb_res_modes *mode)
+static int sunxi_lcdc_get_clk_delay(const struct ctfb_res_modes *mode, int tcon)
{
int delay;
- delay = mode->lower_margin + mode->vsync_len + mode->upper_margin - 2;
+ delay = mode->lower_margin + mode->vsync_len + mode->upper_margin;
+ if (mode->vmode == FB_VMODE_INTERLACED)
+ delay /= 2;
+ if (tcon == 1)
+ delay -= 2;
+
return (delay > 30) ? 30 : delay;
}
@@ -678,13 +767,17 @@ static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
int bp, clk_delay, clk_div, clk_double, pin, total, val;
- for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++)
+ for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++) {
#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0);
#endif
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LVDS0);
#endif
+#ifdef CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
+ sunxi_gpio_set_drv(pin, 3);
+#endif
+ }
sunxi_lcdc_pll_set(0, mode->pixclock_khz, &clk_div, &clk_double);
@@ -692,7 +785,7 @@ static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
SUNXI_LCDC_CTRL_IO_MAP_TCON0);
- clk_delay = sunxi_lcdc_get_clk_delay(mode);
+ clk_delay = sunxi_lcdc_get_clk_delay(mode, 0);
writel(SUNXI_LCDC_TCON0_CTRL_ENABLE |
SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon0_ctrl);
@@ -757,28 +850,33 @@ static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
writel(0, &lcdc->tcon0_io_tristate);
}
-#if defined CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA
+#if defined CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE
static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
int *clk_div, int *clk_double,
bool use_portd_hvsync)
{
struct sunxi_lcdc_reg * const lcdc =
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
- int bp, clk_delay, total, val;
+ int bp, clk_delay, total, val, yres;
/* Use tcon1 */
clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
SUNXI_LCDC_CTRL_IO_MAP_TCON1);
- clk_delay = sunxi_lcdc_get_clk_delay(mode);
+ clk_delay = sunxi_lcdc_get_clk_delay(mode, 1);
writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
+ ((mode->vmode == FB_VMODE_INTERLACED) ?
+ SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE : 0) |
SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon1_ctrl);
- writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
+ yres = mode->yres;
+ if (mode->vmode == FB_VMODE_INTERLACED)
+ yres /= 2;
+ writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres),
&lcdc->tcon1_timing_source);
- writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
+ writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres),
&lcdc->tcon1_timing_scale);
- writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
+ writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres),
&lcdc->tcon1_timing_out);
bp = mode->hsync_len + mode->left_margin;
@@ -788,6 +886,8 @@ static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
bp = mode->vsync_len + mode->upper_margin;
total = mode->yres + mode->lower_margin + bp;
+ if (mode->vmode == FB_VMODE_NONINTERLACED)
+ total *= 2;
writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
@@ -809,9 +909,16 @@ static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
SUNXI_LCDC_TCON_VSYNC_MASK |
SUNXI_LCDC_TCON_HSYNC_MASK);
}
+
+#ifdef CONFIG_MACH_SUN5I
+ if (sunxi_is_composite())
+ clrsetbits_le32(&lcdc->mux_ctrl, SUNXI_LCDC_MUX_CTRL_SRC0_MASK,
+ SUNXI_LCDC_MUX_CTRL_SRC0(1));
+#endif
+
sunxi_lcdc_pll_set(1, mode->pixclock_khz, clk_div, clk_double);
}
-#endif /* CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA */
+#endif /* CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA || CONFIG_VIDEO_COMPOSITE */
#ifdef CONFIG_VIDEO_HDMI
@@ -925,28 +1032,89 @@ static void sunxi_hdmi_enable(void)
#endif /* CONFIG_VIDEO_HDMI */
-#ifdef CONFIG_VIDEO_VGA
+#if defined CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE
-static void sunxi_vga_mode_set(void)
+static void sunxi_tvencoder_mode_set(void)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct sunxi_tve_reg * const tve =
(struct sunxi_tve_reg *)SUNXI_TVE0_BASE;
+ /* Reset off */
+ setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_TVE_RST);
/* Clock on */
setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_TVE0);
- /* Set TVE in VGA mode */
- writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) |
- SUNXI_TVE_GCTRL_DAC_INPUT(1, 2) |
- SUNXI_TVE_GCTRL_DAC_INPUT(2, 3), &tve->gctrl);
- writel(SUNXI_TVE_GCTRL_CFG0_VGA, &tve->cfg0);
- writel(SUNXI_TVE_GCTRL_DAC_CFG0_VGA, &tve->dac_cfg0);
- writel(SUNXI_TVE_GCTRL_UNKNOWN1_VGA, &tve->unknown1);
+ switch (sunxi_display.monitor) {
+ case sunxi_monitor_vga:
+ writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) |
+ SUNXI_TVE_GCTRL_DAC_INPUT(1, 2) |
+ SUNXI_TVE_GCTRL_DAC_INPUT(2, 3), &tve->gctrl);
+ writel(SUNXI_TVE_CFG0_VGA, &tve->cfg0);
+ writel(SUNXI_TVE_DAC_CFG0_VGA, &tve->dac_cfg0);
+ writel(SUNXI_TVE_UNKNOWN1_VGA, &tve->unknown1);
+ break;
+ case sunxi_monitor_composite_pal_nc:
+ writel(SUNXI_TVE_CHROMA_FREQ_PAL_NC, &tve->chroma_freq);
+ /* Fall through */
+ case sunxi_monitor_composite_pal:
+ writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) |
+ SUNXI_TVE_GCTRL_DAC_INPUT(1, 2) |
+ SUNXI_TVE_GCTRL_DAC_INPUT(2, 3) |
+ SUNXI_TVE_GCTRL_DAC_INPUT(3, 4), &tve->gctrl);
+ writel(SUNXI_TVE_CFG0_PAL, &tve->cfg0);
+ writel(SUNXI_TVE_DAC_CFG0_COMPOSITE, &tve->dac_cfg0);
+ writel(SUNXI_TVE_FILTER_COMPOSITE, &tve->filter);
+ writel(SUNXI_TVE_PORCH_NUM_PAL, &tve->porch_num);
+ writel(SUNXI_TVE_LINE_NUM_PAL, &tve->line_num);
+ writel(SUNXI_TVE_BLANK_BLACK_LEVEL_PAL, &tve->blank_black_level);
+ writel(SUNXI_TVE_UNKNOWN1_COMPOSITE, &tve->unknown1);
+ writel(SUNXI_TVE_CBR_LEVEL_PAL, &tve->cbr_level);
+ writel(SUNXI_TVE_BURST_WIDTH_COMPOSITE, &tve->burst_width);
+ writel(SUNXI_TVE_UNKNOWN2_PAL, &tve->unknown2);
+ writel(SUNXI_TVE_ACTIVE_NUM_COMPOSITE, &tve->active_num);
+ writel(SUNXI_TVE_CHROMA_BW_GAIN_COMP, &tve->chroma_bw_gain);
+ writel(SUNXI_TVE_NOTCH_WIDTH_COMPOSITE, &tve->notch_width);
+ writel(SUNXI_TVE_RESYNC_NUM_PAL, &tve->resync_num);
+ writel(SUNXI_TVE_SLAVE_PARA_COMPOSITE, &tve->slave_para);
+ break;
+ case sunxi_monitor_composite_pal_m:
+ writel(SUNXI_TVE_CHROMA_FREQ_PAL_M, &tve->chroma_freq);
+ writel(SUNXI_TVE_COLOR_BURST_PAL_M, &tve->color_burst);
+ /* Fall through */
+ case sunxi_monitor_composite_ntsc:
+ writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) |
+ SUNXI_TVE_GCTRL_DAC_INPUT(1, 2) |
+ SUNXI_TVE_GCTRL_DAC_INPUT(2, 3) |
+ SUNXI_TVE_GCTRL_DAC_INPUT(3, 4), &tve->gctrl);
+ writel(SUNXI_TVE_CFG0_NTSC, &tve->cfg0);
+ writel(SUNXI_TVE_DAC_CFG0_COMPOSITE, &tve->dac_cfg0);
+ writel(SUNXI_TVE_FILTER_COMPOSITE, &tve->filter);
+ writel(SUNXI_TVE_PORCH_NUM_NTSC, &tve->porch_num);
+ writel(SUNXI_TVE_LINE_NUM_NTSC, &tve->line_num);
+ writel(SUNXI_TVE_BLANK_BLACK_LEVEL_NTSC, &tve->blank_black_level);
+ writel(SUNXI_TVE_UNKNOWN1_COMPOSITE, &tve->unknown1);
+ writel(SUNXI_TVE_CBR_LEVEL_NTSC, &tve->cbr_level);
+ writel(SUNXI_TVE_BURST_PHASE_NTSC, &tve->burst_phase);
+ writel(SUNXI_TVE_BURST_WIDTH_COMPOSITE, &tve->burst_width);
+ writel(SUNXI_TVE_UNKNOWN2_NTSC, &tve->unknown2);
+ writel(SUNXI_TVE_SYNC_VBI_LEVEL_NTSC, &tve->sync_vbi_level);
+ writel(SUNXI_TVE_ACTIVE_NUM_COMPOSITE, &tve->active_num);
+ writel(SUNXI_TVE_CHROMA_BW_GAIN_COMP, &tve->chroma_bw_gain);
+ writel(SUNXI_TVE_NOTCH_WIDTH_COMPOSITE, &tve->notch_width);
+ writel(SUNXI_TVE_RESYNC_NUM_NTSC, &tve->resync_num);
+ writel(SUNXI_TVE_SLAVE_PARA_COMPOSITE, &tve->slave_para);
+ break;
+ case sunxi_monitor_none:
+ case sunxi_monitor_dvi:
+ case sunxi_monitor_hdmi:
+ case sunxi_monitor_lcd:
+ break;
+ }
}
-static void sunxi_vga_enable(void)
+static void sunxi_tvencoder_enable(void)
{
struct sunxi_tve_reg * const tve =
(struct sunxi_tve_reg *)SUNXI_TVE0_BASE;
@@ -954,7 +1122,7 @@ static void sunxi_vga_enable(void)
setbits_le32(&tve->gctrl, SUNXI_TVE_GCTRL_ENABLE);
}
-#endif /* CONFIG_VIDEO_VGA */
+#endif /* CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE */
static void sunxi_drc_init(void)
{
@@ -1046,6 +1214,17 @@ static void sunxi_mode_set(const struct ctfb_res_modes *mode,
break;
case sunxi_monitor_lcd:
sunxi_lcdc_panel_enable();
+ if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804)) {
+ /*
+ * The anx9804 needs 1.8V from eldo3, we do this here
+ * and not via CONFIG_AXP221_ELDO3 from board_init()
+ * to avoid turning this on when using hdmi output.
+ */
+ axp221_set_eldo(3, 1800);
+ anx9804_init(CONFIG_VIDEO_LCD_I2C_BUS, 4,
+ ANX9804_DATA_RATE_1620M,
+ sunxi_display.depth);
+ }
if (IS_ENABLED(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM)) {
mdelay(50); /* Wait for lcd controller power on */
hitachi_tx18d42vm_init();
@@ -1069,10 +1248,10 @@ static void sunxi_mode_set(const struct ctfb_res_modes *mode,
#ifdef CONFIG_VIDEO_VGA
sunxi_composer_mode_set(mode, address);
sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 1);
- sunxi_vga_mode_set();
+ sunxi_tvencoder_mode_set();
sunxi_composer_enable();
sunxi_lcdc_enable();
- sunxi_vga_enable();
+ sunxi_tvencoder_enable();
#elif defined CONFIG_VIDEO_VGA_VIA_LCD
sunxi_composer_mode_set(mode, address);
sunxi_lcdc_tcon0_mode_set(mode, true);
@@ -1081,17 +1260,34 @@ static void sunxi_mode_set(const struct ctfb_res_modes *mode,
sunxi_vga_external_dac_enable();
#endif
break;
+ case sunxi_monitor_composite_pal:
+ case sunxi_monitor_composite_ntsc:
+ case sunxi_monitor_composite_pal_m:
+ case sunxi_monitor_composite_pal_nc:
+#ifdef CONFIG_VIDEO_COMPOSITE
+ sunxi_composer_mode_set(mode, address);
+ sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 0);
+ sunxi_tvencoder_mode_set();
+ sunxi_composer_enable();
+ sunxi_lcdc_enable();
+ sunxi_tvencoder_enable();
+#endif
+ break;
}
}
static const char *sunxi_get_mon_desc(enum sunxi_monitor monitor)
{
switch (monitor) {
- case sunxi_monitor_none: return "none";
- case sunxi_monitor_dvi: return "dvi";
- case sunxi_monitor_hdmi: return "hdmi";
- case sunxi_monitor_lcd: return "lcd";
- case sunxi_monitor_vga: return "vga";
+ case sunxi_monitor_none: return "none";
+ case sunxi_monitor_dvi: return "dvi";
+ case sunxi_monitor_hdmi: return "hdmi";
+ case sunxi_monitor_lcd: return "lcd";
+ case sunxi_monitor_vga: return "vga";
+ case sunxi_monitor_composite_pal: return "composite-pal";
+ case sunxi_monitor_composite_ntsc: return "composite-ntsc";
+ case sunxi_monitor_composite_pal_m: return "composite-pal-m";
+ case sunxi_monitor_composite_pal_nc: return "composite-pal-nc";
}
return NULL; /* never reached */
}
@@ -1101,6 +1297,54 @@ ulong board_get_usable_ram_top(ulong total_size)
return gd->ram_top - CONFIG_SUNXI_MAX_FB_SIZE;
}
+static bool sunxi_has_hdmi(void)
+{
+#ifdef CONFIG_VIDEO_HDMI
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool sunxi_has_lcd(void)
+{
+ char *lcd_mode = CONFIG_VIDEO_LCD_MODE;
+
+ return lcd_mode[0] != 0;
+}
+
+static bool sunxi_has_vga(void)
+{
+#if defined CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_VGA_VIA_LCD
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool sunxi_has_composite(void)
+{
+#ifdef CONFIG_VIDEO_COMPOSITE
+ return true;
+#else
+ return false;
+#endif
+}
+
+static enum sunxi_monitor sunxi_get_default_mon(bool allow_hdmi)
+{
+ if (allow_hdmi && sunxi_has_hdmi())
+ return sunxi_monitor_dvi;
+ else if (sunxi_has_lcd())
+ return sunxi_monitor_lcd;
+ else if (sunxi_has_vga())
+ return sunxi_monitor_vga;
+ else if (sunxi_has_composite())
+ return sunxi_monitor_composite_pal;
+ else
+ return sunxi_monitor_none;
+}
+
void *video_hw_init(void)
{
static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
@@ -1110,9 +1354,10 @@ void *video_hw_init(void)
#ifdef CONFIG_VIDEO_HDMI
int ret, hpd, hpd_delay, edid;
#endif
+ int i, overscan_offset, overscan_x, overscan_y;
+ unsigned int fb_dma_addr;
char mon[16];
char *lcd_mode = CONFIG_VIDEO_LCD_MODE;
- int i;
memset(&sunxi_display, 0, sizeof(struct sunxi_display));
@@ -1122,12 +1367,10 @@ void *video_hw_init(void)
hpd = video_get_option_int(options, "hpd", 1);
hpd_delay = video_get_option_int(options, "hpd_delay", 500);
edid = video_get_option_int(options, "edid", 1);
- sunxi_display.monitor = sunxi_monitor_dvi;
-#elif defined CONFIG_VIDEO_VGA_VIA_LCD
- sunxi_display.monitor = sunxi_monitor_vga;
-#else
- sunxi_display.monitor = sunxi_monitor_lcd;
#endif
+ overscan_x = video_get_option_int(options, "overscan_x", -1);
+ overscan_y = video_get_option_int(options, "overscan_y", -1);
+ sunxi_display.monitor = sunxi_get_default_mon(true);
video_get_option_string(options, "monitor", mon, sizeof(mon),
sunxi_get_mon_desc(sunxi_display.monitor));
for (i = 0; i <= SUNXI_MONITOR_LAST; i++) {
@@ -1152,16 +1395,7 @@ void *video_hw_init(void)
mode = &custom;
} else if (hpd) {
sunxi_hdmi_shutdown();
- /* Fallback to lcd / vga / none */
- if (lcd_mode[0]) {
- sunxi_display.monitor = sunxi_monitor_lcd;
- } else {
-#if defined CONFIG_VIDEO_VGA_VIA_LCD || defined CONFIG_VIDEO_VGA
- sunxi_display.monitor = sunxi_monitor_vga;
-#else
- sunxi_display.monitor = sunxi_monitor_none;
-#endif
- }
+ sunxi_display.monitor = sunxi_get_default_mon(false);
} /* else continue with hdmi/dvi without a cable connected */
}
#endif
@@ -1171,43 +1405,61 @@ void *video_hw_init(void)
return NULL;
case sunxi_monitor_dvi:
case sunxi_monitor_hdmi:
-#ifdef CONFIG_VIDEO_HDMI
+ if (!sunxi_has_hdmi()) {
+ printf("HDMI/DVI not supported on this board\n");
+ sunxi_display.monitor = sunxi_monitor_none;
+ return NULL;
+ }
break;
-#else
- printf("HDMI/DVI not supported on this board\n");
- sunxi_display.monitor = sunxi_monitor_none;
- return NULL;
-#endif
case sunxi_monitor_lcd:
- if (lcd_mode[0]) {
- sunxi_display.depth = video_get_params(&custom, lcd_mode);
- mode = &custom;
- break;
+ if (!sunxi_has_lcd()) {
+ printf("LCD not supported on this board\n");
+ sunxi_display.monitor = sunxi_monitor_none;
+ return NULL;
}
- printf("LCD not supported on this board\n");
- sunxi_display.monitor = sunxi_monitor_none;
- return NULL;
+ sunxi_display.depth = video_get_params(&custom, lcd_mode);
+ mode = &custom;
+ break;
case sunxi_monitor_vga:
-#if defined CONFIG_VIDEO_VGA_VIA_LCD || defined CONFIG_VIDEO_VGA
+ if (!sunxi_has_vga()) {
+ printf("VGA not supported on this board\n");
+ sunxi_display.monitor = sunxi_monitor_none;
+ return NULL;
+ }
sunxi_display.depth = 18;
break;
-#else
- printf("VGA not supported on this board\n");
- sunxi_display.monitor = sunxi_monitor_none;
- return NULL;
-#endif
+ case sunxi_monitor_composite_pal:
+ case sunxi_monitor_composite_ntsc:
+ case sunxi_monitor_composite_pal_m:
+ case sunxi_monitor_composite_pal_nc:
+ if (!sunxi_has_composite()) {
+ printf("Composite video not supported on this board\n");
+ sunxi_display.monitor = sunxi_monitor_none;
+ return NULL;
+ }
+ if (sunxi_display.monitor == sunxi_monitor_composite_pal ||
+ sunxi_display.monitor == sunxi_monitor_composite_pal_nc)
+ mode = &composite_video_modes[0];
+ else
+ mode = &composite_video_modes[1];
+ sunxi_display.depth = 24;
+ break;
}
- if (mode->vmode != FB_VMODE_NONINTERLACED) {
- printf("Only non-interlaced modes supported, falling back to 1024x768\n");
- mode = &res_mode_init[RES_MODE_1024x768];
- } else {
- printf("Setting up a %dx%d %s console\n", mode->xres,
- mode->yres, sunxi_get_mon_desc(sunxi_display.monitor));
- }
+ /* Yes these defaults are quite high, overscan on composite sucks... */
+ if (overscan_x == -1)
+ overscan_x = sunxi_is_composite() ? 32 : 0;
+ if (overscan_y == -1)
+ overscan_y = sunxi_is_composite() ? 20 : 0;
sunxi_display.fb_size =
(mode->xres * mode->yres * 4 + 0xfff) & ~0xfff;
+ overscan_offset = (overscan_y * mode->xres + overscan_x) * 4;
+ /* We want to keep the fb_base for simplefb page aligned, where as
+ * the sunxi dma engines will happily accept an unaligned address. */
+ if (overscan_offset)
+ sunxi_display.fb_size += 0x1000;
+
if (sunxi_display.fb_size > CONFIG_SUNXI_MAX_FB_SIZE) {
printf("Error need %dkB for fb, but only %dkB is reserved\n",
sunxi_display.fb_size >> 10,
@@ -1215,21 +1467,36 @@ void *video_hw_init(void)
return NULL;
}
+ printf("Setting up a %dx%d%s %s console (overscan %dx%d)\n",
+ mode->xres, mode->yres,
+ (mode->vmode == FB_VMODE_INTERLACED) ? "i" : "",
+ sunxi_get_mon_desc(sunxi_display.monitor),
+ overscan_x, overscan_y);
+
gd->fb_base = gd->bd->bi_dram[0].start +
gd->bd->bi_dram[0].size - sunxi_display.fb_size;
sunxi_engines_init();
- sunxi_mode_set(mode, gd->fb_base - CONFIG_SYS_SDRAM_BASE);
+
+ fb_dma_addr = gd->fb_base - CONFIG_SYS_SDRAM_BASE;
+ sunxi_display.fb_addr = gd->fb_base;
+ if (overscan_offset) {
+ fb_dma_addr += 0x1000 - (overscan_offset & 0xfff);
+ sunxi_display.fb_addr += (overscan_offset + 0xfff) & ~0xfff;
+ memset((void *)gd->fb_base, 0, sunxi_display.fb_size);
+ flush_cache(gd->fb_base, sunxi_display.fb_size);
+ }
+ sunxi_mode_set(mode, fb_dma_addr);
/*
* These are the only members of this structure that are used. All the
- * others are driver specific. There is nothing to decribe pitch or
- * stride, but we are lucky with our hw.
+ * others are driver specific. The pitch is stored in plnSizeX.
*/
- graphic_device->frameAdrs = gd->fb_base;
+ graphic_device->frameAdrs = sunxi_display.fb_addr;
graphic_device->gdfIndex = GDF_32BIT_X888RGB;
graphic_device->gdfBytesPP = 4;
- graphic_device->winSizeX = mode->xres;
- graphic_device->winSizeY = mode->yres;
+ graphic_device->winSizeX = mode->xres - 2 * overscan_x;
+ graphic_device->winSizeY = mode->yres - 2 * overscan_y;
+ graphic_device->plnSizeX = mode->xres * graphic_device->gdfBytesPP;
return graphic_device;
}
@@ -1268,6 +1535,12 @@ int sunxi_simplefb_setup(void *blob)
pipeline = PIPELINE_PREFIX "de_be0-lcd0";
#endif
break;
+ case sunxi_monitor_composite_pal:
+ case sunxi_monitor_composite_ntsc:
+ case sunxi_monitor_composite_pal_m:
+ case sunxi_monitor_composite_pal_nc:
+ pipeline = PIPELINE_PREFIX "de_be0-lcd0-tve0";
+ break;
}
/* Find a prefilled simpefb node, matching out pipeline config */
@@ -1300,10 +1573,9 @@ int sunxi_simplefb_setup(void *blob)
return ret;
}
- ret = fdt_setup_simplefb_node(blob, offset, gd->fb_base,
+ ret = fdt_setup_simplefb_node(blob, offset, sunxi_display.fb_addr,
graphic_device->winSizeX, graphic_device->winSizeY,
- graphic_device->winSizeX * graphic_device->gdfBytesPP,
- "x8r8g8b8");
+ graphic_device->plnSizeX, "x8r8g8b8");
if (ret)
eprintf("Cannot setup simplefb: Error setting properties\n");
diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c
index b8f3431f24..8e8134614e 100644
--- a/drivers/video/tegra.c
+++ b/drivers/video/tegra.c
@@ -49,7 +49,7 @@ vidinfo_t panel_info = {
.vl_col = -1,
};
-#ifndef CONFIG_OF_CONTROL
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
#error "You must enable CONFIG_OF_CONTROL to get Tegra LCD support"
#endif
@@ -92,7 +92,7 @@ void lcd_ctrl_init(void *lcdbase)
/* Enable flushing after LCD writes if requested */
lcd_set_flush_dcache(config.cache_type & FDT_LCD_CACHE_FLUSH);
- debug("LCD frame buffer at %08X\n", disp_config->frame_buffer);
+ debug("LCD frame buffer at %pa\n", &disp_config->frame_buffer);
}
ulong calc_fbsize(void)
diff --git a/drivers/video/vesa_fb.c b/drivers/video/vesa_fb.c
index 909f8e8091..4e6d070a5f 100644
--- a/drivers/video/vesa_fb.c
+++ b/drivers/video/vesa_fb.c
@@ -24,6 +24,14 @@ void *video_hw_init(void)
int ret;
printf("Video: ");
+ if (!ll_boot_init()) {
+ /*
+ * If we are running from EFI or coreboot, this driver can't
+ * work.
+ */
+ printf("Not available (previous bootloader prevents it)\n");
+ return NULL;
+ }
if (vbe_get_video_info(gdev)) {
dev = pci_find_class(PCI_CLASS_DISPLAY_VGA << 8, 0);
if (dev == -1) {
generated by cgit (git 2.34.1) at 2024-12-29 09:20:42 +0000