diff options
Diffstat (limited to 'drivers/watchdog')
| -rw-r--r-- | drivers/watchdog/Kconfig | 11 | ||||
| -rw-r--r-- | drivers/watchdog/Makefile | 1 | ||||
| -rw-r--r-- | drivers/watchdog/bcm6345_wdt.c | 21 | ||||
| -rw-r--r-- | drivers/watchdog/sp805_wdt.c | 127 |
4 files changed, 153 insertions, 7 deletions
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 3bce0aa0b8..b01dbc446d 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -55,7 +55,7 @@ config WDT help Enable driver model for watchdog timer. At the moment the API is very simple and only supports four operations: - start, restart, stop and reset (expire immediately). + start, stop, reset and expire_now (expire immediately). What exactly happens when the timer expires is up to a particular device/driver. @@ -103,6 +103,13 @@ config WDT_ORION Select this to enable Orion watchdog timer, which can be found on some Marvell Armada chips. +config WDT_SP805 + bool "SP805 watchdog timer support" + depends on WDT + help + Select this to enable SP805 watchdog timer, which can be found on some + nxp layerscape chips. + config WDT_CDNS bool "Cadence watchdog timer support" depends on WDT @@ -143,7 +150,7 @@ config WDT_AT91 config WDT_MT7621 bool "MediaTek MT7621 watchdog timer support" - depends on WDT && ARCH_MT7620 + depends on WDT && SOC_MT7628 help Select this to enable Ralink / Mediatek watchdog timer, which can be found on some MediaTek chips. diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 40b2f4bc66..6f20e73810 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -27,3 +27,4 @@ obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o obj-$(CONFIG_WDT_MTK) += mtk_wdt.o +obj-$(CONFIG_WDT_SP805) += sp805_wdt.o diff --git a/drivers/watchdog/bcm6345_wdt.c b/drivers/watchdog/bcm6345_wdt.c index 44f5662038..9f14e7d777 100644 --- a/drivers/watchdog/bcm6345_wdt.c +++ b/drivers/watchdog/bcm6345_wdt.c @@ -10,6 +10,7 @@ #include <common.h> #include <dm.h> #include <wdt.h> +#include <clk.h> #include <asm/io.h> /* WDT Value register */ @@ -26,6 +27,7 @@ struct bcm6345_wdt_priv { void __iomem *regs; + unsigned long clk_rate; }; static int bcm6345_wdt_reset(struct udevice *dev) @@ -41,16 +43,17 @@ static int bcm6345_wdt_reset(struct udevice *dev) static int bcm6345_wdt_start(struct udevice *dev, u64 timeout, ulong flags) { struct bcm6345_wdt_priv *priv = dev_get_priv(dev); + u32 val = priv->clk_rate / 1000 * timeout; - if (timeout < WDT_VAL_MIN) { + if (val < WDT_VAL_MIN) { debug("watchdog won't fire with less than 2 ticks\n"); - timeout = WDT_VAL_MIN; - } else if (timeout > WDT_VAL_MAX) { + val = WDT_VAL_MIN; + } else if (val > WDT_VAL_MAX) { debug("maximum watchdog timeout exceeded\n"); - timeout = WDT_VAL_MAX; + val = WDT_VAL_MAX; } - writel(timeout, priv->regs + WDT_VAL_REG); + writel(val, priv->regs + WDT_VAL_REG); return bcm6345_wdt_reset(dev); } @@ -85,11 +88,19 @@ static const struct udevice_id bcm6345_wdt_ids[] = { static int bcm6345_wdt_probe(struct udevice *dev) { struct bcm6345_wdt_priv *priv = dev_get_priv(dev); + struct clk clk; + int ret; priv->regs = dev_remap_addr(dev); if (!priv->regs) return -EINVAL; + ret = clk_get_by_index(dev, 0, &clk); + if (!ret) + priv->clk_rate = clk_get_rate(&clk); + else + return -EINVAL; + bcm6345_wdt_stop(dev); return 0; diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c new file mode 100644 index 0000000000..966128216f --- /dev/null +++ b/drivers/watchdog/sp805_wdt.c @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Watchdog driver for SP805 on some Layerscape SoC + * + * Copyright 2019 NXP + */ + +#include <asm/io.h> +#include <common.h> +#include <dm/device.h> +#include <dm/fdtaddr.h> +#include <dm/read.h> +#include <linux/bitops.h> +#include <watchdog.h> +#include <wdt.h> + +#define WDTLOAD 0x000 +#define WDTCONTROL 0x008 +#define WDTINTCLR 0x00C +#define WDTLOCK 0xC00 + +#define TIME_OUT_MIN_MSECS 1 +#define TIME_OUT_MAX_MSECS 120000 +#define SYS_FSL_WDT_CLK_DIV 16 +#define INT_ENABLE BIT(0) +#define RESET_ENABLE BIT(1) +#define DISABLE 0 +#define UNLOCK 0x1ACCE551 +#define LOCK 0x00000001 +#define INT_MASK BIT(0) + +DECLARE_GLOBAL_DATA_PTR; + +struct sp805_wdt_priv { + void __iomem *reg; +}; + +static int sp805_wdt_reset(struct udevice *dev) +{ + struct sp805_wdt_priv *priv = dev_get_priv(dev); + + writel(UNLOCK, priv->reg + WDTLOCK); + writel(INT_MASK, priv->reg + WDTINTCLR); + writel(LOCK, priv->reg + WDTLOCK); + readl(priv->reg + WDTLOCK); + + return 0; +} + +static int sp805_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{ + u32 load_value; + u32 load_time; + struct sp805_wdt_priv *priv = dev_get_priv(dev); + + load_time = (u32)timeout; + if (timeout < TIME_OUT_MIN_MSECS) + load_time = TIME_OUT_MIN_MSECS; + else if (timeout > TIME_OUT_MAX_MSECS) + load_time = TIME_OUT_MAX_MSECS; + /* sp805 runs counter with given value twice, so when the max timeout is + * set 120s, the gd->bus_clk is less than 1145MHz, the load_value will + * not overflow. + */ + load_value = (gd->bus_clk) / + (2 * 1000 * SYS_FSL_WDT_CLK_DIV) * load_time; + + writel(UNLOCK, priv->reg + WDTLOCK); + writel(load_value, priv->reg + WDTLOAD); + writel(INT_MASK, priv->reg + WDTINTCLR); + writel(INT_ENABLE | RESET_ENABLE, priv->reg + WDTCONTROL); + writel(LOCK, priv->reg + WDTLOCK); + readl(priv->reg + WDTLOCK); + + return 0; +} + +static int sp805_wdt_stop(struct udevice *dev) +{ + struct sp805_wdt_priv *priv = dev_get_priv(dev); + + writel(UNLOCK, priv->reg + WDTLOCK); + writel(DISABLE, priv->reg + WDTCONTROL); + writel(LOCK, priv->reg + WDTLOCK); + readl(priv->reg + WDTLOCK); + + return 0; +} + +static int sp805_wdt_probe(struct udevice *dev) +{ + debug("%s: Probing wdt%u\n", __func__, dev->seq); + + return 0; +} + +static int sp805_wdt_ofdata_to_platdata(struct udevice *dev) +{ + struct sp805_wdt_priv *priv = dev_get_priv(dev); + + priv->reg = (void __iomem *)dev_read_addr(dev); + if (IS_ERR(priv->reg)) + return PTR_ERR(priv->reg); + + return 0; +} + +static const struct wdt_ops sp805_wdt_ops = { + .start = sp805_wdt_start, + .reset = sp805_wdt_reset, + .stop = sp805_wdt_stop, +}; + +static const struct udevice_id sp805_wdt_ids[] = { + { .compatible = "arm,sp805-wdt" }, + {} +}; + +U_BOOT_DRIVER(sp805_wdt) = { + .name = "sp805_wdt", + .id = UCLASS_WDT, + .of_match = sp805_wdt_ids, + .probe = sp805_wdt_probe, + .priv_auto_alloc_size = sizeof(struct sp805_wdt_priv), + .ofdata_to_platdata = sp805_wdt_ofdata_to_platdata, + .ops = &sp805_wdt_ops, +}; |