summaryrefslogtreecommitdiff
path: root/drivers
diff options
context:
space:
mode:
Diffstat (limited to 'drivers')
-rw-r--r--drivers/crypto/fsl/jr.c51
-rw-r--r--drivers/crypto/fsl/jr.h2
-rw-r--r--drivers/gpio/stm32_gpio.c29
-rw-r--r--drivers/net/fm/Makefile1
-rw-r--r--drivers/net/fm/fdt.c129
-rw-r--r--drivers/net/fm/fm.c2
-rw-r--r--drivers/pci/pci_rom.c2
-rw-r--r--drivers/power/pmic/pmic_tps65218.c56
-rw-r--r--drivers/qe/fdt.c2
-rw-r--r--drivers/qe/qe.c14
-rw-r--r--drivers/qe/qe.h299
-rw-r--r--drivers/qe/uccf.c2
-rw-r--r--drivers/qe/uccf.h2
-rw-r--r--drivers/qe/uec.c2
-rw-r--r--drivers/qe/uec.h2
-rw-r--r--drivers/qe/uec_phy.c2
-rw-r--r--drivers/serial/Makefile1
-rw-r--r--drivers/serial/serial_stm32x7.c83
-rw-r--r--drivers/serial/serial_stm32x7.h37
-rw-r--r--drivers/usb/eth/usb_ether.c2
-rw-r--r--drivers/usb/gadget/f_dfu.c11
-rw-r--r--drivers/usb/gadget/f_fastboot.c10
-rw-r--r--drivers/usb/host/ehci-generic.c4
-rw-r--r--drivers/usb/host/ehci-hcd.c21
-rw-r--r--drivers/usb/host/ehci.h5
25 files changed, 394 insertions, 377 deletions
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index b553e3c583..b766470ce2 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -12,6 +12,9 @@
#include "jr.h"
#include "jobdesc.h"
#include "desc_constr.h"
+#ifdef CONFIG_FSL_CORENET
+#include <asm/fsl_pamu.h>
+#endif
#define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
#define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
@@ -95,14 +98,16 @@ static int jr_init(void)
JR_SIZE * sizeof(dma_addr_t));
if (!jr.input_ring)
return -1;
+
+ jr.op_size = roundup(JR_SIZE * sizeof(struct op_ring),
+ ARCH_DMA_MINALIGN);
jr.output_ring =
- (struct op_ring *)memalign(ARCH_DMA_MINALIGN,
- JR_SIZE * sizeof(struct op_ring));
+ (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr.op_size);
if (!jr.output_ring)
return -1;
memset(jr.input_ring, 0, JR_SIZE * sizeof(dma_addr_t));
- memset(jr.output_ring, 0, JR_SIZE * sizeof(struct op_ring));
+ memset(jr.output_ring, 0, jr.op_size);
start_jr0();
@@ -190,8 +195,8 @@ static int jr_enqueue(uint32_t *desc_addr,
unsigned long start = (unsigned long)&jr.info[head] &
~(ARCH_DMA_MINALIGN - 1);
- unsigned long end = ALIGN(start + sizeof(struct jr_info),
- ARCH_DMA_MINALIGN);
+ unsigned long end = ALIGN((unsigned long)&jr.info[head] +
+ sizeof(struct jr_info), ARCH_DMA_MINALIGN);
flush_dcache_range(start, end);
#ifdef CONFIG_PHYS_64BIT
@@ -216,11 +221,19 @@ static int jr_enqueue(uint32_t *desc_addr,
#endif /* ifdef CONFIG_PHYS_64BIT */
start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
- end = ALIGN(start + sizeof(phys_addr_t), ARCH_DMA_MINALIGN);
+ end = ALIGN((unsigned long)&jr.input_ring[head] +
+ sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
flush_dcache_range(start, end);
jr.head = (head + 1) & (jr.size - 1);
+ /* Invalidate output ring */
+ start = (unsigned long)jr.output_ring &
+ ~(ARCH_DMA_MINALIGN - 1);
+ end = ALIGN((unsigned long)jr.output_ring + jr.op_size,
+ ARCH_DMA_MINALIGN);
+ invalidate_dcache_range(start, end);
+
sec_out32(&regs->irja, 1);
return 0;
@@ -241,12 +254,6 @@ static int jr_dequeue(void)
#endif
while (sec_in32(&regs->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) {
- unsigned long start = (unsigned long)jr.output_ring &
- ~(ARCH_DMA_MINALIGN - 1);
- unsigned long end = ALIGN(start +
- sizeof(struct op_ring)*JR_SIZE,
- ARCH_DMA_MINALIGN);
- invalidate_dcache_range(start, end);
found = 0;
@@ -530,18 +537,38 @@ int sec_init(void)
uint32_t mcr = sec_in32(&sec->mcfgr);
int ret = 0;
+#ifdef CONFIG_FSL_CORENET
+ uint32_t liodnr;
+ uint32_t liodn_ns;
+ uint32_t liodn_s;
+#endif
+
mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
#ifdef CONFIG_PHYS_64BIT
mcr |= (1 << MCFGR_PS_SHIFT);
#endif
sec_out32(&sec->mcfgr, mcr);
+#ifdef CONFIG_FSL_CORENET
+ liodnr = sec_in32(&sec->jrliodnr[0].ls);
+ liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
+ liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
+#endif
+
ret = jr_init();
if (ret < 0) {
printf("SEC initialization failed\n");
return -1;
}
+#ifdef CONFIG_FSL_CORENET
+ ret = sec_config_pamu_table(liodn_ns, liodn_s);
+ if (ret < 0)
+ return -1;
+
+ pamu_enable();
+#endif
+
if (get_rng_vid() >= 4) {
if (rng_init() < 0) {
printf("RNG instantiation failed\n");
diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h
index 5899696e8a..545d964ced 100644
--- a/drivers/crypto/fsl/jr.h
+++ b/drivers/crypto/fsl/jr.h
@@ -72,6 +72,8 @@ struct jobring {
int write_idx;
/* Size of the rings. */
int size;
+ /* Op ring size aligned to cache line size */
+ int op_size;
/* The ip and output rings have to be accessed by SEC. So the
* pointers will ahve to point to the housekeeping region provided
* by SEC
diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c
index 75a84e111f..50f86d3dd6 100644
--- a/drivers/gpio/stm32_gpio.c
+++ b/drivers/gpio/stm32_gpio.c
@@ -19,17 +19,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_STM32F4)
-#define STM32_GPIOA_BASE (STM32_AHB1PERIPH_BASE + 0x0000)
-#define STM32_GPIOB_BASE (STM32_AHB1PERIPH_BASE + 0x0400)
-#define STM32_GPIOC_BASE (STM32_AHB1PERIPH_BASE + 0x0800)
-#define STM32_GPIOD_BASE (STM32_AHB1PERIPH_BASE + 0x0C00)
-#define STM32_GPIOE_BASE (STM32_AHB1PERIPH_BASE + 0x1000)
-#define STM32_GPIOF_BASE (STM32_AHB1PERIPH_BASE + 0x1400)
-#define STM32_GPIOG_BASE (STM32_AHB1PERIPH_BASE + 0x1800)
-#define STM32_GPIOH_BASE (STM32_AHB1PERIPH_BASE + 0x1C00)
-#define STM32_GPIOI_BASE (STM32_AHB1PERIPH_BASE + 0x2000)
-
+#if defined(CONFIG_STM32F4) || defined(CONFIG_STM32F7)
static const unsigned long io_base[] = {
STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,
@@ -70,8 +60,6 @@ int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
- setbits_le32(&STM32_RCC->ahb1enr, 1 << dsc->port);
-
i = (dsc->pin & 0x07) * 4;
clrsetbits_le32(&gpio_regs->afr[dsc->pin >> 3], 0xF << i, ctl->af << i);
@@ -87,14 +75,6 @@ out:
return rv;
}
#elif defined(CONFIG_STM32F1)
-#define STM32_GPIOA_BASE (STM32_APB2PERIPH_BASE + 0x0800)
-#define STM32_GPIOB_BASE (STM32_APB2PERIPH_BASE + 0x0C00)
-#define STM32_GPIOC_BASE (STM32_APB2PERIPH_BASE + 0x1000)
-#define STM32_GPIOD_BASE (STM32_APB2PERIPH_BASE + 0x1400)
-#define STM32_GPIOE_BASE (STM32_APB2PERIPH_BASE + 0x1800)
-#define STM32_GPIOF_BASE (STM32_APB2PERIPH_BASE + 0x1C00)
-#define STM32_GPIOG_BASE (STM32_APB2PERIPH_BASE + 0x2000)
-
static const unsigned long io_base[] = {
STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,
@@ -141,9 +121,6 @@ int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
- /* Enable clock for GPIO port */
- setbits_le32(&STM32_RCC->apb2enr, 0x04 << dsc->port);
-
if (p < 8) {
cr = &gpio_regs->crl;
crp = p;
@@ -230,7 +207,7 @@ int gpio_direction_input(unsigned gpio)
dsc.port = stm32_gpio_to_port(gpio);
dsc.pin = stm32_gpio_to_pin(gpio);
-#if defined(CONFIG_STM32F4)
+#if defined(CONFIG_STM32F4) || defined(CONFIG_STM32F7)
ctl.af = STM32_GPIO_AF0;
ctl.mode = STM32_GPIO_MODE_IN;
ctl.otype = STM32_GPIO_OTYPE_PP;
@@ -256,7 +233,7 @@ int gpio_direction_output(unsigned gpio, int value)
dsc.port = stm32_gpio_to_port(gpio);
dsc.pin = stm32_gpio_to_pin(gpio);
-#if defined(CONFIG_STM32F4)
+#if defined(CONFIG_STM32F4) || defined(CONFIG_STM32F7)
ctl.af = STM32_GPIO_AF0;
ctl.mode = STM32_GPIO_MODE_OUT;
ctl.pupd = STM32_GPIO_PUPD_NO;
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index a3c9f99627..493cdc6d48 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -6,6 +6,7 @@
obj-y += dtsec.o
obj-y += eth.o
+obj-y += fdt.o
obj-y += fm.o
obj-y += init.o
obj-y += tgec.o
diff --git a/drivers/net/fm/fdt.c b/drivers/net/fm/fdt.c
new file mode 100644
index 0000000000..9918d8089a
--- /dev/null
+++ b/drivers/net/fm/fdt.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <asm/io.h>
+#include <fsl_qe.h> /* For struct qe_firmware */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+/**
+ * fdt_fixup_fman_firmware -- insert the Fman firmware into the device tree
+ *
+ * The binding for an Fman firmware node is documented in
+ * Documentation/powerpc/dts-bindings/fsl/dpaa/fman.txt. This node contains
+ * the actual Fman firmware binary data. The operating system is expected to
+ * be able to parse the binary data to determine any attributes it needs.
+ */
+void fdt_fixup_fman_firmware(void *blob)
+{
+ int rc, fmnode, fwnode = -1;
+ uint32_t phandle;
+ struct qe_firmware *fmanfw;
+ const struct qe_header *hdr;
+ unsigned int length;
+ uint32_t crc;
+ const char *p;
+
+ /* The first Fman we find will contain the actual firmware. */
+ fmnode = fdt_node_offset_by_compatible(blob, -1, "fsl,fman");
+ if (fmnode < 0)
+ /* Exit silently if there are no Fman devices */
+ return;
+
+ /* If we already have a firmware node, then also exit silently. */
+ if (fdt_node_offset_by_compatible(blob, -1, "fsl,fman-firmware") > 0)
+ return;
+
+ /* If the environment variable is not set, then exit silently */
+ p = getenv("fman_ucode");
+ if (!p)
+ return;
+
+ fmanfw = (struct qe_firmware *)simple_strtoul(p, NULL, 16);
+ if (!fmanfw)
+ return;
+
+ hdr = &fmanfw->header;
+ length = fdt32_to_cpu(hdr->length);
+
+ /* Verify the firmware. */
+ if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
+ (hdr->magic[2] != 'F')) {
+ printf("Data at %p is not an Fman firmware\n", fmanfw);
+ return;
+ }
+
+ if (length > CONFIG_SYS_QE_FMAN_FW_LENGTH) {
+ printf("Fman firmware at %p is too large (size=%u)\n",
+ fmanfw, length);
+ return;
+ }
+
+ length -= sizeof(u32); /* Subtract the size of the CRC */
+ crc = fdt32_to_cpu(*(u32 *)((void *)fmanfw + length));
+ if (crc != crc32_no_comp(0, (void *)fmanfw, length)) {
+ printf("Fman firmware at %p has invalid CRC\n", fmanfw);
+ return;
+ }
+
+ length += sizeof(u32);
+
+ /* Increase the size of the fdt to make room for the node. */
+ rc = fdt_increase_size(blob, length);
+ if (rc < 0) {
+ printf("Unable to make room for Fman firmware: %s\n",
+ fdt_strerror(rc));
+ return;
+ }
+
+ /* Create the firmware node. */
+ fwnode = fdt_add_subnode(blob, fmnode, "fman-firmware");
+ if (fwnode < 0) {
+ char s[64];
+ fdt_get_path(blob, fmnode, s, sizeof(s));
+ printf("Could not add firmware node to %s: %s\n", s,
+ fdt_strerror(fwnode));
+ return;
+ }
+ rc = fdt_setprop_string(blob, fwnode, "compatible",
+ "fsl,fman-firmware");
+ if (rc < 0) {
+ char s[64];
+ fdt_get_path(blob, fwnode, s, sizeof(s));
+ printf("Could not add compatible property to node %s: %s\n", s,
+ fdt_strerror(rc));
+ return;
+ }
+ phandle = fdt_create_phandle(blob, fwnode);
+ if (!phandle) {
+ char s[64];
+ fdt_get_path(blob, fwnode, s, sizeof(s));
+ printf("Could not add phandle property to node %s: %s\n", s,
+ fdt_strerror(rc));
+ return;
+ }
+ rc = fdt_setprop(blob, fwnode, "fsl,firmware", fmanfw, length);
+ if (rc < 0) {
+ char s[64];
+ fdt_get_path(blob, fwnode, s, sizeof(s));
+ printf("Could not add firmware property to node %s: %s\n", s,
+ fdt_strerror(rc));
+ return;
+ }
+
+ /* Find all other Fman nodes and point them to the firmware node. */
+ while ((fmnode = fdt_node_offset_by_compatible(blob, fmnode,
+ "fsl,fman")) > 0) {
+ rc = fdt_setprop_cell(blob, fmnode, "fsl,firmware-phandle",
+ phandle);
+ if (rc < 0) {
+ char s[64];
+ fdt_get_path(blob, fmnode, s, sizeof(s));
+ printf("Could not add pointer property to node %s: %s\n",
+ s, fdt_strerror(rc));
+ return;
+ }
+ }
+}
+#endif
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index 40fbf19c75..e2a8ed3919 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -10,7 +10,7 @@
#include <asm/errno.h>
#include "fm.h"
-#include "../../qe/qe.h" /* For struct qe_firmware */
+#include <fsl_qe.h> /* For struct qe_firmware */
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
#include <nand.h>
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index d5bf6f4c47..9eb605be74 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -266,7 +266,7 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void),
int exec_method)
{
struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
- struct pci_rom_header *rom, *ram = NULL;
+ struct pci_rom_header *rom = NULL, *ram = NULL;
int vesa_mode = -1;
bool emulate, alloced;
int ret;
diff --git a/drivers/power/pmic/pmic_tps65218.c b/drivers/power/pmic/pmic_tps65218.c
index dbc7a73a72..0fd0ad478a 100644
--- a/drivers/power/pmic/pmic_tps65218.c
+++ b/drivers/power/pmic/pmic_tps65218.c
@@ -11,6 +11,20 @@
#include <power/pmic.h>
#include <power/tps65218.h>
+int tps65218_reg_read(uchar dest_reg, uchar *dest_val)
+{
+ uchar read_val;
+ int ret;
+
+ ret = i2c_read(TPS65218_CHIP_PM, dest_reg, 1, &read_val, 1);
+ if (ret)
+ return ret;
+
+ *dest_val = read_val;
+
+ return 0;
+}
+
/**
* tps65218_reg_write() - Generic function that can write a TPS65218 PMIC
* register or bit field regardless of protection
@@ -98,6 +112,48 @@ int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel)
return 0;
}
+/**
+ * tps65218_toggle_fseal() - Perform the sequence that toggles the FSEAL bit.
+ *
+ * @return: 0 on success, -EBADE if the sequence was broken
+ */
+int tps65218_toggle_fseal(void)
+{
+ if (tps65218_reg_write(TPS65218_PROT_LEVEL_NONE, TPS65218_PASSWORD,
+ 0xb1, TPS65218_MASK_ALL_BITS))
+ return -EBADE;
+
+ if (tps65218_reg_write(TPS65218_PROT_LEVEL_NONE, TPS65218_PASSWORD,
+ 0xfe, TPS65218_MASK_ALL_BITS))
+ return -EBADE;
+
+ if (tps65218_reg_write(TPS65218_PROT_LEVEL_NONE, TPS65218_PASSWORD,
+ 0xa3, TPS65218_MASK_ALL_BITS))
+ return -EBADE;
+
+ return 0;
+}
+
+/**
+ * tps65218_lock_fseal() - Perform the sequence that locks the FSEAL bit to 1.
+ *
+ * The FSEAL bit prevents the PMIC from turning off DCDC5 and DCDC6. It can be
+ * toggled at most 3 times: 0->1, 1->0, and finally 0->1. After the third switch
+ * its value is locked and can only be reset by powering off the PMIC entirely.
+ *
+ * @return: 0 on success, -EBADE if the sequence was broken
+ */
+int tps65218_lock_fseal(void)
+{
+ int i;
+
+ for (i = 0; i < 3; i++)
+ if (tps65218_toggle_fseal())
+ return -EBADE;
+
+ return 0;
+}
+
int power_tps65218_init(unsigned char bus)
{
static const char name[] = "TPS65218_PMIC";
diff --git a/drivers/qe/fdt.c b/drivers/qe/fdt.c
index dfae4bf64d..4f48f984ab 100644
--- a/drivers/qe/fdt.c
+++ b/drivers/qe/fdt.c
@@ -10,7 +10,7 @@
#include <common.h>
#include <libfdt.h>
#include <fdt_support.h>
-#include "qe.h"
+#include <fsl_qe.h>
#ifdef CONFIG_QE
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 08620b23a7..2b98984ef2 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -12,7 +12,7 @@
#include "asm/errno.h"
#include "asm/io.h"
#include "linux/immap_qe.h"
-#include "qe.h"
+#include <fsl_qe.h>
#ifdef CONFIG_LS102XA
#include <asm/arch/immap_ls102xa.h>
#endif
@@ -20,7 +20,9 @@
#define MPC85xx_DEVDISR_QE_DISABLE 0x1
qe_map_t *qe_immr = NULL;
+#ifdef CONFIG_QE
static qe_snum_t snums[QE_NUM_OF_SNUM];
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -81,6 +83,7 @@ void *qe_muram_addr(uint offset)
return (void *)&qe_immr->muram[offset];
}
+#ifdef CONFIG_QE
static void qe_sdma_init(void)
{
volatile sdma_t *p;
@@ -184,12 +187,12 @@ void qe_init(uint qe_base)
qe_sdma_init();
qe_snums_init();
}
+#endif
#ifdef CONFIG_U_QE
void u_qe_init(void)
{
- uint qe_base = CONFIG_SYS_IMMR + 0x01400000; /* QE immr base */
- qe_immr = (qe_map_t *)qe_base;
+ qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
u_qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR);
out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
@@ -200,9 +203,8 @@ void u_qe_init(void)
void u_qe_resume(void)
{
qe_map_t *qe_immrr;
- uint qe_base = CONFIG_SYS_IMMR + QE_IMMR_OFFSET; /* QE immr base */
- qe_immrr = (qe_map_t *)qe_base;
+ qe_immrr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
u_qe_firmware_resume((const void *)CONFIG_SYS_QE_FW_ADDR, qe_immrr);
out_be32(&qe_immrr->iram.iready, QE_IRAM_READY);
}
@@ -214,6 +216,7 @@ void qe_reset(void)
(u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
}
+#ifdef CONFIG_QE
void qe_assign_page(uint snum, uint para_ram_base)
{
u32 cecr;
@@ -229,6 +232,7 @@ void qe_assign_page(uint snum, uint para_ram_base)
return;
}
+#endif
/*
* brg: 0~15 as BRG1~BRG16
diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
deleted file mode 100644
index 77b18e928f..0000000000
--- a/drivers/qe/qe.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- *
- * Dave Liu <daveliu@freescale.com>
- * based on source code of Shlomi Gridish
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __QE_H__
-#define __QE_H__
-
-#include "common.h"
-#ifdef CONFIG_U_QE
-#include <linux/immap_qe.h>
-#endif
-
-#define QE_NUM_OF_BRGS 16
-#define UCC_MAX_NUM 8
-
-#define QE_DATAONLY_BASE 0
-#define QE_DATAONLY_SIZE (QE_MURAM_SIZE - QE_DATAONLY_BASE)
-
-/* QE threads SNUM
-*/
-typedef enum qe_snum_state {
- QE_SNUM_STATE_USED, /* used */
- QE_SNUM_STATE_FREE /* free */
-} qe_snum_state_e;
-
-typedef struct qe_snum {
- u8 num; /* snum */
- qe_snum_state_e state; /* state */
-} qe_snum_t;
-
-/* QE RISC allocation
-*/
-#define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
-#define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
-#define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
-#define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
-#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \
- QE_RISC_ALLOCATION_RISC2)
-#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
- QE_RISC_ALLOCATION_RISC2 | \
- QE_RISC_ALLOCATION_RISC3 | \
- QE_RISC_ALLOCATION_RISC4)
-
-/* QE CECR commands for UCC fast.
-*/
-#define QE_CR_FLG 0x00010000
-#define QE_RESET 0x80000000
-#define QE_INIT_TX_RX 0x00000000
-#define QE_INIT_RX 0x00000001
-#define QE_INIT_TX 0x00000002
-#define QE_ENTER_HUNT_MODE 0x00000003
-#define QE_STOP_TX 0x00000004
-#define QE_GRACEFUL_STOP_TX 0x00000005
-#define QE_RESTART_TX 0x00000006
-#define QE_SWITCH_COMMAND 0x00000007
-#define QE_SET_GROUP_ADDRESS 0x00000008
-#define QE_INSERT_CELL 0x00000009
-#define QE_ATM_TRANSMIT 0x0000000a
-#define QE_CELL_POOL_GET 0x0000000b
-#define QE_CELL_POOL_PUT 0x0000000c
-#define QE_IMA_HOST_CMD 0x0000000d
-#define QE_ATM_MULTI_THREAD_INIT 0x00000011
-#define QE_ASSIGN_PAGE 0x00000012
-#define QE_START_FLOW_CONTROL 0x00000014
-#define QE_STOP_FLOW_CONTROL 0x00000015
-#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
-#define QE_GRACEFUL_STOP_RX 0x0000001a
-#define QE_RESTART_RX 0x0000001b
-
-/* QE CECR Sub Block Code - sub block code of QE command.
-*/
-#define QE_CR_SUBBLOCK_INVALID 0x00000000
-#define QE_CR_SUBBLOCK_USB 0x03200000
-#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
-#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
-#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
-#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
-#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
-#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
-#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
-#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
-#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
-#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
-#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
-#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
-#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
-#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
-#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
-#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
-#define QE_CR_SUBBLOCK_MCC1 0x03800000
-#define QE_CR_SUBBLOCK_MCC2 0x03a00000
-#define QE_CR_SUBBLOCK_MCC3 0x03000000
-#define QE_CR_SUBBLOCK_IDMA1 0x02800000
-#define QE_CR_SUBBLOCK_IDMA2 0x02a00000
-#define QE_CR_SUBBLOCK_IDMA3 0x02c00000
-#define QE_CR_SUBBLOCK_IDMA4 0x02e00000
-#define QE_CR_SUBBLOCK_HPAC 0x01e00000
-#define QE_CR_SUBBLOCK_SPI1 0x01400000
-#define QE_CR_SUBBLOCK_SPI2 0x01600000
-#define QE_CR_SUBBLOCK_RAND 0x01c00000
-#define QE_CR_SUBBLOCK_TIMER 0x01e00000
-#define QE_CR_SUBBLOCK_GENERAL 0x03c00000
-
-/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command.
-*/
-#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
-#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
-#define QE_CR_PROTOCOL_ATM_POS 0x0A
-#define QE_CR_PROTOCOL_ETHERNET 0x0C
-#define QE_CR_PROTOCOL_L2_SWITCH 0x0D
-#define QE_CR_PROTOCOL_SHIFT 6
-
-/* QE ASSIGN PAGE command
-*/
-#define QE_CR_ASSIGN_PAGE_SNUM_SHIFT 17
-
-/* Communication Direction.
-*/
-typedef enum comm_dir {
- COMM_DIR_NONE = 0,
- COMM_DIR_RX = 1,
- COMM_DIR_TX = 2,
- COMM_DIR_RX_AND_TX = 3
-} comm_dir_e;
-
-/* Clocks and BRG's
-*/
-typedef enum qe_clock {
- QE_CLK_NONE = 0,
- QE_BRG1, /* Baud Rate Generator 1 */
- QE_BRG2, /* Baud Rate Generator 2 */
- QE_BRG3, /* Baud Rate Generator 3 */
- QE_BRG4, /* Baud Rate Generator 4 */
- QE_BRG5, /* Baud Rate Generator 5 */
- QE_BRG6, /* Baud Rate Generator 6 */
- QE_BRG7, /* Baud Rate Generator 7 */
- QE_BRG8, /* Baud Rate Generator 8 */
- QE_BRG9, /* Baud Rate Generator 9 */
- QE_BRG10, /* Baud Rate Generator 10 */
- QE_BRG11, /* Baud Rate Generator 11 */
- QE_BRG12, /* Baud Rate Generator 12 */
- QE_BRG13, /* Baud Rate Generator 13 */
- QE_BRG14, /* Baud Rate Generator 14 */
- QE_BRG15, /* Baud Rate Generator 15 */
- QE_BRG16, /* Baud Rate Generator 16 */
- QE_CLK1, /* Clock 1 */
- QE_CLK2, /* Clock 2 */
- QE_CLK3, /* Clock 3 */
- QE_CLK4, /* Clock 4 */
- QE_CLK5, /* Clock 5 */
- QE_CLK6, /* Clock 6 */
- QE_CLK7, /* Clock 7 */
- QE_CLK8, /* Clock 8 */
- QE_CLK9, /* Clock 9 */
- QE_CLK10, /* Clock 10 */
- QE_CLK11, /* Clock 11 */
- QE_CLK12, /* Clock 12 */
- QE_CLK13, /* Clock 13 */
- QE_CLK14, /* Clock 14 */
- QE_CLK15, /* Clock 15 */
- QE_CLK16, /* Clock 16 */
- QE_CLK17, /* Clock 17 */
- QE_CLK18, /* Clock 18 */
- QE_CLK19, /* Clock 19 */
- QE_CLK20, /* Clock 20 */
- QE_CLK21, /* Clock 21 */
- QE_CLK22, /* Clock 22 */
- QE_CLK23, /* Clock 23 */
- QE_CLK24, /* Clock 24 */
- QE_CLK_DUMMY
-} qe_clock_e;
-
-/* QE CMXGCR register
-*/
-#define QE_CMXGCR_MII_ENET_MNG_MASK 0x00007000
-#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
-
-/* QE CMXUCR registers
- */
-#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
-
-/* QE BRG configuration register
-*/
-#define QE_BRGC_ENABLE 0x00010000
-#define QE_BRGC_DIVISOR_SHIFT 1
-#define QE_BRGC_DIVISOR_MAX 0xFFF
-#define QE_BRGC_DIV16 1
-
-/* QE SDMA registers
-*/
-#define QE_SDSR_BER1 0x02000000
-#define QE_SDSR_BER2 0x01000000
-
-#define QE_SDMR_GLB_1_MSK 0x80000000
-#define QE_SDMR_ADR_SEL 0x20000000
-#define QE_SDMR_BER1_MSK 0x02000000
-#define QE_SDMR_BER2_MSK 0x01000000
-#define QE_SDMR_EB1_MSK 0x00800000
-#define QE_SDMR_ER1_MSK 0x00080000
-#define QE_SDMR_ER2_MSK 0x00040000
-#define QE_SDMR_CEN_MASK 0x0000E000
-#define QE_SDMR_SBER_1 0x00000200
-#define QE_SDMR_SBER_2 0x00000200
-#define QE_SDMR_EB1_PR_MASK 0x000000C0
-#define QE_SDMR_ER1_PR 0x00000008
-
-#define QE_SDMR_CEN_SHIFT 13
-#define QE_SDMR_EB1_PR_SHIFT 6
-
-#define QE_SDTM_MSNUM_SHIFT 24
-
-#define QE_SDEBCR_BA_MASK 0x01FFFFFF
-
-/* Communication Processor */
-#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
-#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */
-#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
-
-/* I-RAM */
-#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
-#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
-#define QE_IRAM_READY 0x80000000
-
-/* Structure that defines QE firmware binary files.
- *
- * See doc/README.qe_firmware for a description of these fields.
- */
-struct qe_firmware {
- struct qe_header {
- u32 length; /* Length of the entire structure, in bytes */
- u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */
- u8 version; /* Version of this layout. First ver is '1' */
- } header;
- u8 id[62]; /* Null-terminated identifier string */
- u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
- u8 count; /* Number of microcode[] structures */
- struct {
- u16 model; /* The SOC model */
- u8 major; /* The SOC revision major */
- u8 minor; /* The SOC revision minor */
- } __attribute__ ((packed)) soc;
- u8 padding[4]; /* Reserved, for alignment */
- u64 extended_modes; /* Extended modes */
- u32 vtraps[8]; /* Virtual trap addresses */
- u8 reserved[4]; /* Reserved, for future expansion */
- struct qe_microcode {
- u8 id[32]; /* Null-terminated identifier */
- u32 traps[16]; /* Trap addresses, 0 == ignore */
- u32 eccr; /* The value for the ECCR register */
- u32 iram_offset;/* Offset into I-RAM for the code */
- u32 count; /* Number of 32-bit words of the code */
- u32 code_offset;/* Offset of the actual microcode */
- u8 major; /* The microcode version major */
- u8 minor; /* The microcode version minor */
- u8 revision; /* The microcode version revision */
- u8 padding; /* Reserved, for alignment */
- u8 reserved[4]; /* Reserved, for future expansion */
- } __attribute__ ((packed)) microcode[1];
- /* All microcode binaries should be located here */
- /* CRC32 should be located here, after the microcode binaries */
-} __attribute__ ((packed));
-
-struct qe_firmware_info {
- char id[64]; /* Firmware name */
- u32 vtraps[8]; /* Virtual trap addresses */
- u64 extended_modes; /* Extended modes */
-};
-
-void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign);
-void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data);
-uint qe_muram_alloc(uint size, uint align);
-void *qe_muram_addr(uint offset);
-int qe_get_snum(void);
-void qe_put_snum(u8 snum);
-void qe_init(uint qe_base);
-void qe_reset(void);
-void qe_assign_page(uint snum, uint para_ram_base);
-int qe_set_brg(uint brg, uint rate);
-int qe_set_mii_clk_src(int ucc_num);
-int qe_upload_firmware(const struct qe_firmware *firmware);
-struct qe_firmware_info *qe_get_firmware_info(void);
-void ft_qe_setup(void *blob);
-void qe_init(uint qe_base);
-void qe_reset(void);
-
-#ifdef CONFIG_U_QE
-void u_qe_init(void);
-int u_qe_upload_firmware(const struct qe_firmware *firmware);
-void u_qe_resume(void);
-int u_qe_firmware_resume(const struct qe_firmware *firmware,
- qe_map_t *qe_immrr);
-#endif
-
-#endif /* __QE_H__ */
diff --git a/drivers/qe/uccf.c b/drivers/qe/uccf.c
index 85386bfc70..e011886505 100644
--- a/drivers/qe/uccf.c
+++ b/drivers/qe/uccf.c
@@ -12,8 +12,8 @@
#include "asm/errno.h"
#include "asm/io.h"
#include "linux/immap_qe.h"
-#include "qe.h"
#include "uccf.h"
+#include <fsl_qe.h>
void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf)
{
diff --git a/drivers/qe/uccf.h b/drivers/qe/uccf.h
index 55941e4601..aa817e73ec 100644
--- a/drivers/qe/uccf.h
+++ b/drivers/qe/uccf.h
@@ -11,8 +11,8 @@
#define __UCCF_H__
#include "common.h"
-#include "qe.h"
#include "linux/immap_qe.h"
+#include <fsl_qe.h>
/* Fast or Giga ethernet
*/
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index e0ab04abc2..40cccc2406 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -12,11 +12,11 @@
#include "asm/errno.h"
#include "asm/io.h"
#include "linux/immap_qe.h"
-#include "qe.h"
#include "uccf.h"
#include "uec.h"
#include "uec_phy.h"
#include "miiphy.h"
+#include <fsl_qe.h>
#include <phy.h>
/* Default UTBIPAR SMI address */
diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h
index 6b559f7974..22e248ff1d 100644
--- a/drivers/qe/uec.h
+++ b/drivers/qe/uec.h
@@ -10,8 +10,8 @@
#ifndef __UEC_H__
#define __UEC_H__
-#include "qe.h"
#include "uccf.h"
+#include <fsl_qe.h>
#include <phy.h>
#define MAX_TX_THREADS 8
diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
index e701787c41..272874d3b0 100644
--- a/drivers/qe/uec_phy.c
+++ b/drivers/qe/uec_phy.c
@@ -16,11 +16,11 @@
#include "asm/errno.h"
#include "linux/immap_qe.h"
#include "asm/io.h"
-#include "qe.h"
#include "uccf.h"
#include "uec.h"
#include "uec_phy.h"
#include "miiphy.h"
+#include <fsl_qe.h>
#include <phy.h>
#define ugphy_printk(format, arg...) \
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index c63999ac41..05bdf56c6f 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o
+obj-$(CONFIG_STM32X7_SERIAL) += serial_stm32x7.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c
new file mode 100644
index 0000000000..cfbfab7e41
--- /dev/null
+++ b/drivers/serial/serial_stm32x7.c
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2016
+ * Vikas Manocha, <vikas.manocha@st.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <serial.h>
+#include <dm/platform_data/serial_stm32x7.h>
+#include "serial_stm32x7.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
+{
+ struct stm32x7_serial_platdata *plat = dev->platdata;
+ struct stm32_usart *const usart = plat->base;
+ writel(plat->clock/baudrate, &usart->brr);
+
+ return 0;
+}
+
+static int stm32_serial_getc(struct udevice *dev)
+{
+ struct stm32x7_serial_platdata *plat = dev->platdata;
+ struct stm32_usart *const usart = plat->base;
+
+ if ((readl(&usart->sr) & USART_SR_FLAG_RXNE) == 0)
+ return -EAGAIN;
+
+ return readl(&usart->rd_dr);
+}
+
+static int stm32_serial_putc(struct udevice *dev, const char c)
+{
+ struct stm32x7_serial_platdata *plat = dev->platdata;
+ struct stm32_usart *const usart = plat->base;
+
+ if ((readl(&usart->sr) & USART_SR_FLAG_TXE) == 0)
+ return -EAGAIN;
+
+ writel(c, &usart->tx_dr);
+
+ return 0;
+}
+
+static int stm32_serial_pending(struct udevice *dev, bool input)
+{
+ struct stm32x7_serial_platdata *plat = dev->platdata;
+ struct stm32_usart *const usart = plat->base;
+
+ if (input)
+ return readl(&usart->sr) & USART_SR_FLAG_RXNE ? 1 : 0;
+ else
+ return readl(&usart->sr) & USART_SR_FLAG_TXE ? 0 : 1;
+}
+
+static int stm32_serial_probe(struct udevice *dev)
+{
+ struct stm32x7_serial_platdata *plat = dev->platdata;
+ struct stm32_usart *const usart = plat->base;
+ setbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE);
+
+ return 0;
+}
+
+static const struct dm_serial_ops stm32_serial_ops = {
+ .putc = stm32_serial_putc,
+ .pending = stm32_serial_pending,
+ .getc = stm32_serial_getc,
+ .setbrg = stm32_serial_setbrg,
+};
+
+U_BOOT_DRIVER(serial_stm32) = {
+ .name = "serial_stm32x7",
+ .id = UCLASS_SERIAL,
+ .ops = &stm32_serial_ops,
+ .probe = stm32_serial_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32x7.h
new file mode 100644
index 0000000000..6190d67406
--- /dev/null
+++ b/drivers/serial/serial_stm32x7.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2016
+ * Vikas Manocha, <vikas.manocha@st.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SERIAL_STM32_X7_
+#define _SERIAL_STM32_X7_
+
+struct stm32_usart {
+ u32 cr1;
+ u32 cr2;
+ u32 cr3;
+ u32 brr;
+ u32 gtpr;
+ u32 rtor;
+ u32 rqr;
+ u32 sr;
+ u32 icr;
+ u32 rd_dr;
+ u32 tx_dr;
+};
+
+
+#define USART_CR1_RE (1 << 2)
+#define USART_CR1_TE (1 << 3)
+#define USART_CR1_UE (1 << 0)
+
+#define USART_SR_FLAG_RXNE (1 << 5)
+#define USART_SR_FLAG_TXE (1 << 7)
+
+#define USART_BRR_F_MASK 0xFF
+#define USART_BRR_M_SHIFT 4
+#define USART_BRR_M_MASK 0xFFF0
+
+#endif
diff --git a/drivers/usb/eth/usb_ether.c b/drivers/usb/eth/usb_ether.c
index b9c9a8402e..36734e2e51 100644
--- a/drivers/usb/eth/usb_ether.c
+++ b/drivers/usb/eth/usb_ether.c
@@ -73,7 +73,7 @@ int usb_ether_register(struct udevice *dev, struct ueth_data *ueth, int rxsize)
}
ueth->rxsize = rxsize;
- ueth->rxbuf = memalign(rxsize, ARCH_DMA_MINALIGN);
+ ueth->rxbuf = memalign(ARCH_DMA_MINALIGN, rxsize);
if (!ueth->rxbuf)
return -ENOMEM;
diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c
index 77a1567a94..7d88008f74 100644
--- a/drivers/usb/gadget/f_dfu.c
+++ b/drivers/usb/gadget/f_dfu.c
@@ -44,6 +44,8 @@ struct f_dfu {
unsigned int poll_timeout;
};
+struct dfu_entity *dfu_defer_flush;
+
typedef int (*dfu_state_fn) (struct f_dfu *,
const struct usb_ctrlrequest *,
struct usb_gadget *,
@@ -167,14 +169,7 @@ static void dnload_request_complete(struct usb_ep *ep, struct usb_request *req)
static void dnload_request_flush(struct usb_ep *ep, struct usb_request *req)
{
struct f_dfu *f_dfu = req->context;
- int ret;
-
- ret = dfu_flush(dfu_get_entity(f_dfu->altsetting), req->buf,
- req->length, f_dfu->blk_seq_num);
- if (ret) {
- f_dfu->dfu_status = DFU_STATUS_errUNKNOWN;
- f_dfu->dfu_state = DFU_STATE_dfuERROR;
- }
+ dfu_set_defer_flush(dfu_get_entity(f_dfu->altsetting));
}
static inline int dfu_get_manifest_timeout(struct dfu_entity *dfu)
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index 87e54ebec7..a54b4eebcc 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -382,7 +382,7 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req)
strsep(&cmd, ":");
if (!cmd) {
- error("missing variable\n");
+ error("missing variable");
fastboot_tx_write_str("FAILmissing var");
return;
}
@@ -413,7 +413,7 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req)
else
strcpy(response, "FAILValue not set");
} else {
- error("unknown variable: %s\n", cmd);
+ printf("WARNING: unknown variable: %s\n", cmd);
strcpy(response, "FAILVariable not implemented");
}
fastboot_tx_write_str(response);
@@ -561,7 +561,7 @@ static void cb_flash(struct usb_ep *ep, struct usb_request *req)
strsep(&cmd, ":");
if (!cmd) {
- error("missing partition name\n");
+ error("missing partition name");
fastboot_tx_write_str("FAILmissing partition name");
return;
}
@@ -683,7 +683,7 @@ static void rx_handler_command(struct usb_ep *ep, struct usb_request *req)
}
if (!func_cb) {
- error("unknown command: %s\n", cmdbuf);
+ error("unknown command: %s", cmdbuf);
fastboot_tx_write_str("FAILunknown command");
} else {
if (req->actual < req->length) {
@@ -691,7 +691,7 @@ static void rx_handler_command(struct usb_ep *ep, struct usb_request *req)
buf[req->actual] = 0;
func_cb(ep, req);
} else {
- error("buffer overflow\n");
+ error("buffer overflow");
fastboot_tx_write_str("FAILbuffer overflow");
}
}
diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c
index 84114c5df9..4444988e36 100644
--- a/drivers/usb/host/ehci-generic.c
+++ b/drivers/usb/host/ehci-generic.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <clk.h>
+#include <asm/io.h>
#include <dm.h>
#include "ehci.h"
@@ -20,7 +21,7 @@ struct generic_ehci {
static int ehci_usb_probe(struct udevice *dev)
{
- struct ehci_hccr *hccr = (struct ehci_hccr *)dev_get_addr(dev);
+ struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
int i;
@@ -36,6 +37,7 @@ static int ehci_usb_probe(struct udevice *dev)
clk_dev->name, clk_id);
}
+ hccr = map_physmem(dev_get_addr(dev), 0x100, MAP_NOCACHE);
hcor = (struct ehci_hcor *)((uintptr_t)hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index c664b1629e..8f259bee4f 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -134,6 +134,8 @@ static void ehci_set_usbmode(struct ehci_ctrl *ctrl)
tmp |= USBMODE_CM_HC;
#if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
tmp |= USBMODE_BE;
+#else
+ tmp &= ~USBMODE_BE;
#endif
ehci_writel(reg_ptr, tmp);
}
@@ -245,7 +247,7 @@ static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
idx = 0;
while (idx < QT_BUFFER_CNT) {
- td->qt_buffer[idx] = cpu_to_hc32(addr);
+ td->qt_buffer[idx] = cpu_to_hc32(virt_to_phys((void *)addr));
td->qt_buffer_hi[idx] = 0;
next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
delta = next - addr;
@@ -398,7 +400,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
* qh_overlay.qt_next ...... 13-10 H
* - qh_overlay.qt_altnext
*/
- qh->qh_link = cpu_to_hc32((unsigned long)&ctrl->qh_list | QH_LINK_TYPE_QH);
+ qh->qh_link = cpu_to_hc32(virt_to_phys(&ctrl->qh_list) | QH_LINK_TYPE_QH);
c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe);
maxpacket = usb_maxpacket(dev, pipe);
endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
@@ -415,7 +417,6 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
tdp = &qh->qh_overlay.qt_next;
-
if (req != NULL) {
/*
* Setup request qTD (3.5 in ehci-r10.pdf)
@@ -438,7 +439,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
goto fail;
}
/* Update previous qTD! */
- *tdp = cpu_to_hc32((unsigned long)&qtd[qtd_counter]);
+ *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
tdp = &qtd[qtd_counter++].qt_next;
toggle = 1;
}
@@ -497,7 +498,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
goto fail;
}
/* Update previous qTD! */
- *tdp = cpu_to_hc32((unsigned long)&qtd[qtd_counter]);
+ *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
tdp = &qtd[qtd_counter++].qt_next;
/*
* Data toggle has to be adjusted since the qTD transfer
@@ -528,11 +529,11 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
qtd[qtd_counter].qt_token = cpu_to_hc32(token);
/* Update previous qTD! */
- *tdp = cpu_to_hc32((unsigned long)&qtd[qtd_counter]);
+ *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
tdp = &qtd[qtd_counter++].qt_next;
}
- ctrl->qh_list.qh_link = cpu_to_hc32((unsigned long)qh | QH_LINK_TYPE_QH);
+ ctrl->qh_list.qh_link = cpu_to_hc32(virt_to_phys(qh) | QH_LINK_TYPE_QH);
/* Flush dcache */
flush_dcache_range((unsigned long)&ctrl->qh_list,
@@ -542,7 +543,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
/* Set async. queue head pointer. */
- ehci_writel(&ctrl->hcor->or_asynclistaddr, (unsigned long)&ctrl->qh_list);
+ ehci_writel(&ctrl->hcor->or_asynclistaddr, virt_to_phys(&ctrl->qh_list));
usbsts = ehci_readl(&ctrl->hcor->or_usbsts);
ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f));
@@ -989,7 +990,7 @@ static int ehci_common_init(struct ehci_ctrl *ctrl, uint tweaks)
/* Set head of reclaim list */
memset(qh_list, 0, sizeof(*qh_list));
- qh_list->qh_link = cpu_to_hc32((unsigned long)qh_list | QH_LINK_TYPE_QH);
+ qh_list->qh_link = cpu_to_hc32(virt_to_phys(qh_list) | QH_LINK_TYPE_QH);
qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
QH_ENDPT1_EPS(USB_SPEED_HIGH));
qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
@@ -1001,7 +1002,7 @@ static int ehci_common_init(struct ehci_ctrl *ctrl, uint tweaks)
ALIGN_END_ADDR(struct QH, qh_list, 1));
/* Set async. queue head pointer. */
- ehci_writel(&ctrl->hcor->or_asynclistaddr, (unsigned long)qh_list);
+ ehci_writel(&ctrl->hcor->or_asynclistaddr, virt_to_phys(qh_list));
/*
* Set up periodic list
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
index b41c04a8b3..826b3fe580 100644
--- a/drivers/usb/host/ehci.h
+++ b/drivers/usb/host/ehci.h
@@ -102,8 +102,9 @@ struct usb_linux_config_descriptor {
} __attribute__ ((packed));
#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
-#define ehci_readl(x) (*((volatile u32 *)(x)))
-#define ehci_writel(a, b) (*((volatile u32 *)(a)) = ((volatile u32)b))
+#define ehci_readl(x) cpu_to_be32((*((volatile u32 *)(x))))
+#define ehci_writel(a, b) (*((volatile u32 *)(a)) = \
+ cpu_to_be32(((volatile u32)b)))
#else
#define ehci_readl(x) cpu_to_le32((*((volatile u32 *)(x))))
#define ehci_writel(a, b) (*((volatile u32 *)(a)) = \
generated by cgit (git 2.34.1) at 2025-01-13 21:44:02 +0000