summaryrefslogtreecommitdiff
path: root/drivers
diff options
context:
space:
mode:
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/uniphier/clk-uniphier-core.c2
-rw-r--r--drivers/misc/i2c_eeprom.c4
-rw-r--r--drivers/mmc/fsl_esdhc.c53
-rw-r--r--drivers/net/phy/Kconfig8
-rw-r--r--drivers/pci/pcie_imx.c38
-rw-r--r--drivers/power/regulator/pfuze100.c14
-rw-r--r--drivers/reset/reset-uniphier.c18
7 files changed, 97 insertions, 40 deletions
diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c
index d88bd62812..0fb48541b9 100644
--- a/drivers/clk/uniphier/clk-uniphier-core.c
+++ b/drivers/clk/uniphier/clk-uniphier-core.c
@@ -121,7 +121,7 @@ static ulong uniphier_clk_set_rate(struct clk *clk, ulong rate)
return best_rate;
}
-const struct clk_ops uniphier_clk_ops = {
+static const struct clk_ops uniphier_clk_ops = {
.enable = uniphier_clk_enable,
.get_rate = uniphier_clk_get_rate,
.set_rate = uniphier_clk_set_rate,
diff --git a/drivers/misc/i2c_eeprom.c b/drivers/misc/i2c_eeprom.c
index da6e2b05f7..a14e83225b 100644
--- a/drivers/misc/i2c_eeprom.c
+++ b/drivers/misc/i2c_eeprom.c
@@ -42,7 +42,7 @@ static int i2c_eeprom_std_write(struct udevice *dev, int offset,
return -ENODEV;
}
-struct i2c_eeprom_ops i2c_eeprom_std_ops = {
+static const struct i2c_eeprom_ops i2c_eeprom_std_ops = {
.read = i2c_eeprom_std_read,
.write = i2c_eeprom_std_write,
};
@@ -59,7 +59,7 @@ static int i2c_eeprom_std_ofdata_to_platdata(struct udevice *dev)
return 0;
}
-int i2c_eeprom_std_probe(struct udevice *dev)
+static int i2c_eeprom_std_probe(struct udevice *dev)
{
return 0;
}
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 5ee712f09b..73748c5658 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -521,7 +521,13 @@ out:
static void set_sysctl(struct mmc *mmc, uint clock)
{
- int div, pre_div;
+ int div = 1;
+#ifdef ARCH_MXC
+ int pre_div = 1;
+#else
+ int pre_div = 2;
+#endif
+ int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
struct fsl_esdhc_priv *priv = mmc->priv;
struct fsl_esdhc *regs = priv->esdhc_regs;
int sdhc_clk = priv->sdhc_clk;
@@ -530,18 +536,13 @@ static void set_sysctl(struct mmc *mmc, uint clock)
if (clock < mmc->cfg->f_min)
clock = mmc->cfg->f_min;
- if (sdhc_clk / 16 > clock) {
- for (pre_div = 2; pre_div < 256; pre_div *= 2)
- if ((sdhc_clk / pre_div) <= (clock * 16))
- break;
- } else
- pre_div = 2;
+ while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
+ pre_div *= 2;
- for (div = 1; div <= 16; div++)
- if ((sdhc_clk / (div * pre_div)) <= clock)
- break;
+ while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
+ div++;
- pre_div >>= mmc->ddr_mode ? 2 : 1;
+ pre_div >>= 1;
div -= 1;
clk = (pre_div << 8) | (div << 4);
@@ -723,20 +724,6 @@ static const struct mmc_ops esdhc_ops = {
.getcd = esdhc_getcd,
};
-static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
- struct fsl_esdhc_priv *priv)
-{
- if (!cfg || !priv)
- return -EINVAL;
-
- priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
- priv->bus_width = cfg->max_bus_width;
- priv->sdhc_clk = cfg->sdhc_clk;
- priv->wp_enable = cfg->wp_enable;
-
- return 0;
-};
-
static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
{
struct fsl_esdhc *regs;
@@ -833,6 +820,21 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
return 0;
}
+#ifndef CONFIG_DM_MMC
+static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
+ struct fsl_esdhc_priv *priv)
+{
+ if (!cfg || !priv)
+ return -EINVAL;
+
+ priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
+ priv->bus_width = cfg->max_bus_width;
+ priv->sdhc_clk = cfg->sdhc_clk;
+ priv->wp_enable = cfg->wp_enable;
+
+ return 0;
+};
+
int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
{
struct fsl_esdhc_priv *priv;
@@ -871,6 +873,7 @@ int fsl_esdhc_mmc_init(bd_t *bis)
cfg->sdhc_clk = gd->arch.sdhc_clk;
return fsl_esdhc_initialize(bis, cfg);
}
+#endif
#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
void mmc_adapter_card_type_ident(void)
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 1afd8097b2..0230852244 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -92,6 +92,14 @@ config PHY_MICREL_KSZ9031
endif # PHY_MICREL
+config PHY_MICREL_KSZ9021
+ bool "Micrel KSZ9021 Ethernet PHYs support"
+ depends on PHY_MICREL
+ help
+ KSZ9021 is a completely integrated triple speed (10Base-T/100Base-TX/1000Base-T)
+ Ethernet Physical Layer Transceiver for transmission and reception of data over
+ standard CAT-5 unshielded twisted pair (UTP) cable.
+
config PHY_MSCC
bool "Microsemi Corp Ethernet PHYs support"
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index 732d59d711..eab0a2b602 100644
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -42,6 +42,9 @@
/* PCIe Port Logic registers (memory-mapped) */
#define PL_OFFSET 0x700
+#define PCIE_PL_PFLR (PL_OFFSET + 0x08)
+#define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
+#define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
#define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4)
@@ -445,6 +448,36 @@ static int imx6_pcie_assert_core_reset(void)
/* Power up PCIe PHY */
setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
#else
+ /*
+ * If the bootloader already enabled the link we need some special
+ * handling to get the core back into a state where it is safe to
+ * touch it for configuration. As there is no dedicated reset signal
+ * wired up for MX6QDL, we need to manually force LTSSM into "detect"
+ * state before completely disabling LTSSM, which is a prerequisite
+ * for core configuration.
+ *
+ * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
+ * indication that the bootloader activated the link.
+ */
+ if (is_mx6dq()) {
+ u32 val, gpr1, gpr12;
+
+ gpr1 = readl(&iomuxc_regs->gpr[1]);
+ gpr12 = readl(&iomuxc_regs->gpr[12]);
+ if ((gpr1 & IOMUXC_GPR1_PCIE_REF_CLK_EN) &&
+ (gpr12 & IOMUXC_GPR12_PCIE_CTL_2)) {
+ val = readl(MX6_DBI_ADDR + PCIE_PL_PFLR);
+ val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
+ val |= PCIE_PL_PFLR_FORCE_LINK;
+
+ imx_pcie_fix_dabt_handler(true);
+ writel(val, MX6_DBI_ADDR + PCIE_PL_PFLR);
+ imx_pcie_fix_dabt_handler(false);
+
+ gpr12 &= ~IOMUXC_GPR12_PCIE_CTL_2;
+ writel(val, &iomuxc_regs->gpr[12]);
+ }
+ }
setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
#endif
@@ -652,6 +685,11 @@ void imx_pcie_init(void)
}
}
+void imx_pcie_remove(void)
+{
+ imx6_pcie_assert_core_reset();
+}
+
/* Probe function. */
void pci_init_board(void)
{
diff --git a/drivers/power/regulator/pfuze100.c b/drivers/power/regulator/pfuze100.c
index 4702161bdf..02f3894445 100644
--- a/drivers/power/regulator/pfuze100.c
+++ b/drivers/power/regulator/pfuze100.c
@@ -1,3 +1,11 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
#include <common.h>
#include <fdtdec.h>
#include <errno.h>
@@ -306,7 +314,7 @@ static int pfuze100_regulator_probe(struct udevice *dev)
static int pfuze100_regulator_mode(struct udevice *dev, int op, int *opmode)
{
- unsigned char val;
+ int val;
struct pfuze100_regulator_platdata *plat = dev_get_platdata(dev);
struct pfuze100_regulator_desc *desc = plat->desc;
@@ -376,7 +384,7 @@ static int pfuze100_regulator_mode(struct udevice *dev, int op, int *opmode)
static int pfuze100_regulator_enable(struct udevice *dev, int op, bool *enable)
{
- unsigned char val;
+ int val;
int ret, on_off;
struct dm_regulator_uclass_platdata *uc_pdata =
dev_get_uclass_platdata(dev);
@@ -440,7 +448,7 @@ static int pfuze100_regulator_enable(struct udevice *dev, int op, bool *enable)
static int pfuze100_regulator_val(struct udevice *dev, int op, int *uV)
{
int i;
- unsigned char val;
+ int val;
struct pfuze100_regulator_platdata *plat = dev_get_platdata(dev);
struct pfuze100_regulator_desc *desc = plat->desc;
struct dm_regulator_uclass_platdata *uc_pdata =
diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c
index e98df43bdb..17e971a427 100644
--- a/drivers/reset/reset-uniphier.c
+++ b/drivers/reset/reset-uniphier.c
@@ -56,12 +56,12 @@ struct uniphier_reset_data {
#define UNIPHIER_PRO4_SYS_RESET_USB3(id, ch) \
UNIPHIER_RESETX((id), 0x2000 + 0x4 * (ch), 17)
-const struct uniphier_reset_data uniphier_sld3_sys_reset_data[] = {
+static const struct uniphier_reset_data uniphier_sld3_sys_reset_data[] = {
UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* Ether, HSC, MIO */
UNIPHIER_RESET_END,
};
-const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
+static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, MIO, RLE */
UNIPHIER_PRO4_SYS_RESET_GIO(12), /* Ether, SATA, USB3 */
UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
@@ -69,7 +69,7 @@ const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
UNIPHIER_RESET_END,
};
-const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = {
+static const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = {
UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC */
UNIPHIER_PRO4_SYS_RESET_GIO(12), /* PCIe, USB3 */
UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
@@ -77,7 +77,7 @@ const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = {
UNIPHIER_RESET_END,
};
-const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
+static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, RLE */
UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
UNIPHIER_PRO4_SYS_RESET_USB3(15, 1),
@@ -91,12 +91,12 @@ const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
UNIPHIER_RESET_END,
};
-const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = {
+static const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = {
UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC, MIO */
UNIPHIER_RESET_END,
};
-const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
+static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC */
UNIPHIER_LD20_SYS_RESET_GIO(12), /* PCIe, USB3 */
UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */
@@ -125,7 +125,7 @@ const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
#define UNIPHIER_MIO_RESET_DMAC(id) \
UNIPHIER_RESETX((id), 0x110, 17)
-const struct uniphier_reset_data uniphier_mio_reset_data[] = {
+static const struct uniphier_reset_data uniphier_mio_reset_data[] = {
UNIPHIER_MIO_RESET_SD(0, 0),
UNIPHIER_MIO_RESET_SD(1, 1),
UNIPHIER_MIO_RESET_SD(2, 2),
@@ -155,7 +155,7 @@ const struct uniphier_reset_data uniphier_mio_reset_data[] = {
#define UNIPHIER_PERI_RESET_FI2C(id, ch) \
UNIPHIER_RESETX((id), 0x114, 24 + (ch))
-const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = {
+static const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = {
UNIPHIER_PERI_RESET_UART(0, 0),
UNIPHIER_PERI_RESET_UART(1, 1),
UNIPHIER_PERI_RESET_UART(2, 2),
@@ -168,7 +168,7 @@ const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = {
UNIPHIER_RESET_END,
};
-const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = {
+static const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = {
UNIPHIER_PERI_RESET_UART(0, 0),
UNIPHIER_PERI_RESET_UART(1, 1),
UNIPHIER_PERI_RESET_UART(2, 2),
generated by cgit (git 2.34.1) at 2025-01-21 11:55:36 +0000