diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/misc/ds4510.c | 22 | ||||
| -rw-r--r-- | drivers/misc/ds4510.h | 53 |
2 files changed, 63 insertions, 12 deletions
diff --git a/drivers/misc/ds4510.c b/drivers/misc/ds4510.c index c08a0bee63..9ffdafc992 100644 --- a/drivers/misc/ds4510.c +++ b/drivers/misc/ds4510.c @@ -12,7 +12,7 @@ #include <common.h> #include <i2c.h> #include <command.h> -#include <ds4510.h> +#include "ds4510.h" /* Default to an address that hopefully won't corrupt other i2c devices */ #ifndef CONFIG_SYS_I2C_DS4510_ADDR @@ -35,7 +35,7 @@ enum { /* * Write to DS4510, taking page boundaries into account */ -int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count) +static int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count) { int wrlen; int i = 0; @@ -64,7 +64,7 @@ int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count) /* * General read from DS4510 */ -int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count) +static int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count) { return i2c_read(chip, offset, 1, buf, count); } @@ -74,7 +74,7 @@ int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count) * nv = 0 - Writes to SEEPROM registers behave like EEPROM * nv = 1 - Writes to SEEPROM registers behave like SRAM */ -int ds4510_see_write(uint8_t chip, uint8_t nv) +static int ds4510_see_write(uint8_t chip, uint8_t nv) { uint8_t data; @@ -92,7 +92,7 @@ int ds4510_see_write(uint8_t chip, uint8_t nv) /* * Write de-assertion of reset signal delay */ -int ds4510_rstdelay_write(uint8_t chip, uint8_t delay) +static int ds4510_rstdelay_write(uint8_t chip, uint8_t delay) { uint8_t data; @@ -108,7 +108,7 @@ int ds4510_rstdelay_write(uint8_t chip, uint8_t delay) /* * Write pullup characteristics of IO pins */ -int ds4510_pullup_write(uint8_t chip, uint8_t val) +static int ds4510_pullup_write(uint8_t chip, uint8_t val) { val &= DS4510_IO_MASK; @@ -118,7 +118,7 @@ int ds4510_pullup_write(uint8_t chip, uint8_t val) /* * Read pullup characteristics of IO pins */ -int ds4510_pullup_read(uint8_t chip) +static int ds4510_pullup_read(uint8_t chip) { uint8_t val; @@ -131,7 +131,7 @@ int ds4510_pullup_read(uint8_t chip) /* * Write drive level of IO pins */ -int ds4510_gpio_write(uint8_t chip, uint8_t val) +static int ds4510_gpio_write(uint8_t chip, uint8_t val) { uint8_t data; int i; @@ -155,7 +155,7 @@ int ds4510_gpio_write(uint8_t chip, uint8_t val) /* * Read drive level of IO pins */ -int ds4510_gpio_read(uint8_t chip) +static int ds4510_gpio_read(uint8_t chip) { uint8_t data; int val = 0; @@ -175,7 +175,7 @@ int ds4510_gpio_read(uint8_t chip) /* * Read physical level of IO pins */ -int ds4510_gpio_read_val(uint8_t chip) +static int ds4510_gpio_read_val(uint8_t chip) { uint8_t val; @@ -185,7 +185,6 @@ int ds4510_gpio_read_val(uint8_t chip) return val & DS4510_IO_MASK; } -#ifdef CONFIG_CMD_DS4510 /* * Display DS4510 information */ @@ -384,4 +383,3 @@ U_BOOT_CMD( "ds4510 sram write addr off cnt\n" " - read/write 'cnt' bytes at SRAM offset 'off'" ); -#endif /* CONFIG_CMD_DS4510 */ diff --git a/drivers/misc/ds4510.h b/drivers/misc/ds4510.h new file mode 100644 index 0000000000..a6c6c58cc4 --- /dev/null +++ b/drivers/misc/ds4510.h @@ -0,0 +1,53 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __DS4510_H_ +#define __DS4510_H_ + +/* General defines */ +#define DS4510_NUM_IO 0x04 +#define DS4510_IO_MASK ((1 << DS4510_NUM_IO) - 1) +#define DS4510_EEPROM_PAGE_WRITE_DELAY_MS 20 + +/* EEPROM from 0x00 - 0x39 */ +#define DS4510_EEPROM 0x00 +#define DS4510_EEPROM_SIZE 0x40 +#define DS4510_EEPROM_PAGE_SIZE 0x08 +#define DS4510_EEPROM_PAGE_OFFSET(x) ((x) & (DS4510_EEPROM_PAGE_SIZE - 1)) + +/* SEEPROM from 0xf0 - 0xf7 */ +#define DS4510_SEEPROM 0xf0 +#define DS4510_SEEPROM_SIZE 0x08 + +/* Registers overlapping SEEPROM from 0xf0 - 0xf7 */ +#define DS4510_PULLUP 0xF0 +#define DS4510_PULLUP_DIS 0x00 +#define DS4510_PULLUP_EN 0x01 +#define DS4510_RSTDELAY 0xF1 +#define DS4510_RSTDELAY_MASK 0x03 +#define DS4510_RSTDELAY_125 0x00 +#define DS4510_RSTDELAY_250 0x01 +#define DS4510_RSTDELAY_500 0x02 +#define DS4510_RSTDELAY_1000 0x03 +#define DS4510_IO3 0xF4 +#define DS4510_IO2 0xF5 +#define DS4510_IO1 0xF6 +#define DS4510_IO0 0xF7 + +/* Status configuration registers from 0xf8 - 0xf9*/ +#define DS4510_IO_STATUS 0xF8 +#define DS4510_CFG 0xF9 +#define DS4510_CFG_READY 0x80 +#define DS4510_CFG_TRIP_POINT 0x40 +#define DS4510_CFG_RESET 0x20 +#define DS4510_CFG_SEE 0x10 +#define DS4510_CFG_SWRST 0x08 + +/* SRAM from 0xfa - 0xff */ +#define DS4510_SRAM 0xfa +#define DS4510_SRAM_SIZE 0x06 + +#endif /* __DS4510_H_ */ |