diff options
Diffstat (limited to 'drivers')
27 files changed, 994 insertions, 481 deletions
diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c index 634f0717c6..63116e0bac 100644 --- a/drivers/clk/clk_stm32f.c +++ b/drivers/clk/clk_stm32f.c @@ -12,7 +12,6 @@ #include <asm/io.h> #include <asm/arch/stm32.h> -#include <asm/arch/stm32_periph.h> #include <asm/arch/stm32_pwr.h> #include <dt-bindings/mfd/stm32f7-rcc.h> @@ -88,6 +87,12 @@ */ #define RCC_APB2ENR_SYSCFGEN BIT(14) +enum periph_clock { + SYSCFG_CLOCK_CFG, + TIMER2_CLOCK_CFG, + STMMAC_CLOCK_CFG, +}; + struct stm32_clk_info stm32f4_clk_info = { /* 180 MHz */ .sys_pll_psc = { diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c index 280ebb9ba2..510a00a3aa 100644 --- a/drivers/clk/rockchip/clk_rk3036.c +++ b/drivers/clk/rockchip/clk_rk3036.c @@ -347,6 +347,13 @@ static int rk3036_clk_bind(struct udevice *dev) sys_child->priv = priv; } +#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) + ret = offsetof(struct rk3036_cru, cru_softrst_con[0]); + ret = rockchip_reset_bind(dev, ret, 9); + if (ret) + debug("Warning: software reset driver bind faile\n"); +#endif + return 0; } diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c index fca6899d8b..6451c95a32 100644 --- a/drivers/clk/rockchip/clk_rk3188.c +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -590,6 +590,13 @@ static int rk3188_clk_bind(struct udevice *dev) sys_child->priv = priv; } +#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) + ret = offsetof(struct rk3188_cru, cru_softrst_con[0]); + ret = rockchip_reset_bind(dev, ret, 9); + if (ret) + debug("Warning: software reset driver bind faile\n"); +#endif + return 0; } diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index ff52b55229..c8a241355a 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -402,6 +402,13 @@ static int rk322x_clk_bind(struct udevice *dev) sys_child->priv = priv; } +#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) + ret = offsetof(struct rk322x_cru, cru_softrst_con[0]); + ret = rockchip_reset_bind(dev, ret, 9); + if (ret) + debug("Warning: software reset driver bind faile\n"); +#endif + return 0; } diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index ac53239363..b64c1071c1 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -876,6 +876,13 @@ static int rk3288_clk_bind(struct udevice *dev) sys_child->priv = priv; } +#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) + ret = offsetof(struct rk3288_cru, cru_softrst_con[0]); + ret = rockchip_reset_bind(dev, ret, 12); + if (ret) + debug("Warning: software reset driver bind faile\n"); +#endif + return 0; } diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index 4d522a7816..fa0c777044 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -614,6 +614,13 @@ static int rk3328_clk_bind(struct udevice *dev) sys_child->priv = priv; } +#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) + ret = offsetof(struct rk3328_cru, softrst_con[0]); + ret = rockchip_reset_bind(dev, ret, 12); + if (ret) + debug("Warning: software reset driver bind faile\n"); +#endif + return ret; } diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c index bfeef39d2a..a8319917bb 100644 --- a/drivers/clk/rockchip/clk_rk3368.c +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -543,6 +543,13 @@ static int rk3368_clk_bind(struct udevice *dev) sys_child->priv = priv; } +#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) + ret = offsetof(struct rk3368_cru, softrst_con[0]); + ret = rockchip_reset_bind(dev, ret, 15); + if (ret) + debug("Warning: software reset driver bind faile\n"); +#endif + return ret; } diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 2e85ac7df2..2f4c4e343c 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1046,6 +1046,13 @@ static int rk3399_clk_bind(struct udevice *dev) sys_child->priv = priv; } +#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) + ret = offsetof(struct rk3399_cru, softrst_con[0]); + ret = rockchip_reset_bind(dev, ret, 21); + if (ret) + debug("Warning: software reset driver bind faile\n"); +#endif + return 0; } @@ -1221,6 +1228,19 @@ static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev) return 0; } +static int rk3399_pmuclk_bind(struct udevice *dev) +{ +#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) + int ret; + + ret = offsetof(struct rk3399_pmucru, pmucru_softrst_con[0]); + ret = rockchip_reset_bind(dev, ret, 2); + if (ret) + debug("Warning: software reset driver bind faile\n"); +#endif + return 0; +} + static const struct udevice_id rk3399_pmuclk_ids[] = { { .compatible = "rockchip,rk3399-pmucru" }, { } @@ -1234,6 +1254,7 @@ U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = { .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata, .ops = &rk3399_pmuclk_ops, .probe = rk3399_pmuclk_probe, + .bind = rk3399_pmuclk_bind, #if CONFIG_IS_ENABLED(OF_PLATDATA) .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat), #endif diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c index a1195486a9..224c81355e 100644 --- a/drivers/clk/rockchip/clk_rv1108.c +++ b/drivers/clk/rockchip/clk_rv1108.c @@ -240,6 +240,13 @@ static int rv1108_clk_bind(struct udevice *dev) sys_child->priv = priv; } +#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) + ret = offsetof(struct rk3368_cru, softrst_con[0]); + ret = rockchip_reset_bind(dev, ret, 13); + if (ret) + debug("Warning: software reset driver bind faile\n"); +#endif + return 0; } diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 201d7bfff9..8525679091 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -48,7 +48,6 @@ obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o obj-$(CONFIG_TCA642X) += tca642x.o obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o -obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o obj-$(CONFIG_STM32F7_GPIO) += stm32f7_gpio.o obj-$(CONFIG_GPIO_UNIPHIER) += gpio-uniphier.o obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c deleted file mode 100644 index c04cef4cb9..0000000000 --- a/drivers/gpio/stm32_gpio.c +++ /dev/null @@ -1,182 +0,0 @@ -/* - * (C) Copyright 2011 - * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com - * - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - * - * Copyright 2015 ATS Advanced Telematics Systems GmbH - * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <linux/errno.h> -#include <asm/arch/stm32.h> -#include <asm/arch/gpio.h> - -DECLARE_GLOBAL_DATA_PTR; - -static const unsigned long io_base[] = { - STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE, - STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE, - STM32_GPIOG_BASE, STM32_GPIOH_BASE, STM32_GPIOI_BASE -}; - -struct stm32_gpio_regs { - u32 moder; /* GPIO port mode */ - u32 otyper; /* GPIO port output type */ - u32 ospeedr; /* GPIO port output speed */ - u32 pupdr; /* GPIO port pull-up/pull-down */ - u32 idr; /* GPIO port input data */ - u32 odr; /* GPIO port output data */ - u32 bsrr; /* GPIO port bit set/reset */ - u32 lckr; /* GPIO port configuration lock */ - u32 afr[2]; /* GPIO alternate function */ -}; - -#define CHECK_DSC(x) (!x || x->port > 8 || x->pin > 15) -#define CHECK_CTL(x) (!x || x->af > 15 || x->mode > 3 || x->otype > 1 || \ - x->pupd > 2 || x->speed > 3) - -int stm32_gpio_config(const struct stm32_gpio_dsc *dsc, - const struct stm32_gpio_ctl *ctl) -{ - struct stm32_gpio_regs *gpio_regs; - u32 i; - int rv; - - if (CHECK_DSC(dsc)) { - rv = -EINVAL; - goto out; - } - if (CHECK_CTL(ctl)) { - rv = -EINVAL; - goto out; - } - - gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port]; - - i = (dsc->pin & 0x07) * 4; - clrsetbits_le32(&gpio_regs->afr[dsc->pin >> 3], 0xF << i, ctl->af << i); - - i = dsc->pin * 2; - - clrsetbits_le32(&gpio_regs->moder, 0x3 << i, ctl->mode << i); - clrsetbits_le32(&gpio_regs->otyper, 0x3 << i, ctl->otype << i); - clrsetbits_le32(&gpio_regs->ospeedr, 0x3 << i, ctl->speed << i); - clrsetbits_le32(&gpio_regs->pupdr, 0x3 << i, ctl->pupd << i); - - rv = 0; -out: - return rv; -} - -int stm32_gpout_set(const struct stm32_gpio_dsc *dsc, int state) -{ - struct stm32_gpio_regs *gpio_regs; - int rv; - - if (CHECK_DSC(dsc)) { - rv = -EINVAL; - goto out; - } - - gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port]; - - if (state) - writel(1 << dsc->pin, &gpio_regs->bsrr); - else - writel(1 << (dsc->pin + 16), &gpio_regs->bsrr); - - rv = 0; -out: - return rv; -} - -int stm32_gpin_get(const struct stm32_gpio_dsc *dsc) -{ - struct stm32_gpio_regs *gpio_regs; - int rv; - - if (CHECK_DSC(dsc)) { - rv = -EINVAL; - goto out; - } - - gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port]; - rv = readl(&gpio_regs->idr) & (1 << dsc->pin); -out: - return rv; -} - -/* Common GPIO API */ - -int gpio_request(unsigned gpio, const char *label) -{ - return 0; -} - -int gpio_free(unsigned gpio) -{ - return 0; -} - -int gpio_direction_input(unsigned gpio) -{ - struct stm32_gpio_dsc dsc; - struct stm32_gpio_ctl ctl; - - dsc.port = stm32_gpio_to_port(gpio); - dsc.pin = stm32_gpio_to_pin(gpio); - ctl.af = STM32_GPIO_AF0; - ctl.mode = STM32_GPIO_MODE_IN; - ctl.otype = STM32_GPIO_OTYPE_PP; - ctl.pupd = STM32_GPIO_PUPD_NO; - ctl.speed = STM32_GPIO_SPEED_50M; - - return stm32_gpio_config(&dsc, &ctl); -} - -int gpio_direction_output(unsigned gpio, int value) -{ - struct stm32_gpio_dsc dsc; - struct stm32_gpio_ctl ctl; - int res; - - dsc.port = stm32_gpio_to_port(gpio); - dsc.pin = stm32_gpio_to_pin(gpio); - ctl.af = STM32_GPIO_AF0; - ctl.mode = STM32_GPIO_MODE_OUT; - ctl.pupd = STM32_GPIO_PUPD_NO; - ctl.speed = STM32_GPIO_SPEED_50M; - - res = stm32_gpio_config(&dsc, &ctl); - if (res < 0) - goto out; - res = stm32_gpout_set(&dsc, value); -out: - return res; -} - -int gpio_get_value(unsigned gpio) -{ - struct stm32_gpio_dsc dsc; - - dsc.port = stm32_gpio_to_port(gpio); - dsc.pin = stm32_gpio_to_pin(gpio); - - return stm32_gpin_get(&dsc); -} - -int gpio_set_value(unsigned gpio, int value) -{ - struct stm32_gpio_dsc dsc; - - dsc.port = stm32_gpio_to_port(gpio); - dsc.pin = stm32_gpio_to_pin(gpio); - - return stm32_gpout_set(&dsc, value); -} diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index d42d915f17..ee1cc3ab24 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -160,12 +160,12 @@ config FTMAC100 This MAC is present in Andestech SoCs. config MVNETA - bool "Marvell Armada 385 network interface support" - depends on ARMADA_XP || ARMADA_38X + bool "Marvell Armada XP/385/3700 network interface support" + depends on ARMADA_XP || ARMADA_38X || ARMADA_3700 select PHYLIB help This driver supports the network interface units in the - Marvell ARMADA XP and 38X SoCs + Marvell ARMADA XP, ARMADA 38X and ARMADA 3700 SoCs config MVPP2 bool "Marvell Armada 375/7K/8K network interface support" diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 5eb12efbf5..5410897e40 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -29,7 +29,6 @@ obj-$(CONFIG_SH4_PCI) += pci_sh4.o obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o -obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o diff --git a/drivers/pci/tsi108_pci.c b/drivers/pci/tsi108_pci.c deleted file mode 100644 index d48e1e6fe6..0000000000 --- a/drivers/pci/tsi108_pci.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * (C) Copyright 2004 Tundra Semiconductor Corp. - * Alex Bounine <alexandreb@tundra.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * PCI initialisation for the Tsi108 EMU board. - */ - -#include <config.h> - -#include <common.h> -#include <pci.h> -#include <asm/io.h> -#include <tsi108.h> -#if defined(CONFIG_OF_LIBFDT) -#include <libfdt.h> -#include <fdt_support.h> -#endif - -struct pci_controller local_hose; - -void tsi108_clear_pci_error (void) -{ - u32 err_stat, err_addr, pci_stat; - - /* - * Quietly clear errors signalled as result of PCI/X configuration read - * requests. - */ - /* Read PB Error Log Registers */ - err_stat = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE + - TSI108_PB_REG_OFFSET + PB_ERRCS); - err_addr = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE + - TSI108_PB_REG_OFFSET + PB_AERR); - if (err_stat & PB_ERRCS_ES) { - /* Clear PCI/X bus errors if applicable */ - if ((err_addr & 0xFF000000) == CONFIG_SYS_PCI_CFG_BASE) { - /* Clear error flag */ - *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + - TSI108_PB_REG_OFFSET + PB_ERRCS) = - PB_ERRCS_ES; - - /* Clear read error reported in PB_ISR */ - *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + - TSI108_PB_REG_OFFSET + PB_ISR) = - PB_ISR_PBS_RD_ERR; - - /* Clear errors reported by PCI CSR (Normally Master Abort) */ - pci_stat = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE + - TSI108_PCI_REG_OFFSET + - PCI_CSR); - *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE + - TSI108_PCI_REG_OFFSET + PCI_CSR) = - pci_stat; - - *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE + - TSI108_PCI_REG_OFFSET + - PCI_IRP_STAT) = PCI_IRP_STAT_P_CSR; - } - } - - return; -} - -unsigned int __get_pci_config_dword (u32 addr) -{ - unsigned int retval; - - __asm__ __volatile__ (" lwbrx %0,0,%1\n" - "1: eieio\n" - "2:\n" - ".section .fixup,\"ax\"\n" - "3: li %0,-1\n" - " b 2b\n" - ".section __ex_table,\"a\"\n" - " .align 2\n" - " .long 1b,3b\n" - ".section .text.__get_pci_config_dword" - : "=r"(retval) : "r"(addr)); - - return (retval); -} - -static int tsi108_read_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 * value) -{ - dev &= (CONFIG_SYS_PCI_CFG_SIZE - 1); - dev |= (CONFIG_SYS_PCI_CFG_BASE | (offset & 0xfc)); - *value = __get_pci_config_dword(dev); - if (0xFFFFFFFF == *value) - tsi108_clear_pci_error (); - return 0; -} - -static int tsi108_write_config_dword (struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - dev &= (CONFIG_SYS_PCI_CFG_SIZE - 1); - dev |= (CONFIG_SYS_PCI_CFG_BASE | (offset & 0xfc)); - - out_le32 ((volatile unsigned *)dev, value); - - return 0; -} - -void pci_init_board (void) -{ - struct pci_controller *hose = (struct pci_controller *)&local_hose; - - hose->first_busno = 0; - hose->last_busno = 0xff; - - pci_set_region (hose->regions + 0, - CONFIG_SYS_PCI_MEMORY_BUS, - CONFIG_SYS_PCI_MEMORY_PHYS, - CONFIG_SYS_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - /* PCI memory space */ - pci_set_region (hose->regions + 1, - CONFIG_SYS_PCI_MEM_BUS, - CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region (hose->regions + 2, - CONFIG_SYS_PCI_IO_BUS, - CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO); - - hose->region_count = 3; - - pci_set_ops (hose, - pci_hose_read_config_byte_via_dword, - pci_hose_read_config_word_via_dword, - tsi108_read_config_dword, - pci_hose_write_config_byte_via_dword, - pci_hose_write_config_word_via_dword, - tsi108_write_config_dword); - - pci_register_hose (hose); - - hose->last_busno = pci_hose_scan (hose); - - debug ("Done PCI initialization\n"); - return; -} - -#if defined(CONFIG_OF_LIBFDT) -void ft_pci_setup(void *blob, bd_t *bd) -{ - int nodeoffset; - int tmp[2]; - const char *path; - - nodeoffset = fdt_path_offset(blob, "/aliases"); - if (nodeoffset >= 0) { - path = fdt_getprop(blob, nodeoffset, "pci", NULL); - if (path) { - tmp[0] = cpu_to_be32(local_hose.first_busno); - tmp[1] = cpu_to_be32(local_hose.last_busno); - do_fixup_by_path(blob, path, "bus-range", - &tmp, sizeof(tmp), 1); - } - } -} -#endif /* CONFIG_OF_LIBFDT */ diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig index a9388ff7e2..07d4f3e216 100644 --- a/drivers/pinctrl/mvebu/Kconfig +++ b/drivers/pinctrl/mvebu/Kconfig @@ -1,14 +1,14 @@ if ARCH_MVEBU config PINCTRL_ARMADA_37XX - depends on ARMADA_3700 + depends on ARMADA_3700 && PINCTRL_FULL bool "Armada 37xx pin control driver" help Support pin multiplexing and pin configuration control on Marvell's Armada-37xx SoC. config PINCTRL_ARMADA_8K - depends on ARMADA_8K + depends on ARMADA_8K && PINCTRL_FULL bool "Armada 7k/8k pin control driver" help Support pin multiplexing and pin configuration control on diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index 51fdfb3851..2066e11cf1 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -182,6 +182,8 @@ static struct pinctrl_ops stm32_pinctrl_ops = { }; static const struct udevice_id stm32_pinctrl_ids[] = { + { .compatible = "st,stm32f429-pinctrl" }, + { .compatible = "st,stm32f469-pinctrl" }, { .compatible = "st,stm32f746-pinctrl" }, { .compatible = "st,stm32h743-pinctrl" }, { } diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c index 6e92b2222d..ec2edd67dd 100644 --- a/drivers/ram/stm32_sdram.c +++ b/drivers/ram/stm32_sdram.c @@ -11,6 +11,9 @@ #include <ram.h> #include <asm/io.h> +#define MEM_MODE_MASK GENMASK(2, 0) +#define NOT_FOUND 0xff + DECLARE_GLOBAL_DATA_PTR; struct stm32_fmc_regs { @@ -253,9 +256,31 @@ static int stm32_fmc_ofdata_to_platdata(struct udevice *dev) { struct stm32_sdram_params *params = dev_get_platdata(dev); struct bank_params *bank_params; + struct ofnode_phandle_args args; + u32 *syscfg_base; + u32 mem_remap; ofnode bank_node; char *bank_name; u8 bank = 0; + int ret; + + mem_remap = dev_read_u32_default(dev, "st,mem_remap", NOT_FOUND); + if (mem_remap != NOT_FOUND) { + ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0, + &args); + if (ret) { + debug("%s: can't find syscon device (%d)\n", __func__, + ret); + return ret; + } + + syscfg_base = (u32 *)ofnode_get_addr(args.node); + + /* set memory mapping selection */ + clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap); + } else { + debug("%s: cannot find st,mem_remap property\n", __func__); + } dev_for_each_subnode(bank_node, dev) { /* extract the bank index from DT */ diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index ce46e2752c..3964b9eb6e 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -74,4 +74,13 @@ config AST2500_RESET resets that are supported by watchdog. The main limitation though is that some reset signals, like I2C or MISC reset multiple devices. +config RESET_ROCKCHIP + bool "Reset controller driver for Rockchip SoCs" + depends on DM_RESET && ARCH_ROCKCHIP && CLK + default y + help + Support for reset controller on rockchip SoC. The main limitation + though is that some reset signals, like I2C or MISC reset multiple + devices. + endmenu diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 252cefeed5..7d7e080c78 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -12,3 +12,4 @@ obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o +obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o diff --git a/drivers/reset/reset-rockchip.c b/drivers/reset/reset-rockchip.c new file mode 100644 index 0000000000..01047a2f71 --- /dev/null +++ b/drivers/reset/reset-rockchip.c @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <reset-uclass.h> +#include <linux/io.h> +#include <asm/arch/hardware.h> +#include <dm/lists.h> +/* + * Each reg has 16 bits reset signal for devices + * Note: Not including rk2818 and older SoCs + */ +#define ROCKCHIP_RESET_NUM_IN_REG 16 + +struct rockchip_reset_priv { + void __iomem *base; + /* Rockchip reset reg locate at cru controller */ + u32 reset_reg_offset; + /* Rockchip reset reg number */ + u32 reset_reg_num; +}; + +static int rockchip_reset_request(struct reset_ctl *reset_ctl) +{ + struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_num=%d)\n", __func__, + reset_ctl, reset_ctl->dev, reset_ctl->id, priv->reset_reg_num); + + if (reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG >= priv->reset_reg_num) + return -EINVAL; + + return 0; +} + +static int rockchip_reset_free(struct reset_ctl *reset_ctl) +{ + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl, + reset_ctl->dev, reset_ctl->id); + + return 0; +} + +static int rockchip_reset_assert(struct reset_ctl *reset_ctl) +{ + struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev); + int bank = reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG; + int offset = reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG; + + debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__, + reset_ctl, reset_ctl->dev, reset_ctl->id, + priv->base + (bank * 4)); + + rk_setreg(priv->base + (bank * 4), BIT(offset)); + + return 0; +} + +static int rockchip_reset_deassert(struct reset_ctl *reset_ctl) +{ + struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev); + int bank = reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG; + int offset = reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG; + + debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__, + reset_ctl, reset_ctl->dev, reset_ctl->id, + priv->base + (bank * 4)); + + rk_clrreg(priv->base + (bank * 4), BIT(offset)); + + return 0; +} + +struct reset_ops rockchip_reset_ops = { + .request = rockchip_reset_request, + .free = rockchip_reset_free, + .rst_assert = rockchip_reset_assert, + .rst_deassert = rockchip_reset_deassert, +}; + +static int rockchip_reset_probe(struct udevice *dev) +{ + struct rockchip_reset_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + fdt_size_t size; + + addr = dev_read_addr_size(dev, "reg", &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + if ((priv->reset_reg_offset == 0) && (priv->reset_reg_num == 0)) + return -EINVAL; + + addr += priv->reset_reg_offset; + priv->base = ioremap(addr, size); + + debug("%s(base=%p) (reg_offset=%x, reg_num=%d)\n", __func__, + priv->base, priv->reset_reg_offset, priv->reset_reg_num); + + return 0; +} + +int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number) +{ + struct udevice *rst_dev; + struct rockchip_reset_priv *priv; + int ret; + + ret = device_bind_driver_to_node(pdev, "rockchip_reset", "reset", + dev_ofnode(pdev), &rst_dev); + if (ret) { + debug("Warning: No rockchip reset driver: ret=%d\n", ret); + return ret; + } + priv = malloc(sizeof(struct rockchip_reset_priv)); + priv->reset_reg_offset = reg_offset; + priv->reset_reg_num = reg_number; + rst_dev->priv = priv; + + return 0; +} + +U_BOOT_DRIVER(rockchip_reset) = { + .name = "rockchip_reset", + .id = UCLASS_RESET, + .probe = rockchip_reset_probe, + .ops = &rockchip_reset_ops, + .priv_auto_alloc_size = sizeof(struct rockchip_reset_priv), +}; diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c deleted file mode 100644 index c793ba6e90..0000000000 --- a/drivers/serial/serial_stm32.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <dm.h> -#include <asm/io.h> -#include <serial.h> -#include <asm/arch/stm32.h> -#include <dm/platform_data/serial_stm32.h> - -struct stm32_usart { - u32 sr; - u32 dr; - u32 brr; - u32 cr1; - u32 cr2; - u32 cr3; - u32 gtpr; -}; - -#define USART_CR1_RE (1 << 2) -#define USART_CR1_TE (1 << 3) -#define USART_CR1_UE (1 << 13) - -#define USART_SR_FLAG_RXNE (1 << 5) -#define USART_SR_FLAG_TXE (1 << 7) - -#define USART_BRR_F_MASK 0xF -#define USART_BRR_M_SHIFT 4 -#define USART_BRR_M_MASK 0xFFF0 - -DECLARE_GLOBAL_DATA_PTR; - -static int stm32_serial_setbrg(struct udevice *dev, int baudrate) -{ - struct stm32_serial_platdata *plat = dev->platdata; - struct stm32_usart *const usart = plat->base; - u32 clock, int_div, frac_div, tmp; - - if (((u32)usart & STM32_BUS_MASK) == STM32_APB1PERIPH_BASE) - clock = clock_get(CLOCK_APB1); - else if (((u32)usart & STM32_BUS_MASK) == STM32_APB2PERIPH_BASE) - clock = clock_get(CLOCK_APB2); - else - return -EINVAL; - - int_div = (25 * clock) / (4 * baudrate); - tmp = ((int_div / 100) << USART_BRR_M_SHIFT) & USART_BRR_M_MASK; - frac_div = int_div - (100 * (tmp >> USART_BRR_M_SHIFT)); - tmp |= (((frac_div * 16) + 50) / 100) & USART_BRR_F_MASK; - writel(tmp, &usart->brr); - - return 0; -} - -static int stm32_serial_getc(struct udevice *dev) -{ - struct stm32_serial_platdata *plat = dev->platdata; - struct stm32_usart *const usart = plat->base; - - if ((readl(&usart->sr) & USART_SR_FLAG_RXNE) == 0) - return -EAGAIN; - - return readl(&usart->dr); -} - -static int stm32_serial_putc(struct udevice *dev, const char c) -{ - struct stm32_serial_platdata *plat = dev->platdata; - struct stm32_usart *const usart = plat->base; - - if ((readl(&usart->sr) & USART_SR_FLAG_TXE) == 0) - return -EAGAIN; - - writel(c, &usart->dr); - - return 0; -} - -static int stm32_serial_pending(struct udevice *dev, bool input) -{ - struct stm32_serial_platdata *plat = dev->platdata; - struct stm32_usart *const usart = plat->base; - - if (input) - return readl(&usart->sr) & USART_SR_FLAG_RXNE ? 1 : 0; - else - return readl(&usart->sr) & USART_SR_FLAG_TXE ? 0 : 1; -} - -static int stm32_serial_probe(struct udevice *dev) -{ - struct stm32_serial_platdata *plat = dev->platdata; - struct stm32_usart *const usart = plat->base; - setbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE); - - return 0; -} - -static const struct dm_serial_ops stm32_serial_ops = { - .putc = stm32_serial_putc, - .pending = stm32_serial_pending, - .getc = stm32_serial_getc, - .setbrg = stm32_serial_setbrg, -}; - -U_BOOT_DRIVER(serial_stm32) = { - .name = "serial_stm32", - .id = UCLASS_SERIAL, - .ops = &stm32_serial_ops, - .probe = stm32_serial_probe, - .flags = DM_FLAG_PRE_RELOC, -}; diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 102a63b8ee..c387f5e497 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -134,6 +134,14 @@ config USB_FUNCTION_SDP allows to download images into memory and execute (jump to) them using the same protocol as implemented by the i.MX family's boot ROM. +config USB_FUNCTION_ROCKUSB + bool "Enable USB rockusb gadget" + help + Rockusb protocol is widely used by Rockchip SoC based devices. It can + read/write info, image to/from devices. This enables the USB part of + the rockusb gadget.for more detail about Rockusb protocol, please see + doc/README.rockusb + endif # USB_GADGET_DOWNLOAD config USB_ETHER diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 7258099c1c..ee8bc994c5 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_USB_FUNCTION_DFU) += f_dfu.o obj-$(CONFIG_USB_FUNCTION_MASS_STORAGE) += f_mass_storage.o obj-$(CONFIG_USB_FUNCTION_FASTBOOT) += f_fastboot.o obj-$(CONFIG_USB_FUNCTION_SDP) += f_sdp.o +obj-$(CONFIG_USB_FUNCTION_ROCKUSB) += f_rockusb.o endif endif ifdef CONFIG_USB_ETHER diff --git a/drivers/usb/gadget/f_rockusb.c b/drivers/usb/gadget/f_rockusb.c new file mode 100644 index 0000000000..d5a10f1904 --- /dev/null +++ b/drivers/usb/gadget/f_rockusb.c @@ -0,0 +1,718 @@ +/* + * (C) Copyright 2017 + * + * Eddie Cai <eddie.cai.linux@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <config.h> +#include <common.h> +#include <errno.h> +#include <malloc.h> +#include <memalign.h> +#include <linux/usb/ch9.h> +#include <linux/usb/gadget.h> +#include <linux/usb/composite.h> +#include <linux/compiler.h> +#include <version.h> +#include <g_dnl.h> +#include <asm/arch/f_rockusb.h> + +static inline struct f_rockusb *func_to_rockusb(struct usb_function *f) +{ + return container_of(f, struct f_rockusb, usb_function); +} + +static struct usb_endpoint_descriptor fs_ep_in = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_DIR_IN, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = cpu_to_le16(64), +}; + +static struct usb_endpoint_descriptor fs_ep_out = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_DIR_OUT, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = cpu_to_le16(64), +}; + +static struct usb_endpoint_descriptor hs_ep_in = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_DIR_IN, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = cpu_to_le16(512), +}; + +static struct usb_endpoint_descriptor hs_ep_out = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_DIR_OUT, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = cpu_to_le16(512), +}; + +static struct usb_interface_descriptor interface_desc = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 0x00, + .bAlternateSetting = 0x00, + .bNumEndpoints = 0x02, + .bInterfaceClass = ROCKUSB_INTERFACE_CLASS, + .bInterfaceSubClass = ROCKUSB_INTERFACE_SUB_CLASS, + .bInterfaceProtocol = ROCKUSB_INTERFACE_PROTOCOL, +}; + +static struct usb_descriptor_header *rkusb_fs_function[] = { + (struct usb_descriptor_header *)&interface_desc, + (struct usb_descriptor_header *)&fs_ep_in, + (struct usb_descriptor_header *)&fs_ep_out, +}; + +static struct usb_descriptor_header *rkusb_hs_function[] = { + (struct usb_descriptor_header *)&interface_desc, + (struct usb_descriptor_header *)&hs_ep_in, + (struct usb_descriptor_header *)&hs_ep_out, + NULL, +}; + +static const char rkusb_name[] = "Rockchip Rockusb"; + +static struct usb_string rkusb_string_defs[] = { + [0].s = rkusb_name, + { } /* end of list */ +}; + +static struct usb_gadget_strings stringtab_rkusb = { + .language = 0x0409, /* en-us */ + .strings = rkusb_string_defs, +}; + +static struct usb_gadget_strings *rkusb_strings[] = { + &stringtab_rkusb, + NULL, +}; + +static struct f_rockusb *rockusb_func; +static void rx_handler_command(struct usb_ep *ep, struct usb_request *req); +static int rockusb_tx_write_csw(u32 tag, int residue, u8 status, int size); + +struct f_rockusb *get_rkusb(void) +{ + struct f_rockusb *f_rkusb = rockusb_func; + + if (!f_rkusb) { + f_rkusb = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*f_rkusb)); + if (!f_rkusb) + return 0; + + rockusb_func = f_rkusb; + memset(f_rkusb, 0, sizeof(*f_rkusb)); + } + + if (!f_rkusb->buf_head) { + f_rkusb->buf_head = memalign(CONFIG_SYS_CACHELINE_SIZE, + RKUSB_BUF_SIZE); + if (!f_rkusb->buf_head) + return 0; + + f_rkusb->buf = f_rkusb->buf_head; + memset(f_rkusb->buf_head, 0, RKUSB_BUF_SIZE); + } + return f_rkusb; +} + +static struct usb_endpoint_descriptor *rkusb_ep_desc( +struct usb_gadget *g, +struct usb_endpoint_descriptor *fs, +struct usb_endpoint_descriptor *hs) +{ + if (gadget_is_dualspeed(g) && g->speed == USB_SPEED_HIGH) + return hs; + return fs; +} + +static void rockusb_complete(struct usb_ep *ep, struct usb_request *req) +{ + int status = req->status; + + if (!status) + return; + debug("status: %d ep '%s' trans: %d\n", status, ep->name, req->actual); +} + +/* config the rockusb device*/ +static int rockusb_bind(struct usb_configuration *c, struct usb_function *f) +{ + int id; + struct usb_gadget *gadget = c->cdev->gadget; + struct f_rockusb *f_rkusb = func_to_rockusb(f); + const char *s; + + id = usb_interface_id(c, f); + if (id < 0) + return id; + interface_desc.bInterfaceNumber = id; + + id = usb_string_id(c->cdev); + if (id < 0) + return id; + + rkusb_string_defs[0].id = id; + interface_desc.iInterface = id; + + f_rkusb->in_ep = usb_ep_autoconfig(gadget, &fs_ep_in); + if (!f_rkusb->in_ep) + return -ENODEV; + f_rkusb->in_ep->driver_data = c->cdev; + + f_rkusb->out_ep = usb_ep_autoconfig(gadget, &fs_ep_out); + if (!f_rkusb->out_ep) + return -ENODEV; + f_rkusb->out_ep->driver_data = c->cdev; + + f->descriptors = rkusb_fs_function; + + if (gadget_is_dualspeed(gadget)) { + hs_ep_in.bEndpointAddress = fs_ep_in.bEndpointAddress; + hs_ep_out.bEndpointAddress = fs_ep_out.bEndpointAddress; + f->hs_descriptors = rkusb_hs_function; + } + + s = env_get("serial#"); + if (s) + g_dnl_set_serialnumber((char *)s); + + return 0; +} + +static void rockusb_unbind(struct usb_configuration *c, struct usb_function *f) +{ + /* clear the configuration*/ + memset(rockusb_func, 0, sizeof(*rockusb_func)); +} + +static void rockusb_disable(struct usb_function *f) +{ + struct f_rockusb *f_rkusb = func_to_rockusb(f); + + usb_ep_disable(f_rkusb->out_ep); + usb_ep_disable(f_rkusb->in_ep); + + if (f_rkusb->out_req) { + free(f_rkusb->out_req->buf); + usb_ep_free_request(f_rkusb->out_ep, f_rkusb->out_req); + f_rkusb->out_req = NULL; + } + if (f_rkusb->in_req) { + free(f_rkusb->in_req->buf); + usb_ep_free_request(f_rkusb->in_ep, f_rkusb->in_req); + f_rkusb->in_req = NULL; + } + if (f_rkusb->buf_head) { + free(f_rkusb->buf_head); + f_rkusb->buf_head = NULL; + f_rkusb->buf = NULL; + } +} + +static struct usb_request *rockusb_start_ep(struct usb_ep *ep) +{ + struct usb_request *req; + + req = usb_ep_alloc_request(ep, 0); + if (!req) + return NULL; + + req->length = EP_BUFFER_SIZE; + req->buf = memalign(CONFIG_SYS_CACHELINE_SIZE, EP_BUFFER_SIZE); + if (!req->buf) { + usb_ep_free_request(ep, req); + return NULL; + } + memset(req->buf, 0, req->length); + + return req; +} + +static int rockusb_set_alt(struct usb_function *f, unsigned int interface, + unsigned int alt) +{ + int ret; + struct usb_composite_dev *cdev = f->config->cdev; + struct usb_gadget *gadget = cdev->gadget; + struct f_rockusb *f_rkusb = func_to_rockusb(f); + const struct usb_endpoint_descriptor *d; + + debug("%s: func: %s intf: %d alt: %d\n", + __func__, f->name, interface, alt); + + d = rkusb_ep_desc(gadget, &fs_ep_out, &hs_ep_out); + ret = usb_ep_enable(f_rkusb->out_ep, d); + if (ret) { + printf("failed to enable out ep\n"); + return ret; + } + + f_rkusb->out_req = rockusb_start_ep(f_rkusb->out_ep); + if (!f_rkusb->out_req) { + printf("failed to alloc out req\n"); + ret = -EINVAL; + goto err; + } + f_rkusb->out_req->complete = rx_handler_command; + + d = rkusb_ep_desc(gadget, &fs_ep_in, &hs_ep_in); + ret = usb_ep_enable(f_rkusb->in_ep, d); + if (ret) { + printf("failed to enable in ep\n"); + goto err; + } + + f_rkusb->in_req = rockusb_start_ep(f_rkusb->in_ep); + if (!f_rkusb->in_req) { + printf("failed alloc req in\n"); + ret = -EINVAL; + goto err; + } + f_rkusb->in_req->complete = rockusb_complete; + + ret = usb_ep_queue(f_rkusb->out_ep, f_rkusb->out_req, 0); + if (ret) + goto err; + + return 0; +err: + rockusb_disable(f); + return ret; +} + +static int rockusb_add(struct usb_configuration *c) +{ + struct f_rockusb *f_rkusb = get_rkusb(); + int status; + + debug("%s: cdev: 0x%p\n", __func__, c->cdev); + + f_rkusb->usb_function.name = "f_rockusb"; + f_rkusb->usb_function.bind = rockusb_bind; + f_rkusb->usb_function.unbind = rockusb_unbind; + f_rkusb->usb_function.set_alt = rockusb_set_alt; + f_rkusb->usb_function.disable = rockusb_disable; + f_rkusb->usb_function.strings = rkusb_strings; + + status = usb_add_function(c, &f_rkusb->usb_function); + if (status) { + free(f_rkusb); + rockusb_func = f_rkusb; + } + return status; +} + +void rockusb_dev_init(char *dev_type, int dev_index) +{ + struct f_rockusb *f_rkusb = get_rkusb(); + + f_rkusb->dev_type = dev_type; + f_rkusb->dev_index = dev_index; +} + +DECLARE_GADGET_BIND_CALLBACK(usb_dnl_rockusb, rockusb_add); + +static int rockusb_tx_write(const char *buffer, unsigned int buffer_size) +{ + struct usb_request *in_req = rockusb_func->in_req; + int ret; + + memcpy(in_req->buf, buffer, buffer_size); + in_req->length = buffer_size; + usb_ep_dequeue(rockusb_func->in_ep, in_req); + ret = usb_ep_queue(rockusb_func->in_ep, in_req, 0); + if (ret) + printf("Error %d on queue\n", ret); + return 0; +} + +static int rockusb_tx_write_str(const char *buffer) +{ + return rockusb_tx_write(buffer, strlen(buffer)); +} + +#ifdef DEBUG +static void printcbw(char *buf) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw, + sizeof(struct fsg_bulk_cb_wrap)); + + memcpy((char *)cbw, buf, USB_BULK_CB_WRAP_LEN); + + debug("cbw: signature:%x\n", cbw->signature); + debug("cbw: tag=%x\n", cbw->tag); + debug("cbw: data_transfer_length=%d\n", cbw->data_transfer_length); + debug("cbw: flags=%x\n", cbw->flags); + debug("cbw: lun=%d\n", cbw->lun); + debug("cbw: length=%d\n", cbw->length); + debug("cbw: ucOperCode=%x\n", cbw->CDB[0]); + debug("cbw: ucReserved=%x\n", cbw->CDB[1]); + debug("cbw: dwAddress:%x %x %x %x\n", cbw->CDB[5], cbw->CDB[4], + cbw->CDB[3], cbw->CDB[2]); + debug("cbw: ucReserved2=%x\n", cbw->CDB[6]); + debug("cbw: uslength:%x %x\n", cbw->CDB[8], cbw->CDB[7]); +} + +static void printcsw(char *buf) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct bulk_cs_wrap, csw, + sizeof(struct bulk_cs_wrap)); + memcpy((char *)csw, buf, USB_BULK_CS_WRAP_LEN); + debug("csw: signature:%x\n", csw->signature); + debug("csw: tag:%x\n", csw->tag); + debug("csw: residue:%x\n", csw->residue); + debug("csw: status:%x\n", csw->status); +} +#endif + +static int rockusb_tx_write_csw(u32 tag, int residue, u8 status, int size) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct bulk_cs_wrap, csw, + sizeof(struct bulk_cs_wrap)); + csw->signature = cpu_to_le32(USB_BULK_CS_SIG); + csw->tag = tag; + csw->residue = cpu_to_be32(residue); + csw->status = status; +#ifdef DEBUG + printcsw((char *)&csw); +#endif + return rockusb_tx_write((char *)csw, size); +} + +static unsigned int rx_bytes_expected(struct usb_ep *ep) +{ + struct f_rockusb *f_rkusb = get_rkusb(); + int rx_remain = f_rkusb->dl_size - f_rkusb->dl_bytes; + unsigned int rem; + unsigned int maxpacket = ep->maxpacket; + + if (rx_remain <= 0) + return 0; + else if (rx_remain > EP_BUFFER_SIZE) + return EP_BUFFER_SIZE; + + rem = rx_remain % maxpacket; + if (rem > 0) + rx_remain = rx_remain + (maxpacket - rem); + + return rx_remain; +} + +/* usb_request complete call back to handle down load image */ +static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req) +{ + struct f_rockusb *f_rkusb = get_rkusb(); + unsigned int transfer_size = 0; + const unsigned char *buffer = req->buf; + unsigned int buffer_size = req->actual; + + transfer_size = f_rkusb->dl_size - f_rkusb->dl_bytes; + if (!f_rkusb->desc) { + char *type = f_rkusb->dev_type; + int index = f_rkusb->dev_index; + + f_rkusb->desc = blk_get_dev(type, index); + if (!f_rkusb->desc || + f_rkusb->desc->type == DEV_TYPE_UNKNOWN) { + puts("invalid mmc device\n"); + rockusb_tx_write_csw(f_rkusb->tag, 0, CSW_FAIL, + USB_BULK_CS_WRAP_LEN); + return; + } + } + + if (req->status != 0) { + printf("Bad status: %d\n", req->status); + rockusb_tx_write_csw(f_rkusb->tag, 0, CSW_FAIL, + USB_BULK_CS_WRAP_LEN); + return; + } + + if (buffer_size < transfer_size) + transfer_size = buffer_size; + + memcpy((void *)f_rkusb->buf, buffer, transfer_size); + f_rkusb->dl_bytes += transfer_size; + int blks = 0, blkcnt = transfer_size / 512; + + debug("dl %x bytes, %x blks, write lba %x, dl_size:%x, dl_bytes:%x, ", + transfer_size, blkcnt, f_rkusb->lba, f_rkusb->dl_size, + f_rkusb->dl_bytes); + blks = blk_dwrite(f_rkusb->desc, f_rkusb->lba, blkcnt, f_rkusb->buf); + if (blks != blkcnt) { + printf("failed writing to device %s: %d\n", f_rkusb->dev_type, + f_rkusb->dev_index); + rockusb_tx_write_csw(f_rkusb->tag, 0, CSW_FAIL, + USB_BULK_CS_WRAP_LEN); + return; + } + f_rkusb->lba += blkcnt; + + /* Check if transfer is done */ + if (f_rkusb->dl_bytes >= f_rkusb->dl_size) { + req->complete = rx_handler_command; + req->length = EP_BUFFER_SIZE; + f_rkusb->buf = f_rkusb->buf_head; + printf("transfer 0x%x bytes done\n", f_rkusb->dl_size); + f_rkusb->dl_size = 0; + rockusb_tx_write_csw(f_rkusb->tag, 0, CSW_GOOD, + USB_BULK_CS_WRAP_LEN); + } else { + req->length = rx_bytes_expected(ep); + if (f_rkusb->buf == f_rkusb->buf_head) + f_rkusb->buf = f_rkusb->buf_head + EP_BUFFER_SIZE; + else + f_rkusb->buf = f_rkusb->buf_head; + + debug("remain %x bytes, %x sectors\n", req->length, + req->length / 512); + } + + req->actual = 0; + usb_ep_queue(ep, req, 0); +} + +static void cb_test_unit_ready(struct usb_ep *ep, struct usb_request *req) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw, + sizeof(struct fsg_bulk_cb_wrap)); + + memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN); + + rockusb_tx_write_csw(cbw->tag, cbw->data_transfer_length, + CSW_GOOD, USB_BULK_CS_WRAP_LEN); +} + +static void cb_read_storage_id(struct usb_ep *ep, struct usb_request *req) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw, + sizeof(struct fsg_bulk_cb_wrap)); + char emmc_id[] = "EMMC "; + + printf("read storage id\n"); + memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN); + rockusb_tx_write_str(emmc_id); + rockusb_tx_write_csw(cbw->tag, cbw->data_transfer_length, CSW_GOOD, + USB_BULK_CS_WRAP_LEN); +} + +static void cb_write_lba(struct usb_ep *ep, struct usb_request *req) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw, + sizeof(struct fsg_bulk_cb_wrap)); + struct f_rockusb *f_rkusb = get_rkusb(); + int sector_count; + + memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN); + sector_count = (int)get_unaligned_be16(&cbw->CDB[7]); + f_rkusb->lba = get_unaligned_be32(&cbw->CDB[2]); + f_rkusb->dl_size = sector_count * 512; + f_rkusb->dl_bytes = 0; + f_rkusb->tag = cbw->tag; + debug("require write %x bytes, %x sectors to lba %x\n", + f_rkusb->dl_size, sector_count, f_rkusb->lba); + + if (f_rkusb->dl_size == 0) { + rockusb_tx_write_csw(cbw->tag, cbw->data_transfer_length, + CSW_FAIL, USB_BULK_CS_WRAP_LEN); + } else { + req->complete = rx_handler_dl_image; + req->length = rx_bytes_expected(ep); + } +} + +void __weak rkusb_set_reboot_flag(int flag) +{ + struct f_rockusb *f_rkusb = get_rkusb(); + + printf("rockkusb set reboot flag: %d\n", f_rkusb->reboot_flag); +} + +static void compl_do_reset(struct usb_ep *ep, struct usb_request *req) +{ + struct f_rockusb *f_rkusb = get_rkusb(); + + rkusb_set_reboot_flag(f_rkusb->reboot_flag); + do_reset(NULL, 0, 0, NULL); +} + +static void cb_reboot(struct usb_ep *ep, struct usb_request *req) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw, + sizeof(struct fsg_bulk_cb_wrap)); + struct f_rockusb *f_rkusb = get_rkusb(); + + f_rkusb->reboot_flag = 0; + memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN); + f_rkusb->reboot_flag = cbw->CDB[1]; + rockusb_func->in_req->complete = compl_do_reset; + rockusb_tx_write_csw(cbw->tag, cbw->data_transfer_length, CSW_GOOD, + USB_BULK_CS_WRAP_LEN); +} + +static void cb_not_support(struct usb_ep *ep, struct usb_request *req) +{ + ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw, + sizeof(struct fsg_bulk_cb_wrap)); + + memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN); + printf("Rockusb command %x not support yet\n", cbw->CDB[0]); + rockusb_tx_write_csw(cbw->tag, 0, CSW_FAIL, USB_BULK_CS_WRAP_LEN); +} + +static const struct cmd_dispatch_info cmd_dispatch_info[] = { + { + .cmd = K_FW_TEST_UNIT_READY, + .cb = cb_test_unit_ready, + }, + { + .cmd = K_FW_READ_FLASH_ID, + .cb = cb_read_storage_id, + }, + { + .cmd = K_FW_SET_DEVICE_ID, + .cb = cb_not_support, + }, + { + .cmd = K_FW_TEST_BAD_BLOCK, + .cb = cb_not_support, + }, + { + .cmd = K_FW_READ_10, + .cb = cb_not_support, + }, + { + .cmd = K_FW_WRITE_10, + .cb = cb_not_support, + }, + { + .cmd = K_FW_ERASE_10, + .cb = cb_not_support, + }, + { + .cmd = K_FW_WRITE_SPARE, + .cb = cb_not_support, + }, + { + .cmd = K_FW_READ_SPARE, + .cb = cb_not_support, + }, + { + .cmd = K_FW_ERASE_10_FORCE, + .cb = cb_not_support, + }, + { + .cmd = K_FW_GET_VERSION, + .cb = cb_not_support, + }, + { + .cmd = K_FW_LBA_READ_10, + .cb = cb_not_support, + }, + { + .cmd = K_FW_LBA_WRITE_10, + .cb = cb_write_lba, + }, + { + .cmd = K_FW_ERASE_SYS_DISK, + .cb = cb_not_support, + }, + { + .cmd = K_FW_SDRAM_READ_10, + .cb = cb_not_support, + }, + { + .cmd = K_FW_SDRAM_WRITE_10, + .cb = cb_not_support, + }, + { + .cmd = K_FW_SDRAM_EXECUTE, + .cb = cb_not_support, + }, + { + .cmd = K_FW_READ_FLASH_INFO, + .cb = cb_not_support, + }, + { + .cmd = K_FW_GET_CHIP_VER, + .cb = cb_not_support, + }, + { + .cmd = K_FW_LOW_FORMAT, + .cb = cb_not_support, + }, + { + .cmd = K_FW_SET_RESET_FLAG, + .cb = cb_not_support, + }, + { + .cmd = K_FW_SPI_READ_10, + .cb = cb_not_support, + }, + { + .cmd = K_FW_SPI_WRITE_10, + .cb = cb_not_support, + }, + { + .cmd = K_FW_SESSION, + .cb = cb_not_support, + }, + { + .cmd = K_FW_RESET, + .cb = cb_reboot, + }, +}; + +static void rx_handler_command(struct usb_ep *ep, struct usb_request *req) +{ + void (*func_cb)(struct usb_ep *ep, struct usb_request *req) = NULL; + + ALLOC_CACHE_ALIGN_BUFFER(struct fsg_bulk_cb_wrap, cbw, + sizeof(struct fsg_bulk_cb_wrap)); + char *cmdbuf = req->buf; + int i; + + if (req->status || req->length == 0) + return; + + memcpy((char *)cbw, req->buf, USB_BULK_CB_WRAP_LEN); +#ifdef DEBUG + printcbw(req->buf); +#endif + + for (i = 0; i < ARRAY_SIZE(cmd_dispatch_info); i++) { + if (cmd_dispatch_info[i].cmd == cbw->CDB[0]) { + func_cb = cmd_dispatch_info[i].cb; + break; + } + } + + if (!func_cb) { + printf("unknown command: %s\n", (char *)req->buf); + rockusb_tx_write_str("FAILunknown command"); + } else { + if (req->actual < req->length) { + u8 *buf = (u8 *)req->buf; + + buf[req->actual] = 0; + func_cb(ep, req); + } else { + puts("buffer overflow\n"); + rockusb_tx_write_str("FAILbuffer overflow"); + } + } + + *cmdbuf = '\0'; + req->actual = 0; + usb_ep_queue(ep, req, 0); +} diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index c79f866cf1..90b2f78ec7 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -186,6 +186,12 @@ config USB_EHCI_GENERIC ---help--- Enables support for generic EHCI controller. +config USB_EHCI_FSL + bool "Support for FSL on-chip EHCI USB controller" + default n + select CONFIG_EHCI_HCD_INIT_AFTER_RESET + ---help--- + Enables support for the on-chip EHCI controller on FSL chips. endif # USB_EHCI_HCD config USB_OHCI_HCD diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 62c431b99f..17d1fae382 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -106,14 +106,14 @@ static int ehci_fsl_probe(struct udevice *dev) ehci = (struct usb_ehci *)priv->hcd_base; hccr = (struct ehci_hccr *)(&ehci->caplength); hcor = (struct ehci_hcor *) - ((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + ((void *)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); if (ehci_fsl_init(priv, ehci, hccr, hcor) < 0) return -ENXIO; - debug("ehci-fsl: init hccr %x and hcor %x hc_length %d\n", - (u32)hccr, (u32)hcor, - (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + debug("ehci-fsl: init hccr %p and hcor %p hc_length %d\n", + (void *)hccr, (void *)hcor, + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); return ehci_register(dev, hccr, hcor, &fsl_ehci_ops, 0, USB_INIT_HOST); } diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index 7ee44ea919..aedc24b937 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -312,13 +312,16 @@ static int musb_usb_probe(struct udevice *dev) { struct musb_host_data *host = dev_get_priv(dev); struct usb_bus_priv *priv = dev_get_uclass_priv(dev); + void *base = dev_read_addr_ptr(dev); int ret; + if (!base) + return -EINVAL; + priv->desc_before_addr = true; #ifdef CONFIG_USB_MUSB_HOST - host->host = musb_init_controller(&musb_plat, NULL, - (void *)SUNXI_USB0_BASE); + host->host = musb_init_controller(&musb_plat, NULL, base); if (!host->host) return -EIO; @@ -326,7 +329,7 @@ static int musb_usb_probe(struct udevice *dev) if (!ret) printf("Allwinner mUSB OTG (Host)\n"); #else - ret = musb_register(&musb_plat, NULL, (void *)SUNXI_USB0_BASE); + ret = musb_register(&musb_plat, NULL, base); if (!ret) printf("Allwinner mUSB OTG (Peripheral)\n"); #endif |