summaryrefslogtreecommitdiff
path: root/drivers
diff options
context:
space:
mode:
Diffstat (limited to 'drivers')
-rw-r--r--drivers/i2c/fsl_i2c.c2
-rw-r--r--drivers/mmc/arm_pl180_mmci.c26
-rw-r--r--drivers/mmc/tegra2_mmc.c130
-rw-r--r--drivers/mmc/tegra2_mmc.h49
-rw-r--r--drivers/net/fm/fm.c3
-rw-r--r--drivers/net/tsec.c93
-rw-r--r--drivers/qe/uec.c7
-rw-r--r--drivers/usb/host/ehci-fsl.c4
8 files changed, 232 insertions, 82 deletions
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index 258be0a908..5b017a910c 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -225,7 +225,7 @@ unsigned int get_i2c_clock(int bus)
void
i2c_init(int speed, int slaveadd)
{
- struct fsl_i2c *dev;
+ const struct fsl_i2c *dev;
unsigned int temp;
int bus_num, i;
diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c
index ed296ee026..e6467a2d18 100644
--- a/drivers/mmc/arm_pl180_mmci.c
+++ b/drivers/mmc/arm_pl180_mmci.c
@@ -111,7 +111,6 @@ static int do_command(struct mmc *dev, struct mmc_cmd *cmd)
static int read_bytes(struct mmc *dev, u32 *dest, u32 blkcount, u32 blksize)
{
u32 *tempbuff = dest;
- int i;
u64 xfercount = blkcount * blksize;
struct mmc_host *host = dev->priv;
u32 status, status_err;
@@ -121,31 +120,6 @@ static int read_bytes(struct mmc *dev, u32 *dest, u32 blkcount, u32 blksize)
status = readl(&host->base->status);
status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT |
SDI_STA_RXOVERR);
- while (!status_err &&
- (xfercount >= SDI_FIFO_BURST_SIZE * sizeof(u32))) {
- if (status & SDI_STA_RXFIFOBR) {
- for (i = 0; i < SDI_FIFO_BURST_SIZE; i++)
- *(tempbuff + i) = readl(&host->base->fifo);
- tempbuff += SDI_FIFO_BURST_SIZE;
- xfercount -= SDI_FIFO_BURST_SIZE * sizeof(u32);
- }
- status = readl(&host->base->status);
- status_err = status &
- (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_RXOVERR);
- }
-
- if (status & SDI_STA_DTIMEOUT) {
- printf("Read data timed out, xfercount: %llu, status: 0x%08X\n",
- xfercount, status);
- return -ETIMEDOUT;
- } else if (status & SDI_STA_DCRCFAIL) {
- printf("Read data blk CRC error: 0x%x\n", status);
- return -EILSEQ;
- } else if (status & SDI_STA_RXOVERR) {
- printf("Read data RX overflow error\n");
- return -EIO;
- }
-
while ((!status_err) && (xfercount >= sizeof(u32))) {
if (status & SDI_STA_RXDAVL) {
*(tempbuff) = readl(&host->base->fifo);
diff --git a/drivers/mmc/tegra2_mmc.c b/drivers/mmc/tegra2_mmc.c
index 78b11900ed..ccf48bbb17 100644
--- a/drivers/mmc/tegra2_mmc.c
+++ b/drivers/mmc/tegra2_mmc.c
@@ -81,7 +81,8 @@ static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
* 11 = Selects 64-bit Address ADMA2
*/
ctrl = readb(&host->reg->hostctl);
- ctrl &= ~(3 << 3); /* SDMA */
+ ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
+ ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
writeb(ctrl, &host->reg->hostctl);
/* We do not handle DMA boundaries, so set it to max (512 KiB) */
@@ -103,43 +104,36 @@ static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
* ENBLKCNT[1] : Block Count Enable
* ENDMA[0] : DMA Enable
*/
- mode = (1 << 1) | (1 << 0);
+ mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
+ TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
+
if (data->blocks > 1)
- mode |= (1 << 5);
+ mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
+
if (data->flags & MMC_DATA_READ)
- mode |= (1 << 4);
+ mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
writew(mode, &host->reg->trnmod);
}
-static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
- struct mmc_data *data)
+static int mmc_wait_inhibit(struct mmc_host *host,
+ struct mmc_cmd *cmd,
+ struct mmc_data *data,
+ unsigned int timeout)
{
- struct mmc_host *host = (struct mmc_host *)mmc->priv;
- int flags, i;
- unsigned int timeout;
- unsigned int mask;
- unsigned int retry = 0x100000;
- debug(" mmc_send_cmd called\n");
-
- /* Wait max 10 ms */
- timeout = 10;
-
/*
* PRNSTS
- * CMDINHDAT[1] : Command Inhibit (DAT)
- * CMDINHCMD[0] : Command Inhibit (CMD)
+ * CMDINHDAT[1] : Command Inhibit (DAT)
+ * CMDINHCMD[0] : Command Inhibit (CMD)
*/
- mask = (1 << 0);
- if ((data != NULL) || (cmd->resp_type & MMC_RSP_BUSY))
- mask |= (1 << 1);
+ unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
/*
* We shouldn't wait for data inhibit for stop commands, even
* though they might use busy signaling
*/
- if (data)
- mask &= ~(1 << 1);
+ if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
+ mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
while (readl(&host->reg->prnsts) & mask) {
if (timeout == 0) {
@@ -150,6 +144,24 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
udelay(1000);
}
+ return 0;
+}
+
+static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct mmc_host *host = (struct mmc_host *)mmc->priv;
+ int flags, i;
+ int result;
+ unsigned int mask;
+ unsigned int retry = 0x100000;
+ debug(" mmc_send_cmd called\n");
+
+ result = mmc_wait_inhibit(host, cmd, data, 10 /* ms */);
+
+ if (result < 0)
+ return result;
+
if (data)
mmc_prepare_data(host, data);
@@ -175,20 +187,20 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
* 11 = Length 48 Check busy after response
*/
if (!(cmd->resp_type & MMC_RSP_PRESENT))
- flags = 0;
+ flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
else if (cmd->resp_type & MMC_RSP_136)
- flags = (1 << 0);
+ flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
else if (cmd->resp_type & MMC_RSP_BUSY)
- flags = (3 << 0);
+ flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
else
- flags = (2 << 0);
+ flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
if (cmd->resp_type & MMC_RSP_CRC)
- flags |= (1 << 3);
+ flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
if (cmd->resp_type & MMC_RSP_OPCODE)
- flags |= (1 << 4);
+ flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
if (data)
- flags |= (1 << 5);
+ flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
debug("cmd: %d\n", cmd->cmdidx);
@@ -197,7 +209,7 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
for (i = 0; i < retry; i++) {
mask = readl(&host->reg->norintsts);
/* Command Complete */
- if (mask & (1 << 0)) {
+ if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
if (!data)
writel(mask, &host->reg->norintsts);
break;
@@ -209,11 +221,11 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
return TIMEOUT;
}
- if (mask & (1 << 16)) {
+ if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
/* Timeout Error */
debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
return TIMEOUT;
- } else if (mask & (1 << 15)) {
+ } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
/* Error Interrupt */
debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
return -1;
@@ -256,23 +268,44 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
}
if (data) {
+ unsigned long start = get_timer(0);
+
while (1) {
mask = readl(&host->reg->norintsts);
- if (mask & (1 << 15)) {
+ if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
/* Error Interrupt */
writel(mask, &host->reg->norintsts);
printf("%s: error during transfer: 0x%08x\n",
__func__, mask);
return -1;
- } else if (mask & (1 << 3)) {
- /* DMA Interrupt */
+ } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
+ /*
+ * DMA Interrupt, restart the transfer where
+ * it was interrupted.
+ */
+ unsigned int address = readl(&host->reg->sysad);
+
debug("DMA end\n");
- break;
- } else if (mask & (1 << 1)) {
+ writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
+ &host->reg->norintsts);
+ writel(address, &host->reg->sysad);
+ } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
/* Transfer Complete */
debug("r/w is done\n");
break;
+ } else if (get_timer(start) > 2000UL) {
+ writel(mask, &host->reg->norintsts);
+ printf("%s: MMC Timeout\n"
+ " Interrupt status 0x%08x\n"
+ " Interrupt status enable 0x%08x\n"
+ " Interrupt signal enable 0x%08x\n"
+ " Present status 0x%08x\n",
+ __func__, mask,
+ readl(&host->reg->norintstsen),
+ readl(&host->reg->norintsigen),
+ readl(&host->reg->prnsts));
+ return -1;
}
}
writel(mask, &host->reg->norintsts);
@@ -310,12 +343,14 @@ static void mmc_change_clock(struct mmc_host *host, uint clock)
* ENINTCLK[0] : Internal Clock Enable
*/
div >>= 1;
- clk = (div << 8) | (1 << 0);
+ clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
+ TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
writew(clk, &host->reg->clkcon);
/* Wait max 10 ms */
timeout = 10;
- while (!(readw(&host->reg->clkcon) & (1 << 1))) {
+ while (!(readw(&host->reg->clkcon) &
+ TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
if (timeout == 0) {
printf("%s: timeout error\n", __func__);
return;
@@ -324,7 +359,7 @@ static void mmc_change_clock(struct mmc_host *host, uint clock)
udelay(1000);
}
- clk |= (1 << 2);
+ clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
writew(clk, &host->reg->clkcon);
debug("mmc_change_clock: clkcon = %08X\n", clk);
@@ -375,7 +410,7 @@ static void mmc_reset(struct mmc_host *host)
* 1 = reset
* 0 = work
*/
- writeb((1 << 0), &host->reg->swrst);
+ writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &host->reg->swrst);
host->clock = 0;
@@ -383,7 +418,7 @@ static void mmc_reset(struct mmc_host *host)
timeout = 100;
/* hw clears the bit when it's done */
- while (readb(&host->reg->swrst) & (1 << 0)) {
+ while (readb(&host->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
if (timeout == 0) {
printf("%s: timeout error\n", __func__);
return;
@@ -413,12 +448,17 @@ static int mmc_core_init(struct mmc *mmc)
* NORMAL Interrupt Status Enable Register init
* [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
* [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
+ * [3] ENSTADMAINT : DMA boundary interrupt
* [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
* [0] ENSTACMDCMPLT : Command Complete Status Enable
*/
mask = readl(&host->reg->norintstsen);
mask &= ~(0xffff);
- mask |= (1 << 5) | (1 << 4) | (1 << 1) | (1 << 0);
+ mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
+ TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
+ TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
+ TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
+ TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
writel(mask, &host->reg->norintstsen);
/*
@@ -427,7 +467,7 @@ static int mmc_core_init(struct mmc *mmc)
*/
mask = readl(&host->reg->norintsigen);
mask &= ~(0xffff);
- mask |= (1 << 1);
+ mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
writel(mask, &host->reg->norintsigen);
return 0;
diff --git a/drivers/mmc/tegra2_mmc.h b/drivers/mmc/tegra2_mmc.h
index 28698e0fc0..671583c422 100644
--- a/drivers/mmc/tegra2_mmc.h
+++ b/drivers/mmc/tegra2_mmc.h
@@ -68,6 +68,55 @@ struct tegra2_mmc {
unsigned char res6[0x100]; /* RESERVED, offset 100h-1FFh */
};
+#define TEGRA_MMC_HOSTCTL_DMASEL_MASK (3 << 3)
+#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA (0 << 3)
+#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT (2 << 3)
+#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT (3 << 3)
+
+#define TEGRA_MMC_TRNMOD_DMA_ENABLE (1 << 0)
+#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE (1 << 1)
+#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE (0 << 4)
+#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ (1 << 4)
+#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT (1 << 5)
+
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK (3 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE (0 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136 (1 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48 (2 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY (3 << 0)
+
+#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK (1 << 3)
+#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK (1 << 4)
+#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER (1 << 5)
+
+#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD (1 << 0)
+#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT (1 << 1)
+
+#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE (1 << 0)
+#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE (1 << 1)
+#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE (1 << 2)
+
+#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT 8
+#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK (0xff << 8)
+
+#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL (1 << 0)
+#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE (1 << 1)
+#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE (1 << 2)
+
+#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE (1 << 0)
+#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE (1 << 1)
+#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT (1 << 3)
+#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT (1 << 15)
+#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT (1 << 16)
+
+#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE (1 << 0)
+#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE (1 << 1)
+#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT (1 << 3)
+#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY (1 << 4)
+#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY (1 << 5)
+
+#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1)
+
struct mmc_host {
struct tegra2_mmc *reg;
unsigned int version; /* SDHCI spec. version */
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index 23ef14baf4..846c37249b 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -395,7 +395,6 @@ int fm_init_common(int index, struct ccsr_fman *reg)
int dev = CONFIG_SYS_MMC_ENV_DEV;
void *addr = malloc(CONFIG_SYS_FMAN_FW_LENGTH);
u32 cnt = CONFIG_SYS_FMAN_FW_LENGTH / 512;
- u32 n;
u32 blk = CONFIG_SYS_QE_FW_IN_MMC / 512;
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
@@ -405,7 +404,7 @@ int fm_init_common(int index, struct ccsr_fman *reg)
printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
dev, blk, cnt);
mmc_init(mmc);
- n = mmc->block_dev.block_read(dev, blk, cnt, addr);
+ (void)mmc->block_dev.block_read(dev, blk, cnt, addr);
/* flush cache after read */
flush_cache((ulong)addr, cnt * 512);
}
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 78ffc95c53..160bc0597d 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -19,6 +19,7 @@
#include <tsec.h>
#include <fsl_mdio.h>
#include <asm/errno.h>
+#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -43,6 +44,9 @@ static RTXBD rtx __attribute__ ((aligned(8)));
#error "rtx must be 64-bit aligned"
#endif
+static int tsec_send(struct eth_device *dev,
+ volatile void *packet, int length);
+
/* Default initializations for TSEC controllers. */
static struct tsec_info_struct tsec_info[] = {
@@ -236,6 +240,87 @@ static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
(phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
}
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
+/*
+ * When MACCFG1[Rx_EN] is enabled during system boot as part
+ * of the eTSEC port initialization sequence,
+ * the eTSEC Rx logic may not be properly initialized.
+ */
+void redundant_init(struct eth_device *dev)
+{
+ struct tsec_private *priv = dev->priv;
+ tsec_t *regs = priv->regs;
+ uint t, count = 0;
+ int fail = 1;
+ static const u8 pkt[] = {
+ 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
+ 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
+ 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
+ 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
+ 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
+ 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
+ 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
+ 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
+ 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
+ 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
+ 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
+ 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
+ 0x71, 0x72};
+
+ /* Enable promiscuous mode */
+ setbits_be32(&regs->rctrl, 0x8);
+ /* Enable loopback mode */
+ setbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
+ /* Enable transmit and receive */
+ setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
+
+ /* Tell the DMA it is clear to go */
+ setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
+ out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
+ out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
+ clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+
+ do {
+ tsec_send(dev, (void *)pkt, sizeof(pkt));
+
+ /* Wait for buffer to be received */
+ for (t = 0; rtx.rxbd[rxIdx].status & RXBD_EMPTY; t++) {
+ if (t >= 10 * TOUT_LOOP) {
+ printf("%s: tsec: rx error\n", dev->name);
+ break;
+ }
+ }
+
+ if (!memcmp(pkt, (void *)NetRxPackets[rxIdx], sizeof(pkt)))
+ fail = 0;
+
+ rtx.rxbd[rxIdx].length = 0;
+ rtx.rxbd[rxIdx].status =
+ RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
+ rxIdx = (rxIdx + 1) % PKTBUFSRX;
+
+ if (in_be32(&regs->ievent) & IEVENT_BSY) {
+ out_be32(&regs->ievent, IEVENT_BSY);
+ out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
+ }
+ if (fail) {
+ printf("loopback recv packet error!\n");
+ clrbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
+ udelay(1000);
+ setbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
+ }
+ } while ((count++ < 4) && (fail == 1));
+
+ if (fail)
+ panic("eTSEC init fail!\n");
+ /* Disable promiscuous mode */
+ clrbits_be32(&regs->rctrl, 0x8);
+ /* Disable loopback mode */
+ clrbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
+}
+#endif
+
/* Set up the buffers and their descriptors, and bring up the
* interface
*/
@@ -248,6 +333,9 @@ static void startup_tsec(struct eth_device *dev)
/* reset the indices to zero */
rxIdx = 0;
txIdx = 0;
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
+ uint svr;
+#endif
/* Point to the buffer descriptors */
out_be32(&regs->tbase, (unsigned int)(&rtx.txbd[txIdx]));
@@ -269,6 +357,11 @@ static void startup_tsec(struct eth_device *dev)
}
rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
+ svr = get_svr();
+ if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
+ redundant_init(dev);
+#endif
/* Enable Transmit and Receive */
setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index 1ecb1379a5..3e46e3515f 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -264,13 +264,10 @@ static int uec_open(uec_private_t *uec, comm_dir_e mode)
static int uec_stop(uec_private_t *uec, comm_dir_e mode)
{
- ucc_fast_private_t *uccf;
-
if (!uec || !uec->uccf) {
printf("%s: No handle passed.\n", __FUNCTION__);
return -EINVAL;
}
- uccf = uec->uccf;
/* check if the UCC number is in range. */
if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
@@ -325,7 +322,6 @@ static int uec_set_mac_if_mode(uec_private_t *uec,
phy_interface_t if_mode, int speed)
{
phy_interface_t enet_if_mode;
- uec_info_t *uec_info;
uec_t *uec_regs;
u32 upsmr;
u32 maccfg2;
@@ -335,7 +331,6 @@ static int uec_set_mac_if_mode(uec_private_t *uec,
return -EINVAL;
}
- uec_info = uec->uec_info;
uec_regs = uec->uec_regs;
enet_if_mode = if_mode;
@@ -516,12 +511,10 @@ bus_fail:
static void adjust_link(struct eth_device *dev)
{
uec_private_t *uec = (uec_private_t *)dev->priv;
- uec_t *uec_regs;
struct uec_mii_info *mii_info = uec->mii_info;
extern void change_phy_interface_mode(struct eth_device *dev,
phy_interface_t mode, int speed);
- uec_regs = uec->uec_regs;
if (mii_info->link) {
/* Now we make sure that we can be in full duplex mode.
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 5a65d92719..b2d294ee88 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -40,11 +40,13 @@
int ehci_hcd_init(void)
{
struct usb_ehci *ehci;
- char usb_phy[5];
const char *phy_type = NULL;
size_t len;
+#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+ char usb_phy[5];
usb_phy[0] = '\0';
+#endif
ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
generated by cgit (git 2.34.1) at 2024-12-27 04:15:36 +0000