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-rw-r--r--drivers/clk/renesas/clk-rcar-gen2.c58
-rw-r--r--drivers/mmc/mmc.c3
-rw-r--r--drivers/mmc/sh_mmcif.c2
-rw-r--r--drivers/mmc/tmio-common.c5
-rw-r--r--drivers/pinctrl/rockchip/pinctrl-rk3288.c17
-rw-r--r--drivers/pinctrl/rockchip/pinctrl-rockchip-core.c39
-rw-r--r--drivers/pinctrl/rockchip/pinctrl-rockchip.h33
7 files changed, 134 insertions, 23 deletions
diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c
index 6dfd02f2eb..13111b341a 100644
--- a/drivers/clk/renesas/clk-rcar-gen2.c
+++ b/drivers/clk/renesas/clk-rcar-gen2.c
@@ -44,13 +44,17 @@ static const struct clk_div_table cpg_sd01_div_table[] = {
{ 0, 0 },
};
-static u8 gen2_clk_get_sdh_div(const struct clk_div_table *table, u8 div)
+static u8 gen2_clk_get_sdh_div(const struct clk_div_table *table, u8 val)
{
- while ((*table++).val) {
- if ((*table).div == div)
- return div;
+ for (;;) {
+ if (!(*table).div)
+ return 0xff;
+
+ if ((*table).val == val)
+ return (*table).div;
+
+ table++;
}
- return 0xff;
}
static int gen2_clk_enable(struct clk *clk)
@@ -117,7 +121,7 @@ static ulong gen2_clk_get_rate(struct clk *clk)
case CLK_TYPE_FF:
rate = (gen2_clk_get_rate(&parent) * core->mult) / core->div;
- debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n",
+ debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%u\n",
__func__, __LINE__,
core->parent, core->mult, core->div, rate);
return rate;
@@ -202,8 +206,50 @@ static ulong gen2_clk_get_rate(struct clk *clk)
return -ENOENT;
}
+static int gen2_clk_setup_mmcif_div(struct clk *clk, ulong rate)
+{
+ struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
+ struct cpg_mssr_info *info = priv->info;
+ const struct cpg_core_clk *core;
+ struct clk parent, pparent;
+ u32 val;
+ int ret;
+
+ ret = renesas_clk_get_parent(clk, info, &parent);
+ if (ret) {
+ debug("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
+ return ret;
+ }
+
+ if (renesas_clk_is_mod(&parent))
+ return 0;
+
+ ret = renesas_clk_get_core(&parent, info, &core);
+ if (ret)
+ return ret;
+
+ if (strcmp(core->name, "mmc0") && strcmp(core->name, "mmc1"))
+ return 0;
+
+ ret = renesas_clk_get_parent(&parent, info, &pparent);
+ if (ret) {
+ debug("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
+ return ret;
+ }
+
+ val = (gen2_clk_get_rate(&pparent) / rate) - 1;
+
+ debug("%s[%i] MMCIF offset=%x\n", __func__, __LINE__, core->offset);
+
+ writel(val, priv->base + core->offset);
+
+ return 0;
+}
+
static ulong gen2_clk_set_rate(struct clk *clk, ulong rate)
{
+ /* Force correct MMC-IF divider configuration if applicable */
+ gen2_clk_setup_mmcif_div(clk, rate);
return gen2_clk_get_rate(clk);
}
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 89b255daf4..456c1b4cc9 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1892,8 +1892,7 @@ static int mmc_select_hs400(struct mmc *mmc)
}
/* Set back to HS */
- mmc_set_card_speed(mmc, MMC_HS, false);
- mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false);
+ mmc_set_card_speed(mmc, MMC_HS, true);
err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG);
diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c
index 306daf1415..c8875ce8f8 100644
--- a/drivers/mmc/sh_mmcif.c
+++ b/drivers/mmc/sh_mmcif.c
@@ -696,7 +696,7 @@ static int sh_mmcif_dm_probe(struct udevice *dev)
return ret;
}
- host->clk = clk_get_rate(&sh_mmcif_clk);
+ host->clk = clk_set_rate(&sh_mmcif_clk, 97500000);
plat->cfg.name = dev->name;
plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c
index 01d8c2b925..812205a21f 100644
--- a/drivers/mmc/tmio-common.c
+++ b/drivers/mmc/tmio-common.c
@@ -783,7 +783,10 @@ int tmio_sd_probe(struct udevice *dev, u32 quirks)
plat->cfg.f_min = mclk /
(priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512);
plat->cfg.f_max = mclk;
- plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */
+ if (quirks & TMIO_SD_CAP_16BIT)
+ plat->cfg.b_max = U16_MAX; /* max value of TMIO_SD_SECCNT */
+ else
+ plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */
upriv->mmc = &plat->mmc;
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c
index 60585f3208..8b6ce11a63 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c
@@ -92,10 +92,19 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
}
static struct rockchip_pin_bank rk3288_pin_banks[] = {
- PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
- IOMUX_SOURCE_PMU,
- IOMUX_SOURCE_PMU,
- IOMUX_UNROUTED
+ PIN_BANK_IOMUX_DRV_PULL_FLAGS(0, 24, "gpio0",
+ IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
+ IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
+ IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
+ IOMUX_UNROUTED,
+ DRV_TYPE_WRITABLE_32BIT,
+ DRV_TYPE_WRITABLE_32BIT,
+ DRV_TYPE_WRITABLE_32BIT,
+ 0,
+ PULL_TYPE_WRITABLE_32BIT,
+ PULL_TYPE_WRITABLE_32BIT,
+ PULL_TYPE_WRITABLE_32BIT,
+ 0
),
PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
IOMUX_UNROUTED,
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
index b84b079064..ce935656f0 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
@@ -228,7 +228,13 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
}
}
- data = (mask << (bit + 16));
+ if (mux_type & IOMUX_WRITABLE_32BIT) {
+ regmap_read(regmap, reg, &data);
+ data &= ~(mask << bit);
+ } else {
+ data = (mask << (bit + 16));
+ }
+
data |= (mux & mask) << bit;
ret = regmap_write(regmap, reg, data);
@@ -252,7 +258,8 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
int reg, ret, i;
u32 data, rmask_bits, temp;
u8 bit;
- int drv_type = bank->drv[pin_num / 8].drv_type;
+ /* Where need to clean the special mask for rockchip_perpin_drv_list */
+ int drv_type = bank->drv[pin_num / 8].drv_type & (~DRV_TYPE_IO_MASK);
debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num,
pin_num, strength);
@@ -324,10 +331,15 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
return -EINVAL;
}
- /* enable the write to the equivalent lower bits */
- data = ((1 << rmask_bits) - 1) << (bit + 16);
- data |= (ret << bit);
+ if (bank->drv[pin_num / 8].drv_type & DRV_TYPE_WRITABLE_32BIT) {
+ regmap_read(regmap, reg, &data);
+ data &= ~(((1 << rmask_bits) - 1) << bit);
+ } else {
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << rmask_bits) - 1) << (bit + 16);
+ }
+ data |= (ret << bit);
ret = regmap_write(regmap, reg, data);
return ret;
}
@@ -375,7 +387,11 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
case RK3288:
case RK3368:
case RK3399:
- pull_type = bank->pull_type[pin_num / 8];
+ /*
+ * Where need to clean the special mask for
+ * rockchip_pull_list.
+ */
+ pull_type = bank->pull_type[pin_num / 8] & (~PULL_TYPE_IO_MASK);
ret = -EINVAL;
for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
i++) {
@@ -390,10 +406,15 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
return ret;
}
- /* enable the write to the equivalent lower bits */
- data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
- data |= (ret << bit);
+ if (bank->pull_type[pin_num / 8] & PULL_TYPE_WRITABLE_32BIT) {
+ regmap_read(regmap, reg, &data);
+ data &= ~(((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << bit);
+ } else {
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+ }
+ data |= (ret << bit);
ret = regmap_write(regmap, reg, data);
break;
default:
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h
index bc809630c1..5a6849c996 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h
@@ -26,6 +26,7 @@ enum rockchip_pinctrl_type {
#define IOMUX_SOURCE_PMU BIT(2)
#define IOMUX_UNROUTED BIT(3)
#define IOMUX_WIDTH_3BIT BIT(4)
+#define IOMUX_WRITABLE_32BIT BIT(5)
/**
* Defined some common pins constants
@@ -49,6 +50,9 @@ struct rockchip_iomux {
int offset;
};
+#define DRV_TYPE_IO_MASK GENMASK(31, 16)
+#define DRV_TYPE_WRITABLE_32BIT BIT(31)
+
/**
* enum type index corresponding to rockchip_perpin_drv_list arrays index.
*/
@@ -61,6 +65,9 @@ enum rockchip_pin_drv_type {
DRV_TYPE_MAX
};
+#define PULL_TYPE_IO_MASK GENMASK(31, 16)
+#define PULL_TYPE_WRITABLE_32BIT BIT(31)
+
/**
* enum type index corresponding to rockchip_pull_list arrays index.
*/
@@ -200,6 +207,32 @@ struct rockchip_pin_bank {
}, \
}
+#define PIN_BANK_IOMUX_DRV_PULL_FLAGS(id, pins, label, iom0, iom1, \
+ iom2, iom3, drv0, drv1, drv2, \
+ drv3, pull0, pull1, pull2, \
+ pull3) \
+ { \
+ .bank_num = id, \
+ .nr_pins = pins, \
+ .name = label, \
+ .iomux = { \
+ { .type = iom0, .offset = -1 }, \
+ { .type = iom1, .offset = -1 }, \
+ { .type = iom2, .offset = -1 }, \
+ { .type = iom3, .offset = -1 }, \
+ }, \
+ .drv = { \
+ { .drv_type = drv0, .offset = -1 }, \
+ { .drv_type = drv1, .offset = -1 }, \
+ { .drv_type = drv2, .offset = -1 }, \
+ { .drv_type = drv3, .offset = -1 }, \
+ }, \
+ .pull_type[0] = pull0, \
+ .pull_type[1] = pull1, \
+ .pull_type[2] = pull2, \
+ .pull_type[3] = pull3, \
+ }
+
#define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
label, iom0, iom1, iom2, \
iom3, drv0, drv1, drv2, \
generated by cgit (git 2.34.1) at 2025-01-30 05:16:36 +0000