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-rw-r--r--drivers/spi/Kconfig10
-rw-r--r--drivers/spi/mpc8xxx_spi.c279
-rw-r--r--drivers/video/meson/meson_dw_hdmi.c14
-rw-r--r--drivers/video/mxsfb.c219
4 files changed, 382 insertions, 140 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 7044da35d6..eb32f082fe 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -137,6 +137,11 @@ config MPC8XX_SPI
help
Enable support for SPI on MPC8XX
+config MPC8XXX_SPI
+ bool "MPC8XXX SPI Driver"
+ help
+ Enable support for SPI on the MPC8XXX PowerPC SoCs.
+
config MT7621_SPI
bool "MediaTek MT7621 SPI driver"
depends on SOC_MT7628
@@ -370,11 +375,6 @@ config LPC32XX_SSP
help
Enable support for SPI on LPC32xx
-config MPC8XXX_SPI
- bool "MPC8XXX SPI Driver"
- help
- Enable support for SPI on the MPC8XXX PowerPC SoCs.
-
config MXC_SPI
bool "MXC SPI Driver"
help
diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c
index 8d6d86d2b0..1c7bf10f91 100644
--- a/drivers/spi/mpc8xxx_spi.c
+++ b/drivers/spi/mpc8xxx_spi.c
@@ -5,161 +5,258 @@
*/
#include <common.h>
-
+#include <dm.h>
+#include <errno.h>
#include <malloc.h>
#include <spi.h>
#include <asm/mpc8xxx_spi.h>
+#include <asm-generic/gpio.h>
+
+enum {
+ SPI_EV_NE = BIT(31 - 22), /* Receiver Not Empty */
+ SPI_EV_NF = BIT(31 - 23), /* Transmitter Not Full */
+};
+
+enum {
+ SPI_MODE_LOOP = BIT(31 - 1), /* Loopback mode */
+ SPI_MODE_CI = BIT(31 - 2), /* Clock invert */
+ SPI_MODE_CP = BIT(31 - 3), /* Clock phase */
+ SPI_MODE_DIV16 = BIT(31 - 4), /* Divide clock source by 16 */
+ SPI_MODE_REV = BIT(31 - 5), /* Reverse mode - MSB first */
+ SPI_MODE_MS = BIT(31 - 6), /* Always master */
+ SPI_MODE_EN = BIT(31 - 7), /* Enable interface */
+
+ SPI_MODE_LEN_MASK = 0xf00000,
+ SPI_MODE_PM_MASK = 0xf0000,
+
+ SPI_COM_LST = BIT(31 - 9),
+};
+
+struct mpc8xxx_priv {
+ spi8xxx_t *spi;
+ struct gpio_desc gpios[16];
+ int max_cs;
+};
+
+static inline u32 to_prescale_mod(u32 val)
+{
+ return (min(val, (u32)15) << 16);
+}
-#define SPI_EV_NE (0x80000000 >> 22) /* Receiver Not Empty */
-#define SPI_EV_NF (0x80000000 >> 23) /* Transmitter Not Full */
-
-#define SPI_MODE_LOOP (0x80000000 >> 1) /* Loopback mode */
-#define SPI_MODE_REV (0x80000000 >> 5) /* Reverse mode - MSB first */
-#define SPI_MODE_MS (0x80000000 >> 6) /* Always master */
-#define SPI_MODE_EN (0x80000000 >> 7) /* Enable interface */
+static void set_char_len(spi8xxx_t *spi, u32 val)
+{
+ clrsetbits_be32(&spi->mode, SPI_MODE_LEN_MASK, (val << 20));
+}
#define SPI_TIMEOUT 1000
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
+static int __spi_set_speed(spi8xxx_t *spi, uint speed)
{
- struct spi_slave *slave;
+ /* TODO(mario.six@gdsys.cc): This only ever sets one fixed speed */
- if (!spi_cs_is_valid(bus, cs))
- return NULL;
+ /* Use SYSCLK / 8 (16.67MHz typ.) */
+ clrsetbits_be32(&spi->mode, SPI_MODE_PM_MASK, to_prescale_mod(1));
- slave = spi_alloc_slave_base(bus, cs);
- if (!slave)
- return NULL;
-
- /*
- * TODO: Some of the code in spi_init() should probably move
- * here, or into spi_claim_bus() below.
- */
-
- return slave;
+ return 0;
}
-void spi_free_slave(struct spi_slave *slave)
+static int mpc8xxx_spi_ofdata_to_platdata(struct udevice *dev)
{
- free(slave);
+ struct mpc8xxx_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->spi = (spi8xxx_t *)dev_read_addr(dev);
+
+ /* TODO(mario.six@gdsys.cc): Read clock and save the value */
+
+ ret = gpio_request_list_by_name(dev, "gpios", priv->gpios,
+ ARRAY_SIZE(priv->gpios), GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
+ if (ret < 0)
+ return -EINVAL;
+
+ priv->max_cs = ret;
+
+ return 0;
}
-void spi_init(void)
+static int mpc8xxx_spi_probe(struct udevice *dev)
{
- volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi;
+ struct mpc8xxx_priv *priv = dev_get_priv(dev);
/*
* SPI pins on the MPC83xx are not muxed, so all we do is initialize
* some registers
*/
- spi->mode = SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN;
- spi->mode = (spi->mode & 0xfff0ffff) | BIT(16); /* Use SYSCLK / 8
- (16.67MHz typ.) */
- spi->event = 0xffffffff; /* Clear all SPI events */
- spi->mask = 0x00000000; /* Mask all SPI interrupts */
- spi->com = 0; /* LST bit doesn't do anything, so disregard */
+ out_be32(&priv->spi->mode, SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN);
+
+ __spi_set_speed(priv->spi, 16666667);
+
+ /* Clear all SPI events */
+ setbits_be32(&priv->spi->event, 0xffffffff);
+ /* Mask all SPI interrupts */
+ clrbits_be32(&priv->spi->mask, 0xffffffff);
+ /* LST bit doesn't do anything, so disregard */
+ out_be32(&priv->spi->com, 0);
+
+ return 0;
}
-int spi_claim_bus(struct spi_slave *slave)
+static void mpc8xxx_spi_cs_activate(struct udevice *dev)
{
- return 0;
+ struct mpc8xxx_priv *priv = dev_get_priv(dev->parent);
+ struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
+
+ dm_gpio_set_dir_flags(&priv->gpios[platdata->cs], GPIOD_IS_OUT);
+ dm_gpio_set_value(&priv->gpios[platdata->cs], 0);
}
-void spi_release_bus(struct spi_slave *slave)
+static void mpc8xxx_spi_cs_deactivate(struct udevice *dev)
{
+ struct mpc8xxx_priv *priv = dev_get_priv(dev->parent);
+ struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
+ dm_gpio_set_dir_flags(&priv->gpios[platdata->cs], GPIOD_IS_OUT);
+ dm_gpio_set_value(&priv->gpios[platdata->cs], 1);
}
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
- void *din, unsigned long flags)
+static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen,
+ const void *dout, void *din, ulong flags)
{
- volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi;
- unsigned int tmpdout, tmpdin, event;
- int numBlks = DIV_ROUND_UP(bitlen, 32);
- int tm, isRead = 0;
- unsigned char charSize = 32;
+ struct udevice *bus = dev->parent;
+ struct mpc8xxx_priv *priv = dev_get_priv(bus);
+ spi8xxx_t *spi = priv->spi;
+ struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev);
+ u32 tmpdin = 0;
+ int num_blks = DIV_ROUND_UP(bitlen, 32);
- debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
- slave->bus, slave->cs, *(uint *) dout, *(uint *) din, bitlen);
+ debug("%s: slave %s:%u dout %08X din %08X bitlen %u\n", __func__,
+ bus->name, platdata->cs, *(uint *)dout, *(uint *)din, bitlen);
if (flags & SPI_XFER_BEGIN)
- spi_cs_activate(slave);
+ mpc8xxx_spi_cs_activate(dev);
+
+ /* Clear all SPI events */
+ setbits_be32(&spi->event, 0xffffffff);
+
+ /* Handle data in 32-bit chunks */
+ while (num_blks--) {
+ u32 tmpdout = 0;
+ uchar xfer_bitlen = (bitlen >= 32 ? 32 : bitlen);
+ ulong start;
- spi->event = 0xffffffff; /* Clear all SPI events */
+ clrbits_be32(&spi->mode, SPI_MODE_EN);
- /* handle data in 32-bit chunks */
- while (numBlks--) {
- tmpdout = 0;
- charSize = (bitlen >= 32 ? 32 : bitlen);
+ /* Set up length for this transfer */
+
+ if (bitlen <= 4) /* 4 bits or less */
+ set_char_len(spi, 3);
+ else if (bitlen <= 16) /* at most 16 bits */
+ set_char_len(spi, bitlen - 1);
+ else /* more than 16 bits -> full 32 bit transfer */
+ set_char_len(spi, 0);
+
+ setbits_be32(&spi->mode, SPI_MODE_EN);
/* Shift data so it's msb-justified */
- tmpdout = *(u32 *) dout >> (32 - charSize);
-
- /* The LEN field of the SPMODE register is set as follows:
- *
- * Bit length setting
- * len <= 4 3
- * 4 < len <= 16 len - 1
- * len > 16 0
- */
+ tmpdout = *(u32 *)dout >> (32 - xfer_bitlen);
- spi->mode &= ~SPI_MODE_EN;
-
- if (bitlen <= 16) {
- if (bitlen <= 4)
- spi->mode = (spi->mode & 0xff0fffff) |
- (3 << 20);
- else
- spi->mode = (spi->mode & 0xff0fffff) |
- ((bitlen - 1) << 20);
- } else {
- spi->mode = (spi->mode & 0xff0fffff);
+ if (bitlen > 32) {
/* Set up the next iteration if sending > 32 bits */
bitlen -= 32;
dout += 4;
}
- spi->mode |= SPI_MODE_EN;
+ /* Write the data out */
+ out_be32(&spi->tx, tmpdout);
- spi->tx = tmpdout; /* Write the data out */
- debug("*** spi_xfer: ... %08x written\n", tmpdout);
+ debug("*** %s: ... %08x written\n", __func__, tmpdout);
/*
* Wait for SPI transmit to get out
* or time out (1 second = 1000 ms)
* The NE event must be read and cleared first
*/
- for (tm = 0, isRead = 0; tm < SPI_TIMEOUT; ++tm) {
- event = spi->event;
- if (event & SPI_EV_NE) {
- tmpdin = spi->rx;
- spi->event |= SPI_EV_NE;
- isRead = 1;
-
- *(u32 *) din = (tmpdin << (32 - charSize));
- if (charSize == 32) {
- /* Advance output buffer by 32 bits */
- din += 4;
- }
+ start = get_timer(0);
+ do {
+ u32 event = in_be32(&spi->event);
+ bool have_ne = event & SPI_EV_NE;
+ bool have_nf = event & SPI_EV_NF;
+
+ if (!have_ne)
+ continue;
+
+ tmpdin = in_be32(&spi->rx);
+ setbits_be32(&spi->event, SPI_EV_NE);
+
+ *(u32 *)din = (tmpdin << (32 - xfer_bitlen));
+ if (xfer_bitlen == 32) {
+ /* Advance output buffer by 32 bits */
+ din += 4;
}
+
/*
* Only bail when we've had both NE and NF events.
* This will cause timeouts on RO devices, so maybe
* in the future put an arbitrary delay after writing
* the device. Arbitrary delays suck, though...
*/
- if (isRead && (event & SPI_EV_NF))
+ if (have_nf)
break;
+
+ mdelay(1);
+ } while (get_timer(start) < SPI_TIMEOUT);
+
+ if (get_timer(start) >= SPI_TIMEOUT) {
+ debug("*** %s: Time out during SPI transfer\n",
+ __func__);
+ return -ETIMEDOUT;
}
- if (tm >= SPI_TIMEOUT)
- puts("*** spi_xfer: Time out during SPI transfer");
- debug("*** spi_xfer: transfer ended. Value=%08x\n", tmpdin);
+ debug("*** %s: transfer ended. Value=%08x\n", __func__, tmpdin);
}
if (flags & SPI_XFER_END)
- spi_cs_deactivate(slave);
+ mpc8xxx_spi_cs_deactivate(dev);
return 0;
}
+
+static int mpc8xxx_spi_set_speed(struct udevice *dev, uint speed)
+{
+ struct mpc8xxx_priv *priv = dev_get_priv(dev);
+
+ return __spi_set_speed(priv->spi, speed);
+}
+
+static int mpc8xxx_spi_set_mode(struct udevice *dev, uint mode)
+{
+ /* TODO(mario.six@gdsys.cc): Using SPI_CPHA (for clock phase) and
+ * SPI_CPOL (for clock polarity) should work
+ */
+ return 0;
+}
+
+static const struct dm_spi_ops mpc8xxx_spi_ops = {
+ .xfer = mpc8xxx_spi_xfer,
+ .set_speed = mpc8xxx_spi_set_speed,
+ .set_mode = mpc8xxx_spi_set_mode,
+ /*
+ * cs_info is not needed, since we require all chip selects to be
+ * in the device tree explicitly
+ */
+};
+
+static const struct udevice_id mpc8xxx_spi_ids[] = {
+ { .compatible = "fsl,spi" },
+ { }
+};
+
+U_BOOT_DRIVER(mpc8xxx_spi) = {
+ .name = "mpc8xxx_spi",
+ .id = UCLASS_SPI,
+ .of_match = mpc8xxx_spi_ids,
+ .ops = &mpc8xxx_spi_ops,
+ .ofdata_to_platdata = mpc8xxx_spi_ofdata_to_platdata,
+ .probe = mpc8xxx_spi_probe,
+ .priv_auto_alloc_size = sizeof(struct mpc8xxx_priv),
+};
diff --git a/drivers/video/meson/meson_dw_hdmi.c b/drivers/video/meson/meson_dw_hdmi.c
index 7a1c060856..483c93f6b6 100644
--- a/drivers/video/meson/meson_dw_hdmi.c
+++ b/drivers/video/meson/meson_dw_hdmi.c
@@ -361,13 +361,19 @@ static int meson_dw_hdmi_probe(struct udevice *dev)
priv->hdmi.i2c_clk_high = 0x67;
priv->hdmi.i2c_clk_low = 0x78;
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
ret = device_get_supply_regulator(dev, "hdmi-supply", &supply);
- if (ret)
+ if (ret && ret != -ENOENT) {
+ pr_err("Failed to get HDMI regulator\n");
return ret;
+ }
- ret = regulator_set_enable(supply, true);
- if (ret)
- return ret;
+ if (!ret) {
+ ret = regulator_set_enable(supply, true);
+ if (ret)
+ return ret;
+ }
+#endif
ret = reset_get_bulk(dev, &resets);
if (ret)
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 02fde05908..f02ba20138 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -5,22 +5,26 @@
* Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
*/
#include <common.h>
+#include <dm.h>
+#include <linux/errno.h>
#include <malloc.h>
+#include <video.h>
#include <video_fb.h>
-#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
-#include <linux/errno.h>
-#include <asm/io.h>
-
#include <asm/mach-imx/dma.h>
+#include <asm/io.h>
#include "videomodes.h"
#define PS2KHZ(ps) (1000000000UL / (ps))
+#define HZ2PS(hz) (1000000000UL / ((hz) / 1000))
+
+#define BITS_PP 18
+#define BYTES_PP 4
-static GraphicDevice panel;
struct mxs_dma_desc desc;
/**
@@ -46,8 +50,7 @@ __weak void mxsfb_system_setup(void)
* le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
*/
-static void mxs_lcd_init(GraphicDevice *panel,
- struct ctfb_res_modes *mode, int bpp)
+static void mxs_lcd_init(u32 fb_addr, struct ctfb_res_modes *mode, int bpp)
{
struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
uint32_t word_len = 0, bus_width = 0;
@@ -112,8 +115,8 @@ static void mxs_lcd_init(GraphicDevice *panel,
writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | mode->xres,
&regs->hw_lcdif_vdctrl4);
- writel(panel->frameAdrs, &regs->hw_lcdif_cur_buf);
- writel(panel->frameAdrs, &regs->hw_lcdif_next_buf);
+ writel(fb_addr, &regs->hw_lcdif_cur_buf);
+ writel(fb_addr, &regs->hw_lcdif_next_buf);
/* Flush FIFO first */
writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_set);
@@ -130,16 +133,47 @@ static void mxs_lcd_init(GraphicDevice *panel,
writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
}
-void lcdif_power_down(void)
+static int mxs_probe_common(struct ctfb_res_modes *mode, int bpp, u32 fb)
+{
+ /* Start framebuffer */
+ mxs_lcd_init(fb, mode, bpp);
+
+#ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
+ /*
+ * If the LCD runs in system mode, the LCD refresh has to be triggered
+ * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
+ * having to set this bit manually after every single change in the
+ * framebuffer memory, we set up specially crafted circular DMA, which
+ * sets the RUN bit, then waits until it gets cleared and repeats this
+ * infinitelly. This way, we get smooth continuous updates of the LCD.
+ */
+ struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
+
+ memset(&desc, 0, sizeof(struct mxs_dma_desc));
+ desc.address = (dma_addr_t)&desc;
+ desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
+ MXS_DMA_DESC_WAIT4END |
+ (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
+ desc.cmd.pio_words[0] = readl(&regs->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
+ desc.cmd.next = (uint32_t)&desc.cmd;
+
+ /* Execute the DMA chain. */
+ mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
+#endif
+
+ return 0;
+}
+
+static int mxs_remove_common(u32 fb)
{
struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
int timeout = 1000000;
- if (!panel.frameAdrs)
- return;
+ if (!fb)
+ return -EINVAL;
- writel(panel.frameAdrs, &regs->hw_lcdif_cur_buf_reg);
- writel(panel.frameAdrs, &regs->hw_lcdif_next_buf_reg);
+ writel(fb, &regs->hw_lcdif_cur_buf_reg);
+ writel(fb, &regs->hw_lcdif_next_buf_reg);
writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, &regs->hw_lcdif_ctrl1_clr);
while (--timeout) {
if (readl(&regs->hw_lcdif_ctrl1_reg) &
@@ -148,13 +182,25 @@ void lcdif_power_down(void)
udelay(1);
}
mxs_reset_block((struct mxs_register_32 *)&regs->hw_lcdif_ctrl_reg);
+
+ return 0;
+}
+
+#ifndef CONFIG_DM_VIDEO
+
+static GraphicDevice panel;
+
+void lcdif_power_down(void)
+{
+ mxs_remove_common(panel.frameAdrs);
}
void *video_hw_init(void)
{
int bpp = -1;
+ int ret = 0;
char *penv;
- void *fb;
+ void *fb = NULL;
struct ctfb_res_modes mode;
puts("Video: ");
@@ -169,8 +215,7 @@ void *video_hw_init(void)
bpp = video_get_params(&mode, penv);
/* fill in Graphic device struct */
- sprintf(panel.modeIdent, "%dx%dx%d",
- mode.xres, mode.yres, bpp);
+ sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp);
panel.winSizeX = mode.xres;
panel.winSizeY = mode.yres;
@@ -213,31 +258,125 @@ void *video_hw_init(void)
printf("%s\n", panel.modeIdent);
- /* Start framebuffer */
- mxs_lcd_init(&panel, &mode, bpp);
+ ret = mxs_probe_common(&mode, bpp, (u32)fb);
+ if (ret)
+ goto dealloc_fb;
-#ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
- /*
- * If the LCD runs in system mode, the LCD refresh has to be triggered
- * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
- * having to set this bit manually after every single change in the
- * framebuffer memory, we set up specially crafted circular DMA, which
- * sets the RUN bit, then waits until it gets cleared and repeats this
- * infinitelly. This way, we get smooth continuous updates of the LCD.
- */
- struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
+ return (void *)&panel;
- memset(&desc, 0, sizeof(struct mxs_dma_desc));
- desc.address = (dma_addr_t)&desc;
- desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
- MXS_DMA_DESC_WAIT4END |
- (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
- desc.cmd.pio_words[0] = readl(&regs->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
- desc.cmd.next = (uint32_t)&desc.cmd;
+dealloc_fb:
+ free(fb);
- /* Execute the DMA chain. */
- mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
-#endif
+ return NULL;
+}
+#else /* ifndef CONFIG_DM_VIDEO */
- return (void *)&panel;
+static int mxs_video_probe(struct udevice *dev)
+{
+ struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ struct ctfb_res_modes mode;
+ struct display_timing timings;
+ int bpp = -1;
+ u32 fb_start, fb_end;
+ int ret;
+
+ debug("%s() plat: base 0x%lx, size 0x%x\n",
+ __func__, plat->base, plat->size);
+
+ ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, &timings);
+ if (ret) {
+ dev_err(dev, "failed to get any display timings\n");
+ return -EINVAL;
+ }
+
+ mode.xres = timings.hactive.typ;
+ mode.yres = timings.vactive.typ;
+ mode.left_margin = timings.hback_porch.typ;
+ mode.right_margin = timings.hfront_porch.typ;
+ mode.upper_margin = timings.vback_porch.typ;
+ mode.lower_margin = timings.vfront_porch.typ;
+ mode.hsync_len = timings.hsync_len.typ;
+ mode.vsync_len = timings.vsync_len.typ;
+ mode.pixclock = HZ2PS(timings.pixelclock.typ);
+
+ bpp = BITS_PP;
+
+ ret = mxs_probe_common(&mode, bpp, plat->base);
+ if (ret)
+ return ret;
+
+ switch (bpp) {
+ case 24:
+ case 18:
+ uc_priv->bpix = VIDEO_BPP32;
+ break;
+ case 16:
+ uc_priv->bpix = VIDEO_BPP16;
+ break;
+ case 8:
+ uc_priv->bpix = VIDEO_BPP8;
+ break;
+ default:
+ dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
+ return -EINVAL;
+ }
+
+ uc_priv->xsize = mode.xres;
+ uc_priv->ysize = mode.yres;
+
+ /* Enable dcache for the frame buffer */
+ fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
+ fb_end = plat->base + plat->size;
+ fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
+ mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
+ DCACHE_WRITEBACK);
+ video_set_flush_dcache(dev, true);
+
+ return ret;
+}
+
+static int mxs_video_bind(struct udevice *dev)
+{
+ struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct display_timing timings;
+ int ret;
+
+ ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, &timings);
+ if (ret) {
+ dev_err(dev, "failed to get any display timings\n");
+ return -EINVAL;
+ }
+
+ plat->size = timings.hactive.typ * timings.vactive.typ * BYTES_PP;
+
+ return 0;
}
+
+static int mxs_video_remove(struct udevice *dev)
+{
+ struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+
+ mxs_remove_common(plat->base);
+
+ return 0;
+}
+
+static const struct udevice_id mxs_video_ids[] = {
+ { .compatible = "fsl,imx23-lcdif" },
+ { .compatible = "fsl,imx28-lcdif" },
+ { .compatible = "fsl,imx7ulp-lcdif" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(mxs_video) = {
+ .name = "mxs_video",
+ .id = UCLASS_VIDEO,
+ .of_match = mxs_video_ids,
+ .bind = mxs_video_bind,
+ .probe = mxs_video_probe,
+ .remove = mxs_video_remove,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+#endif /* ifndef CONFIG_DM_VIDEO */
generated by cgit (git 2.34.1) at 2025-01-25 14:47:09 +0000