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-rw-r--r--drivers/i2c/Kconfig6
-rw-r--r--drivers/i2c/i2c-uniphier-f.c6
-rw-r--r--drivers/i2c/i2c-uniphier.c6
-rw-r--r--drivers/i2c/omap24xx_i2c.c2
-rw-r--r--drivers/mtd/nand/Makefile1
-rw-r--r--drivers/mtd/nand/sunxi_nand_spl.c273
-rw-r--r--drivers/serial/Kconfig5
-rw-r--r--drivers/serial/serial_uniphier.c6
-rw-r--r--drivers/usb/gadget/ci_udc.c135
-rw-r--r--drivers/usb/gadget/ci_udc.h1
-rw-r--r--drivers/usb/host/Kconfig10
-rw-r--r--drivers/usb/host/dwc2.c3
-rw-r--r--drivers/usb/host/dwc2.h1
-rw-r--r--drivers/usb/host/ehci-uniphier.c6
-rw-r--r--drivers/usb/host/xhci-uniphier.c5
-rw-r--r--drivers/video/am335x-fb.c2
-rw-r--r--drivers/video/am335x-fb.h2
17 files changed, 417 insertions, 53 deletions
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index ba43019ab9..86fb36b5d4 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -63,13 +63,13 @@ config SYS_I2C_UNIPHIER
depends on ARCH_UNIPHIER && DM_I2C
default y
help
- Support for Panasonic UniPhier I2C controller driver. This I2C
- controller is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
+ Support for UniPhier I2C controller driver. This I2C controller
+ is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
config SYS_I2C_UNIPHIER_F
bool "UniPhier FIFO-builtin I2C driver"
depends on ARCH_UNIPHIER && DM_I2C
default y
help
- Support for Panasonic UniPhier FIFO-builtin I2C controller driver.
+ Support for UniPhier FIFO-builtin I2C controller driver.
This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
diff --git a/drivers/i2c/i2c-uniphier-f.c b/drivers/i2c/i2c-uniphier-f.c
index d29dd4565d..b3349af9e1 100644
--- a/drivers/i2c/i2c-uniphier-f.c
+++ b/drivers/i2c/i2c-uniphier-f.c
@@ -1,14 +1,12 @@
/*
- * Copyright (C) 2014 Panasonic Corporation
- * Copyright (C) 2015 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/types.h>
-#include <asm/io.h>
+#include <linux/io.h>
#include <asm/errno.h>
#include <dm/device.h>
#include <dm/root.h>
diff --git a/drivers/i2c/i2c-uniphier.c b/drivers/i2c/i2c-uniphier.c
index c4972ff501..85b9eff5f8 100644
--- a/drivers/i2c/i2c-uniphier.c
+++ b/drivers/i2c/i2c-uniphier.c
@@ -1,14 +1,12 @@
/*
- * Copyright (C) 2014 Panasonic Corporation
- * Copyright (C) 2015 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/types.h>
-#include <asm/io.h>
+#include <linux/io.h>
#include <asm/errno.h>
#include <dm/device.h>
#include <dm/root.h>
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index 0f1e35c460..79a5c94f1c 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -33,7 +33,7 @@
* (except for OMAP243X and OMAP34XX).
* - Driver now supports up to I2C5 (OMAP5).
*
- * Copyright (c) 2014 Hannes Petermaier <oe5hpm@oevsv.at>, B&R
+ * Copyright (c) 2014 Hannes Schmelzer <oe5hpm@oevsv.at>, B&R
* - Added support for set_speed
*
*/
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 347ea62e0b..a0cf4d5fe4 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -73,5 +73,6 @@ obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o
obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o
obj-$(CONFIG_NAND_MXC) += mxc_nand_spl.o
obj-$(CONFIG_NAND_MXS) += mxs_nand_spl.o mxs_nand.o
+obj-$(CONFIG_NAND_SUNXI) += sunxi_nand_spl.o
endif # drivers
diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c
new file mode 100644
index 0000000000..75982f54cc
--- /dev/null
+++ b/drivers/mtd/nand/sunxi_nand_spl.c
@@ -0,0 +1,273 @@
+/*
+ * Copyright (c) 2014, Antmicro Ltd <www.antmicro.com>
+ * Copyright (c) 2015, Turtle Solutions <www.turtle-solutions.eu>
+ * Copyright (c) 2015, Roy Spliet <rspliet@ultimaker.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * \todo Detect chip parameters (page size, ECC mode, randomisation...)
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/dma.h>
+#include <asm/arch/nand.h>
+
+void
+nand_init(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_nand * const nand = (struct sunxi_nand *)SUNXI_NFC_BASE;
+ u32 val;
+
+ board_nand_init();
+
+ /* "un-gate" NAND clock and clock source
+ * This assumes that the clock was already correctly configured by
+ * BootROM */
+ setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_NAND0));
+#ifdef CONFIG_MACH_SUN9I
+ setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
+#else
+ setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
+#endif
+ setbits_le32(&ccm->nand0_clk_cfg, 0x80000000);
+
+ val = readl(&nand->ctl);
+ val |= SUNXI_NAND_CTL_RST;
+ writel(val, &nand->ctl);
+
+ /* Wait until reset pin is deasserted */
+ do {
+ val = readl(&nand->ctl);
+ if (!(val & SUNXI_NAND_CTL_RST))
+ break;
+ } while (1);
+
+ /** \todo Chip select, currently kind of static */
+ val = readl(&nand->ctl);
+ val &= 0xf0fff0f2;
+ val |= SUNXI_NAND_CTL_EN;
+ val |= SUNXI_NAND_CTL_PAGE_SIZE(CONFIG_NAND_SUNXI_PAGE_SIZE);
+ writel(val, &nand->ctl);
+
+ writel(0x100, &nand->timing_ctl);
+ writel(0x7ff, &nand->timing_cfg);
+
+ /* reset CMD */
+ val = SUNXI_NAND_CMD_SEND_CMD1 | SUNXI_NAND_CMD_WAIT_FLAG |
+ NAND_CMD_RESET;
+ writel(val, &nand->cmd);
+ do {
+ val = readl(&nand->st);
+ if (val & (1<<1))
+ break;
+ udelay(1000);
+ } while (1);
+
+ printf("Nand initialised\n");
+}
+
+int
+nand_wait_timeout(u32 *reg, u32 mask, u32 val)
+{
+ unsigned long tmo = timer_get_us() + 1000000; /* 1s */
+
+ while ((readl(reg) & mask) != val) {
+ if (timer_get_us() > tmo)
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+/* random seed */
+static const uint16_t random_seed[128] = {
+ 0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
+ 0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
+ 0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
+ 0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
+ 0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
+ 0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
+ 0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
+ 0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
+ 0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
+ 0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
+ 0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
+ 0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
+ 0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
+ 0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
+ 0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
+ 0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
+};
+
+uint32_t ecc_errors = 0;
+
+static void
+nand_config_ecc(struct sunxi_nand *nand, uint32_t page, int syndrome)
+{
+ static u8 strength[] = {16, 24, 28, 32, 40, 48, 56, 60, 64};
+ int i;
+ uint32_t ecc_mode;
+ u32 ecc;
+ u16 seed = 0;
+
+ for (i = 0; i < ARRAY_SIZE(strength); i++) {
+ if (CONFIG_NAND_SUNXI_ECC_STRENGTH == strength[i]) {
+ ecc_mode = i;
+ break;
+ }
+ }
+
+ if (i == ARRAY_SIZE(strength)) {
+ printf("ECC strength unsupported\n");
+ return;
+ }
+
+ ecc = SUNXI_NAND_ECC_CTL_ECC_EN |
+ SUNXI_NAND_ECC_CTL_PIPELINE |
+ SUNXI_NAND_ECC_CTL_RND_EN |
+ SUNXI_NAND_ECC_CTL_MODE(ecc_mode);
+
+ if (CONFIG_NAND_SUNXI_ECC_STEP == 512)
+ ecc |= SUNXI_NAND_ECC_CTL_BS_512B;
+
+ if (syndrome)
+ seed = 0x4A80;
+ else
+ seed = random_seed[page % ARRAY_SIZE(random_seed)];
+
+ ecc |= SUNXI_NAND_ECC_CTL_RND_SEED(seed);
+
+ writel(ecc, &nand->ecc_ctl);
+}
+
+/* read CONFIG_NAND_SUNXI_ECC_STEP bytes from real_addr to temp_buf */
+void
+nand_read_block(struct sunxi_nand *nand, phys_addr_t src, dma_addr_t dst,
+ int syndrome)
+{
+ struct sunxi_dma * const dma = (struct sunxi_dma *)SUNXI_DMA_BASE;
+ struct sunxi_dma_cfg * const dma_cfg = &dma->ddma[0];
+
+ uint32_t shift;
+ uint32_t page;
+ uint32_t addr;
+ uint32_t oob_offset;
+ uint32_t ecc_bytes;
+ u32 val;
+ u32 cmd;
+
+ page = src / CONFIG_NAND_SUNXI_PAGE_SIZE;
+ if (page > 0xFFFF) {
+ /* TODO: currently this is not supported */
+ printf("Reading from address >= %08X is not allowed.\n",
+ 0xFFFF * CONFIG_NAND_SUNXI_PAGE_SIZE);
+ return;
+ }
+
+ shift = src % CONFIG_NAND_SUNXI_PAGE_SIZE;
+ writel(0, &nand->ecc_st);
+
+ /* ECC_CTL, randomization */
+ ecc_bytes = CONFIG_NAND_SUNXI_ECC_STRENGTH *
+ fls(CONFIG_NAND_SUNXI_ECC_STEP * 8);
+ ecc_bytes = DIV_ROUND_UP(ecc_bytes, 8);
+ ecc_bytes += (ecc_bytes & 1); /* Align to 2-bytes */
+ ecc_bytes += 4;
+
+ nand_config_ecc(nand, page, syndrome);
+ if (syndrome) {
+ /* shift every 1kB in syndrome */
+ shift += (shift / CONFIG_NAND_SUNXI_ECC_STEP) * ecc_bytes;
+ oob_offset = CONFIG_NAND_SUNXI_ECC_STEP + shift;
+ } else {
+ oob_offset = CONFIG_NAND_SUNXI_PAGE_SIZE +
+ (shift / CONFIG_NAND_SUNXI_ECC_STEP) * ecc_bytes;
+ }
+
+ addr = (page << 16) | shift;
+
+ /* DMA */
+ val = readl(&nand->ctl);
+ writel(val | SUNXI_NAND_CTL_RAM_METHOD_DMA, &nand->ctl);
+
+ writel(oob_offset, &nand->spare_area);
+
+ /* DMAC
+ * \todo Separate this into a tidy driver */
+ writel(0x0, &dma->irq_en); /* clear dma interrupts */
+ writel((uint32_t) &nand->io_data , &dma_cfg->src_addr);
+ writel(dst , &dma_cfg->dst_addr);
+ writel(0x00007F0F , &dma_cfg->ddma_para);
+ writel(CONFIG_NAND_SUNXI_ECC_STEP, &dma_cfg->bc);
+
+ val = SUNXI_DMA_CTL_SRC_DRQ(DDMA_SRC_DRQ_NAND) |
+ SUNXI_DMA_CTL_MODE_IO |
+ SUNXI_DMA_CTL_SRC_DATA_WIDTH_32 |
+ SUNXI_DMA_CTL_DST_DRQ(DDMA_DST_DRQ_SDRAM) |
+ SUNXI_DMA_CTL_DST_DATA_WIDTH_32 |
+ SUNXI_DMA_CTL_TRIGGER;
+ writel(val, &dma_cfg->ctl);
+
+ writel(0x00E00530, &nand->rcmd_set);
+ nand_wait_timeout(&nand->st, SUNXI_NAND_ST_FIFO_FULL, 0);
+
+ writel(1 , &nand->block_num);
+ writel(addr, &nand->addr_low);
+ writel(0 , &nand->addr_high);
+
+ /* CMD (PAGE READ) */
+ cmd = 0x85E80000;
+ cmd |= SUNXI_NAND_CMD_ADDR_CYCLES(CONFIG_NAND_SUNXI_ADDR_CYCLES);
+ cmd |= (syndrome ? SUNXI_NAND_CMD_ORDER_SEQ :
+ SUNXI_NAND_CMD_ORDER_INTERLEAVE);
+ writel(cmd, &nand->cmd);
+
+ if(nand_wait_timeout(&nand->st, SUNXI_NAND_ST_DMA_INT,
+ SUNXI_NAND_ST_DMA_INT)) {
+ printf("NAND timeout reading data\n");
+ return;
+ }
+
+ if(nand_wait_timeout(&dma_cfg->ctl, SUNXI_DMA_CTL_TRIGGER, 0)) {
+ printf("NAND timeout reading data\n");
+ return;
+ }
+
+ if (readl(&nand->ecc_st))
+ ecc_errors++;
+}
+
+int
+nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
+{
+ struct sunxi_nand * const nand = (struct sunxi_nand *)SUNXI_NFC_BASE;
+ dma_addr_t dst_block;
+ dma_addr_t dst_end;
+ phys_addr_t addr = offs;
+
+ dst_end = ((dma_addr_t) dest) + size;
+
+ memset((void *)dest, 0x0, size);
+ ecc_errors = 0;
+ for (dst_block = (dma_addr_t) dest; dst_block < dst_end;
+ dst_block += CONFIG_NAND_SUNXI_ECC_STEP,
+ addr += CONFIG_NAND_SUNXI_ECC_STEP) {
+ /* syndrome read first 4MiB to match Allwinner BootROM */
+ nand_read_block(nand, addr, dst_block, addr < 0x400000);
+ }
+
+ if (ecc_errors)
+ printf("Error: %d ECC failures detected\n", ecc_errors);
+ return ecc_errors == 0;
+}
+
+void
+nand_deselect(void)
+{}
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 54e6f26d38..5611fac0dc 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -77,7 +77,8 @@ config DEBUG_UART_SHIFT
registers, 2=32-bit word registers, etc.
config UNIPHIER_SERIAL
- bool "UniPhier on-chip UART support"
+ bool "Support for UniPhier on-chip UART"
depends on ARCH_UNIPHIER && DM_SERIAL
help
- Support for the on-chip UARTs on the Panasonic UniPhier platform.
+ If you have a UniPhier based board and want to use the on-chip
+ serial ports, say Y to this option. If unsure, say N.
diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c
index 74547eb692..f210986078 100644
--- a/drivers/serial/serial_uniphier.c
+++ b/drivers/serial/serial_uniphier.c
@@ -1,13 +1,11 @@
/*
- * Copyright (C) 2012-2015 Panasonic Corporation
- * Copyright (C) 2015 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <linux/io.h>
#include <linux/serial_reg.h>
-#include <asm/io.h>
#include <asm/errno.h>
#include <dm/device.h>
#include <dm/platform_data/serial-uniphier.h>
diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c
index 22d288c711..aadff42a9c 100644
--- a/drivers/usb/gadget/ci_udc.c
+++ b/drivers/usb/gadget/ci_udc.c
@@ -50,6 +50,8 @@
/* For each endpoint, we need 2 QTDs, one for each of IN and OUT */
#define ILIST_SZ (NUM_ENDPOINTS * 2 * ILIST_ENT_SZ)
+#define EP_MAX_LENGTH_TRANSFER 0x4000
+
#ifndef DEBUG
#define DBG(x...) do {} while (0)
#else
@@ -102,13 +104,28 @@ static struct usb_ep_ops ci_ep_ops = {
};
/* Init values for USB endpoints. */
-static const struct usb_ep ci_ep_init[2] = {
+static const struct usb_ep ci_ep_init[5] = {
[0] = { /* EP 0 */
.maxpacket = 64,
.name = "ep0",
.ops = &ci_ep_ops,
},
- [1] = { /* EP 1..n */
+ [1] = {
+ .maxpacket = 512,
+ .name = "ep1in-bulk",
+ .ops = &ci_ep_ops,
+ },
+ [2] = {
+ .maxpacket = 512,
+ .name = "ep2out-bulk",
+ .ops = &ci_ep_ops,
+ },
+ [3] = {
+ .maxpacket = 512,
+ .name = "ep3in-int",
+ .ops = &ci_ep_ops,
+ },
+ [4] = {
.maxpacket = 512,
.name = "ep-",
.ops = &ci_ep_ops,
@@ -197,6 +214,19 @@ static void ci_flush_qtd(int ep_num)
}
/**
+ * ci_flush_td - flush cache over queue item
+ * @td: td pointer
+ *
+ * This function flushes cache for particular transfer descriptor.
+ */
+static void ci_flush_td(struct ept_queue_item *td)
+{
+ const uint32_t start = (uint32_t)td;
+ const uint32_t end = (uint32_t) td + ILIST_ENT_SZ;
+ flush_dcache_range(start, end);
+}
+
+/**
* ci_invalidate_qtd - invalidate cache over queue item
* @ep_num: Endpoint number
*
@@ -211,6 +241,19 @@ static void ci_invalidate_qtd(int ep_num)
invalidate_dcache_range(start, end);
}
+/**
+ * ci_invalidate_td - invalidate cache over queue item
+ * @td: td pointer
+ *
+ * This function invalidates cache for particular transfer descriptor.
+ */
+static void ci_invalidate_td(struct ept_queue_item *td)
+{
+ const uint32_t start = (uint32_t)td;
+ const uint32_t end = start + ILIST_ENT_SZ;
+ invalidate_dcache_range(start, end);
+}
+
static struct usb_request *
ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags)
{
@@ -376,6 +419,9 @@ static void ci_ep_submit_next_request(struct ci_ep *ci_ep)
struct ept_queue_head *head;
int bit, num, len, in;
struct ci_req *ci_req;
+ u8 *buf;
+ uint32_t length, actlen;
+ struct ept_queue_item *dtd, *qtd;
ci_ep->req_primed = true;
@@ -387,16 +433,41 @@ static void ci_ep_submit_next_request(struct ci_ep *ci_ep)
ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue);
len = ci_req->req.length;
- item->info = INFO_BYTES(len) | INFO_ACTIVE;
- item->page0 = (unsigned long)ci_req->hw_buf;
- item->page1 = ((unsigned long)ci_req->hw_buf & 0xfffff000) + 0x1000;
- item->page2 = ((unsigned long)ci_req->hw_buf & 0xfffff000) + 0x2000;
- item->page3 = ((unsigned long)ci_req->hw_buf & 0xfffff000) + 0x3000;
- item->page4 = ((unsigned long)ci_req->hw_buf & 0xfffff000) + 0x4000;
-
head->next = (unsigned long)item;
head->info = 0;
+ ci_req->dtd_count = 0;
+ buf = ci_req->hw_buf;
+ actlen = 0;
+ dtd = item;
+
+ do {
+ length = min(ci_req->req.length - actlen,
+ (unsigned)EP_MAX_LENGTH_TRANSFER);
+
+ dtd->info = INFO_BYTES(length) | INFO_ACTIVE;
+ dtd->page0 = (unsigned long)buf;
+ dtd->page1 = ((unsigned long)buf & 0xfffff000) + 0x1000;
+ dtd->page2 = ((unsigned long)buf & 0xfffff000) + 0x2000;
+ dtd->page3 = ((unsigned long)buf & 0xfffff000) + 0x3000;
+ dtd->page4 = ((unsigned long)buf & 0xfffff000) + 0x4000;
+
+ len -= length;
+ actlen += length;
+ buf += length;
+
+ if (len) {
+ qtd = (struct ept_queue_item *)
+ memalign(ILIST_ALIGN, ILIST_ENT_SZ);
+ dtd->next = (uint32_t)qtd;
+ dtd = qtd;
+ memset(dtd, 0, ILIST_ENT_SZ);
+ }
+
+ ci_req->dtd_count++;
+ } while (len);
+
+ item = dtd;
/*
* When sending the data for an IN transaction, the attached host
* knows that all data for the IN is sent when one of the following
@@ -432,6 +503,12 @@ static void ci_ep_submit_next_request(struct ci_ep *ci_ep)
ci_flush_qtd(num);
+ item = (struct ept_queue_item *)head->next;
+ while (item->next != TERMINATE) {
+ ci_flush_td((struct ept_queue_item *)item->next);
+ item = (struct ept_queue_item *)item->next;
+ }
+
DBG("ept%d %s queue len %x, req %p, buffer %p\n",
num, in ? "in" : "out", len, ci_req, ci_req->hw_buf);
ci_flush_qh(num);
@@ -497,21 +574,31 @@ static void flip_ep0_direction(void)
static void handle_ep_complete(struct ci_ep *ci_ep)
{
- struct ept_queue_item *item;
- int num, in, len;
+ struct ept_queue_item *item, *next_td;
+ int num, in, len, j;
struct ci_req *ci_req;
num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
item = ci_get_qtd(num, in);
ci_invalidate_qtd(num);
+ ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue);
- len = (item->info >> 16) & 0x7fff;
- if (item->info & 0xff)
- printf("EP%d/%s FAIL info=%x pg0=%x\n",
- num, in ? "in" : "out", item->info, item->page0);
+ next_td = item;
+ len = 0;
+ for (j = 0; j < ci_req->dtd_count; j++) {
+ ci_invalidate_td(next_td);
+ item = next_td;
+ len += (item->info >> 16) & 0x7fff;
+ if (item->info & 0xff)
+ printf("EP%d/%s FAIL info=%x pg0=%x\n",
+ num, in ? "in" : "out", item->info, item->page0);
+ if (j != ci_req->dtd_count - 1)
+ next_td = (struct ept_queue_item *)item->next;
+ if (j != 0)
+ free(item);
+ }
- ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue);
list_del_init(&ci_req->queue);
ci_ep->req_primed = false;
@@ -852,9 +939,19 @@ static int ci_udc_probe(void)
controller.gadget.ep0 = &controller.ep[0].ep;
INIT_LIST_HEAD(&controller.gadget.ep0->ep_list);
- /* Init EP 1..n */
- for (i = 1; i < NUM_ENDPOINTS; i++) {
- memcpy(&controller.ep[i].ep, &ci_ep_init[1],
+ /* Init EP 1..3 */
+ for (i = 1; i < 4; i++) {
+ memcpy(&controller.ep[i].ep, &ci_ep_init[i],
+ sizeof(*ci_ep_init));
+ INIT_LIST_HEAD(&controller.ep[i].queue);
+ controller.ep[i].req_primed = false;
+ list_add_tail(&controller.ep[i].ep.ep_list,
+ &controller.gadget.ep_list);
+ }
+
+ /* Init EP 4..n */
+ for (i = 4; i < NUM_ENDPOINTS; i++) {
+ memcpy(&controller.ep[i].ep, &ci_ep_init[4],
sizeof(*ci_ep_init));
INIT_LIST_HEAD(&controller.ep[i].queue);
controller.ep[i].req_primed = false;
diff --git a/drivers/usb/gadget/ci_udc.h b/drivers/usb/gadget/ci_udc.h
index 346164a641..95cc07992b 100644
--- a/drivers/usb/gadget/ci_udc.h
+++ b/drivers/usb/gadget/ci_udc.h
@@ -86,6 +86,7 @@ struct ci_req {
/* Buffer for the current transfer. Either req.buf/len or b_buf/len */
uint8_t *hw_buf;
uint32_t hw_len;
+ uint32_t dtd_count;
};
struct ci_ep {
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 24a595fb42..8705c7c44c 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -18,12 +18,11 @@ config USB_XHCI
if USB_XHCI_HCD
config USB_XHCI_UNIPHIER
- bool "Support for Panasonic UniPhier on-chip xHCI USB controller"
+ bool "Support for UniPhier on-chip xHCI USB controller"
depends on ARCH_UNIPHIER
default y
---help---
- Enables support for the on-chip xHCI controller on Panasonic
- UniPhier SoCs.
+ Enables support for the on-chip xHCI controller on UniPhier SoCs.
endif
@@ -54,11 +53,10 @@ config USB_EHCI
if USB_EHCI_HCD
config USB_EHCI_UNIPHIER
- bool "Support for Panasonic UniPhier on-chip EHCI USB controller"
+ bool "Support for UniPhier on-chip EHCI USB controller"
depends on ARCH_UNIPHIER && OF_CONTROL
default y
---help---
- Enables support for the on-chip EHCI controller on Panasonic
- UniPhier SoCs.
+ Enables support for the on-chip EHCI controller on UniPhier SoCs.
endif
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 2ac00177a2..eee60a2b03 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -932,7 +932,8 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
snpsid = readl(&regs->gsnpsid);
printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
- if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx) {
+ if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
+ (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
return -ENODEV;
}
diff --git a/drivers/usb/host/dwc2.h b/drivers/usb/host/dwc2.h
index 45408c6f5c..f69372e6b4 100644
--- a/drivers/usb/host/dwc2.h
+++ b/drivers/usb/host/dwc2.h
@@ -732,6 +732,7 @@ struct dwc2_core_regs {
#define DWC2_PCGCCTL_DEEP_SLEEP (1 << 7)
#define DWC2_PCGCCTL_DEEP_SLEEP_OFFSET 7
#define DWC2_SNPSID_DEVID_VER_2xx (0x4f542 << 12)
+#define DWC2_SNPSID_DEVID_VER_3xx (0x4f543 << 12)
#define DWC2_SNPSID_DEVID_MASK (0xfffff << 12)
#define DWC2_SNPSID_DEVID_OFFSET 12
diff --git a/drivers/usb/host/ehci-uniphier.c b/drivers/usb/host/ehci-uniphier.c
index 846bf509d6..c3f827ca0a 100644
--- a/drivers/usb/host/ehci-uniphier.c
+++ b/drivers/usb/host/ehci-uniphier.c
@@ -1,14 +1,12 @@
/*
- * Copyright (C) 2014 Panasonic Corporation
- * Copyright (C) 2015 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/err.h>
-#include <asm/io.h>
+#include <linux/io.h>
#include <usb.h>
#include <mach/mio-regs.h>
#include <fdtdec.h>
diff --git a/drivers/usb/host/xhci-uniphier.c b/drivers/usb/host/xhci-uniphier.c
index e0ef322172..1b3f3d22de 100644
--- a/drivers/usb/host/xhci-uniphier.c
+++ b/drivers/usb/host/xhci-uniphier.c
@@ -1,13 +1,12 @@
/*
- * Copyright (C) 2015 Panasonic Corporation
- * Copyright (C) 2015 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/err.h>
+#include <linux/io.h>
#include <usb.h>
#include <fdtdec.h>
#include "xhci.h"
diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c
index 6f956499d7..e23d172001 100644
--- a/drivers/video/am335x-fb.c
+++ b/drivers/video/am335x-fb.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
+ * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
*
* minimal framebuffer driver for TI's AM335x SoC to be compatible with
diff --git a/drivers/video/am335x-fb.h b/drivers/video/am335x-fb.h
index 7f799d1f31..3f4b567ce2 100644
--- a/drivers/video/am335x-fb.h
+++ b/drivers/video/am335x-fb.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> -
+ * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> -
* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
*
* SPDX-License-Identifier: GPL-2.0+
generated by cgit (git 2.34.1) at 2024-12-29 09:03:48 +0000