diff options
Diffstat (limited to 'drivers')
54 files changed, 1807 insertions, 486 deletions
diff --git a/drivers/Makefile b/drivers/Makefile index dab5c182c2..e6062a5683 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -50,6 +50,7 @@ obj-$(CONFIG_SPL_SATA_SUPPORT) += ata/ scsi/ obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/ obj-$(CONFIG_SPL_MMC_SUPPORT) += block/ obj-$(CONFIG_SPL_FPGA_SUPPORT) += fpga/ +obj-$(CONFIG_SPL_THERMAL) += thermal/ endif endif diff --git a/drivers/clk/clk_stm32f7.c b/drivers/clk/clk_stm32f7.c index a273f8ff5e..f1a9e9ca44 100644 --- a/drivers/clk/clk_stm32f7.c +++ b/drivers/clk/clk_stm32f7.c @@ -136,13 +136,15 @@ static int configure_clocks(struct udevice *dev) | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT))); /* Configure the main PLL */ - uint32_t pllcfgr = 0; - pllcfgr = RCC_PLLCFGR_PLLSRC; /* pll source HSE */ - pllcfgr |= sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT; - pllcfgr |= sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT; - pllcfgr |= ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT; - pllcfgr |= sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT; - writel(pllcfgr, ®s->pllcfgr); + setbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */ + clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLM_MASK, + sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT); + clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLN_MASK, + sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT); + clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLP_MASK, + ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); + clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLQ_MASK, + sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT); /* Enable the main PLL */ setbits_le32(®s->cr, RCC_CR_PLLON); diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c index 83f4ae6ca3..280ebb9ba2 100644 --- a/drivers/clk/rockchip/clk_rk3036.c +++ b/drivers/clk/rockchip/clk_rk3036.c @@ -330,11 +330,22 @@ static int rk3036_clk_probe(struct udevice *dev) static int rk3036_clk_bind(struct udevice *dev) { int ret; + struct udevice *sys_child; + struct sysreset_reg *priv; /* The reset driver does not have a device node, so bind it here */ - ret = device_bind_driver(gd->dm_root, "rk3036_sysreset", "reset", &dev); - if (ret) - debug("Warning: No RK3036 reset driver: ret=%d\n", ret); + ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", + &sys_child); + if (ret) { + debug("Warning: No sysreset driver: ret=%d\n", ret); + } else { + priv = malloc(sizeof(struct sysreset_reg)); + priv->glb_srst_fst_value = offsetof(struct rk3036_cru, + cru_glb_srst_fst_value); + priv->glb_srst_snd_value = offsetof(struct rk3036_cru, + cru_glb_srst_snd_value); + sys_child->priv = priv; + } return 0; } diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c index 8c2c9bc1d8..fca6899d8b 100644 --- a/drivers/clk/rockchip/clk_rk3188.c +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -573,11 +573,22 @@ static int rk3188_clk_probe(struct udevice *dev) static int rk3188_clk_bind(struct udevice *dev) { int ret; + struct udevice *sys_child; + struct sysreset_reg *priv; /* The reset driver does not have a device node, so bind it here */ - ret = device_bind_driver(gd->dm_root, "rk3188_sysreset", "reset", &dev); - if (ret) - debug("Warning: No rk3188 reset driver: ret=%d\n", ret); + ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", + &sys_child); + if (ret) { + debug("Warning: No sysreset driver: ret=%d\n", ret); + } else { + priv = malloc(sizeof(struct sysreset_reg)); + priv->glb_srst_fst_value = offsetof(struct rk3188_cru, + cru_glb_srst_fst_value); + priv->glb_srst_snd_value = offsetof(struct rk3188_cru, + cru_glb_srst_snd_value); + sys_child->priv = priv; + } return 0; } diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index e87267d239..ff52b55229 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -385,11 +385,22 @@ static int rk322x_clk_probe(struct udevice *dev) static int rk322x_clk_bind(struct udevice *dev) { int ret; + struct udevice *sys_child; + struct sysreset_reg *priv; /* The reset driver does not have a device node, so bind it here */ - ret = device_bind_driver(gd->dm_root, "rk322x_sysreset", "reset", &dev); - if (ret) - debug("Warning: No RK322x reset driver: ret=%d\n", ret); + ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", + &sys_child); + if (ret) { + debug("Warning: No sysreset driver: ret=%d\n", ret); + } else { + priv = malloc(sizeof(struct sysreset_reg)); + priv->glb_srst_fst_value = offsetof(struct rk322x_cru, + cru_glb_srst_fst_value); + priv->glb_srst_snd_value = offsetof(struct rk322x_cru, + cru_glb_srst_snd_value); + sys_child->priv = priv; + } return 0; } diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index a133810bf6..ac53239363 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -859,11 +859,22 @@ static int rk3288_clk_probe(struct udevice *dev) static int rk3288_clk_bind(struct udevice *dev) { int ret; + struct udevice *sys_child; + struct sysreset_reg *priv; /* The reset driver does not have a device node, so bind it here */ - ret = device_bind_driver(gd->dm_root, "rk3288_sysreset", "reset", &dev); - if (ret) - debug("Warning: No RK3288 reset driver: ret=%d\n", ret); + ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", + &sys_child); + if (ret) { + debug("Warning: No sysreset driver: ret=%d\n", ret); + } else { + priv = malloc(sizeof(struct sysreset_reg)); + priv->glb_srst_fst_value = offsetof(struct rk3288_cru, + cru_glb_srst_fst_value); + priv->glb_srst_snd_value = offsetof(struct rk3288_cru, + cru_glb_srst_snd_value); + sys_child->priv = priv; + } return 0; } diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index 540d9104c3..4d522a7816 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -597,11 +597,22 @@ static int rk3328_clk_ofdata_to_platdata(struct udevice *dev) static int rk3328_clk_bind(struct udevice *dev) { int ret; + struct udevice *sys_child; + struct sysreset_reg *priv; /* The reset driver does not have a device node, so bind it here */ - ret = device_bind_driver(gd->dm_root, "rk3328_sysreset", "reset", &dev); - if (ret) - printf("Warning: No RK3328 reset driver: ret=%d\n", ret); + ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", + &sys_child); + if (ret) { + debug("Warning: No sysreset driver: ret=%d\n", ret); + } else { + priv = malloc(sizeof(struct sysreset_reg)); + priv->glb_srst_fst_value = offsetof(struct rk3328_cru, + glb_srst_fst_value); + priv->glb_srst_snd_value = offsetof(struct rk3328_cru, + glb_srst_snd_value); + sys_child->priv = priv; + } return ret; } diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c index 3661769748..bfeef39d2a 100644 --- a/drivers/clk/rockchip/clk_rk3368.c +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -526,11 +526,22 @@ static int rk3368_clk_ofdata_to_platdata(struct udevice *dev) static int rk3368_clk_bind(struct udevice *dev) { int ret; + struct udevice *sys_child; + struct sysreset_reg *priv; /* The reset driver does not have a device node, so bind it here */ - ret = device_bind_driver(gd->dm_root, "rk3368_sysreset", "reset", &dev); - if (ret) - pr_err("bind RK3368 reset driver failed: ret=%d\n", ret); + ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", + &sys_child); + if (ret) { + debug("Warning: No sysreset driver: ret=%d\n", ret); + } else { + priv = malloc(sizeof(struct sysreset_reg)); + priv->glb_srst_fst_value = offsetof(struct rk3368_cru, + glb_srst_fst_val); + priv->glb_srst_snd_value = offsetof(struct rk3368_cru, + glb_srst_snd_val); + sys_child->priv = priv; + } return ret; } diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 6f85a38e41..2e85ac7df2 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -569,11 +569,6 @@ static const struct spi_clkreg spi_clkregs[] = { .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, }, }; -static inline u32 extract_bits(u32 val, unsigned width, unsigned shift) -{ - return (val >> shift) & ((1 << width) - 1); -} - static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id) { const struct spi_clkreg *spiclk = NULL; @@ -590,7 +585,8 @@ static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id) } val = readl(&cru->clksel_con[spiclk->reg]); - div = extract_bits(val, CLK_SPI_PLL_DIV_CON_WIDTH, spiclk->div_shift); + div = bitfield_extract(val, spiclk->div_shift, + CLK_SPI_PLL_DIV_CON_WIDTH); return DIV_TO_RATE(GPLL_HZ, div); } @@ -1033,11 +1029,22 @@ static int rk3399_clk_ofdata_to_platdata(struct udevice *dev) static int rk3399_clk_bind(struct udevice *dev) { int ret; + struct udevice *sys_child; + struct sysreset_reg *priv; /* The reset driver does not have a device node, so bind it here */ - ret = device_bind_driver(gd->dm_root, "rk3399_sysreset", "reset", &dev); - if (ret) - printf("Warning: No RK3399 reset driver: ret=%d\n", ret); + ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", + &sys_child); + if (ret) { + debug("Warning: No sysreset driver: ret=%d\n", ret); + } else { + priv = malloc(sizeof(struct sysreset_reg)); + priv->glb_srst_fst_value = offsetof(struct rk3399_cru, + glb_srst_fst_value); + priv->glb_srst_snd_value = offsetof(struct rk3399_cru, + glb_srst_snd_value); + sys_child->priv = priv; + } return 0; } diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c index 55741c3a1e..a1195486a9 100644 --- a/drivers/clk/rockchip/clk_rv1108.c +++ b/drivers/clk/rockchip/clk_rv1108.c @@ -223,11 +223,22 @@ static int rv1108_clk_probe(struct udevice *dev) static int rv1108_clk_bind(struct udevice *dev) { int ret; + struct udevice *sys_child; + struct sysreset_reg *priv; /* The reset driver does not have a device node, so bind it here */ - ret = device_bind_driver(gd->dm_root, "rv1108_sysreset", "reset", &dev); - if (ret) - pr_err("No Rv1108 reset driver: ret=%d\n", ret); + ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", + &sys_child); + if (ret) { + debug("Warning: No sysreset driver: ret=%d\n", ret); + } else { + priv = malloc(sizeof(struct sysreset_reg)); + priv->glb_srst_fst_value = offsetof(struct rv1108_cru, + glb_srst_fst_val); + priv->glb_srst_snd_value = offsetof(struct rv1108_cru, + glb_srst_snd_val); + sys_child->priv = priv; + } return 0; } diff --git a/drivers/core/read.c b/drivers/core/read.c index eacf1716fd..5d440cee72 100644 --- a/drivers/core/read.c +++ b/drivers/core/read.c @@ -7,6 +7,7 @@ #include <common.h> #include <dm.h> +#include <mapmem.h> #include <dm/of_access.h> int dev_read_u32_default(struct udevice *dev, const char *propname, int def) @@ -61,7 +62,7 @@ void *dev_read_addr_ptr(struct udevice *dev) { fdt_addr_t addr = dev_read_addr(dev); - return (addr == FDT_ADDR_T_NONE) ? NULL : (void *)addr; + return (addr == FDT_ADDR_T_NONE) ? NULL : map_sysmem(addr, 0); } fdt_addr_t dev_read_addr_size(struct udevice *dev, const char *property, diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 6240c39539..2acb33bb51 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -80,6 +80,13 @@ config IMX_RGPIO2P help This driver supports i.MX7ULP Rapid GPIO2P controller. +config HSDK_CREG_GPIO + bool "HSDK CREG GPIO griver" + depends on DM + default n + help + This driver supports CREG GPIOs on Synopsys HSDK SOC. + config LPC32XX_GPIO bool "LPC32XX GPIO driver" depends on DM diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 81f55a576b..201d7bfff9 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -54,6 +54,7 @@ obj-$(CONFIG_GPIO_UNIPHIER) += gpio-uniphier.o obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o +obj-$(CONFIG_HSDK_CREG_GPIO) += hsdk-creg-gpio.o obj-$(CONFIG_IMX_RGPIO2P) += imx_rgpio2p.o obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o diff --git a/drivers/gpio/hsdk-creg-gpio.c b/drivers/gpio/hsdk-creg-gpio.c new file mode 100644 index 0000000000..8ca807a18f --- /dev/null +++ b/drivers/gpio/hsdk-creg-gpio.c @@ -0,0 +1,110 @@ +/* + * Synopsys HSDK SDP Generic PLL clock driver + * + * Copyright (C) 2017 Synopsys + * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <asm-generic/gpio.h> +#include <asm/io.h> +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <linux/printk.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define HSDK_CREG_MAX_GPIO 8 + +#define GPIO_ACTIVATE 0x2 +#define GPIO_DEACTIVATE 0x3 +#define GPIO_PIN_MASK 0x3 +#define BIT_PER_GPIO 2 + +struct hsdk_creg_gpio { + uint32_t *regs; +}; + +static int hsdk_creg_gpio_set_value(struct udevice *dev, unsigned oft, int val) +{ + struct hsdk_creg_gpio *hcg = dev_get_priv(dev); + uint32_t reg = readl(hcg->regs); + uint32_t cmd = val ? GPIO_DEACTIVATE : GPIO_ACTIVATE; + + reg &= ~(GPIO_PIN_MASK << (oft * BIT_PER_GPIO)); + reg |= (cmd << (oft * BIT_PER_GPIO)); + + writel(reg, hcg->regs); + + return 0; +} + +static int hsdk_creg_gpio_direction_output(struct udevice *dev, unsigned oft, + int val) +{ + hsdk_creg_gpio_set_value(dev, oft, val); + + return 0; +} + +static int hsdk_creg_gpio_direction_input(struct udevice *dev, unsigned oft) +{ + pr_err("hsdk-creg-gpio can't be used as input!\n"); + + return -ENOTSUPP; +} + +static int hsdk_creg_gpio_get_value(struct udevice *dev, unsigned int oft) +{ + struct hsdk_creg_gpio *hcg = dev_get_priv(dev); + uint32_t val = readl(hcg->regs); + + val = (val >> (oft * BIT_PER_GPIO)) & GPIO_PIN_MASK; + return (val == GPIO_DEACTIVATE) ? 1 : 0; +} + +static const struct dm_gpio_ops hsdk_creg_gpio_ops = { + .direction_output = hsdk_creg_gpio_direction_output, + .direction_input = hsdk_creg_gpio_direction_input, + .set_value = hsdk_creg_gpio_set_value, + .get_value = hsdk_creg_gpio_get_value, +}; + +static int hsdk_creg_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct hsdk_creg_gpio *hcg = dev_get_priv(dev); + + hcg->regs = (uint32_t *)devfdt_get_addr_ptr(dev); + + uc_priv->gpio_count = dev_read_u32_default(dev, "gpio-count", 1); + if (uc_priv->gpio_count > HSDK_CREG_MAX_GPIO) + uc_priv->gpio_count = HSDK_CREG_MAX_GPIO; + + uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name"); + if (!uc_priv->bank_name) + uc_priv->bank_name = dev_read_name(dev); + + pr_debug("%s GPIO [0x%p] controller with %d gpios probed\n", + uc_priv->bank_name, hcg->regs, uc_priv->gpio_count); + + return 0; +} + +static const struct udevice_id hsdk_creg_gpio_ids[] = { + { .compatible = "snps,hsdk-creg-gpio" }, + { } +}; + +U_BOOT_DRIVER(gpio_hsdk_creg) = { + .name = "gpio_hsdk_creg", + .id = UCLASS_GPIO, + .ops = &hsdk_creg_gpio_ops, + .probe = hsdk_creg_gpio_probe, + .of_match = hsdk_creg_gpio_ids, + .platdata_auto_alloc_size = sizeof(struct hsdk_creg_gpio), +}; diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index c296985d9b..1989f8eb57 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -137,6 +137,12 @@ config SYS_I2C_IMX_LPI2C help Add support for the NXP i.MX LPI2C driver. +config SYS_I2C_MESON + bool "Amlogic Meson I2C driver" + depends on DM_I2C && ARCH_MESON + help + Add support for the Amlogic Meson I2C driver. + config SYS_I2C_MXC bool "NXP i.MX I2C driver" depends on MX6 diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 3a8c61b485..733cd3e92f 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o obj-$(CONFIG_SYS_I2C_IMX_LPI2C) += imx_lpi2c.o obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o +obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o obj-$(CONFIG_SYS_I2C_MXS) += mxs_i2c.o diff --git a/drivers/i2c/meson_i2c.c b/drivers/i2c/meson_i2c.c new file mode 100644 index 0000000000..2434d9ed53 --- /dev/null +++ b/drivers/i2c/meson_i2c.c @@ -0,0 +1,263 @@ +/* + * (C) Copyright 2017 - Beniamino Galvani <b.galvani@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <asm/arch/i2c.h> +#include <asm/io.h> +#include <dm.h> +#include <i2c.h> + +#define I2C_TIMEOUT_MS 500 + +/* Control register fields */ +#define REG_CTRL_START BIT(0) +#define REG_CTRL_ACK_IGNORE BIT(1) +#define REG_CTRL_STATUS BIT(2) +#define REG_CTRL_ERROR BIT(3) +#define REG_CTRL_CLKDIV_SHIFT 12 +#define REG_CTRL_CLKDIV_MASK GENMASK(21, 12) +#define REG_CTRL_CLKDIVEXT_SHIFT 28 +#define REG_CTRL_CLKDIVEXT_MASK GENMASK(29, 28) + +enum { + TOKEN_END = 0, + TOKEN_START, + TOKEN_SLAVE_ADDR_WRITE, + TOKEN_SLAVE_ADDR_READ, + TOKEN_DATA, + TOKEN_DATA_LAST, + TOKEN_STOP, +}; + +struct i2c_regs { + u32 ctrl; + u32 slave_addr; + u32 tok_list0; + u32 tok_list1; + u32 tok_wdata0; + u32 tok_wdata1; + u32 tok_rdata0; + u32 tok_rdata1; +}; + +struct meson_i2c { + struct i2c_regs *regs; + struct i2c_msg *msg; + bool last; + uint count; + uint pos; + u32 tokens[2]; + uint num_tokens; +}; + +static void meson_i2c_reset_tokens(struct meson_i2c *i2c) +{ + i2c->tokens[0] = 0; + i2c->tokens[1] = 0; + i2c->num_tokens = 0; +} + +static void meson_i2c_add_token(struct meson_i2c *i2c, int token) +{ + if (i2c->num_tokens < 8) + i2c->tokens[0] |= (token & 0xf) << (i2c->num_tokens * 4); + else + i2c->tokens[1] |= (token & 0xf) << ((i2c->num_tokens % 8) * 4); + + i2c->num_tokens++; +} + +static void meson_i2c_get_data(struct meson_i2c *i2c, u8 *buf, int len) +{ + u32 rdata0, rdata1; + int i; + + rdata0 = readl(&i2c->regs->tok_rdata0); + rdata1 = readl(&i2c->regs->tok_rdata1); + + debug("meson i2c: read data %08x %08x len %d\n", rdata0, rdata1, len); + + for (i = 0; i < min(4, len); i++) + *buf++ = (rdata0 >> i * 8) & 0xff; + + for (i = 4; i < min(8, len); i++) + *buf++ = (rdata1 >> (i - 4) * 8) & 0xff; +} + +static void meson_i2c_put_data(struct meson_i2c *i2c, u8 *buf, int len) +{ + u32 wdata0 = 0, wdata1 = 0; + int i; + + for (i = 0; i < min(4, len); i++) + wdata0 |= *buf++ << (i * 8); + + for (i = 4; i < min(8, len); i++) + wdata1 |= *buf++ << ((i - 4) * 8); + + writel(wdata0, &i2c->regs->tok_wdata0); + writel(wdata1, &i2c->regs->tok_wdata1); + + debug("meson i2c: write data %08x %08x len %d\n", wdata0, wdata1, len); +} + +static void meson_i2c_prepare_xfer(struct meson_i2c *i2c) +{ + bool write = !(i2c->msg->flags & I2C_M_RD); + int i; + + i2c->count = min(i2c->msg->len - i2c->pos, 8u); + + for (i = 0; i + 1 < i2c->count; i++) + meson_i2c_add_token(i2c, TOKEN_DATA); + + if (i2c->count) { + if (write || i2c->pos + i2c->count < i2c->msg->len) + meson_i2c_add_token(i2c, TOKEN_DATA); + else + meson_i2c_add_token(i2c, TOKEN_DATA_LAST); + } + + if (write) + meson_i2c_put_data(i2c, i2c->msg->buf + i2c->pos, i2c->count); + + if (i2c->last && i2c->pos + i2c->count >= i2c->msg->len) + meson_i2c_add_token(i2c, TOKEN_STOP); + + writel(i2c->tokens[0], &i2c->regs->tok_list0); + writel(i2c->tokens[1], &i2c->regs->tok_list1); +} + +static void meson_i2c_do_start(struct meson_i2c *i2c, struct i2c_msg *msg) +{ + int token; + + token = (msg->flags & I2C_M_RD) ? TOKEN_SLAVE_ADDR_READ : + TOKEN_SLAVE_ADDR_WRITE; + + writel(msg->addr << 1, &i2c->regs->slave_addr); + meson_i2c_add_token(i2c, TOKEN_START); + meson_i2c_add_token(i2c, token); +} + +static int meson_i2c_xfer_msg(struct meson_i2c *i2c, struct i2c_msg *msg, + int last) +{ + ulong start; + + debug("meson i2c: %s addr %u len %u\n", + (msg->flags & I2C_M_RD) ? "read" : "write", + msg->addr, msg->len); + + i2c->msg = msg; + i2c->last = last; + i2c->pos = 0; + i2c->count = 0; + + meson_i2c_reset_tokens(i2c); + meson_i2c_do_start(i2c, msg); + + do { + meson_i2c_prepare_xfer(i2c); + + /* start the transfer */ + setbits_le32(&i2c->regs->ctrl, REG_CTRL_START); + start = get_timer(0); + while (readl(&i2c->regs->ctrl) & REG_CTRL_STATUS) { + if (get_timer(start) > I2C_TIMEOUT_MS) { + clrbits_le32(&i2c->regs->ctrl, REG_CTRL_START); + debug("meson i2c: timeout\n"); + return -ETIMEDOUT; + } + udelay(1); + } + meson_i2c_reset_tokens(i2c); + clrbits_le32(&i2c->regs->ctrl, REG_CTRL_START); + + if (readl(&i2c->regs->ctrl) & REG_CTRL_ERROR) { + debug("meson i2c: error\n"); + return -ENXIO; + } + + if ((msg->flags & I2C_M_RD) && i2c->count) { + meson_i2c_get_data(i2c, i2c->msg->buf + i2c->pos, + i2c->count); + } + i2c->pos += i2c->count; + } while (i2c->pos < msg->len); + + return 0; +} + +static int meson_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, + int nmsgs) +{ + struct meson_i2c *i2c = dev_get_priv(bus); + int i, ret = 0; + + for (i = 0; i < nmsgs; i++) { + ret = meson_i2c_xfer_msg(i2c, msg + i, i == nmsgs - 1); + if (ret) + return -EREMOTEIO; + } + + return 0; +} + +static int meson_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +{ + struct meson_i2c *i2c = dev_get_priv(bus); + unsigned int clk_rate = MESON_I2C_CLK_RATE; + unsigned int div; + + div = DIV_ROUND_UP(clk_rate, speed * 4); + + /* clock divider has 12 bits */ + if (div >= (1 << 12)) { + debug("meson i2c: requested bus frequency too low\n"); + div = (1 << 12) - 1; + } + + clrsetbits_le32(&i2c->regs->ctrl, REG_CTRL_CLKDIV_MASK, + (div & GENMASK(9, 0)) << REG_CTRL_CLKDIV_SHIFT); + + clrsetbits_le32(&i2c->regs->ctrl, REG_CTRL_CLKDIVEXT_MASK, + (div >> 10) << REG_CTRL_CLKDIVEXT_SHIFT); + + debug("meson i2c: set clk %u, src %u, div %u\n", speed, clk_rate, div); + + return 0; +} + +static int meson_i2c_probe(struct udevice *bus) +{ + struct meson_i2c *i2c = dev_get_priv(bus); + + i2c->regs = dev_read_addr_ptr(bus); + clrbits_le32(&i2c->regs->ctrl, REG_CTRL_START); + + return 0; +} + +static const struct dm_i2c_ops meson_i2c_ops = { + .xfer = meson_i2c_xfer, + .set_bus_speed = meson_i2c_set_bus_speed, +}; + +static const struct udevice_id meson_i2c_ids[] = { + { .compatible = "amlogic,meson6-i2c" }, + { .compatible = "amlogic,meson-gx-i2c" }, + { .compatible = "amlogic,meson-gxbb-i2c" }, + { } +}; + +U_BOOT_DRIVER(i2c_meson) = { + .name = "i2c_meson", + .id = UCLASS_I2C, + .of_match = meson_i2c_ids, + .probe = meson_i2c_probe, + .priv_auto_alloc_size = sizeof(struct meson_i2c), + .ops = &meson_i2c_ops, +}; diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 940508364a..62ce0af7d3 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -33,6 +33,15 @@ config SPL_DM_MMC if MMC +config ARM_PL180_MMCI + bool "ARM AMBA Multimedia Card Interface and compatible support" + depends on DM_MMC && OF_CONTROL + help + This selects the ARM(R) AMBA(R) PrimeCell Multimedia Card + Interface (PL180, PL181 and compatible) support. + If you have an ARM(R) platform with a Multimedia Card slot, + say Y or M here. + config SPL_MMC_TINY bool "Tiny MMC framework in SPL" help diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c index ddf8383f1c..89a7c19242 100644 --- a/drivers/mmc/arm_pl180_mmci.c +++ b/drivers/mmc/arm_pl180_mmci.c @@ -12,12 +12,29 @@ /* #define DEBUG */ -#include <asm/io.h> #include "common.h" +#include <clk.h> #include <errno.h> +#include <malloc.h> #include <mmc.h> + +#include <asm/io.h> +#include <asm-generic/gpio.h> + #include "arm_pl180_mmci.h" -#include <malloc.h> + +#ifdef CONFIG_DM_MMC +#include <dm.h> +DECLARE_GLOBAL_DATA_PTR; + +#define MMC_CLOCK_MAX 48000000 +#define MMC_CLOCK_MIN 400000 + +struct arm_pl180_mmc_plat { + struct mmc_config cfg; + struct mmc mmc; +}; +#endif static int wait_for_command_end(struct mmc *dev, struct mmc_cmd *cmd) { @@ -265,16 +282,6 @@ static int host_request(struct mmc *dev, return result; } -/* MMC uses open drain drivers in the enumeration phase */ -static int mmc_host_reset(struct mmc *dev) -{ - struct pl180_mmc_host *host = dev->priv; - - writel(host->pwr_init, &host->base->power); - - return 0; -} - static int host_set_ios(struct mmc *dev) { struct pl180_mmc_host *host = dev->priv; @@ -337,20 +344,31 @@ static int host_set_ios(struct mmc *dev) return 0; } +#ifndef CONFIG_DM_MMC +/* MMC uses open drain drivers in the enumeration phase */ +static int mmc_host_reset(struct mmc *dev) +{ + struct pl180_mmc_host *host = dev->priv; + + writel(host->pwr_init, &host->base->power); + + return 0; +} + static const struct mmc_ops arm_pl180_mmci_ops = { .send_cmd = host_request, .set_ios = host_set_ios, .init = mmc_host_reset, }; +#endif /* * mmc_host_init - initialize the mmc controller. * Set initial clock and power for mmc slot. * Initialize mmc struct and register with mmc framework. */ -int arm_pl180_mmci_init(struct pl180_mmc_host *host) +int arm_pl180_mmci_init(struct pl180_mmc_host *host, struct mmc **mmc) { - struct mmc *mmc; u32 sdi_u32; writel(host->pwr_init, &host->base->power); @@ -362,7 +380,9 @@ int arm_pl180_mmci_init(struct pl180_mmc_host *host) writel(sdi_u32, &host->base->mask0); host->cfg.name = host->name; +#ifndef CONFIG_DM_MMC host->cfg.ops = &arm_pl180_mmci_ops; +#endif /* TODO remove the duplicates */ host->cfg.host_caps = host->caps; host->cfg.voltages = host->voltages; @@ -373,11 +393,144 @@ int arm_pl180_mmci_init(struct pl180_mmc_host *host) else host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; - mmc = mmc_create(&host->cfg, host); - if (mmc == NULL) + *mmc = mmc_create(&host->cfg, host); + if (!*mmc) return -1; - debug("registered mmc interface number is:%d\n", mmc->block_dev.devnum); + debug("registered mmc interface number is:%d\n", + (*mmc)->block_dev.devnum); return 0; } + +#ifdef CONFIG_DM_MMC +static int arm_pl180_mmc_probe(struct udevice *dev) +{ + struct arm_pl180_mmc_plat *pdata = dev_get_platdata(dev); + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct mmc *mmc = &pdata->mmc; + struct pl180_mmc_host *host = mmc->priv; + struct clk clk; + u32 bus_width; + int ret; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) + return ret; + + ret = clk_enable(&clk); + if (ret) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } + + strcpy(host->name, "MMC"); + host->pwr_init = INIT_PWR; + host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN | + SDI_CLKCR_HWFC_EN; + host->voltages = VOLTAGE_WINDOW_SD; + host->caps = 0; + host->clock_in = clk_get_rate(&clk); + host->clock_min = host->clock_in / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1)); + host->clock_max = dev_read_u32_default(dev, "max-frequency", + MMC_CLOCK_MAX); + host->version2 = dev_get_driver_data(dev); + + gpio_request_by_name(dev, "cd-gpios", 0, &host->cd_gpio, GPIOD_IS_IN); + + bus_width = dev_read_u32_default(dev, "bus-width", 1); + switch (bus_width) { + case 8: + host->caps |= MMC_MODE_8BIT; + /* Hosts capable of 8-bit transfers can also do 4 bits */ + case 4: + host->caps |= MMC_MODE_4BIT; + break; + case 1: + break; + default: + dev_err(dev, "Invalid bus-width value %u\n", bus_width); + } + + ret = arm_pl180_mmci_init(host, &mmc); + if (ret) { + dev_err(dev, "arm_pl180_mmci init failed\n"); + return ret; + } + + mmc->dev = dev; + dev->priv = host; + upriv->mmc = mmc; + + return 0; +} + +static int dm_host_request(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct mmc *mmc = mmc_get_mmc_dev(dev); + + return host_request(mmc, cmd, data); +} + +static int dm_host_set_ios(struct udevice *dev) +{ + struct mmc *mmc = mmc_get_mmc_dev(dev); + + return host_set_ios(mmc); +} + +static int dm_mmc_getcd(struct udevice *dev) +{ + struct arm_pl180_mmc_plat *pdata = dev_get_platdata(dev); + struct mmc *mmc = &pdata->mmc; + struct pl180_mmc_host *host = mmc->priv; + int value = 1; + + if (dm_gpio_is_valid(&host->cd_gpio)) { + value = dm_gpio_get_value(&host->cd_gpio); + if (host->cd_inverted) + return !value; + } + + return value; +} + +static const struct dm_mmc_ops arm_pl180_dm_mmc_ops = { + .send_cmd = dm_host_request, + .set_ios = dm_host_set_ios, + .get_cd = dm_mmc_getcd, +}; + +static int arm_pl180_mmc_ofdata_to_platdata(struct udevice *dev) +{ + struct arm_pl180_mmc_plat *pdata = dev_get_platdata(dev); + struct mmc *mmc = &pdata->mmc; + struct pl180_mmc_host *host = mmc->priv; + fdt_addr_t addr; + + addr = devfdt_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + host->base = (void *)addr; + + return 0; +} + +static const struct udevice_id arm_pl180_mmc_match[] = { + { .compatible = "st,stm32f4xx-sdio", .data = VERSION1 }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(arm_pl180_mmc) = { + .name = "arm_pl180_mmc", + .id = UCLASS_MMC, + .of_match = arm_pl180_mmc_match, + .ops = &arm_pl180_dm_mmc_ops, + .probe = arm_pl180_mmc_probe, + .ofdata_to_platdata = arm_pl180_mmc_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct pl180_mmc_host), + .platdata_auto_alloc_size = sizeof(struct arm_pl180_mmc_plat), +}; +#endif diff --git a/drivers/mmc/arm_pl180_mmci.h b/drivers/mmc/arm_pl180_mmci.h index f23bd391ee..9df4b75470 100644 --- a/drivers/mmc/arm_pl180_mmci.h +++ b/drivers/mmc/arm_pl180_mmci.h @@ -142,6 +142,9 @@ #define SDI_FIFO_BURST_SIZE 8 +#define VERSION1 false +#define VERSION2 true + struct sdi_registers { u32 power; /* 0x00*/ u32 clock; /* 0x04*/ @@ -188,8 +191,12 @@ struct pl180_mmc_host { unsigned int pwr_init; int version2; struct mmc_config cfg; +#ifdef CONFIG_DM_MMC + struct gpio_desc cd_gpio; + bool cd_inverted; +#endif }; -int arm_pl180_mmci_init(struct pl180_mmc_host *); +int arm_pl180_mmci_init(struct pl180_mmc_host *host, struct mmc **mmc); #endif diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 794410a152..ca9819344e 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -55,6 +55,7 @@ config NAND_OMAP_GPMC config NAND_OMAP_GPMC_PREFETCH bool "Enable GPMC Prefetch" depends on NAND_OMAP_GPMC + default y help On OMAP platforms that use the GPMC controller (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index bc6bdc9b2c..a757a3be44 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -48,7 +48,6 @@ struct fsl_ifc_ctrl { /* device info */ struct fsl_ifc regs; void __iomem *addr; /* Address of assigned IFC buffer */ - unsigned int cs_nand; /* On which chipsel NAND is connected */ unsigned int page; /* Last page written to / read from */ unsigned int read_bytes; /* Number of bytes read during command */ unsigned int column; /* Saved column from SEQIN */ @@ -296,7 +295,7 @@ static int fsl_ifc_run_command(struct mtd_info *mtd) int i; /* set the chip select for NAND Transaction */ - ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); + ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT); /* start read/write seq */ ifc_out32(&ifc->ifc_nand.nandseq_strt, @@ -798,7 +797,7 @@ static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip) { } -static int fsl_ifc_sram_init(uint32_t ver) +static int fsl_ifc_sram_init(struct fsl_ifc_mtd *priv, uint32_t ver) { struct fsl_ifc_runtime *ifc = ifc_ctrl->regs.rregs; uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0; @@ -823,7 +822,7 @@ static int fsl_ifc_sram_init(uint32_t ver) return 1; } - cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT; + cs = priv->bank; /* Save CSOR and CSOR_ext */ csor = ifc_in32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor); @@ -850,7 +849,7 @@ static int fsl_ifc_sram_init(uint32_t ver) ifc_out32(&ifc->ifc_nand.col0, 0x0); /* set the chip select for NAND Transaction */ - ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); + ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT); /* start read seq */ ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT); @@ -911,10 +910,8 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) csor = ifc_in32(&gregs->csor_cs[priv->bank].csor); if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND && - (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) { - ifc_ctrl->cs_nand = priv->bank << IFC_NAND_CSEL_SHIFT; + (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) break; - } } if (priv->bank >= MAX_BANKS) { @@ -1029,7 +1026,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) ver = ifc_in32(&gregs->ifc_rev); if (ver >= FSL_IFC_V1_1_0) - ret = fsl_ifc_sram_init(ver); + ret = fsl_ifc_sram_init(priv, ver); if (ret) return ret; diff --git a/drivers/mtd/ubi/attach.c b/drivers/mtd/ubi/attach.c index 90fb74a5c9..33c176a77b 100644 --- a/drivers/mtd/ubi/attach.c +++ b/drivers/mtd/ubi/attach.c @@ -1205,8 +1205,7 @@ static void destroy_ai(struct ubi_attach_info *ai) } } - if (ai->aeb_slab_cache) - kmem_cache_destroy(ai->aeb_slab_cache); + kmem_cache_destroy(ai->aeb_slab_cache); kfree(ai); } diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index be2b6117d7..c76f58253d 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -826,7 +826,7 @@ unsigned long mc_get_dram_block_size(void) if (dram_block_size_env_var) { dram_block_size = simple_strtoul(dram_block_size_env_var, NULL, - 10); + 16); if (dram_block_size < CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE) { printf("fsl-mc: WARNING: Invalid value for \'" diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index f235b622b6..21be79a58a 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -334,7 +334,7 @@ static int ldpaa_eth_tx(struct eth_device *net_dev, void *buf, int len) &buffer_start, 1); } while (err == -EBUSY); - if (err < 0) { + if (err <= 0) { printf("qbman_swp_acquire() failed\n"); return -ENOMEM; } diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 4d02d8bb19..e32f1eb1c0 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -55,6 +55,9 @@ config PHY_LXT config PHY_MARVELL bool "Marvell Ethernet PHYs support" +config PHY_MESON_GXL + bool "Amlogic Meson GXL Internal PHY support" + config PHY_MICREL bool "Micrel Ethernet PHYs support" help diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 54f32f606b..1e264b2f2b 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_PHY_LXT) += lxt.o obj-$(CONFIG_PHY_MARVELL) += marvell.o obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o +obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o obj-$(CONFIG_PHY_NATSEMI) += natsemi.o obj-$(CONFIG_PHY_REALTEK) += realtek.o obj-$(CONFIG_PHY_SMSC) += smsc.o diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c new file mode 100644 index 0000000000..ccf70c94be --- /dev/null +++ b/drivers/net/phy/meson-gxl.c @@ -0,0 +1,57 @@ +/* + * Meson GXL Internal PHY Driver + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * Copyright (C) 2016 BayLibre, SAS. All rights reserved. + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <config.h> +#include <common.h> +#include <linux/bitops.h> +#include <phy.h> + +static int meson_gxl_phy_config(struct phy_device *phydev) +{ + /* Enable Analog and DSP register Bank access by */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); + + /* Write Analog register 23 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417); + + /* Enable fractional PLL */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B); + + /* Program fraction FR_PLL_DIV1 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D); + + /* Program fraction FR_PLL_DIV1 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA); + phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C); + + return genphy_config(phydev); +} + +static struct phy_driver meson_gxl_phy_driver = { + .name = "Meson GXL Internal PHY", + .uid = 0x01814400, + .mask = 0xfffffff0, + .features = PHY_BASIC_FEATURES, + .config = &meson_gxl_phy_config, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + +int phy_meson_gxl_init(void) +{ + phy_register(&meson_gxl_phy_driver); + + return 0; +} diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 5be51d73ce..fd3dd556c8 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -494,6 +494,9 @@ int phy_init(void) #ifdef CONFIG_PHY_MICREL_KSZ90X1 phy_micrel_ksz90x1_init(); #endif +#ifdef CONFIG_PHY_MESON_GXL + phy_meson_gxl_init(); +#endif #ifdef CONFIG_PHY_NATSEMI phy_natsemi_init(); #endif diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index ee9a854bda..c2bc32678a 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -181,8 +181,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) /* Configure bus number registers */ dm_pci_write_config8(dev, PCI_PRIMARY_BUS, - PCI_BUS(dm_pci_get_bdf(dev))); - dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus); + PCI_BUS(dm_pci_get_bdf(dev)) - ctlr->seq); + dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus - ctlr->seq); dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff); if (pci_mem) { @@ -257,7 +257,7 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus) pci_io = ctlr_hose->pci_io; /* Configure bus number registers */ - dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus); + dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - ctlr->seq); if (pci_mem) { /* Round memory allocator to 1MB boundary */ diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index da0aa29865..076a63f210 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -82,11 +82,11 @@ struct mvebu_pcie { /* * MVEBU PCIe controller needs MEMORY and I/O BARs to be mapped - * into SoCs address space. Each controller will map 32M of MEM + * into SoCs address space. Each controller will map 128M of MEM * and 64K of I/O space when registered. */ static void __iomem *mvebu_pcie_membase = (void __iomem *)MBUS_PCI_MEM_BASE; -#define PCIE_MEM_SIZE (32 << 20) +#define PCIE_MEM_SIZE (128 << 20) #if defined(CONFIG_ARMADA_38X) #define PCIE_BASE(if) \ diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c index 202cfe9d03..a19885501c 100644 --- a/drivers/pci/pcie_dw_mvebu.c +++ b/drivers/pci/pcie_dw_mvebu.c @@ -162,6 +162,7 @@ static uintptr_t set_cfg_address(struct pcie_dw_mvebu *pcie, /* Accessing root port configuration space. */ va_address = (uintptr_t)pcie->ctrl_base; } else { + d = PCI_MASK_BUS(d) | (PCI_BUS(d) - pcie->first_busno); writel(d << 8, pcie->ctrl_base + PCIE_ATU_LOWER_TARGET); va_address = (uintptr_t)pcie->cfg_base; } diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 0cb7f6d564..503fd5e507 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -255,7 +255,7 @@ int ls_pcie_conf_address(struct udevice *bus, pci_dev_t bdf, return 0; } - busdev = PCIE_ATU_BUS(PCI_BUS(bdf)) | + busdev = PCIE_ATU_BUS(PCI_BUS(bdf) - bus->seq) | PCIE_ATU_DEV(PCI_DEV(bdf)) | PCIE_ATU_FUNC(PCI_FUNC(bdf)); diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig index c3e6901b9a..27ba8909d7 100644 --- a/drivers/pinctrl/meson/Kconfig +++ b/drivers/pinctrl/meson/Kconfig @@ -8,4 +8,8 @@ config PINCTRL_MESON_GXBB bool "Amlogic Meson GXBB SoC pinctrl driver" select PINCTRL_MESON +config PINCTRL_MESON_GXL + bool "Amlogic Meson GXL SoC pinctrl driver" + select PINCTRL_MESON + endif diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile index 6dde4bcb68..18921e35aa 100644 --- a/drivers/pinctrl/meson/Makefile +++ b/drivers/pinctrl/meson/Makefile @@ -4,3 +4,4 @@ obj-y += pinctrl-meson.o obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o +obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c new file mode 100644 index 0000000000..eebfaa9de6 --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c @@ -0,0 +1,736 @@ +/* + * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com> + * + * Based on code from Linux kernel: + * Copyright (C) 2016 Endless Mobile, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <dt-bindings/gpio/meson-gxl-gpio.h> + +#include "pinctrl-meson.h" + +#define EE_OFF 10 + +static const unsigned int emmc_nand_d07_pins[] = { + PIN(BOOT_0, EE_OFF), PIN(BOOT_1, EE_OFF), PIN(BOOT_2, EE_OFF), + PIN(BOOT_3, EE_OFF), PIN(BOOT_4, EE_OFF), PIN(BOOT_5, EE_OFF), + PIN(BOOT_6, EE_OFF), PIN(BOOT_7, EE_OFF), +}; +static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) }; +static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) }; +static const unsigned int emmc_ds_pins[] = { PIN(BOOT_15, EE_OFF) }; + +static const unsigned int nor_d_pins[] = { PIN(BOOT_11, EE_OFF) }; +static const unsigned int nor_q_pins[] = { PIN(BOOT_12, EE_OFF) }; +static const unsigned int nor_c_pins[] = { PIN(BOOT_13, EE_OFF) }; +static const unsigned int nor_cs_pins[] = { PIN(BOOT_15, EE_OFF) }; + +static const unsigned int spi_mosi_pins[] = { PIN(GPIOX_8, EE_OFF) }; +static const unsigned int spi_miso_pins[] = { PIN(GPIOX_9, EE_OFF) }; +static const unsigned int spi_ss0_pins[] = { PIN(GPIOX_10, EE_OFF) }; +static const unsigned int spi_sclk_pins[] = { PIN(GPIOX_11, EE_OFF) }; + +static const unsigned int sdcard_d0_pins[] = { PIN(CARD_1, EE_OFF) }; +static const unsigned int sdcard_d1_pins[] = { PIN(CARD_0, EE_OFF) }; +static const unsigned int sdcard_d2_pins[] = { PIN(CARD_5, EE_OFF) }; +static const unsigned int sdcard_d3_pins[] = { PIN(CARD_4, EE_OFF) }; +static const unsigned int sdcard_cmd_pins[] = { PIN(CARD_3, EE_OFF) }; +static const unsigned int sdcard_clk_pins[] = { PIN(CARD_2, EE_OFF) }; + +static const unsigned int sdio_d0_pins[] = { PIN(GPIOX_0, EE_OFF) }; +static const unsigned int sdio_d1_pins[] = { PIN(GPIOX_1, EE_OFF) }; +static const unsigned int sdio_d2_pins[] = { PIN(GPIOX_2, EE_OFF) }; +static const unsigned int sdio_d3_pins[] = { PIN(GPIOX_3, EE_OFF) }; +static const unsigned int sdio_cmd_pins[] = { PIN(GPIOX_4, EE_OFF) }; +static const unsigned int sdio_clk_pins[] = { PIN(GPIOX_5, EE_OFF) }; +static const unsigned int sdio_irq_pins[] = { PIN(GPIOX_7, EE_OFF) }; + +static const unsigned int nand_ce0_pins[] = { PIN(BOOT_8, EE_OFF) }; +static const unsigned int nand_ce1_pins[] = { PIN(BOOT_9, EE_OFF) }; +static const unsigned int nand_rb0_pins[] = { PIN(BOOT_10, EE_OFF) }; +static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, EE_OFF) }; +static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, EE_OFF) }; +static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, EE_OFF) }; +static const unsigned int nand_ren_wr_pins[] = { PIN(BOOT_14, EE_OFF) }; +static const unsigned int nand_dqs_pins[] = { PIN(BOOT_15, EE_OFF) }; + +static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_12, EE_OFF) }; +static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_13, EE_OFF) }; +static const unsigned int uart_cts_a_pins[] = { PIN(GPIOX_14, EE_OFF) }; +static const unsigned int uart_rts_a_pins[] = { PIN(GPIOX_15, EE_OFF) }; + +static const unsigned int uart_tx_b_pins[] = { PIN(GPIODV_24, EE_OFF) }; +static const unsigned int uart_rx_b_pins[] = { PIN(GPIODV_25, EE_OFF) }; +static const unsigned int uart_cts_b_pins[] = { PIN(GPIODV_26, EE_OFF) }; +static const unsigned int uart_rts_b_pins[] = { PIN(GPIODV_27, EE_OFF) }; + +static const unsigned int uart_tx_c_pins[] = { PIN(GPIOX_8, EE_OFF) }; +static const unsigned int uart_rx_c_pins[] = { PIN(GPIOX_9, EE_OFF) }; +static const unsigned int uart_cts_c_pins[] = { PIN(GPIOX_10, EE_OFF) }; +static const unsigned int uart_rts_c_pins[] = { PIN(GPIOX_11, EE_OFF) }; + +static const unsigned int i2c_sck_a_pins[] = { PIN(GPIODV_25, EE_OFF) }; +static const unsigned int i2c_sda_a_pins[] = { PIN(GPIODV_24, EE_OFF) }; + +static const unsigned int i2c_sck_b_pins[] = { PIN(GPIODV_27, EE_OFF) }; +static const unsigned int i2c_sda_b_pins[] = { PIN(GPIODV_26, EE_OFF) }; + +static const unsigned int i2c_sck_c_pins[] = { PIN(GPIODV_29, EE_OFF) }; +static const unsigned int i2c_sda_c_pins[] = { PIN(GPIODV_28, EE_OFF) }; + +static const unsigned int i2c_sck_c_dv19_pins[] = { PIN(GPIODV_19, EE_OFF) }; +static const unsigned int i2c_sda_c_dv18_pins[] = { PIN(GPIODV_18, EE_OFF) }; + +static const unsigned int eth_mdio_pins[] = { PIN(GPIOZ_0, EE_OFF) }; +static const unsigned int eth_mdc_pins[] = { PIN(GPIOZ_1, EE_OFF) }; +static const unsigned int eth_clk_rx_clk_pins[] = { PIN(GPIOZ_2, EE_OFF) }; +static const unsigned int eth_rx_dv_pins[] = { PIN(GPIOZ_3, EE_OFF) }; +static const unsigned int eth_rxd0_pins[] = { PIN(GPIOZ_4, EE_OFF) }; +static const unsigned int eth_rxd1_pins[] = { PIN(GPIOZ_5, EE_OFF) }; +static const unsigned int eth_rxd2_pins[] = { PIN(GPIOZ_6, EE_OFF) }; +static const unsigned int eth_rxd3_pins[] = { PIN(GPIOZ_7, EE_OFF) }; +static const unsigned int eth_rgmii_tx_clk_pins[] = { PIN(GPIOZ_8, EE_OFF) }; +static const unsigned int eth_tx_en_pins[] = { PIN(GPIOZ_9, EE_OFF) }; +static const unsigned int eth_txd0_pins[] = { PIN(GPIOZ_10, EE_OFF) }; +static const unsigned int eth_txd1_pins[] = { PIN(GPIOZ_11, EE_OFF) }; +static const unsigned int eth_txd2_pins[] = { PIN(GPIOZ_12, EE_OFF) }; +static const unsigned int eth_txd3_pins[] = { PIN(GPIOZ_13, EE_OFF) }; + +static const unsigned int pwm_a_pins[] = { PIN(GPIOX_6, EE_OFF) }; + +static const unsigned int pwm_b_pins[] = { PIN(GPIODV_29, EE_OFF) }; + +static const unsigned int pwm_c_pins[] = { PIN(GPIOZ_15, EE_OFF) }; + +static const unsigned int pwm_d_pins[] = { PIN(GPIODV_28, EE_OFF) }; + +static const unsigned int pwm_e_pins[] = { PIN(GPIOX_16, EE_OFF) }; + +static const unsigned int pwm_f_clk_pins[] = { PIN(GPIOCLK_1, EE_OFF) }; +static const unsigned int pwm_f_x_pins[] = { PIN(GPIOX_7, EE_OFF) }; + +static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, EE_OFF) }; +static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, EE_OFF) }; +static const unsigned int hdmi_scl_pins[] = { PIN(GPIOH_2, EE_OFF) }; + +static const unsigned int i2s_am_clk_pins[] = { PIN(GPIOH_6, EE_OFF) }; +static const unsigned int i2s_out_ao_clk_pins[] = { PIN(GPIOH_7, EE_OFF) }; +static const unsigned int i2s_out_lr_clk_pins[] = { PIN(GPIOH_8, EE_OFF) }; +static const unsigned int i2s_out_ch01_pins[] = { PIN(GPIOH_9, EE_OFF) }; +static const unsigned int i2s_out_ch23_z_pins[] = { PIN(GPIOZ_5, EE_OFF) }; +static const unsigned int i2s_out_ch45_z_pins[] = { PIN(GPIOZ_6, EE_OFF) }; +static const unsigned int i2s_out_ch67_z_pins[] = { PIN(GPIOZ_7, EE_OFF) }; + +static const unsigned int spdif_out_h_pins[] = { PIN(GPIOH_4, EE_OFF) }; + +static const unsigned int eth_link_led_pins[] = { PIN(GPIOZ_14, EE_OFF) }; +static const unsigned int eth_act_led_pins[] = { PIN(GPIOZ_15, EE_OFF) }; + +static const unsigned int tsin_a_d0_pins[] = { PIN(GPIODV_0, EE_OFF) }; +static const unsigned int tsin_a_d0_x_pins[] = { PIN(GPIOX_10, EE_OFF) }; +static const unsigned int tsin_a_clk_pins[] = { PIN(GPIODV_8, EE_OFF) }; +static const unsigned int tsin_a_clk_x_pins[] = { PIN(GPIOX_11, EE_OFF) }; +static const unsigned int tsin_a_sop_pins[] = { PIN(GPIODV_9, EE_OFF) }; +static const unsigned int tsin_a_sop_x_pins[] = { PIN(GPIOX_8, EE_OFF) }; +static const unsigned int tsin_a_d_valid_pins[] = { PIN(GPIODV_10, EE_OFF) }; +static const unsigned int tsin_a_d_valid_x_pins[] = { PIN(GPIOX_9, EE_OFF) }; +static const unsigned int tsin_a_fail_pins[] = { PIN(GPIODV_11, EE_OFF) }; +static const unsigned int tsin_a_dp_pins[] = { + PIN(GPIODV_1, EE_OFF), + PIN(GPIODV_2, EE_OFF), + PIN(GPIODV_3, EE_OFF), + PIN(GPIODV_4, EE_OFF), + PIN(GPIODV_5, EE_OFF), + PIN(GPIODV_6, EE_OFF), + PIN(GPIODV_7, EE_OFF), +}; + +static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, 0) }; +static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, 0) }; +static const unsigned int uart_tx_ao_b_0_pins[] = { PIN(GPIOAO_0, 0) }; +static const unsigned int uart_rx_ao_b_1_pins[] = { PIN(GPIOAO_1, 0) }; +static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, 0) }; +static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, 0) }; +static const unsigned int uart_tx_ao_b_pins[] = { PIN(GPIOAO_4, 0) }; +static const unsigned int uart_rx_ao_b_pins[] = { PIN(GPIOAO_5, 0) }; +static const unsigned int uart_cts_ao_b_pins[] = { PIN(GPIOAO_2, 0) }; +static const unsigned int uart_rts_ao_b_pins[] = { PIN(GPIOAO_3, 0) }; + +static const unsigned int i2c_sck_ao_pins[] = {PIN(GPIOAO_4, 0) }; +static const unsigned int i2c_sda_ao_pins[] = {PIN(GPIOAO_5, 0) }; +static const unsigned int i2c_slave_sck_ao_pins[] = {PIN(GPIOAO_4, 0) }; +static const unsigned int i2c_slave_sda_ao_pins[] = {PIN(GPIOAO_5, 0) }; + +static const unsigned int remote_input_ao_pins[] = {PIN(GPIOAO_7, 0) }; + +static const unsigned int pwm_ao_a_3_pins[] = { PIN(GPIOAO_3, 0) }; +static const unsigned int pwm_ao_a_8_pins[] = { PIN(GPIOAO_8, 0) }; + +static const unsigned int pwm_ao_b_pins[] = { PIN(GPIOAO_9, 0) }; +static const unsigned int pwm_ao_b_6_pins[] = { PIN(GPIOAO_6, 0) }; + +static const unsigned int i2s_out_ch23_ao_pins[] = { PIN(GPIOAO_8, 0) }; +static const unsigned int i2s_out_ch45_ao_pins[] = { PIN(GPIOAO_9, 0) }; + +static const unsigned int spdif_out_ao_6_pins[] = { PIN(GPIOAO_6, 0) }; +static const unsigned int spdif_out_ao_9_pins[] = { PIN(GPIOAO_9, 0) }; + +static const unsigned int ao_cec_pins[] = { PIN(GPIOAO_8, 0) }; +static const unsigned int ee_cec_pins[] = { PIN(GPIOAO_8, 0) }; + +static struct meson_pmx_group meson_gxl_periphs_groups[] = { + GPIO_GROUP(GPIOZ_0, EE_OFF), + GPIO_GROUP(GPIOZ_1, EE_OFF), + GPIO_GROUP(GPIOZ_2, EE_OFF), + GPIO_GROUP(GPIOZ_3, EE_OFF), + GPIO_GROUP(GPIOZ_4, EE_OFF), + GPIO_GROUP(GPIOZ_5, EE_OFF), + GPIO_GROUP(GPIOZ_6, EE_OFF), + GPIO_GROUP(GPIOZ_7, EE_OFF), + GPIO_GROUP(GPIOZ_8, EE_OFF), + GPIO_GROUP(GPIOZ_9, EE_OFF), + GPIO_GROUP(GPIOZ_10, EE_OFF), + GPIO_GROUP(GPIOZ_11, EE_OFF), + GPIO_GROUP(GPIOZ_12, EE_OFF), + GPIO_GROUP(GPIOZ_13, EE_OFF), + GPIO_GROUP(GPIOZ_14, EE_OFF), + GPIO_GROUP(GPIOZ_15, EE_OFF), + + GPIO_GROUP(GPIOH_0, EE_OFF), + GPIO_GROUP(GPIOH_1, EE_OFF), + GPIO_GROUP(GPIOH_2, EE_OFF), + GPIO_GROUP(GPIOH_3, EE_OFF), + GPIO_GROUP(GPIOH_4, EE_OFF), + GPIO_GROUP(GPIOH_5, EE_OFF), + GPIO_GROUP(GPIOH_6, EE_OFF), + GPIO_GROUP(GPIOH_7, EE_OFF), + GPIO_GROUP(GPIOH_8, EE_OFF), + GPIO_GROUP(GPIOH_9, EE_OFF), + + GPIO_GROUP(BOOT_0, EE_OFF), + GPIO_GROUP(BOOT_1, EE_OFF), + GPIO_GROUP(BOOT_2, EE_OFF), + GPIO_GROUP(BOOT_3, EE_OFF), + GPIO_GROUP(BOOT_4, EE_OFF), + GPIO_GROUP(BOOT_5, EE_OFF), + GPIO_GROUP(BOOT_6, EE_OFF), + GPIO_GROUP(BOOT_7, EE_OFF), + GPIO_GROUP(BOOT_8, EE_OFF), + GPIO_GROUP(BOOT_9, EE_OFF), + GPIO_GROUP(BOOT_10, EE_OFF), + GPIO_GROUP(BOOT_11, EE_OFF), + GPIO_GROUP(BOOT_12, EE_OFF), + GPIO_GROUP(BOOT_13, EE_OFF), + GPIO_GROUP(BOOT_14, EE_OFF), + GPIO_GROUP(BOOT_15, EE_OFF), + + GPIO_GROUP(CARD_0, EE_OFF), + GPIO_GROUP(CARD_1, EE_OFF), + GPIO_GROUP(CARD_2, EE_OFF), + GPIO_GROUP(CARD_3, EE_OFF), + GPIO_GROUP(CARD_4, EE_OFF), + GPIO_GROUP(CARD_5, EE_OFF), + GPIO_GROUP(CARD_6, EE_OFF), + + GPIO_GROUP(GPIODV_0, EE_OFF), + GPIO_GROUP(GPIODV_1, EE_OFF), + GPIO_GROUP(GPIODV_2, EE_OFF), + GPIO_GROUP(GPIODV_3, EE_OFF), + GPIO_GROUP(GPIODV_4, EE_OFF), + GPIO_GROUP(GPIODV_5, EE_OFF), + GPIO_GROUP(GPIODV_6, EE_OFF), + GPIO_GROUP(GPIODV_7, EE_OFF), + GPIO_GROUP(GPIODV_8, EE_OFF), + GPIO_GROUP(GPIODV_9, EE_OFF), + GPIO_GROUP(GPIODV_10, EE_OFF), + GPIO_GROUP(GPIODV_11, EE_OFF), + GPIO_GROUP(GPIODV_12, EE_OFF), + GPIO_GROUP(GPIODV_13, EE_OFF), + GPIO_GROUP(GPIODV_14, EE_OFF), + GPIO_GROUP(GPIODV_15, EE_OFF), + GPIO_GROUP(GPIODV_16, EE_OFF), + GPIO_GROUP(GPIODV_17, EE_OFF), + GPIO_GROUP(GPIODV_19, EE_OFF), + GPIO_GROUP(GPIODV_20, EE_OFF), + GPIO_GROUP(GPIODV_21, EE_OFF), + GPIO_GROUP(GPIODV_22, EE_OFF), + GPIO_GROUP(GPIODV_23, EE_OFF), + GPIO_GROUP(GPIODV_24, EE_OFF), + GPIO_GROUP(GPIODV_25, EE_OFF), + GPIO_GROUP(GPIODV_26, EE_OFF), + GPIO_GROUP(GPIODV_27, EE_OFF), + GPIO_GROUP(GPIODV_28, EE_OFF), + GPIO_GROUP(GPIODV_29, EE_OFF), + + GPIO_GROUP(GPIOX_0, EE_OFF), + GPIO_GROUP(GPIOX_1, EE_OFF), + GPIO_GROUP(GPIOX_2, EE_OFF), + GPIO_GROUP(GPIOX_3, EE_OFF), + GPIO_GROUP(GPIOX_4, EE_OFF), + GPIO_GROUP(GPIOX_5, EE_OFF), + GPIO_GROUP(GPIOX_6, EE_OFF), + GPIO_GROUP(GPIOX_7, EE_OFF), + GPIO_GROUP(GPIOX_8, EE_OFF), + GPIO_GROUP(GPIOX_9, EE_OFF), + GPIO_GROUP(GPIOX_10, EE_OFF), + GPIO_GROUP(GPIOX_11, EE_OFF), + GPIO_GROUP(GPIOX_12, EE_OFF), + GPIO_GROUP(GPIOX_13, EE_OFF), + GPIO_GROUP(GPIOX_14, EE_OFF), + GPIO_GROUP(GPIOX_15, EE_OFF), + GPIO_GROUP(GPIOX_16, EE_OFF), + GPIO_GROUP(GPIOX_17, EE_OFF), + GPIO_GROUP(GPIOX_18, EE_OFF), + + GPIO_GROUP(GPIOCLK_0, EE_OFF), + GPIO_GROUP(GPIOCLK_1, EE_OFF), + + GPIO_GROUP(GPIO_TEST_N, EE_OFF), + + /* Bank X */ + GROUP(sdio_d0, 5, 31), + GROUP(sdio_d1, 5, 30), + GROUP(sdio_d2, 5, 29), + GROUP(sdio_d3, 5, 28), + GROUP(sdio_clk, 5, 27), + GROUP(sdio_cmd, 5, 26), + GROUP(sdio_irq, 5, 24), + GROUP(uart_tx_a, 5, 19), + GROUP(uart_rx_a, 5, 18), + GROUP(uart_cts_a, 5, 17), + GROUP(uart_rts_a, 5, 16), + GROUP(uart_tx_c, 5, 13), + GROUP(uart_rx_c, 5, 12), + GROUP(uart_cts_c, 5, 11), + GROUP(uart_rts_c, 5, 10), + GROUP(pwm_a, 5, 25), + GROUP(pwm_e, 5, 15), + GROUP(pwm_f_x, 5, 14), + GROUP(spi_mosi, 5, 3), + GROUP(spi_miso, 5, 2), + GROUP(spi_ss0, 5, 1), + GROUP(spi_sclk, 5, 0), + GROUP(tsin_a_sop_x, 6, 3), + GROUP(tsin_a_d_valid_x, 6, 2), + GROUP(tsin_a_d0_x, 6, 1), + GROUP(tsin_a_clk_x, 6, 0), + + /* Bank Z */ + GROUP(eth_mdio, 4, 23), + GROUP(eth_mdc, 4, 22), + GROUP(eth_clk_rx_clk, 4, 21), + GROUP(eth_rx_dv, 4, 20), + GROUP(eth_rxd0, 4, 19), + GROUP(eth_rxd1, 4, 18), + GROUP(eth_rxd2, 4, 17), + GROUP(eth_rxd3, 4, 16), + GROUP(eth_rgmii_tx_clk, 4, 15), + GROUP(eth_tx_en, 4, 14), + GROUP(eth_txd0, 4, 13), + GROUP(eth_txd1, 4, 12), + GROUP(eth_txd2, 4, 11), + GROUP(eth_txd3, 4, 10), + GROUP(pwm_c, 3, 20), + GROUP(i2s_out_ch23_z, 3, 26), + GROUP(i2s_out_ch45_z, 3, 25), + GROUP(i2s_out_ch67_z, 3, 24), + GROUP(eth_link_led, 4, 25), + GROUP(eth_act_led, 4, 24), + + /* Bank H */ + GROUP(hdmi_hpd, 6, 31), + GROUP(hdmi_sda, 6, 30), + GROUP(hdmi_scl, 6, 29), + GROUP(i2s_am_clk, 6, 26), + GROUP(i2s_out_ao_clk, 6, 25), + GROUP(i2s_out_lr_clk, 6, 24), + GROUP(i2s_out_ch01, 6, 23), + GROUP(spdif_out_h, 6, 28), + + /* Bank DV */ + GROUP(uart_tx_b, 2, 16), + GROUP(uart_rx_b, 2, 15), + GROUP(uart_cts_b, 2, 14), + GROUP(uart_rts_b, 2, 13), + GROUP(i2c_sda_c_dv18, 1, 17), + GROUP(i2c_sck_c_dv19, 1, 16), + GROUP(i2c_sda_a, 1, 15), + GROUP(i2c_sck_a, 1, 14), + GROUP(i2c_sda_b, 1, 13), + GROUP(i2c_sck_b, 1, 12), + GROUP(i2c_sda_c, 1, 11), + GROUP(i2c_sck_c, 1, 10), + GROUP(pwm_b, 2, 11), + GROUP(pwm_d, 2, 12), + GROUP(tsin_a_d0, 2, 4), + GROUP(tsin_a_dp, 2, 3), + GROUP(tsin_a_clk, 2, 2), + GROUP(tsin_a_sop, 2, 1), + GROUP(tsin_a_d_valid, 2, 0), + GROUP(tsin_a_fail, 1, 31), + + /* Bank BOOT */ + GROUP(emmc_nand_d07, 7, 31), + GROUP(emmc_clk, 7, 30), + GROUP(emmc_cmd, 7, 29), + GROUP(emmc_ds, 7, 28), + GROUP(nor_d, 7, 13), + GROUP(nor_q, 7, 12), + GROUP(nor_c, 7, 11), + GROUP(nor_cs, 7, 10), + GROUP(nand_ce0, 7, 7), + GROUP(nand_ce1, 7, 6), + GROUP(nand_rb0, 7, 5), + GROUP(nand_ale, 7, 4), + GROUP(nand_cle, 7, 3), + GROUP(nand_wen_clk, 7, 2), + GROUP(nand_ren_wr, 7, 1), + GROUP(nand_dqs, 7, 0), + + /* Bank CARD */ + GROUP(sdcard_d1, 6, 5), + GROUP(sdcard_d0, 6, 4), + GROUP(sdcard_d3, 6, 1), + GROUP(sdcard_d2, 6, 0), + GROUP(sdcard_cmd, 6, 2), + GROUP(sdcard_clk, 6, 3), + + /* Bank CLK */ + GROUP(pwm_f_clk, 8, 30), +}; + +static struct meson_pmx_group meson_gxl_aobus_groups[] = { + GPIO_GROUP(GPIOAO_0, 0), + GPIO_GROUP(GPIOAO_1, 0), + GPIO_GROUP(GPIOAO_2, 0), + GPIO_GROUP(GPIOAO_3, 0), + GPIO_GROUP(GPIOAO_4, 0), + GPIO_GROUP(GPIOAO_5, 0), + GPIO_GROUP(GPIOAO_6, 0), + GPIO_GROUP(GPIOAO_7, 0), + GPIO_GROUP(GPIOAO_8, 0), + GPIO_GROUP(GPIOAO_9, 0), + + /* bank AO */ + GROUP(uart_tx_ao_b_0, 0, 26), + GROUP(uart_rx_ao_b_1, 0, 25), + GROUP(uart_tx_ao_b, 0, 24), + GROUP(uart_rx_ao_b, 0, 23), + GROUP(uart_tx_ao_a, 0, 12), + GROUP(uart_rx_ao_a, 0, 11), + GROUP(uart_cts_ao_a, 0, 10), + GROUP(uart_rts_ao_a, 0, 9), + GROUP(uart_cts_ao_b, 0, 8), + GROUP(uart_rts_ao_b, 0, 7), + GROUP(i2c_sck_ao, 0, 6), + GROUP(i2c_sda_ao, 0, 5), + GROUP(i2c_slave_sck_ao, 0, 2), + GROUP(i2c_slave_sda_ao, 0, 1), + GROUP(remote_input_ao, 0, 0), + GROUP(pwm_ao_a_3, 0, 22), + GROUP(pwm_ao_b_6, 0, 18), + GROUP(pwm_ao_a_8, 0, 17), + GROUP(pwm_ao_b, 0, 3), + GROUP(i2s_out_ch23_ao, 1, 0), + GROUP(i2s_out_ch45_ao, 1, 1), + GROUP(spdif_out_ao_6, 0, 16), + GROUP(spdif_out_ao_9, 0, 4), + GROUP(ao_cec, 0, 15), + GROUP(ee_cec, 0, 14), +}; + +static const char * const gpio_periphs_groups[] = { + "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", + "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", + "GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14", + "GPIOZ_15", + + "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", + "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9", + + "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4", + "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9", + "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14", + "BOOT_15", + + "CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4", + "CARD_5", "CARD_6", + + "GPIODV_0", "GPIODV_1", "GPIODV_2", "GPIODV_3", "GPIODV_4", + "GPIODV_5", "GPIODV_6", "GPIODV_7", "GPIODV_8", "GPIODV_9", + "GPIODV_10", "GPIODV_11", "GPIODV_12", "GPIODV_13", "GPIODV_14", + "GPIODV_15", "GPIODV_16", "GPIODV_17", "GPIODV_18", "GPIODV_19", + "GPIODV_20", "GPIODV_21", "GPIODV_22", "GPIODV_23", "GPIODV_24", + "GPIODV_25", "GPIODV_26", "GPIODV_27", "GPIODV_28", "GPIODV_29", + + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", + "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", + "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14", + "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", + + "GPIO_TEST_N", +}; + +static const char * const emmc_groups[] = { + "emmc_nand_d07", "emmc_clk", "emmc_cmd", "emmc_ds", +}; + +static const char * const nor_groups[] = { + "nor_d", "nor_q", "nor_c", "nor_cs", +}; + +static const char * const spi_groups[] = { + "spi_mosi", "spi_miso", "spi_ss0", "spi_sclk", +}; + +static const char * const sdcard_groups[] = { + "sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3", + "sdcard_cmd", "sdcard_clk", +}; + +static const char * const sdio_groups[] = { + "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", + "sdio_cmd", "sdio_clk", "sdio_irq", +}; + +static const char * const nand_groups[] = { + "nand_ce0", "nand_ce1", "nand_rb0", "nand_ale", "nand_cle", + "nand_wen_clk", "nand_ren_wr", "nand_dqs", +}; + +static const char * const uart_a_groups[] = { + "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a", +}; + +static const char * const uart_b_groups[] = { + "uart_tx_b", "uart_rx_b", "uart_cts_b", "uart_rts_b", +}; + +static const char * const uart_c_groups[] = { + "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c", +}; + +static const char * const i2c_a_groups[] = { + "i2c_sck_a", "i2c_sda_a", +}; + +static const char * const i2c_b_groups[] = { + "i2c_sck_b", "i2c_sda_b", +}; + +static const char * const i2c_c_groups[] = { + "i2c_sck_c", "i2c_sda_c", "i2c_sda_c_dv18", "i2c_sck_c_dv19", +}; + +static const char * const eth_groups[] = { + "eth_mdio", "eth_mdc", "eth_clk_rx_clk", "eth_rx_dv", + "eth_rxd0", "eth_rxd1", "eth_rxd2", "eth_rxd3", + "eth_rgmii_tx_clk", "eth_tx_en", + "eth_txd0", "eth_txd1", "eth_txd2", "eth_txd3", +}; + +static const char * const pwm_a_groups[] = { + "pwm_a", +}; + +static const char * const pwm_b_groups[] = { + "pwm_b", +}; + +static const char * const pwm_c_groups[] = { + "pwm_c", +}; + +static const char * const pwm_d_groups[] = { + "pwm_d", +}; + +static const char * const pwm_e_groups[] = { + "pwm_e", +}; + +static const char * const pwm_f_groups[] = { + "pwm_f_clk", "pwm_f_x", +}; + +static const char * const hdmi_hpd_groups[] = { + "hdmi_hpd", +}; + +static const char * const hdmi_i2c_groups[] = { + "hdmi_sda", "hdmi_scl", +}; + +static const char * const i2s_out_groups[] = { + "i2s_am_clk", "i2s_out_ao_clk", "i2s_out_lr_clk", + "i2s_out_ch01", "i2s_out_ch23_z", "i2s_out_ch45_z", "i2s_out_ch67_z", +}; + +static const char * const spdif_out_groups[] = { + "spdif_out_h", +}; + +static const char * const eth_led_groups[] = { + "eth_link_led", "eth_act_led", +}; + +static const char * const tsin_a_groups[] = { + "tsin_a_clk", "tsin_a_clk_x", "tsin_a_sop", "tsin_a_sop_x", + "tsin_a_d_valid", "tsin_a_d_valid_x", "tsin_a_d0", "tsin_a_d0_x", + "tsin_a_dp", "tsin_a_fail", +}; + +static const char * const gpio_aobus_groups[] = { + "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4", + "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9", +}; + +static const char * const uart_ao_groups[] = { + "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a", +}; + +static const char * const uart_ao_b_groups[] = { + "uart_tx_ao_b", "uart_rx_ao_b", "uart_cts_ao_b", "uart_rts_ao_b", + "uart_tx_ao_b_0", "uart_rx_ao_b_1", +}; + +static const char * const i2c_ao_groups[] = { + "i2c_sck_ao", "i2c_sda_ao", +}; + +static const char * const i2c_slave_ao_groups[] = { + "i2c_slave_sck_ao", "i2c_slave_sda_ao", +}; + +static const char * const remote_input_ao_groups[] = { + "remote_input_ao", +}; + +static const char * const pwm_ao_a_groups[] = { + "pwm_ao_a_3", "pwm_ao_a_8", +}; + +static const char * const pwm_ao_b_groups[] = { + "pwm_ao_b", "pwm_ao_b_6", +}; + +static const char * const i2s_out_ao_groups[] = { + "i2s_out_ch23_ao", "i2s_out_ch45_ao", +}; + +static const char * const spdif_out_ao_groups[] = { + "spdif_out_ao_6", "spdif_out_ao_9", +}; + +static const char * const cec_ao_groups[] = { + "ao_cec", "ee_cec", +}; + +static struct meson_pmx_func meson_gxl_periphs_functions[] = { + FUNCTION(gpio_periphs), + FUNCTION(emmc), + FUNCTION(nor), + FUNCTION(spi), + FUNCTION(sdcard), + FUNCTION(sdio), + FUNCTION(nand), + FUNCTION(uart_a), + FUNCTION(uart_b), + FUNCTION(uart_c), + FUNCTION(i2c_a), + FUNCTION(i2c_b), + FUNCTION(i2c_c), + FUNCTION(eth), + FUNCTION(pwm_a), + FUNCTION(pwm_b), + FUNCTION(pwm_c), + FUNCTION(pwm_d), + FUNCTION(pwm_e), + FUNCTION(pwm_f), + FUNCTION(hdmi_hpd), + FUNCTION(hdmi_i2c), + FUNCTION(i2s_out), + FUNCTION(spdif_out), + FUNCTION(eth_led), + FUNCTION(tsin_a), +}; + +static struct meson_pmx_func meson_gxl_aobus_functions[] = { + FUNCTION(gpio_aobus), + FUNCTION(uart_ao), + FUNCTION(uart_ao_b), + FUNCTION(i2c_ao), + FUNCTION(i2c_slave_ao), + FUNCTION(remote_input_ao), + FUNCTION(pwm_ao_a), + FUNCTION(pwm_ao_b), + FUNCTION(i2s_out_ao), + FUNCTION(spdif_out_ao), + FUNCTION(cec_ao), +}; + +static struct meson_bank meson_gxl_periphs_banks[] = { + /* name first last pullen pull dir out in */ + BANK("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_18, EE_OFF), 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), + BANK("DV", PIN(GPIODV_0, EE_OFF), PIN(GPIODV_29, EE_OFF), 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), + BANK("H", PIN(GPIOH_0, EE_OFF), PIN(GPIOH_9, EE_OFF), 1, 20, 1, 20, 3, 20, 4, 20, 5, 20), + BANK("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_15, EE_OFF), 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), + BANK("CARD", PIN(CARD_0, EE_OFF), PIN(CARD_6, EE_OFF), 2, 20, 2, 20, 6, 20, 7, 20, 8, 20), + BANK("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_15, EE_OFF), 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), + BANK("CLK", PIN(GPIOCLK_0, EE_OFF), PIN(GPIOCLK_1, EE_OFF), 3, 28, 3, 28, 9, 28, 10, 28, 11, 28), +}; + +static struct meson_bank meson_gxl_aobus_banks[] = { + /* name first last pullen pull dir out in */ + BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_9, 0), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), +}; + +struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = { + .name = "periphs-banks", + .pin_base = 10, + .groups = meson_gxl_periphs_groups, + .funcs = meson_gxl_periphs_functions, + .banks = meson_gxl_periphs_banks, + .num_pins = 101, + .num_groups = ARRAY_SIZE(meson_gxl_periphs_groups), + .num_funcs = ARRAY_SIZE(meson_gxl_periphs_functions), + .num_banks = ARRAY_SIZE(meson_gxl_periphs_banks), +}; + +struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = { + .name = "aobus-banks", + .pin_base = 0, + .groups = meson_gxl_aobus_groups, + .funcs = meson_gxl_aobus_functions, + .banks = meson_gxl_aobus_banks, + .num_pins = 10, + .num_groups = ARRAY_SIZE(meson_gxl_aobus_groups), + .num_funcs = ARRAY_SIZE(meson_gxl_aobus_functions), + .num_banks = ARRAY_SIZE(meson_gxl_aobus_banks), +}; + +static const struct udevice_id meson_gxl_pinctrl_match[] = { + { + .compatible = "amlogic,meson-gxl-periphs-pinctrl", + .data = (ulong)&meson_gxl_periphs_pinctrl_data, + }, + { + .compatible = "amlogic,meson-gxl-aobus-pinctrl", + .data = (ulong)&meson_gxl_aobus_pinctrl_data, + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(meson_gxl_pinctrl) = { + .name = "meson-gxl-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(meson_gxl_pinctrl_match), + .probe = meson_pinctrl_probe, + .priv_auto_alloc_size = sizeof(struct meson_pinctrl), + .ops = &meson_pinctrl_ops, +}; diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c index cab268c7d6..19a7415522 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c @@ -70,11 +70,21 @@ static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs *grf, PMUGRF_GPIO1C0_SEL_MASK, PMUGRF_I2C0PMU_SCL << PMUGRF_GPIO1C0_SEL_SHIFT); break; + case PERIPH_ID_I2C8: + rk_clrsetreg(&pmugrf->gpio1c_iomux, + PMUGRF_GPIO1C4_SEL_MASK, + PMUGRF_I2C8PMU_SDA << PMUGRF_GPIO1C4_SEL_SHIFT); + rk_clrsetreg(&pmugrf->gpio1c_iomux, + PMUGRF_GPIO1C5_SEL_MASK, + PMUGRF_I2C8PMU_SCL << PMUGRF_GPIO1C5_SEL_SHIFT); + break; case PERIPH_ID_I2C1: case PERIPH_ID_I2C2: case PERIPH_ID_I2C3: case PERIPH_ID_I2C4: case PERIPH_ID_I2C5: + case PERIPH_ID_I2C6: + case PERIPH_ID_I2C7: default: debug("i2c id = %d iomux error!\n", i2c_id); break; @@ -301,6 +311,9 @@ static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags) case PERIPH_ID_I2C3: case PERIPH_ID_I2C4: case PERIPH_ID_I2C5: + case PERIPH_ID_I2C6: + case PERIPH_ID_I2C7: + case PERIPH_ID_I2C8: pinctrl_rk3399_i2c_config(priv->grf, priv->pmugrf, func); break; case PERIPH_ID_SPI0: @@ -375,6 +388,12 @@ static int rk3399_pinctrl_get_periph_id(struct udevice *dev, return PERIPH_ID_I2C4; case 38: return PERIPH_ID_I2C5; + case 37: + return PERIPH_ID_I2C6; + case 36: + return PERIPH_ID_I2C7; + case 58: + return PERIPH_ID_I2C8; case 65: return PERIPH_ID_SDMMC1; #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) diff --git a/drivers/serial/serial_nulldev.c b/drivers/serial/serial_nulldev.c index 07683086db..17b2310ee3 100644 --- a/drivers/serial/serial_nulldev.c +++ b/drivers/serial/serial_nulldev.c @@ -18,6 +18,11 @@ static int nulldev_serial_getc(struct udevice *dev) return -EAGAIN; } +static int nulldev_serial_pending(struct udevice *dev, bool input) +{ + return 0; +} + static int nulldev_serial_input(struct udevice *dev) { return 0; @@ -36,6 +41,7 @@ static const struct udevice_id nulldev_serial_ids[] = { const struct dm_serial_ops nulldev_serial_ops = { .putc = nulldev_serial_putc, + .pending = nulldev_serial_pending, .getc = nulldev_serial_getc, .setbrg = nulldev_serial_setbrg, }; diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index ebbdcaf14a..1da4542af0 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -548,7 +548,8 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, } if (max_hz > OMAP3_MCSPI_MAX_FREQ) { - printf("SPI error: unsupported frequency %i Hz. Max frequency is 48 Mhz\n", max_hz); + printf("SPI error: unsupported frequency %i Hz. Max frequency is 48 MHz\n", + max_hz); return NULL; } diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c index b18db74e7e..03d3fa6763 100644 --- a/drivers/spi/rk_spi.c +++ b/drivers/spi/rk_spi.c @@ -94,7 +94,7 @@ static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed) */ if (clk_div > 0xfffe) { clk_div = 0xfffe; - debug("%s: can't divide down to %d hz (actual will be %d hz)\n", + debug("%s: can't divide down to %d Hz (actual will be %d Hz)\n", __func__, speed, priv->input_rate / clk_div); } diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index 476d361297..2e9598e300 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -9,16 +9,7 @@ obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o -ifndef CONFIG_SPL_BUILD -obj-$(CONFIG_ROCKCHIP_RK3036) += sysreset_rk3036.o -endif -obj-$(CONFIG_ROCKCHIP_RK3188) += sysreset_rk3188.o -obj-$(CONFIG_ROCKCHIP_RK322X) += sysreset_rk322x.o -obj-$(CONFIG_ROCKCHIP_RK3288) += sysreset_rk3288.o -obj-$(CONFIG_ROCKCHIP_RK3328) += sysreset_rk3328.o -obj-$(CONFIG_ROCKCHIP_RK3368) += sysreset_rk3368.o -obj-$(CONFIG_ROCKCHIP_RK3399) += sysreset_rk3399.o -obj-$(CONFIG_ROCKCHIP_RV1108) += sysreset_rv1108.o +obj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o obj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o obj-$(CONFIG_ARCH_STI) += sysreset_sti.o diff --git a/drivers/sysreset/sysreset_rk3036.c b/drivers/sysreset/sysreset_rk3036.c deleted file mode 100644 index b3d2113239..0000000000 --- a/drivers/sysreset/sysreset_rk3036.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * (C) Copyright 2015 Rockchip Electronics Co., Ltd - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <sysreset.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3036.h> -#include <asm/arch/hardware.h> -#include <linux/err.h> - -int rk3036_sysreset_request(struct udevice *dev, enum sysreset_t type) -{ - struct rk3036_cru *cru = rockchip_get_cru(); - - if (IS_ERR(cru)) - return PTR_ERR(cru); - switch (type) { - case SYSRESET_WARM: - writel(0xeca8, &cru->cru_glb_srst_snd_value); - break; - case SYSRESET_COLD: - writel(0xfdb9, &cru->cru_glb_srst_fst_value); - break; - default: - return -EPROTONOSUPPORT; - } - - return -EINPROGRESS; -} - -static struct sysreset_ops rk3036_sysreset = { - .request = rk3036_sysreset_request, -}; - -U_BOOT_DRIVER(sysreset_rk3036) = { - .name = "rk3036_sysreset", - .id = UCLASS_SYSRESET, - .ops = &rk3036_sysreset, -}; diff --git a/drivers/sysreset/sysreset_rk3188.c b/drivers/sysreset/sysreset_rk3188.c deleted file mode 100644 index 053a6344f5..0000000000 --- a/drivers/sysreset/sysreset_rk3188.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * (C) Copyright 2015 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <syscon.h> -#include <sysreset.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3188.h> -#include <asm/arch/grf_rk3188.h> -#include <asm/arch/hardware.h> -#include <linux/err.h> - -int rk3188_sysreset_request(struct udevice *dev, enum sysreset_t type) -{ - struct rk3188_cru *cru = rockchip_get_cru(); - struct rk3188_grf *grf; - - if (IS_ERR(cru)) - return PTR_ERR(cru); - switch (type) { - case SYSRESET_WARM: - grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - if (IS_ERR(grf)) - return -EPROTONOSUPPORT; - - /* - * warm-reset keeps the remap value, - * so make sure it's disabled. - */ - rk_clrsetreg(&grf->soc_con0, - NOC_REMAP_MASK << NOC_REMAP_SHIFT, - 0 << NOC_REMAP_SHIFT); - - rk_clrreg(&cru->cru_mode_con, 0xffff); - writel(0xeca8, &cru->cru_glb_srst_snd_value); - break; - case SYSRESET_COLD: - rk_clrreg(&cru->cru_mode_con, 0xffff); - writel(0xfdb9, &cru->cru_glb_srst_fst_value); - break; - default: - return -EPROTONOSUPPORT; - } - - return -EINPROGRESS; -} - -static struct sysreset_ops rk3188_sysreset = { - .request = rk3188_sysreset_request, -}; - -U_BOOT_DRIVER(sysreset_rk3188) = { - .name = "rk3188_sysreset", - .id = UCLASS_SYSRESET, - .ops = &rk3188_sysreset, -}; diff --git a/drivers/sysreset/sysreset_rk322x.c b/drivers/sysreset/sysreset_rk322x.c deleted file mode 100644 index 5fce79b685..0000000000 --- a/drivers/sysreset/sysreset_rk322x.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <sysreset.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk322x.h> -#include <asm/arch/hardware.h> -#include <linux/err.h> - -int rk322x_sysreset_request(struct udevice *dev, enum sysreset_t type) -{ - struct rk322x_cru *cru = rockchip_get_cru(); - - if (IS_ERR(cru)) - return PTR_ERR(cru); - switch (type) { - case SYSRESET_WARM: - writel(0xeca8, &cru->cru_glb_srst_snd_value); - break; - case SYSRESET_COLD: - writel(0xfdb9, &cru->cru_glb_srst_fst_value); - break; - default: - return -EPROTONOSUPPORT; - } - - return -EINPROGRESS; -} - -static struct sysreset_ops rk322x_sysreset = { - .request = rk322x_sysreset_request, -}; - -U_BOOT_DRIVER(sysreset_rk322x) = { - .name = "rk322x_sysreset", - .id = UCLASS_SYSRESET, - .ops = &rk322x_sysreset, -}; diff --git a/drivers/sysreset/sysreset_rk3288.c b/drivers/sysreset/sysreset_rk3288.c deleted file mode 100644 index 0aad1c2160..0000000000 --- a/drivers/sysreset/sysreset_rk3288.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * (C) Copyright 2015 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <sysreset.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3288.h> -#include <asm/arch/hardware.h> -#include <linux/err.h> - -int rk3288_sysreset_request(struct udevice *dev, enum sysreset_t type) -{ - struct rk3288_cru *cru = rockchip_get_cru(); - - if (IS_ERR(cru)) - return PTR_ERR(cru); - switch (type) { - case SYSRESET_WARM: - rk_clrreg(&cru->cru_mode_con, 0xffff); - writel(0xeca8, &cru->cru_glb_srst_snd_value); - break; - case SYSRESET_COLD: - rk_clrreg(&cru->cru_mode_con, 0xffff); - writel(0xfdb9, &cru->cru_glb_srst_fst_value); - break; - default: - return -EPROTONOSUPPORT; - } - - return -EINPROGRESS; -} - -static struct sysreset_ops rk3288_sysreset = { - .request = rk3288_sysreset_request, -}; - -U_BOOT_DRIVER(sysreset_rk3288) = { - .name = "rk3288_sysreset", - .id = UCLASS_SYSRESET, - .ops = &rk3288_sysreset, -}; diff --git a/drivers/sysreset/sysreset_rk3328.c b/drivers/sysreset/sysreset_rk3328.c deleted file mode 100644 index 7b9af0925b..0000000000 --- a/drivers/sysreset/sysreset_rk3328.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <sysreset.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3328.h> -#include <asm/arch/hardware.h> -#include <asm/io.h> -#include <linux/err.h> - -int rk3328_sysreset_request(struct udevice *dev, enum sysreset_t type) -{ - struct rk3328_cru *cru = rockchip_get_cru(); - - if (IS_ERR(cru)) - return PTR_ERR(cru); - switch (type) { - case SYSRESET_WARM: - writel(0xeca8, &cru->glb_srst_snd_value); - break; - case SYSRESET_COLD: - writel(0xfdb9, &cru->glb_srst_fst_value); - break; - default: - return -EPROTONOSUPPORT; - } - - return -EINPROGRESS; -} - -static struct sysreset_ops rk3328_sysreset = { - .request = rk3328_sysreset_request, -}; - -U_BOOT_DRIVER(sysreset_rk3328) = { - .name = "rk3328_sysreset", - .id = UCLASS_SYSRESET, - .ops = &rk3328_sysreset, -}; diff --git a/drivers/sysreset/sysreset_rk3368.c b/drivers/sysreset/sysreset_rk3368.c deleted file mode 100644 index de62921b78..0000000000 --- a/drivers/sysreset/sysreset_rk3368.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * (C) Copyright Rockchip Electronics Co., Ltd - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <sysreset.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3368.h> -#include <asm/arch/hardware.h> -#include <linux/err.h> - -static void rk3368_pll_enter_slow_mode(struct rk3368_cru *cru) -{ - struct rk3368_pll *pll; - int i; - - for (i = 0; i < 6; i++) { - pll = &cru->pll[i]; - rk_clrreg(&pll->con3, PLL_MODE_MASK); - } -} - -static int rk3368_sysreset_request(struct udevice *dev, enum sysreset_t type) -{ - struct rk3368_cru *cru = rockchip_get_cru(); - - if (IS_ERR(cru)) - return PTR_ERR(cru); - switch (type) { - case SYSRESET_WARM: - rk3368_pll_enter_slow_mode(cru); - rk_clrsetreg(&cru->glb_rst_con, PMU_GLB_SRST_CTRL_MASK, - PMU_RST_BY_SND_GLB_SRST << PMU_GLB_SRST_CTRL_SHIFT); - writel(0xeca8, &cru->glb_srst_snd_val); - break; - case SYSRESET_COLD: - rk3368_pll_enter_slow_mode(cru); - rk_clrsetreg(&cru->glb_rst_con, PMU_GLB_SRST_CTRL_MASK, - PMU_RST_BY_FST_GLB_SRST << PMU_GLB_SRST_CTRL_SHIFT); - writel(0xfdb9, &cru->glb_srst_fst_val); - break; - default: - return -EPROTONOSUPPORT; - } - - return -EINPROGRESS; -} - -static struct sysreset_ops rk3368_sysreset = { - .request = rk3368_sysreset_request, -}; - -U_BOOT_DRIVER(sysreset_rk3368) = { - .name = "rk3368_sysreset", - .id = UCLASS_SYSRESET, - .ops = &rk3368_sysreset, -}; diff --git a/drivers/sysreset/sysreset_rk3399.c b/drivers/sysreset/sysreset_rk3399.c deleted file mode 100644 index 9a555464c6..0000000000 --- a/drivers/sysreset/sysreset_rk3399.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <sysreset.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3399.h> -#include <asm/arch/hardware.h> -#include <linux/err.h> - -int rk3399_sysreset_request(struct udevice *dev, enum sysreset_t type) -{ - struct rk3399_cru *cru = rockchip_get_cru(); - - if (IS_ERR(cru)) - return PTR_ERR(cru); - switch (type) { - case SYSRESET_WARM: - writel(0xeca8, &cru->glb_srst_snd_value); - break; - case SYSRESET_COLD: - writel(0xfdb9, &cru->glb_srst_fst_value); - break; - default: - return -EPROTONOSUPPORT; - } - - return -EINPROGRESS; -} - -static struct sysreset_ops rk3399_sysreset = { - .request = rk3399_sysreset_request, -}; - -U_BOOT_DRIVER(sysreset_rk3399) = { - .name = "rk3399_sysreset", - .id = UCLASS_SYSRESET, - .ops = &rk3399_sysreset, -}; diff --git a/drivers/sysreset/sysreset_rockchip.c b/drivers/sysreset/sysreset_rockchip.c new file mode 100644 index 0000000000..894975f3fe --- /dev/null +++ b/drivers/sysreset/sysreset_rockchip.c @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <sysreset.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3328.h> +#include <asm/arch/hardware.h> +#include <linux/err.h> + +int rockchip_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + struct sysreset_reg *offset = dev_get_priv(dev); + unsigned long cru_base = (unsigned long)rockchip_get_cru(); + + if (IS_ERR_VALUE(cru_base)) + return (int)cru_base; + + switch (type) { + case SYSRESET_WARM: + writel(0xeca8, cru_base + offset->glb_srst_snd_value); + break; + case SYSRESET_COLD: + writel(0xfdb9, cru_base + offset->glb_srst_fst_value); + break; + default: + return -EPROTONOSUPPORT; + } + + return -EINPROGRESS; +} + +static struct sysreset_ops rockchip_sysreset = { + .request = rockchip_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_rockchip) = { + .name = "rockchip_sysreset", + .id = UCLASS_SYSRESET, + .ops = &rockchip_sysreset, +}; diff --git a/drivers/sysreset/sysreset_rv1108.c b/drivers/sysreset/sysreset_rv1108.c deleted file mode 100644 index 9d8e9f7ade..0000000000 --- a/drivers/sysreset/sysreset_rv1108.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * (C) Copyright 2015 Rockchip Electronics Co., Ltd - * Author: Andy Yan <andy.yan@rock-chips.com> - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <sysreset.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rv1108.h> -#include <asm/arch/hardware.h> -#include <linux/err.h> - -int rv1108_sysreset_request(struct udevice *dev, enum sysreset_t type) -{ - struct rv1108_cru *cru = rockchip_get_cru(); - - if (IS_ERR(cru)) - return PTR_ERR(cru); - - switch (type) { - case SYSRESET_WARM: - writel(0xeca8, &cru->glb_srst_snd_val); - break; - case SYSRESET_COLD: - writel(0xfdb9, &cru->glb_srst_fst_val); - break; - default: - return -EPROTONOSUPPORT; - } - - return -EINPROGRESS; -} - -static struct sysreset_ops rv1108_sysreset = { - .request = rv1108_sysreset_request, -}; - -U_BOOT_DRIVER(sysreset_rv1108) = { - .name = "rv1108_sysreset", - .id = UCLASS_SYSRESET, - .ops = &rv1108_sysreset, -}; diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 886f5fa546..a71b9be5fb 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -17,4 +17,10 @@ config IMX_THERMAL cpufreq is used as the cooling device to throttle CPUs when the passive trip is crossed. +config TI_DRA7_THERMAL + bool "Temperature sensor driver for TI dra7xx SOCs" + help + Enable thermal support for for the Texas Instruments DRA752 SoC family. + The driver supports reading CPU temperature. + endif # if DM_THERMAL diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index d768f5ef80..f6271a533b 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_DM_THERMAL) += thermal-uclass.o obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o +obj-$(CONFIG_TI_DRA7_THERMAL) += ti-bandgap.o diff --git a/drivers/thermal/ti-bandgap.c b/drivers/thermal/ti-bandgap.c new file mode 100644 index 0000000000..b490391e96 --- /dev/null +++ b/drivers/thermal/ti-bandgap.c @@ -0,0 +1,198 @@ +/* + * TI Bandgap temperature sensor driver + * + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Taken from Linux v4.9 (drivers/thermal/ti-soc-thermal/ti-bandgap.c) + * and ported to uboot. + * + */ + +#include <asm/io.h> +#include <dm.h> +#include <thermal.h> + +#define CTRL_CORE_TEMP_SENSOR_MPU 0 +#define DRA752_ADC_START_VALUE 540 + +struct ti_bandgap { + ulong base; + int temperature; /* in mili degree celsius */ +}; + +/* + * DRA752 : Temperature values in milli degree celsius + * ADC code values from 540 to 945 + */ +static int dra752_adc_to_temp[] = { + /* Index 540 - 549 */ + -40000, -40000, -40000, -40000, -39800, -39400, -39000, -38600, -38200, + -37800, + /* Index 550 - 559 */ + -37400, -37000, -36600, -36200, -35800, -35300, -34700, -34200, -33800, + -33400, + /* Index 560 - 569 */ + -33000, -32600, -32200, -31800, -31400, -31000, -30600, -30200, -29800, + -29400, + /* Index 570 - 579 */ + -29000, -28600, -28200, -27700, -27100, -26600, -26200, -25800, -25400, + -25000, + /* Index 580 - 589 */ + -24600, -24200, -23800, -23400, -23000, -22600, -22200, -21800, -21400, + -21000, + /* Index 590 - 599 */ + -20500, -19900, -19400, -19000, -18600, -18200, -17800, -17400, -17000, + -16600, + /* Index 600 - 609 */ + -16200, -15800, -15400, -15000, -14600, -14200, -13800, -13400, -13000, + -12500, + /* Index 610 - 619 */ + -11900, -11400, -11000, -10600, -10200, -9800, -9400, -9000, -8600, + -8200, + /* Index 620 - 629 */ + -7800, -7400, -7000, -6600, -6200, -5800, -5400, -5000, -4500, + -3900, + /* Index 630 - 639 */ + -3400, -3000, -2600, -2200, -1800, -1400, -1000, -600, -200, + 200, + /* Index 640 - 649 */ + 600, 1000, 1400, 1800, 2200, 2600, 3000, 3400, 3900, + 4500, + /* Index 650 - 659 */ + 5000, 5400, 5800, 6200, 6600, 7000, 7400, 7800, 8200, + 8600, + /* Index 660 - 669 */ + 9000, 9400, 9800, 10200, 10600, 11000, 11400, 11800, 12200, + 12700, + /* Index 670 - 679 */ + 13300, 13800, 14200, 14600, 15000, 15400, 15800, 16200, 16600, + 17000, + /* Index 680 - 689 */ + 17400, 17800, 18200, 18600, 19000, 19400, 19800, 20200, 20600, + 21000, + /* Index 690 - 699 */ + 21400, 21900, 22500, 23000, 23400, 23800, 24200, 24600, 25000, + 25400, + /* Index 700 - 709 */ + 25800, 26200, 26600, 27000, 27400, 27800, 28200, 28600, 29000, + 29400, + /* Index 710 - 719 */ + 29800, 30200, 30600, 31000, 31400, 31900, 32500, 33000, 33400, + 33800, + /* Index 720 - 729 */ + 34200, 34600, 35000, 35400, 35800, 36200, 36600, 37000, 37400, + 37800, + /* Index 730 - 739 */ + 38200, 38600, 39000, 39400, 39800, 40200, 40600, 41000, 41400, + 41800, + /* Index 740 - 749 */ + 42200, 42600, 43100, 43700, 44200, 44600, 45000, 45400, 45800, + 46200, + /* Index 750 - 759 */ + 46600, 47000, 47400, 47800, 48200, 48600, 49000, 49400, 49800, + 50200, + /* Index 760 - 769 */ + 50600, 51000, 51400, 51800, 52200, 52600, 53000, 53400, 53800, + 54200, + /* Index 770 - 779 */ + 54600, 55000, 55400, 55900, 56500, 57000, 57400, 57800, 58200, + 58600, + /* Index 780 - 789 */ + 59000, 59400, 59800, 60200, 60600, 61000, 61400, 61800, 62200, + 62600, + /* Index 790 - 799 */ + 63000, 63400, 63800, 64200, 64600, 65000, 65400, 65800, 66200, + 66600, + /* Index 800 - 809 */ + 67000, 67400, 67800, 68200, 68600, 69000, 69400, 69800, 70200, + 70600, + /* Index 810 - 819 */ + 71000, 71500, 72100, 72600, 73000, 73400, 73800, 74200, 74600, + 75000, + /* Index 820 - 829 */ + 75400, 75800, 76200, 76600, 77000, 77400, 77800, 78200, 78600, + 79000, + /* Index 830 - 839 */ + 79400, 79800, 80200, 80600, 81000, 81400, 81800, 82200, 82600, + 83000, + /* Index 840 - 849 */ + 83400, 83800, 84200, 84600, 85000, 85400, 85800, 86200, 86600, + 87000, + /* Index 850 - 859 */ + 87400, 87800, 88200, 88600, 89000, 89400, 89800, 90200, 90600, + 91000, + /* Index 860 - 869 */ + 91400, 91800, 92200, 92600, 93000, 93400, 93800, 94200, 94600, + 95000, + /* Index 870 - 879 */ + 95400, 95800, 96200, 96600, 97000, 97500, 98100, 98600, 99000, + 99400, + /* Index 880 - 889 */ + 99800, 100200, 100600, 101000, 101400, 101800, 102200, 102600, 103000, + 103400, + /* Index 890 - 899 */ + 103800, 104200, 104600, 105000, 105400, 105800, 106200, 106600, 107000, + 107400, + /* Index 900 - 909 */ + 107800, 108200, 108600, 109000, 109400, 109800, 110200, 110600, 111000, + 111400, + /* Index 910 - 919 */ + 111800, 112200, 112600, 113000, 113400, 113800, 114200, 114600, 115000, + 115400, + /* Index 920 - 929 */ + 115800, 116200, 116600, 117000, 117400, 117800, 118200, 118600, 119000, + 119400, + /* Index 930 - 939 */ + 119800, 120200, 120600, 121000, 121400, 121800, 122200, 122600, 123000, + 123400, + /* Index 940 - 945 */ + 123800, 124200, 124600, 124900, 125000, 125000, +}; + +static int ti_bandgap_get_temp(struct udevice *dev, int *temp) +{ + struct ti_bandgap *bgp = dev_get_priv(dev); + + bgp->temperature = 0x3ff & readl(bgp->base + CTRL_CORE_TEMP_SENSOR_MPU); + *temp = dra752_adc_to_temp[bgp->temperature - DRA752_ADC_START_VALUE]; + + return 0; +} + +static struct dm_thermal_ops ti_thermal_ops = { + .get_temp = ti_bandgap_get_temp, +}; + +static int ti_bandgap_probe(struct udevice *dev) +{ + struct ti_bandgap *bgp = dev_get_priv(dev); + + bgp->base = devfdt_get_addr_index(dev, 1); + + return 0; +} + +static const struct udevice_id of_ti_bandgap_match[] = { + { + .compatible = "ti,dra752-bandgap", + }, + {}, +}; + +U_BOOT_DRIVER(ti_bandgap_thermal) = { + .name = "ti_bandgap_thermal", + .id = UCLASS_THERMAL, + .ops = &ti_thermal_ops, + .probe = ti_bandgap_probe, + .of_match = of_ti_bandgap_match, + .priv_auto_alloc_size = sizeof(struct ti_bandgap), +}; diff --git a/drivers/usb/host/xhci-mvebu.c b/drivers/usb/host/xhci-mvebu.c index b9201a5a6a..dbdfce38da 100644 --- a/drivers/usb/host/xhci-mvebu.c +++ b/drivers/usb/host/xhci-mvebu.c @@ -35,7 +35,7 @@ struct mvebu_xhci { * Dummy implementation that can be overwritten by a board * specific function */ -__weak int board_xhci_enable(void) +__weak int board_xhci_enable(fdt_addr_t base) { return 0; } @@ -62,7 +62,7 @@ static int xhci_usb_probe(struct udevice *dev) } /* Enable USB xHCI (VBUS, reset etc) in board specific code */ - board_xhci_enable(); + board_xhci_enable(devfdt_get_addr_index(dev, 1)); return xhci_register(dev, ctx->hcd, hcor); } @@ -85,6 +85,7 @@ static int xhci_usb_ofdata_to_platdata(struct udevice *dev) static const struct udevice_id xhci_usb_ids[] = { { .compatible = "marvell,armada3700-xhci" }, + { .compatible = "marvell,armada-380-xhci" }, { .compatible = "marvell,armada-8k-xhci" }, { } }; |