diff options
Diffstat (limited to 'drivers')
52 files changed, 2770 insertions, 2026 deletions
diff --git a/drivers/Makefile b/drivers/Makefile index 603aa98590..41933605ce 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -4,7 +4,9 @@ obj-$(CONFIG_$(SPL_TPL_)CLK) += clk/ obj-$(CONFIG_$(SPL_TPL_)DM) += core/ obj-$(CONFIG_$(SPL_TPL_)DFU) += dfu/ obj-$(CONFIG_$(SPL_TPL_)GPIO_SUPPORT) += gpio/ -obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC_SUPPORT) += misc/ sysreset/ firmware/ +obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC_SUPPORT) += misc/ +obj-$(CONFIG_$(SPL_TPL_)SYSRESET) += sysreset/ +obj-$(CONFIG_$(SPL_TPL_)FIRMWARE) +=firmware/ obj-$(CONFIG_$(SPL_TPL_)I2C_SUPPORT) += i2c/ obj-$(CONFIG_$(SPL_TPL_)INPUT) += input/ obj-$(CONFIG_$(SPL_TPL_)LED) += led/ @@ -81,7 +83,6 @@ obj-y += cache/ obj-$(CONFIG_CPU) += cpu/ obj-y += crypto/ obj-$(CONFIG_FASTBOOT) += fastboot/ -obj-y += firmware/ obj-$(CONFIG_FPGA) += fpga/ obj-y += misc/ obj-$(CONFIG_MMC) += mmc/ @@ -96,7 +97,6 @@ obj-y += rtc/ obj-y += scsi/ obj-y += sound/ obj-y += spmi/ -obj-y += sysreset/ obj-y += video/ obj-y += watchdog/ obj-$(CONFIG_QE) += qe/ diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 2cb53fb92d..abb5337e78 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -823,10 +823,7 @@ static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id, case CLKID_MPLL1: case CLKID_MPLL2: case CLKID_CLK81: - if (current_rate != rate) - return -EINVAL; - - return 0; + return -EINVAL; case CLKID_VPU: return meson_clk_set_rate_by_id(clk, meson_mux_get_parent(clk, CLKID_VPU), rate, diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c index 9bb9959c9d..dda686cfb3 100644 --- a/drivers/clk/rockchip/clk_rk3188.c +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -562,6 +562,9 @@ static int rk3188_clk_probe(struct udevice *dev) #endif rkclk_init(priv->cru, priv->grf, priv->has_bwadj); + + /* Init CPU frequency */ + rkclk_configure_cpu(priv->cru, priv->grf, APLL_HZ, priv->has_bwadj); #endif return 0; diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index 0e4526288e..b85b56efe5 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -9,31 +9,27 @@ #include <errno.h> #include "sequencer.h" -static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs = +static const struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs = (struct socfpga_sdr_rw_load_manager *) (SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800); -static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs = - (struct socfpga_sdr_rw_load_jump_manager *) +static const struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs + = (struct socfpga_sdr_rw_load_jump_manager *) (SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00); -static struct socfpga_sdr_reg_file *sdr_reg_file = +static const struct socfpga_sdr_reg_file *sdr_reg_file = (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS; -static struct socfpga_sdr_scc_mgr *sdr_scc_mgr = +static const struct socfpga_sdr_scc_mgr *sdr_scc_mgr = (struct socfpga_sdr_scc_mgr *) (SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00); -static struct socfpga_phy_mgr_cmd *phy_mgr_cmd = +static const struct socfpga_phy_mgr_cmd *phy_mgr_cmd = (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS; -static struct socfpga_phy_mgr_cfg *phy_mgr_cfg = +static const struct socfpga_phy_mgr_cfg *phy_mgr_cfg = (struct socfpga_phy_mgr_cfg *) (SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40); -static struct socfpga_data_mgr *data_mgr = +static const struct socfpga_data_mgr *data_mgr = (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS; -static struct socfpga_sdr_ctrl *sdr_ctrl = +static const struct socfpga_sdr_ctrl *sdr_ctrl = (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS; -const struct socfpga_sdram_rw_mgr_config *rwcfg; -const struct socfpga_sdram_io_config *iocfg; -const struct socfpga_sdram_misc_config *misccfg; - #define DELTA_D 1 /* @@ -55,37 +51,20 @@ const struct socfpga_sdram_misc_config *misccfg; #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \ STATIC_SKIP_DELAY_LOOPS) -/* calibration steps requested by the rtl */ -static u16 dyn_calib_steps; - -/* - * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option - * instead of static, we use boolean logic to select between - * non-skip and skip values - * - * The mask is set to include all bits when not-skipping, but is - * zero when skipping - */ - -static u16 skip_delay_mask; /* mask off bits when skipping/not-skipping */ - #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \ - ((non_skip_value) & skip_delay_mask) - -static struct gbl_type *gbl; -static struct param_type *param; + ((non_skip_value) & seq->skip_delay_mask) -static void set_failing_group_stage(u32 group, u32 stage, - u32 substage) +static void set_failing_group_stage(struct socfpga_sdrseq *seq, + u32 group, u32 stage, u32 substage) { /* * Only set the global stage if there was not been any other * failing group */ - if (gbl->error_stage == CAL_STAGE_NIL) { - gbl->error_substage = substage; - gbl->error_stage = stage; - gbl->error_group = group; + if (seq->gbl.error_stage == CAL_STAGE_NIL) { + seq->gbl.error_substage = substage; + seq->gbl.error_stage = stage; + seq->gbl.error_group = group; } } @@ -110,7 +89,7 @@ static void reg_file_set_sub_stage(u8 set_sub_stage) * * Initialize PHY Manager. */ -static void phy_mgr_initialize(void) +static void phy_mgr_initialize(struct socfpga_sdrseq *seq) { u32 ratio; @@ -132,15 +111,17 @@ static void phy_mgr_initialize(void) writel(0, &phy_mgr_cfg->cal_debug_info); /* Init params only if we do NOT skip calibration. */ - if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) + if ((seq->dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) return; - ratio = rwcfg->mem_dq_per_read_dqs / - rwcfg->mem_virtual_groups_per_read_dqs; - param->read_correct_mask_vg = (1 << ratio) - 1; - param->write_correct_mask_vg = (1 << ratio) - 1; - param->read_correct_mask = (1 << rwcfg->mem_dq_per_read_dqs) - 1; - param->write_correct_mask = (1 << rwcfg->mem_dq_per_write_dqs) - 1; + ratio = seq->rwcfg->mem_dq_per_read_dqs / + seq->rwcfg->mem_virtual_groups_per_read_dqs; + seq->param.read_correct_mask_vg = (1 << ratio) - 1; + seq->param.write_correct_mask_vg = (1 << ratio) - 1; + seq->param.read_correct_mask = (1 << seq->rwcfg->mem_dq_per_read_dqs) + - 1; + seq->param.write_correct_mask = (1 << seq->rwcfg->mem_dq_per_write_dqs) + - 1; } /** @@ -150,7 +131,8 @@ static void phy_mgr_initialize(void) * * Set Rank and ODT mask (On-Die Termination). */ -static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode) +static void set_rank_and_odt_mask(struct socfpga_sdrseq *seq, + const u32 rank, const u32 odt_mode) { u32 odt_mask_0 = 0; u32 odt_mask_1 = 0; @@ -160,14 +142,14 @@ static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode) odt_mask_0 = 0x0; odt_mask_1 = 0x0; } else { /* RW_MGR_ODT_MODE_READ_WRITE */ - switch (rwcfg->mem_number_of_ranks) { + switch (seq->rwcfg->mem_number_of_ranks) { case 1: /* 1 Rank */ /* Read: ODT = 0 ; Write: ODT = 1 */ odt_mask_0 = 0x0; odt_mask_1 = 0x1; break; case 2: /* 2 Ranks */ - if (rwcfg->mem_number_of_cs_per_dimm == 1) { + if (seq->rwcfg->mem_number_of_cs_per_dimm == 1) { /* * - Dual-Slot , Single-Rank (1 CS per DIMM) * OR @@ -307,16 +289,18 @@ static void scc_mgr_set_dq_in_delay(u32 dq_in_group, u32 delay) scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay); } -static void scc_mgr_set_dqs_io_in_delay(u32 delay) +static void scc_mgr_set_dqs_io_in_delay(struct socfpga_sdrseq *seq, + u32 delay) { - scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs, - delay); + scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, + seq->rwcfg->mem_dq_per_write_dqs, delay); } -static void scc_mgr_set_dm_in_delay(u32 dm, u32 delay) +static void scc_mgr_set_dm_in_delay(struct socfpga_sdrseq *seq, u32 dm, + u32 delay) { scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, - rwcfg->mem_dq_per_write_dqs + 1 + dm, + seq->rwcfg->mem_dq_per_write_dqs + 1 + dm, delay); } @@ -325,16 +309,18 @@ static void scc_mgr_set_dq_out1_delay(u32 dq_in_group, u32 delay) scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay); } -static void scc_mgr_set_dqs_out1_delay(u32 delay) +static void scc_mgr_set_dqs_out1_delay(struct socfpga_sdrseq *seq, + u32 delay) { - scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs, - delay); + scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, + seq->rwcfg->mem_dq_per_write_dqs, delay); } -static void scc_mgr_set_dm_out1_delay(u32 dm, u32 delay) +static void scc_mgr_set_dm_out1_delay(struct socfpga_sdrseq *seq, u32 dm, + u32 delay) { scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, - rwcfg->mem_dq_per_write_dqs + 1 + dm, + seq->rwcfg->mem_dq_per_write_dqs + 1 + dm, delay); } @@ -372,12 +358,13 @@ static void scc_mgr_load_dm(u32 dm) * This function sets the SCC Manager (Scan Chain Control Manager) register * and optionally triggers the SCC update for all ranks. */ -static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val, +static void scc_mgr_set_all_ranks(struct socfpga_sdrseq *seq, + const u32 off, const u32 grp, const u32 val, const int update) { u32 r; - for (r = 0; r < rwcfg->mem_number_of_ranks; + for (r = 0; r < seq->rwcfg->mem_number_of_ranks; r += NUM_RANKS_PER_SHADOW_REG) { scc_mgr_set(off, grp, val); @@ -388,7 +375,8 @@ static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val, } } -static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase) +static void scc_mgr_set_dqs_en_phase_all_ranks(struct socfpga_sdrseq *seq, + u32 read_group, u32 phase) { /* * USER although the h/w doesn't support different phases per @@ -398,12 +386,12 @@ static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase) * for efficiency, the scan chain update should occur only * once to sr0. */ - scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET, + scc_mgr_set_all_ranks(seq, SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase, 0); } -static void scc_mgr_set_dqdqs_output_phase_all_ranks(u32 write_group, - u32 phase) +static void scc_mgr_set_dqdqs_output_phase_all_ranks(struct socfpga_sdrseq *seq, + u32 write_group, u32 phase) { /* * USER although the h/w doesn't support different phases per @@ -413,12 +401,12 @@ static void scc_mgr_set_dqdqs_output_phase_all_ranks(u32 write_group, * for efficiency, the scan chain update should occur only * once to sr0. */ - scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, + scc_mgr_set_all_ranks(seq, SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase, 0); } -static void scc_mgr_set_dqs_en_delay_all_ranks(u32 read_group, - u32 delay) +static void scc_mgr_set_dqs_en_delay_all_ranks(struct socfpga_sdrseq *seq, + u32 read_group, u32 delay) { /* * In shadow register mode, the T11 settings are stored in @@ -428,7 +416,7 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(u32 read_group, * select_shadow_regs_for_update with update_scan_chains * set to 0. */ - scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET, + scc_mgr_set_all_ranks(seq, SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay, 1); } @@ -439,10 +427,11 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(u32 read_group, * * This function sets the OCT output delay in SCC manager. */ -static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay) +static void scc_mgr_set_oct_out1_delay(struct socfpga_sdrseq *seq, + const u32 write_group, const u32 delay) { - const int ratio = rwcfg->mem_if_read_dqs_width / - rwcfg->mem_if_write_dqs_width; + const int ratio = seq->rwcfg->mem_if_read_dqs_width / + seq->rwcfg->mem_if_write_dqs_width; const int base = write_group * ratio; int i; /* @@ -490,7 +479,7 @@ static void scc_mgr_set_hhp_extras(void) * * Zero all DQS config. */ -static void scc_mgr_zero_all(void) +static void scc_mgr_zero_all(struct socfpga_sdrseq *seq) { int i, r; @@ -498,23 +487,26 @@ static void scc_mgr_zero_all(void) * USER Zero all DQS config settings, across all groups and all * shadow registers */ - for (r = 0; r < rwcfg->mem_number_of_ranks; + for (r = 0; r < seq->rwcfg->mem_number_of_ranks; r += NUM_RANKS_PER_SHADOW_REG) { - for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) { + for (i = 0; i < seq->rwcfg->mem_if_read_dqs_width; i++) { /* * The phases actually don't exist on a per-rank basis, * but there's no harm updating them several times, so * let's keep the code simple. */ - scc_mgr_set_dqs_bus_in_delay(i, iocfg->dqs_in_reserve); + scc_mgr_set_dqs_bus_in_delay(i, + seq->iocfg->dqs_in_reserve + ); scc_mgr_set_dqs_en_phase(i, 0); scc_mgr_set_dqs_en_delay(i, 0); } - for (i = 0; i < rwcfg->mem_if_write_dqs_width; i++) { + for (i = 0; i < seq->rwcfg->mem_if_write_dqs_width; i++) { scc_mgr_set_dqdqs_output_phase(i, 0); /* Arria V/Cyclone V don't have out2. */ - scc_mgr_set_oct_out1_delay(i, iocfg->dqs_out_reserve); + scc_mgr_set_oct_out1_delay(seq, i, + seq->iocfg->dqs_out_reserve); } } @@ -551,10 +543,11 @@ static void scc_set_bypass_mode(const u32 write_group) * * Load DQS settings for Write Group, do not trigger SCC update. */ -static void scc_mgr_load_dqs_for_write_group(const u32 write_group) +static void scc_mgr_load_dqs_for_write_group(struct socfpga_sdrseq *seq, + const u32 write_group) { - const int ratio = rwcfg->mem_if_read_dqs_width / - rwcfg->mem_if_write_dqs_width; + const int ratio = seq->rwcfg->mem_if_read_dqs_width / + seq->rwcfg->mem_if_write_dqs_width; const int base = write_group * ratio; int i; /* @@ -573,14 +566,15 @@ static void scc_mgr_load_dqs_for_write_group(const u32 write_group) * * Zero DQ, DM, DQS and OCT configs for a group. */ -static void scc_mgr_zero_group(const u32 write_group, const int out_only) +static void scc_mgr_zero_group(struct socfpga_sdrseq *seq, + const u32 write_group, const int out_only) { int i, r; - for (r = 0; r < rwcfg->mem_number_of_ranks; + for (r = 0; r < seq->rwcfg->mem_number_of_ranks; r += NUM_RANKS_PER_SHADOW_REG) { /* Zero all DQ config settings. */ - for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) { + for (i = 0; i < seq->rwcfg->mem_dq_per_write_dqs; i++) { scc_mgr_set_dq_out1_delay(i, 0); if (!out_only) scc_mgr_set_dq_in_delay(i, 0); @@ -592,8 +586,8 @@ static void scc_mgr_zero_group(const u32 write_group, const int out_only) /* Zero all DM config settings. */ for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) { if (!out_only) - scc_mgr_set_dm_in_delay(i, 0); - scc_mgr_set_dm_out1_delay(i, 0); + scc_mgr_set_dm_in_delay(seq, i, 0); + scc_mgr_set_dm_out1_delay(seq, i, 0); } /* Multicast to all DM enables. */ @@ -601,12 +595,13 @@ static void scc_mgr_zero_group(const u32 write_group, const int out_only) /* Zero all DQS IO settings. */ if (!out_only) - scc_mgr_set_dqs_io_in_delay(0); + scc_mgr_set_dqs_io_in_delay(seq, 0); /* Arria V/Cyclone V don't have out2. */ - scc_mgr_set_dqs_out1_delay(iocfg->dqs_out_reserve); - scc_mgr_set_oct_out1_delay(write_group, iocfg->dqs_out_reserve); - scc_mgr_load_dqs_for_write_group(write_group); + scc_mgr_set_dqs_out1_delay(seq, seq->iocfg->dqs_out_reserve); + scc_mgr_set_oct_out1_delay(seq, write_group, + seq->iocfg->dqs_out_reserve); + scc_mgr_load_dqs_for_write_group(seq, write_group); /* Multicast to all DQS IO enables (only 1 in total). */ writel(0, &sdr_scc_mgr->dqs_io_ena); @@ -620,69 +615,76 @@ static void scc_mgr_zero_group(const u32 write_group, const int out_only) * apply and load a particular input delay for the DQ pins in a group * group_bgn is the index of the first dq pin (in the write group) */ -static void scc_mgr_apply_group_dq_in_delay(u32 group_bgn, u32 delay) +static void scc_mgr_apply_group_dq_in_delay(struct socfpga_sdrseq *seq, + u32 group_bgn, u32 delay) { u32 i, p; - for (i = 0, p = group_bgn; i < rwcfg->mem_dq_per_read_dqs; i++, p++) { + for (i = 0, p = group_bgn; i < seq->rwcfg->mem_dq_per_read_dqs; + i++, p++) { scc_mgr_set_dq_in_delay(p, delay); scc_mgr_load_dq(p); } } /** - * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group + * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the + * DQ pins in a group * @delay: Delay value * * Apply and load a particular output delay for the DQ pins in a group. */ -static void scc_mgr_apply_group_dq_out1_delay(const u32 delay) +static void scc_mgr_apply_group_dq_out1_delay(struct socfpga_sdrseq *seq, + const u32 delay) { int i; - for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) { + for (i = 0; i < seq->rwcfg->mem_dq_per_write_dqs; i++) { scc_mgr_set_dq_out1_delay(i, delay); scc_mgr_load_dq(i); } } /* apply and load a particular output delay for the DM pins in a group */ -static void scc_mgr_apply_group_dm_out1_delay(u32 delay1) +static void scc_mgr_apply_group_dm_out1_delay(struct socfpga_sdrseq *seq, + u32 delay1) { u32 i; for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) { - scc_mgr_set_dm_out1_delay(i, delay1); + scc_mgr_set_dm_out1_delay(seq, i, delay1); scc_mgr_load_dm(i); } } /* apply and load delay on both DQS and OCT out1 */ -static void scc_mgr_apply_group_dqs_io_and_oct_out1(u32 write_group, - u32 delay) +static void scc_mgr_apply_group_dqs_io_and_oct_out1(struct socfpga_sdrseq *seq, + u32 write_group, u32 delay) { - scc_mgr_set_dqs_out1_delay(delay); + scc_mgr_set_dqs_out1_delay(seq, delay); scc_mgr_load_dqs_io(); - scc_mgr_set_oct_out1_delay(write_group, delay); - scc_mgr_load_dqs_for_write_group(write_group); + scc_mgr_set_oct_out1_delay(seq, write_group, delay); + scc_mgr_load_dqs_for_write_group(seq, write_group); } /** - * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT + * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output + * side: DQ, DM, DQS, OCT * @write_group: Write group * @delay: Delay value * * Apply a delay to the entire output side: DQ, DM, DQS, OCT. */ -static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group, +static void scc_mgr_apply_group_all_out_delay_add(struct socfpga_sdrseq *seq, + const u32 write_group, const u32 delay) { u32 i, new_delay; /* DQ shift */ - for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) + for (i = 0; i < seq->rwcfg->mem_dq_per_write_dqs; i++) scc_mgr_load_dq(i); /* DM shift */ @@ -691,49 +693,51 @@ static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group, /* DQS shift */ new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay; - if (new_delay > iocfg->io_out2_delay_max) { + if (new_delay > seq->iocfg->io_out2_delay_max) { debug_cond(DLEVEL >= 1, "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n", __func__, __LINE__, write_group, delay, new_delay, - iocfg->io_out2_delay_max, - new_delay - iocfg->io_out2_delay_max); - new_delay -= iocfg->io_out2_delay_max; - scc_mgr_set_dqs_out1_delay(new_delay); + seq->iocfg->io_out2_delay_max, + new_delay - seq->iocfg->io_out2_delay_max); + new_delay -= seq->iocfg->io_out2_delay_max; + scc_mgr_set_dqs_out1_delay(seq, new_delay); } scc_mgr_load_dqs_io(); /* OCT shift */ new_delay = READ_SCC_OCT_OUT2_DELAY + delay; - if (new_delay > iocfg->io_out2_delay_max) { + if (new_delay > seq->iocfg->io_out2_delay_max) { debug_cond(DLEVEL >= 1, "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n", __func__, __LINE__, write_group, delay, - new_delay, iocfg->io_out2_delay_max, - new_delay - iocfg->io_out2_delay_max); - new_delay -= iocfg->io_out2_delay_max; - scc_mgr_set_oct_out1_delay(write_group, new_delay); + new_delay, seq->iocfg->io_out2_delay_max, + new_delay - seq->iocfg->io_out2_delay_max); + new_delay -= seq->iocfg->io_out2_delay_max; + scc_mgr_set_oct_out1_delay(seq, write_group, new_delay); } - scc_mgr_load_dqs_for_write_group(write_group); + scc_mgr_load_dqs_for_write_group(seq, write_group); } /** - * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks + * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output + * side to all ranks * @write_group: Write group * @delay: Delay value * * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks. */ static void -scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group, +scc_mgr_apply_group_all_out_delay_add_all_ranks(struct socfpga_sdrseq *seq, + const u32 write_group, const u32 delay) { int r; - for (r = 0; r < rwcfg->mem_number_of_ranks; + for (r = 0; r < seq->rwcfg->mem_number_of_ranks; r += NUM_RANKS_PER_SHADOW_REG) { - scc_mgr_apply_group_all_out_delay_add(write_group, delay); + scc_mgr_apply_group_all_out_delay_add(seq, write_group, delay); writel(0, &sdr_scc_mgr->update); } } @@ -744,7 +748,7 @@ scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group, * Optimization used to recover some slots in ddr3 inst_rom could be * applied to other protocols if we wanted to */ -static void set_jump_as_return(void) +static void set_jump_as_return(struct socfpga_sdrseq *seq) { /* * To save space, we replace return with jump to special shared @@ -752,7 +756,7 @@ static void set_jump_as_return(void) * we always jump. */ writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0); - writel(rwcfg->rreturn, &sdr_rw_load_jump_mgr_regs->load_jump_add0); + writel(seq->rwcfg->rreturn, &sdr_rw_load_jump_mgr_regs->load_jump_add0); } /** @@ -761,7 +765,8 @@ static void set_jump_as_return(void) * * Delay for N memory clocks. */ -static void delay_for_n_mem_clocks(const u32 clocks) +static void delay_for_n_mem_clocks(struct socfpga_sdrseq *seq, + const u32 clocks) { u32 afi_clocks; u16 c_loop; @@ -771,7 +776,7 @@ static void delay_for_n_mem_clocks(const u32 clocks) debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks); /* Scale (rounding up) to get afi clocks. */ - afi_clocks = DIV_ROUND_UP(clocks, misccfg->afi_rate_ratio); + afi_clocks = DIV_ROUND_UP(clocks, seq->misccfg->afi_rate_ratio); if (afi_clocks) /* Temporary underflow protection */ afi_clocks--; @@ -807,10 +812,10 @@ static void delay_for_n_mem_clocks(const u32 clocks) writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), &sdr_rw_load_mgr_regs->load_cntr1); - writel(rwcfg->idle_loop1, + writel(seq->rwcfg->idle_loop1, &sdr_rw_load_jump_mgr_regs->load_jump_add1); - writel(rwcfg->idle_loop1, SDR_PHYGRP_RWMGRGRP_ADDRESS | + writel(seq->rwcfg->idle_loop1, SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET); } else { writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), @@ -819,14 +824,14 @@ static void delay_for_n_mem_clocks(const u32 clocks) writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer), &sdr_rw_load_mgr_regs->load_cntr1); - writel(rwcfg->idle_loop2, + writel(seq->rwcfg->idle_loop2, &sdr_rw_load_jump_mgr_regs->load_jump_add0); - writel(rwcfg->idle_loop2, + writel(seq->rwcfg->idle_loop2, &sdr_rw_load_jump_mgr_regs->load_jump_add1); do { - writel(rwcfg->idle_loop2, + writel(seq->rwcfg->idle_loop2, SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET); } while (c_loop-- != 0); @@ -843,7 +848,8 @@ static void delay_for_n_mem_clocks(const u32 clocks) * * Load instruction registers. */ -static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump) +static void rw_mgr_mem_init_load_regs(struct socfpga_sdrseq *seq, + u32 cntr0, u32 cntr1, u32 cntr2, u32 jump) { u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET; @@ -873,58 +879,59 @@ static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump) * * Load user calibration values and optionally precharge the banks. */ -static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2, +static void rw_mgr_mem_load_user(struct socfpga_sdrseq *seq, + const u32 fin1, const u32 fin2, const int precharge) { u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET; u32 r; - for (r = 0; r < rwcfg->mem_number_of_ranks; r++) { + for (r = 0; r < seq->rwcfg->mem_number_of_ranks; r++) { /* set rank */ - set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); + set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_OFF); /* precharge all banks ... */ if (precharge) - writel(rwcfg->precharge_all, grpaddr); + writel(seq->rwcfg->precharge_all, grpaddr); /* * USER Use Mirror-ed commands for odd ranks if address * mirrorring is on */ - if ((rwcfg->mem_address_mirroring >> r) & 0x1) { - set_jump_as_return(); - writel(rwcfg->mrs2_mirr, grpaddr); - delay_for_n_mem_clocks(4); - set_jump_as_return(); - writel(rwcfg->mrs3_mirr, grpaddr); - delay_for_n_mem_clocks(4); - set_jump_as_return(); - writel(rwcfg->mrs1_mirr, grpaddr); - delay_for_n_mem_clocks(4); - set_jump_as_return(); + if ((seq->rwcfg->mem_address_mirroring >> r) & 0x1) { + set_jump_as_return(seq); + writel(seq->rwcfg->mrs2_mirr, grpaddr); + delay_for_n_mem_clocks(seq, 4); + set_jump_as_return(seq); + writel(seq->rwcfg->mrs3_mirr, grpaddr); + delay_for_n_mem_clocks(seq, 4); + set_jump_as_return(seq); + writel(seq->rwcfg->mrs1_mirr, grpaddr); + delay_for_n_mem_clocks(seq, 4); + set_jump_as_return(seq); writel(fin1, grpaddr); } else { - set_jump_as_return(); - writel(rwcfg->mrs2, grpaddr); - delay_for_n_mem_clocks(4); - set_jump_as_return(); - writel(rwcfg->mrs3, grpaddr); - delay_for_n_mem_clocks(4); - set_jump_as_return(); - writel(rwcfg->mrs1, grpaddr); - set_jump_as_return(); + set_jump_as_return(seq); + writel(seq->rwcfg->mrs2, grpaddr); + delay_for_n_mem_clocks(seq, 4); + set_jump_as_return(seq); + writel(seq->rwcfg->mrs3, grpaddr); + delay_for_n_mem_clocks(seq, 4); + set_jump_as_return(seq); + writel(seq->rwcfg->mrs1, grpaddr); + set_jump_as_return(seq); writel(fin2, grpaddr); } if (precharge) continue; - set_jump_as_return(); - writel(rwcfg->zqcl, grpaddr); + set_jump_as_return(seq); + writel(seq->rwcfg->zqcl, grpaddr); /* tZQinit = tDLLK = 512 ck cycles */ - delay_for_n_mem_clocks(512); + delay_for_n_mem_clocks(seq, 512); } } @@ -933,7 +940,7 @@ static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2, * * Initialize RW Manager. */ -static void rw_mgr_mem_initialize(void) +static void rw_mgr_mem_initialize(struct socfpga_sdrseq *seq) { debug("%s:%d\n", __func__, __LINE__); @@ -964,10 +971,10 @@ static void rw_mgr_mem_initialize(void) * One possible solution is n = 0 , a = 256 , b = 106 => a = FF, * b = 6A */ - rw_mgr_mem_init_load_regs(misccfg->tinit_cntr0_val, - misccfg->tinit_cntr1_val, - misccfg->tinit_cntr2_val, - rwcfg->init_reset_0_cke_0); + rw_mgr_mem_init_load_regs(seq, seq->misccfg->tinit_cntr0_val, + seq->misccfg->tinit_cntr1_val, + seq->misccfg->tinit_cntr2_val, + seq->rwcfg->init_reset_0_cke_0); /* Indicate that memory is stable. */ writel(1, &phy_mgr_cfg->reset_mem_stbl); @@ -986,18 +993,18 @@ static void rw_mgr_mem_initialize(void) * One possible solution is n = 2 , a = 131 , b = 256 => a = 83, * b = FF */ - rw_mgr_mem_init_load_regs(misccfg->treset_cntr0_val, - misccfg->treset_cntr1_val, - misccfg->treset_cntr2_val, - rwcfg->init_reset_1_cke_0); + rw_mgr_mem_init_load_regs(seq, seq->misccfg->treset_cntr0_val, + seq->misccfg->treset_cntr1_val, + seq->misccfg->treset_cntr2_val, + seq->rwcfg->init_reset_1_cke_0); /* Bring up clock enable. */ /* tXRP < 250 ck cycles */ - delay_for_n_mem_clocks(250); + delay_for_n_mem_clocks(seq, 250); - rw_mgr_mem_load_user(rwcfg->mrs0_dll_reset_mirr, rwcfg->mrs0_dll_reset, - 0); + rw_mgr_mem_load_user(seq, seq->rwcfg->mrs0_dll_reset_mirr, + seq->rwcfg->mrs0_dll_reset, 0); } /** @@ -1006,9 +1013,10 @@ static void rw_mgr_mem_initialize(void) * At the end of calibration we have to program the user settings in * and hand off the memory to the user. */ -static void rw_mgr_mem_handoff(void) +static void rw_mgr_mem_handoff(struct socfpga_sdrseq *seq) { - rw_mgr_mem_load_user(rwcfg->mrs0_user_mirr, rwcfg->mrs0_user, 1); + rw_mgr_mem_load_user(seq, seq->rwcfg->mrs0_user_mirr, + seq->rwcfg->mrs0_user, 1); /* * Need to wait tMOD (12CK or 15ns) time before issuing other * commands, but we will have plenty of NIOS cycles before actual @@ -1024,12 +1032,12 @@ static void rw_mgr_mem_handoff(void) * Issue write test command. Two variants are provided, one that just tests * a write pattern and another that tests datamask functionality. */ -static void rw_mgr_mem_calibrate_write_test_issue(u32 group, - u32 test_dm) +static void rw_mgr_mem_calibrate_write_test_issue(struct socfpga_sdrseq *seq, + u32 group, u32 test_dm) { const u32 quick_write_mode = (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES) && - misccfg->enable_super_quick_calibration; + seq->misccfg->enable_super_quick_calibration; u32 mcc_instruction; u32 rw_wl_nop_cycles; @@ -1059,7 +1067,7 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group, * one counter left to issue this command in "multiple-group" mode */ - rw_wl_nop_cycles = gbl->rw_wl_nop_cycles; + rw_wl_nop_cycles = seq->gbl.rw_wl_nop_cycles; if (rw_wl_nop_cycles == -1) { /* @@ -1072,16 +1080,16 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group, /* CNTR 3 - Not used */ if (test_dm) { - mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0_wl_1; - writel(rwcfg->lfsr_wr_rd_dm_bank_0_data, + mcc_instruction = seq->rwcfg->lfsr_wr_rd_dm_bank_0_wl_1; + writel(seq->rwcfg->lfsr_wr_rd_dm_bank_0_data, &sdr_rw_load_jump_mgr_regs->load_jump_add2); - writel(rwcfg->lfsr_wr_rd_dm_bank_0_nop, + writel(seq->rwcfg->lfsr_wr_rd_dm_bank_0_nop, &sdr_rw_load_jump_mgr_regs->load_jump_add3); } else { - mcc_instruction = rwcfg->lfsr_wr_rd_bank_0_wl_1; - writel(rwcfg->lfsr_wr_rd_bank_0_data, + mcc_instruction = seq->rwcfg->lfsr_wr_rd_bank_0_wl_1; + writel(seq->rwcfg->lfsr_wr_rd_bank_0_data, &sdr_rw_load_jump_mgr_regs->load_jump_add2); - writel(rwcfg->lfsr_wr_rd_bank_0_nop, + writel(seq->rwcfg->lfsr_wr_rd_bank_0_nop, &sdr_rw_load_jump_mgr_regs->load_jump_add3); } } else if (rw_wl_nop_cycles == 0) { @@ -1094,12 +1102,12 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group, /* CNTR 3 - Not used */ if (test_dm) { - mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0; - writel(rwcfg->lfsr_wr_rd_dm_bank_0_dqs, + mcc_instruction = seq->rwcfg->lfsr_wr_rd_dm_bank_0; + writel(seq->rwcfg->lfsr_wr_rd_dm_bank_0_dqs, &sdr_rw_load_jump_mgr_regs->load_jump_add2); } else { - mcc_instruction = rwcfg->lfsr_wr_rd_bank_0; - writel(rwcfg->lfsr_wr_rd_bank_0_dqs, + mcc_instruction = seq->rwcfg->lfsr_wr_rd_bank_0; + writel(seq->rwcfg->lfsr_wr_rd_bank_0_dqs, &sdr_rw_load_jump_mgr_regs->load_jump_add2); } } else { @@ -1117,12 +1125,12 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group, */ writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3); if (test_dm) { - mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0; - writel(rwcfg->lfsr_wr_rd_dm_bank_0_nop, + mcc_instruction = seq->rwcfg->lfsr_wr_rd_dm_bank_0; + writel(seq->rwcfg->lfsr_wr_rd_dm_bank_0_nop, &sdr_rw_load_jump_mgr_regs->load_jump_add3); } else { - mcc_instruction = rwcfg->lfsr_wr_rd_bank_0; - writel(rwcfg->lfsr_wr_rd_bank_0_nop, + mcc_instruction = seq->rwcfg->lfsr_wr_rd_bank_0; + writel(seq->rwcfg->lfsr_wr_rd_bank_0_nop, &sdr_rw_load_jump_mgr_regs->load_jump_add3); } } @@ -1144,10 +1152,10 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group, writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1); if (test_dm) { - writel(rwcfg->lfsr_wr_rd_dm_bank_0_wait, + writel(seq->rwcfg->lfsr_wr_rd_dm_bank_0_wait, &sdr_rw_load_jump_mgr_regs->load_jump_add1); } else { - writel(rwcfg->lfsr_wr_rd_bank_0_wait, + writel(seq->rwcfg->lfsr_wr_rd_bank_0_wait, &sdr_rw_load_jump_mgr_regs->load_jump_add1); } @@ -1157,7 +1165,8 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group, } /** - * rw_mgr_mem_calibrate_write_test() - Test writes, check for single/multiple pass + * rw_mgr_mem_calibrate_write_test() - Test writes, check for single/multiple + * pass * @rank_bgn: Rank number * @write_group: Write Group * @use_dm: Use DM @@ -1168,36 +1177,38 @@ static void rw_mgr_mem_calibrate_write_test_issue(u32 group, * Test writes, can check for a single bit pass or multiple bit pass. */ static int -rw_mgr_mem_calibrate_write_test(const u32 rank_bgn, const u32 write_group, +rw_mgr_mem_calibrate_write_test(struct socfpga_sdrseq *seq, + const u32 rank_bgn, const u32 write_group, const u32 use_dm, const u32 all_correct, u32 *bit_chk, const u32 all_ranks) { const u32 rank_end = all_ranks ? - rwcfg->mem_number_of_ranks : + seq->rwcfg->mem_number_of_ranks : (rank_bgn + NUM_RANKS_PER_SHADOW_REG); - const u32 shift_ratio = rwcfg->mem_dq_per_write_dqs / - rwcfg->mem_virtual_groups_per_write_dqs; - const u32 correct_mask_vg = param->write_correct_mask_vg; + const u32 shift_ratio = seq->rwcfg->mem_dq_per_write_dqs / + seq->rwcfg->mem_virtual_groups_per_write_dqs; + const u32 correct_mask_vg = seq->param.write_correct_mask_vg; - u32 tmp_bit_chk, base_rw_mgr; + u32 tmp_bit_chk, base_rw_mgr, group; int vg, r; - *bit_chk = param->write_correct_mask; + *bit_chk = seq->param.write_correct_mask; for (r = rank_bgn; r < rank_end; r++) { /* Set rank */ - set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE); + set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_READ_WRITE); tmp_bit_chk = 0; - for (vg = rwcfg->mem_virtual_groups_per_write_dqs - 1; + for (vg = seq->rwcfg->mem_virtual_groups_per_write_dqs - 1; vg >= 0; vg--) { /* Reset the FIFOs to get pointers to known state. */ writel(0, &phy_mgr_cmd->fifo_reset); - rw_mgr_mem_calibrate_write_test_issue( - write_group * - rwcfg->mem_virtual_groups_per_write_dqs + vg, - use_dm); + group = write_group * + seq->rwcfg->mem_virtual_groups_per_write_dqs + + vg; + rw_mgr_mem_calibrate_write_test_issue(seq, group, + use_dm); base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS); tmp_bit_chk <<= shift_ratio; @@ -1207,14 +1218,14 @@ rw_mgr_mem_calibrate_write_test(const u32 rank_bgn, const u32 write_group, *bit_chk &= tmp_bit_chk; } - set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF); + set_rank_and_odt_mask(seq, 0, RW_MGR_ODT_MODE_OFF); if (all_correct) { debug_cond(DLEVEL >= 2, "write_test(%u,%u,ALL) : %u == %u => %i\n", write_group, use_dm, *bit_chk, - param->write_correct_mask, - *bit_chk == param->write_correct_mask); - return *bit_chk == param->write_correct_mask; + seq->param.write_correct_mask, + *bit_chk == seq->param.write_correct_mask); + return *bit_chk == seq->param.write_correct_mask; } else { debug_cond(DLEVEL >= 2, "write_test(%u,%u,ONE) : %u != %i => %i\n", @@ -1233,47 +1244,49 @@ rw_mgr_mem_calibrate_write_test(const u32 rank_bgn, const u32 write_group, * read test to ensure memory works. */ static int -rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group, +rw_mgr_mem_calibrate_read_test_patterns(struct socfpga_sdrseq *seq, + const u32 rank_bgn, const u32 group, const u32 all_ranks) { const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET; const u32 addr_offset = - (group * rwcfg->mem_virtual_groups_per_read_dqs) << 2; + (group * seq->rwcfg->mem_virtual_groups_per_read_dqs) + << 2; const u32 rank_end = all_ranks ? - rwcfg->mem_number_of_ranks : + seq->rwcfg->mem_number_of_ranks : (rank_bgn + NUM_RANKS_PER_SHADOW_REG); - const u32 shift_ratio = rwcfg->mem_dq_per_read_dqs / - rwcfg->mem_virtual_groups_per_read_dqs; - const u32 correct_mask_vg = param->read_correct_mask_vg; + const u32 shift_ratio = seq->rwcfg->mem_dq_per_read_dqs / + seq->rwcfg->mem_virtual_groups_per_read_dqs; + const u32 correct_mask_vg = seq->param.read_correct_mask_vg; u32 tmp_bit_chk, base_rw_mgr, bit_chk; int vg, r; int ret = 0; - bit_chk = param->read_correct_mask; + bit_chk = seq->param.read_correct_mask; for (r = rank_bgn; r < rank_end; r++) { /* Set rank */ - set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE); + set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_READ_WRITE); /* Load up a constant bursts of read commands */ writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0); - writel(rwcfg->guaranteed_read, + writel(seq->rwcfg->guaranteed_read, &sdr_rw_load_jump_mgr_regs->load_jump_add0); writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1); - writel(rwcfg->guaranteed_read_cont, + writel(seq->rwcfg->guaranteed_read_cont, &sdr_rw_load_jump_mgr_regs->load_jump_add1); tmp_bit_chk = 0; - for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1; + for (vg = seq->rwcfg->mem_virtual_groups_per_read_dqs - 1; vg >= 0; vg--) { /* Reset the FIFOs to get pointers to known state. */ writel(0, &phy_mgr_cmd->fifo_reset); writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RESET_READ_DATAPATH_OFFSET); - writel(rwcfg->guaranteed_read, + writel(seq->rwcfg->guaranteed_read, addr + addr_offset + (vg << 2)); base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS); @@ -1284,33 +1297,35 @@ rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group, bit_chk &= tmp_bit_chk; } - writel(rwcfg->clear_dqs_enable, addr + (group << 2)); + writel(seq->rwcfg->clear_dqs_enable, addr + (group << 2)); - set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF); + set_rank_and_odt_mask(seq, 0, RW_MGR_ODT_MODE_OFF); - if (bit_chk != param->read_correct_mask) + if (bit_chk != seq->param.read_correct_mask) ret = -EIO; debug_cond(DLEVEL >= 1, "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n", __func__, __LINE__, group, bit_chk, - param->read_correct_mask, ret); + seq->param.read_correct_mask, ret); return ret; } /** - * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test + * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read + * test * @rank_bgn: Rank number * @all_ranks: Test all ranks * * Load up the patterns we are going to use during a read test. */ -static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn, +static void rw_mgr_mem_calibrate_read_load_patterns(struct socfpga_sdrseq *seq, + const u32 rank_bgn, const int all_ranks) { const u32 rank_end = all_ranks ? - rwcfg->mem_number_of_ranks : + seq->rwcfg->mem_number_of_ranks : (rank_bgn + NUM_RANKS_PER_SHADOW_REG); u32 r; @@ -1318,34 +1333,35 @@ static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn, for (r = rank_bgn; r < rank_end; r++) { /* set rank */ - set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE); + set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_READ_WRITE); /* Load up a constant bursts */ writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0); - writel(rwcfg->guaranteed_write_wait0, + writel(seq->rwcfg->guaranteed_write_wait0, &sdr_rw_load_jump_mgr_regs->load_jump_add0); writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1); - writel(rwcfg->guaranteed_write_wait1, + writel(seq->rwcfg->guaranteed_write_wait1, &sdr_rw_load_jump_mgr_regs->load_jump_add1); writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2); - writel(rwcfg->guaranteed_write_wait2, + writel(seq->rwcfg->guaranteed_write_wait2, &sdr_rw_load_jump_mgr_regs->load_jump_add2); writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3); - writel(rwcfg->guaranteed_write_wait3, + writel(seq->rwcfg->guaranteed_write_wait3, &sdr_rw_load_jump_mgr_regs->load_jump_add3); - writel(rwcfg->guaranteed_write, SDR_PHYGRP_RWMGRGRP_ADDRESS | - RW_MGR_RUN_SINGLE_GROUP_OFFSET); + writel(seq->rwcfg->guaranteed_write, + SDR_PHYGRP_RWMGRGRP_ADDRESS | + RW_MGR_RUN_SINGLE_GROUP_OFFSET); } - set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF); + set_rank_and_odt_mask(seq, 0, RW_MGR_ODT_MODE_OFF); } /** @@ -1363,36 +1379,37 @@ static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn, * checks than the regular read test. */ static int -rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group, +rw_mgr_mem_calibrate_read_test(struct socfpga_sdrseq *seq, + const u32 rank_bgn, const u32 group, const u32 num_tries, const u32 all_correct, u32 *bit_chk, const u32 all_groups, const u32 all_ranks) { - const u32 rank_end = all_ranks ? rwcfg->mem_number_of_ranks : + const u32 rank_end = all_ranks ? seq->rwcfg->mem_number_of_ranks : (rank_bgn + NUM_RANKS_PER_SHADOW_REG); const u32 quick_read_mode = ((STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS) && - misccfg->enable_super_quick_calibration); - u32 correct_mask_vg = param->read_correct_mask_vg; + seq->misccfg->enable_super_quick_calibration); + u32 correct_mask_vg = seq->param.read_correct_mask_vg; u32 tmp_bit_chk; u32 base_rw_mgr; u32 addr; int r, vg, ret; - *bit_chk = param->read_correct_mask; + *bit_chk = seq->param.read_correct_mask; for (r = rank_bgn; r < rank_end; r++) { /* set rank */ - set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE); + set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_READ_WRITE); writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1); - writel(rwcfg->read_b2b_wait1, + writel(seq->rwcfg->read_b2b_wait1, &sdr_rw_load_jump_mgr_regs->load_jump_add1); writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2); - writel(rwcfg->read_b2b_wait2, + writel(seq->rwcfg->read_b2b_wait2, &sdr_rw_load_jump_mgr_regs->load_jump_add2); if (quick_read_mode) @@ -1403,21 +1420,21 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group, else writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0); - writel(rwcfg->read_b2b, + writel(seq->rwcfg->read_b2b, &sdr_rw_load_jump_mgr_regs->load_jump_add0); if (all_groups) - writel(rwcfg->mem_if_read_dqs_width * - rwcfg->mem_virtual_groups_per_read_dqs - 1, + writel(seq->rwcfg->mem_if_read_dqs_width * + seq->rwcfg->mem_virtual_groups_per_read_dqs - 1, &sdr_rw_load_mgr_regs->load_cntr3); else writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3); - writel(rwcfg->read_b2b, + writel(seq->rwcfg->read_b2b, &sdr_rw_load_jump_mgr_regs->load_jump_add3); tmp_bit_chk = 0; - for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1; vg >= 0; - vg--) { + for (vg = seq->rwcfg->mem_virtual_groups_per_read_dqs - 1; + vg >= 0; vg--) { /* Reset the FIFOs to get pointers to known state. */ writel(0, &phy_mgr_cmd->fifo_reset); writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS | @@ -1431,14 +1448,15 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group, RW_MGR_RUN_SINGLE_GROUP_OFFSET; } - writel(rwcfg->read_b2b, addr + + writel(seq->rwcfg->read_b2b, addr + ((group * - rwcfg->mem_virtual_groups_per_read_dqs + + seq->rwcfg->mem_virtual_groups_per_read_dqs + vg) << 2)); base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS); - tmp_bit_chk <<= rwcfg->mem_dq_per_read_dqs / - rwcfg->mem_virtual_groups_per_read_dqs; + tmp_bit_chk <<= + seq->rwcfg->mem_dq_per_read_dqs / + seq->rwcfg->mem_virtual_groups_per_read_dqs; tmp_bit_chk |= correct_mask_vg & ~(base_rw_mgr); } @@ -1446,16 +1464,16 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group, } addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET; - writel(rwcfg->clear_dqs_enable, addr + (group << 2)); + writel(seq->rwcfg->clear_dqs_enable, addr + (group << 2)); - set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF); + set_rank_and_odt_mask(seq, 0, RW_MGR_ODT_MODE_OFF); if (all_correct) { - ret = (*bit_chk == param->read_correct_mask); + ret = (*bit_chk == seq->param.read_correct_mask); debug_cond(DLEVEL >= 2, "%s:%d read_test(%u,ALL,%u) => (%u == %u) => %i\n", __func__, __LINE__, group, all_groups, *bit_chk, - param->read_correct_mask, ret); + seq->param.read_correct_mask, ret); } else { ret = (*bit_chk != 0x00); debug_cond(DLEVEL >= 2, @@ -1477,13 +1495,15 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group, * Perform a READ test across all memory ranks. */ static int -rw_mgr_mem_calibrate_read_test_all_ranks(const u32 grp, const u32 num_tries, +rw_mgr_mem_calibrate_read_test_all_ranks(struct socfpga_sdrseq *seq, + const u32 grp, const u32 num_tries, const u32 all_correct, const u32 all_groups) { u32 bit_chk; - return rw_mgr_mem_calibrate_read_test(0, grp, num_tries, all_correct, - &bit_chk, all_groups, 1); + return rw_mgr_mem_calibrate_read_test(seq, 0, grp, num_tries, + all_correct, &bit_chk, all_groups, + 1); } /** @@ -1503,11 +1523,11 @@ static void rw_mgr_incr_vfifo(const u32 grp) * * Decrease VFIFO value. */ -static void rw_mgr_decr_vfifo(const u32 grp) +static void rw_mgr_decr_vfifo(struct socfpga_sdrseq *seq, const u32 grp) { u32 i; - for (i = 0; i < misccfg->read_valid_fifo_size - 1; i++) + for (i = 0; i < seq->misccfg->read_valid_fifo_size - 1; i++) rw_mgr_incr_vfifo(grp); } @@ -1517,15 +1537,16 @@ static void rw_mgr_decr_vfifo(const u32 grp) * * Push VFIFO until a failing read happens. */ -static int find_vfifo_failing_read(const u32 grp) +static int find_vfifo_failing_read(struct socfpga_sdrseq *seq, + const u32 grp) { u32 v, ret, fail_cnt = 0; - for (v = 0; v < misccfg->read_valid_fifo_size; v++) { + for (v = 0; v < seq->misccfg->read_valid_fifo_size; v++) { debug_cond(DLEVEL >= 2, "%s:%d: vfifo %u\n", __func__, __LINE__, v); - ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, - PASS_ONE_BIT, 0); + ret = rw_mgr_mem_calibrate_read_test_all_ranks(seq, grp, 1, + PASS_ONE_BIT, 0); if (!ret) { fail_cnt++; @@ -1553,21 +1574,22 @@ static int find_vfifo_failing_read(const u32 grp) * * Find working or non-working DQS enable phase setting. */ -static int sdr_find_phase_delay(int working, int delay, const u32 grp, - u32 *work, const u32 work_inc, u32 *pd) +static int sdr_find_phase_delay(struct socfpga_sdrseq *seq, int working, + int delay, const u32 grp, u32 *work, + const u32 work_inc, u32 *pd) { - const u32 max = delay ? iocfg->dqs_en_delay_max : - iocfg->dqs_en_phase_max; + const u32 max = delay ? seq->iocfg->dqs_en_delay_max : + seq->iocfg->dqs_en_phase_max; u32 ret; for (; *pd <= max; (*pd)++) { if (delay) - scc_mgr_set_dqs_en_delay_all_ranks(grp, *pd); + scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, *pd); else - scc_mgr_set_dqs_en_phase_all_ranks(grp, *pd); + scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, *pd); - ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, - PASS_ONE_BIT, 0); + ret = rw_mgr_mem_calibrate_read_test_all_ranks(seq, grp, 1, + PASS_ONE_BIT, 0); if (!working) ret = !ret; @@ -1590,22 +1612,22 @@ static int sdr_find_phase_delay(int working, int delay, const u32 grp, * * Find working or non-working DQS enable phase setting. */ -static int sdr_find_phase(int working, const u32 grp, u32 *work, - u32 *i, u32 *p) +static int sdr_find_phase(struct socfpga_sdrseq *seq, int working, + const u32 grp, u32 *work, u32 *i, u32 *p) { - const u32 end = misccfg->read_valid_fifo_size + (working ? 0 : 1); + const u32 end = seq->misccfg->read_valid_fifo_size + (working ? 0 : 1); int ret; for (; *i < end; (*i)++) { if (working) *p = 0; - ret = sdr_find_phase_delay(working, 0, grp, work, - iocfg->delay_per_opa_tap, p); + ret = sdr_find_phase_delay(seq, working, 0, grp, work, + seq->iocfg->delay_per_opa_tap, p); if (!ret) return 0; - if (*p > iocfg->dqs_en_phase_max) { + if (*p > seq->iocfg->dqs_en_phase_max) { /* Fiddle with FIFO. */ rw_mgr_incr_vfifo(grp); if (!working) @@ -1626,22 +1648,22 @@ static int sdr_find_phase(int working, const u32 grp, u32 *work, * * Find working DQS enable phase setting. */ -static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *d, - u32 *p, u32 *i) +static int sdr_working_phase(struct socfpga_sdrseq *seq, const u32 grp, + u32 *work_bgn, u32 *d, u32 *p, u32 *i) { - const u32 dtaps_per_ptap = iocfg->delay_per_opa_tap / - iocfg->delay_per_dqs_en_dchain_tap; + const u32 dtaps_per_ptap = seq->iocfg->delay_per_opa_tap / + seq->iocfg->delay_per_dqs_en_dchain_tap; int ret; *work_bgn = 0; for (*d = 0; *d <= dtaps_per_ptap; (*d)++) { *i = 0; - scc_mgr_set_dqs_en_delay_all_ranks(grp, *d); - ret = sdr_find_phase(1, grp, work_bgn, i, p); + scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, *d); + ret = sdr_find_phase(seq, 1, grp, work_bgn, i, p); if (!ret) return 0; - *work_bgn += iocfg->delay_per_dqs_en_dchain_tap; + *work_bgn += seq->iocfg->delay_per_dqs_en_dchain_tap; } /* Cannot find working solution */ @@ -1658,43 +1680,44 @@ static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *d, * * Find DQS enable backup phase setting. */ -static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p) +static void sdr_backup_phase(struct socfpga_sdrseq *seq, const u32 grp, + u32 *work_bgn, u32 *p) { u32 tmp_delay, d; int ret; /* Special case code for backing up a phase */ if (*p == 0) { - *p = iocfg->dqs_en_phase_max; - rw_mgr_decr_vfifo(grp); + *p = seq->iocfg->dqs_en_phase_max; + rw_mgr_decr_vfifo(seq, grp); } else { (*p)--; } - tmp_delay = *work_bgn - iocfg->delay_per_opa_tap; - scc_mgr_set_dqs_en_phase_all_ranks(grp, *p); + tmp_delay = *work_bgn - seq->iocfg->delay_per_opa_tap; + scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, *p); - for (d = 0; d <= iocfg->dqs_en_delay_max && tmp_delay < *work_bgn; + for (d = 0; d <= seq->iocfg->dqs_en_delay_max && tmp_delay < *work_bgn; d++) { - scc_mgr_set_dqs_en_delay_all_ranks(grp, d); + scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, d); - ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, - PASS_ONE_BIT, 0); + ret = rw_mgr_mem_calibrate_read_test_all_ranks(seq, grp, 1, + PASS_ONE_BIT, 0); if (ret) { *work_bgn = tmp_delay; break; } - tmp_delay += iocfg->delay_per_dqs_en_dchain_tap; + tmp_delay += seq->iocfg->delay_per_dqs_en_dchain_tap; } /* Restore VFIFO to old state before we decremented it (if needed). */ (*p)++; - if (*p > iocfg->dqs_en_phase_max) { + if (*p > seq->iocfg->dqs_en_phase_max) { *p = 0; rw_mgr_incr_vfifo(grp); } - scc_mgr_set_dqs_en_delay_all_ranks(grp, 0); + scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, 0); } /** @@ -1706,19 +1729,20 @@ static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p) * * Find non-working DQS enable phase setting. */ -static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *p, u32 *i) +static int sdr_nonworking_phase(struct socfpga_sdrseq *seq, + const u32 grp, u32 *work_end, u32 *p, u32 *i) { int ret; (*p)++; - *work_end += iocfg->delay_per_opa_tap; - if (*p > iocfg->dqs_en_phase_max) { + *work_end += seq->iocfg->delay_per_opa_tap; + if (*p > seq->iocfg->dqs_en_phase_max) { /* Fiddle with FIFO. */ *p = 0; rw_mgr_incr_vfifo(grp); } - ret = sdr_find_phase(0, grp, work_end, i, p); + ret = sdr_find_phase(seq, 0, grp, work_end, i, p); if (ret) { /* Cannot see edge of failing read. */ debug_cond(DLEVEL >= 2, "%s:%d: end: failed\n", @@ -1736,7 +1760,8 @@ static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *p, u32 *i) * * Find center of the working DQS enable window. */ -static int sdr_find_window_center(const u32 grp, const u32 work_bgn, +static int sdr_find_window_center(struct socfpga_sdrseq *seq, + const u32 grp, const u32 work_bgn, const u32 work_end) { u32 work_mid; @@ -1748,37 +1773,41 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn, debug_cond(DLEVEL >= 2, "work_bgn=%d work_end=%d work_mid=%d\n", work_bgn, work_end, work_mid); /* Get the middle delay to be less than a VFIFO delay */ - tmp_delay = (iocfg->dqs_en_phase_max + 1) * iocfg->delay_per_opa_tap; + tmp_delay = (seq->iocfg->dqs_en_phase_max + 1) + * seq->iocfg->delay_per_opa_tap; debug_cond(DLEVEL >= 2, "vfifo ptap delay %d\n", tmp_delay); work_mid %= tmp_delay; debug_cond(DLEVEL >= 2, "new work_mid %d\n", work_mid); - tmp_delay = rounddown(work_mid, iocfg->delay_per_opa_tap); - if (tmp_delay > iocfg->dqs_en_phase_max * iocfg->delay_per_opa_tap) - tmp_delay = iocfg->dqs_en_phase_max * iocfg->delay_per_opa_tap; - p = tmp_delay / iocfg->delay_per_opa_tap; + tmp_delay = rounddown(work_mid, seq->iocfg->delay_per_opa_tap); + if (tmp_delay > seq->iocfg->dqs_en_phase_max + * seq->iocfg->delay_per_opa_tap) { + tmp_delay = seq->iocfg->dqs_en_phase_max + * seq->iocfg->delay_per_opa_tap; + } + p = tmp_delay / seq->iocfg->delay_per_opa_tap; debug_cond(DLEVEL >= 2, "new p %d, tmp_delay=%d\n", p, tmp_delay); d = DIV_ROUND_UP(work_mid - tmp_delay, - iocfg->delay_per_dqs_en_dchain_tap); - if (d > iocfg->dqs_en_delay_max) - d = iocfg->dqs_en_delay_max; - tmp_delay += d * iocfg->delay_per_dqs_en_dchain_tap; + seq->iocfg->delay_per_dqs_en_dchain_tap); + if (d > seq->iocfg->dqs_en_delay_max) + d = seq->iocfg->dqs_en_delay_max; + tmp_delay += d * seq->iocfg->delay_per_dqs_en_dchain_tap; debug_cond(DLEVEL >= 2, "new d %d, tmp_delay=%d\n", d, tmp_delay); - scc_mgr_set_dqs_en_phase_all_ranks(grp, p); - scc_mgr_set_dqs_en_delay_all_ranks(grp, d); + scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, p); + scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, d); /* * push vfifo until we can successfully calibrate. We can do this * because the largest possible margin in 1 VFIFO cycle. */ - for (i = 0; i < misccfg->read_valid_fifo_size; i++) { + for (i = 0; i < seq->misccfg->read_valid_fifo_size; i++) { debug_cond(DLEVEL >= 2, "find_dqs_en_phase: center\n"); - if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, + if (rw_mgr_mem_calibrate_read_test_all_ranks(seq, grp, 1, PASS_ONE_BIT, 0)) { debug_cond(DLEVEL >= 2, @@ -1797,12 +1826,15 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn, } /** - * rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() - Find a good DQS enable to use + * rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() - Find a good DQS enable to + * use * @grp: Read/Write Group * * Find a good DQS enable to use. */ -static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) +static int +rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(struct socfpga_sdrseq *seq, + const u32 grp) { u32 d, p, i; u32 dtaps_per_ptap; @@ -1814,19 +1846,19 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER); - scc_mgr_set_dqs_en_delay_all_ranks(grp, 0); - scc_mgr_set_dqs_en_phase_all_ranks(grp, 0); + scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, 0); + scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, 0); /* Step 0: Determine number of delay taps for each phase tap. */ - dtaps_per_ptap = iocfg->delay_per_opa_tap / - iocfg->delay_per_dqs_en_dchain_tap; + dtaps_per_ptap = seq->iocfg->delay_per_opa_tap / + seq->iocfg->delay_per_dqs_en_dchain_tap; /* Step 1: First push vfifo until we get a failing read. */ - find_vfifo_failing_read(grp); + find_vfifo_failing_read(seq, grp); /* Step 2: Find first working phase, increment in ptaps. */ work_bgn = 0; - ret = sdr_working_phase(grp, &work_bgn, &d, &p, &i); + ret = sdr_working_phase(seq, grp, &work_bgn, &d, &p, &i); if (ret) return ret; @@ -1842,13 +1874,13 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) * Step 3a: If we have room, back off by one and * increment in dtaps. */ - sdr_backup_phase(grp, &work_bgn, &p); + sdr_backup_phase(seq, grp, &work_bgn, &p); /* * Step 4a: go forward from working phase to non working * phase, increment in ptaps. */ - ret = sdr_nonworking_phase(grp, &work_end, &p, &i); + ret = sdr_nonworking_phase(seq, grp, &work_end, &p, &i); if (ret) return ret; @@ -1856,14 +1888,14 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) /* Special case code for backing up a phase */ if (p == 0) { - p = iocfg->dqs_en_phase_max; - rw_mgr_decr_vfifo(grp); + p = seq->iocfg->dqs_en_phase_max; + rw_mgr_decr_vfifo(seq, grp); } else { p = p - 1; } - work_end -= iocfg->delay_per_opa_tap; - scc_mgr_set_dqs_en_phase_all_ranks(grp, p); + work_end -= seq->iocfg->delay_per_opa_tap; + scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, p); d = 0; @@ -1872,12 +1904,12 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) } /* The dtap increment to find the failing edge is done here. */ - sdr_find_phase_delay(0, 1, grp, &work_end, - iocfg->delay_per_dqs_en_dchain_tap, &d); + sdr_find_phase_delay(seq, 0, 1, grp, &work_end, + seq->iocfg->delay_per_dqs_en_dchain_tap, &d); /* Go back to working dtap */ if (d != 0) - work_end -= iocfg->delay_per_dqs_en_dchain_tap; + work_end -= seq->iocfg->delay_per_dqs_en_dchain_tap; debug_cond(DLEVEL >= 2, "%s:%d p/d: ptap=%u dtap=%u end=%u\n", @@ -1903,8 +1935,8 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) /* Special case code for backing up a phase */ if (p == 0) { - p = iocfg->dqs_en_phase_max; - rw_mgr_decr_vfifo(grp); + p = seq->iocfg->dqs_en_phase_max; + rw_mgr_decr_vfifo(seq, grp); debug_cond(DLEVEL >= 2, "%s:%d backedup cycle/phase: p=%u\n", __func__, __LINE__, p); } else { @@ -1913,7 +1945,7 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) __func__, __LINE__, p); } - scc_mgr_set_dqs_en_phase_all_ranks(grp, p); + scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, p); /* * Increase dtap until we first see a passing read (in case the @@ -1927,14 +1959,14 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) initial_failing_dtap = d; - found_passing_read = !sdr_find_phase_delay(1, 1, grp, NULL, 0, &d); + found_passing_read = !sdr_find_phase_delay(seq, 1, 1, grp, NULL, 0, &d); if (found_passing_read) { /* Find a failing read. */ debug_cond(DLEVEL >= 2, "%s:%d find failing read\n", __func__, __LINE__); d++; - found_failing_read = !sdr_find_phase_delay(0, 1, grp, NULL, 0, - &d); + found_failing_read = !sdr_find_phase_delay(seq, 0, 1, grp, NULL, + 0, &d); } else { debug_cond(DLEVEL >= 1, "%s:%d failed to calculate dtaps per ptap. Fall back on static value\n", @@ -1944,7 +1976,7 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) /* * The dynamically calculated dtaps_per_ptap is only valid if we * found a passing/failing read. If we didn't, it means d hit the max - * (iocfg->dqs_en_delay_max). Otherwise, dtaps_per_ptap retains its + * (seq->iocfg->dqs_en_delay_max). Otherwise, dtaps_per_ptap retains its * statically calculated value. */ if (found_passing_read && found_failing_read) @@ -1955,7 +1987,7 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) __func__, __LINE__, d, initial_failing_dtap, dtaps_per_ptap); /* Step 6: Find the centre of the window. */ - ret = sdr_find_window_center(grp, work_bgn, work_end); + ret = sdr_find_window_center(seq, grp, work_bgn, work_end); return ret; } @@ -1973,33 +2005,35 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) * * Test if the found edge is valid. */ -static u32 search_stop_check(const int write, const int d, const int rank_bgn, +static u32 search_stop_check(struct socfpga_sdrseq *seq, const int write, + const int d, const int rank_bgn, const u32 write_group, const u32 read_group, u32 *bit_chk, u32 *sticky_bit_chk, const u32 use_read_test) { - const u32 ratio = rwcfg->mem_if_read_dqs_width / - rwcfg->mem_if_write_dqs_width; - const u32 correct_mask = write ? param->write_correct_mask : - param->read_correct_mask; - const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : - rwcfg->mem_dq_per_read_dqs; + const u32 ratio = seq->rwcfg->mem_if_read_dqs_width / + seq->rwcfg->mem_if_write_dqs_width; + const u32 correct_mask = write ? seq->param.write_correct_mask : + seq->param.read_correct_mask; + const u32 per_dqs = write ? seq->rwcfg->mem_dq_per_write_dqs : + seq->rwcfg->mem_dq_per_read_dqs; u32 ret; /* * Stop searching when the read test doesn't pass AND when * we've seen a passing read on every bit. */ if (write) { /* WRITE-ONLY */ - ret = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, - 0, PASS_ONE_BIT, - bit_chk, 0); + ret = !rw_mgr_mem_calibrate_write_test(seq, rank_bgn, + write_group, 0, + PASS_ONE_BIT, bit_chk, + 0); } else if (use_read_test) { /* READ-ONLY */ - ret = !rw_mgr_mem_calibrate_read_test(rank_bgn, read_group, + ret = !rw_mgr_mem_calibrate_read_test(seq, rank_bgn, read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT, bit_chk, 0, 0); } else { /* READ-ONLY */ - rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 0, + rw_mgr_mem_calibrate_write_test(seq, rank_bgn, write_group, 0, PASS_ONE_BIT, bit_chk, 0); *bit_chk = *bit_chk >> (per_dqs * (read_group - (write_group * ratio))); @@ -2028,29 +2062,30 @@ static u32 search_stop_check(const int write, const int d, const int rank_bgn, * * Find left edge of DQ/DQS working phase. */ -static void search_left_edge(const int write, const int rank_bgn, - const u32 write_group, const u32 read_group, const u32 test_bgn, - u32 *sticky_bit_chk, - int *left_edge, int *right_edge, const u32 use_read_test) -{ - const u32 delay_max = write ? iocfg->io_out1_delay_max : - iocfg->io_in_delay_max; - const u32 dqs_max = write ? iocfg->io_out1_delay_max : - iocfg->dqs_in_delay_max; - const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : - rwcfg->mem_dq_per_read_dqs; +static void search_left_edge(struct socfpga_sdrseq *seq, const int write, + const int rank_bgn, const u32 write_group, + const u32 read_group, const u32 test_bgn, + u32 *sticky_bit_chk, int *left_edge, + int *right_edge, const u32 use_read_test) +{ + const u32 delay_max = write ? seq->iocfg->io_out1_delay_max : + seq->iocfg->io_in_delay_max; + const u32 dqs_max = write ? seq->iocfg->io_out1_delay_max : + seq->iocfg->dqs_in_delay_max; + const u32 per_dqs = write ? seq->rwcfg->mem_dq_per_write_dqs : + seq->rwcfg->mem_dq_per_read_dqs; u32 stop, bit_chk; int i, d; for (d = 0; d <= dqs_max; d++) { if (write) - scc_mgr_apply_group_dq_out1_delay(d); + scc_mgr_apply_group_dq_out1_delay(seq, d); else - scc_mgr_apply_group_dq_in_delay(test_bgn, d); + scc_mgr_apply_group_dq_in_delay(seq, test_bgn, d); writel(0, &sdr_scc_mgr->update); - stop = search_stop_check(write, d, rank_bgn, write_group, + stop = search_stop_check(seq, write, d, rank_bgn, write_group, read_group, &bit_chk, sticky_bit_chk, use_read_test); if (stop == 1) @@ -2080,9 +2115,9 @@ static void search_left_edge(const int write, const int rank_bgn, /* Reset DQ delay chains to 0 */ if (write) - scc_mgr_apply_group_dq_out1_delay(0); + scc_mgr_apply_group_dq_out1_delay(seq, 0); else - scc_mgr_apply_group_dq_in_delay(test_bgn, 0); + scc_mgr_apply_group_dq_in_delay(seq, test_bgn, 0); *sticky_bit_chk = 0; for (i = per_dqs - 1; i >= 0; i--) { @@ -2138,31 +2173,33 @@ static void search_left_edge(const int write, const int rank_bgn, * * Find right edge of DQ/DQS working phase. */ -static int search_right_edge(const int write, const int rank_bgn, - const u32 write_group, const u32 read_group, - const int start_dqs, const int start_dqs_en, - u32 *sticky_bit_chk, - int *left_edge, int *right_edge, const u32 use_read_test) -{ - const u32 delay_max = write ? iocfg->io_out1_delay_max : - iocfg->io_in_delay_max; - const u32 dqs_max = write ? iocfg->io_out1_delay_max : - iocfg->dqs_in_delay_max; - const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : - rwcfg->mem_dq_per_read_dqs; +static int search_right_edge(struct socfpga_sdrseq *seq, const int write, + const int rank_bgn, const u32 write_group, + const u32 read_group, const int start_dqs, + const int start_dqs_en, u32 *sticky_bit_chk, + int *left_edge, int *right_edge, + const u32 use_read_test) +{ + const u32 delay_max = write ? seq->iocfg->io_out1_delay_max : + seq->iocfg->io_in_delay_max; + const u32 dqs_max = write ? seq->iocfg->io_out1_delay_max : + seq->iocfg->dqs_in_delay_max; + const u32 per_dqs = write ? seq->rwcfg->mem_dq_per_write_dqs : + seq->rwcfg->mem_dq_per_read_dqs; u32 stop, bit_chk; int i, d; for (d = 0; d <= dqs_max - start_dqs; d++) { if (write) { /* WRITE-ONLY */ - scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, + scc_mgr_apply_group_dqs_io_and_oct_out1(seq, + write_group, d + start_dqs); } else { /* READ-ONLY */ scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs); - if (iocfg->shift_dqs_en_when_shift_dqs) { + if (seq->iocfg->shift_dqs_en_when_shift_dqs) { u32 delay = d + start_dqs_en; - if (delay > iocfg->dqs_en_delay_max) - delay = iocfg->dqs_en_delay_max; + if (delay > seq->iocfg->dqs_en_delay_max) + delay = seq->iocfg->dqs_en_delay_max; scc_mgr_set_dqs_en_delay(read_group, delay); } scc_mgr_load_dqs(read_group); @@ -2170,12 +2207,13 @@ static int search_right_edge(const int write, const int rank_bgn, writel(0, &sdr_scc_mgr->update); - stop = search_stop_check(write, d, rank_bgn, write_group, + stop = search_stop_check(seq, write, d, rank_bgn, write_group, read_group, &bit_chk, sticky_bit_chk, use_read_test); if (stop == 1) { if (write && (d == 0)) { /* WRITE-ONLY */ - for (i = 0; i < rwcfg->mem_dq_per_write_dqs; + for (i = 0; + i < seq->rwcfg->mem_dq_per_write_dqs; i++) { /* * d = 0 failed, but it passed when @@ -2263,11 +2301,12 @@ static int search_right_edge(const int write, const int rank_bgn, * * Find index and value of the middle of the DQ/DQS working phase. */ -static int get_window_mid_index(const int write, int *left_edge, +static int get_window_mid_index(struct socfpga_sdrseq *seq, + const int write, int *left_edge, int *right_edge, int *mid_min) { - const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : - rwcfg->mem_dq_per_read_dqs; + const u32 per_dqs = write ? seq->rwcfg->mem_dq_per_write_dqs : + seq->rwcfg->mem_dq_per_read_dqs; int i, mid, min_index; /* Find middle of window for each DQ bit */ @@ -2310,15 +2349,16 @@ static int get_window_mid_index(const int write, int *left_edge, * * Align the DQ/DQS windows in each group. */ -static void center_dq_windows(const int write, int *left_edge, int *right_edge, +static void center_dq_windows(struct socfpga_sdrseq *seq, + const int write, int *left_edge, int *right_edge, const int mid_min, const int orig_mid_min, const int min_index, const int test_bgn, int *dq_margin, int *dqs_margin) { - const s32 delay_max = write ? iocfg->io_out1_delay_max : - iocfg->io_in_delay_max; - const s32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : - rwcfg->mem_dq_per_read_dqs; + const s32 delay_max = write ? seq->iocfg->io_out1_delay_max : + seq->iocfg->io_in_delay_max; + const s32 per_dqs = write ? seq->rwcfg->mem_dq_per_write_dqs : + seq->rwcfg->mem_dq_per_read_dqs; const s32 delay_off = write ? SCC_MGR_IO_OUT1_DELAY_OFFSET : SCC_MGR_IO_IN_DELAY_OFFSET; const s32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | delay_off; @@ -2385,9 +2425,12 @@ static void center_dq_windows(const int write, int *left_edge, int *right_edge, * * Per-bit deskew DQ and centering. */ -static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn, - const u32 rw_group, const u32 test_bgn, - const int use_read_test, const int update_fom) +static int rw_mgr_mem_calibrate_vfifo_center(struct socfpga_sdrseq *seq, + const u32 rank_bgn, + const u32 rw_group, + const u32 test_bgn, + const int use_read_test, + const int update_fom) { const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS + SCC_MGR_DQS_IN_DELAY_OFFSET + @@ -2397,36 +2440,36 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn, * signed numbers. */ u32 sticky_bit_chk; - int32_t left_edge[rwcfg->mem_dq_per_read_dqs]; - int32_t right_edge[rwcfg->mem_dq_per_read_dqs]; - int32_t orig_mid_min, mid_min; - int32_t new_dqs, start_dqs, start_dqs_en = 0, final_dqs_en; - int32_t dq_margin, dqs_margin; + s32 left_edge[seq->rwcfg->mem_dq_per_read_dqs]; + s32 right_edge[seq->rwcfg->mem_dq_per_read_dqs]; + s32 orig_mid_min, mid_min; + s32 new_dqs, start_dqs, start_dqs_en = 0, final_dqs_en; + s32 dq_margin, dqs_margin; int i, min_index; int ret; debug("%s:%d: %u %u", __func__, __LINE__, rw_group, test_bgn); start_dqs = readl(addr); - if (iocfg->shift_dqs_en_when_shift_dqs) - start_dqs_en = readl(addr - iocfg->dqs_en_delay_offset); + if (seq->iocfg->shift_dqs_en_when_shift_dqs) + start_dqs_en = readl(addr - seq->iocfg->dqs_en_delay_offset); /* set the left and right edge of each bit to an illegal value */ - /* use (iocfg->io_in_delay_max + 1) as an illegal value */ + /* use (seq->iocfg->io_in_delay_max + 1) as an illegal value */ sticky_bit_chk = 0; - for (i = 0; i < rwcfg->mem_dq_per_read_dqs; i++) { - left_edge[i] = iocfg->io_in_delay_max + 1; - right_edge[i] = iocfg->io_in_delay_max + 1; + for (i = 0; i < seq->rwcfg->mem_dq_per_read_dqs; i++) { + left_edge[i] = seq->iocfg->io_in_delay_max + 1; + right_edge[i] = seq->iocfg->io_in_delay_max + 1; } /* Search for the left edge of the window for each bit */ - search_left_edge(0, rank_bgn, rw_group, rw_group, test_bgn, + search_left_edge(seq, 0, rank_bgn, rw_group, rw_group, test_bgn, &sticky_bit_chk, left_edge, right_edge, use_read_test); /* Search for the right edge of the window for each bit */ - ret = search_right_edge(0, rank_bgn, rw_group, rw_group, + ret = search_right_edge(seq, 0, rank_bgn, rw_group, rw_group, start_dqs, start_dqs_en, &sticky_bit_chk, left_edge, right_edge, use_read_test); @@ -2437,7 +2480,7 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn, * dqs/ck relationships. */ scc_mgr_set_dqs_bus_in_delay(rw_group, start_dqs); - if (iocfg->shift_dqs_en_when_shift_dqs) + if (seq->iocfg->shift_dqs_en_when_shift_dqs) scc_mgr_set_dqs_en_delay(rw_group, start_dqs_en); scc_mgr_load_dqs(rw_group); @@ -2447,26 +2490,27 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn, "%s:%d vfifo_center: failed to find edge [%u]: %d %d", __func__, __LINE__, i, left_edge[i], right_edge[i]); if (use_read_test) { - set_failing_group_stage(rw_group * - rwcfg->mem_dq_per_read_dqs + i, + set_failing_group_stage(seq, rw_group * + seq->rwcfg->mem_dq_per_read_dqs + i, CAL_STAGE_VFIFO, CAL_SUBSTAGE_VFIFO_CENTER); } else { - set_failing_group_stage(rw_group * - rwcfg->mem_dq_per_read_dqs + i, + set_failing_group_stage(seq, rw_group * + seq->rwcfg->mem_dq_per_read_dqs + i, CAL_STAGE_VFIFO_AFTER_WRITES, CAL_SUBSTAGE_VFIFO_CENTER); } return -EIO; } - min_index = get_window_mid_index(0, left_edge, right_edge, &mid_min); + min_index = get_window_mid_index(seq, 0, left_edge, right_edge, + &mid_min); /* Determine the amount we can change DQS (which is -mid_min) */ orig_mid_min = mid_min; new_dqs = start_dqs - mid_min; - if (new_dqs > iocfg->dqs_in_delay_max) - new_dqs = iocfg->dqs_in_delay_max; + if (new_dqs > seq->iocfg->dqs_in_delay_max) + new_dqs = seq->iocfg->dqs_in_delay_max; else if (new_dqs < 0) new_dqs = 0; @@ -2474,10 +2518,10 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn, debug_cond(DLEVEL >= 1, "vfifo_center: new mid_min=%d new_dqs=%d\n", mid_min, new_dqs); - if (iocfg->shift_dqs_en_when_shift_dqs) { - if (start_dqs_en - mid_min > iocfg->dqs_en_delay_max) + if (seq->iocfg->shift_dqs_en_when_shift_dqs) { + if (start_dqs_en - mid_min > seq->iocfg->dqs_en_delay_max) mid_min += start_dqs_en - mid_min - - iocfg->dqs_en_delay_max; + seq->iocfg->dqs_en_delay_max; else if (start_dqs_en - mid_min < 0) mid_min += start_dqs_en - mid_min; } @@ -2486,15 +2530,15 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn, debug_cond(DLEVEL >= 1, "vfifo_center: start_dqs=%d start_dqs_en=%d new_dqs=%d mid_min=%d\n", start_dqs, - iocfg->shift_dqs_en_when_shift_dqs ? start_dqs_en : -1, + seq->iocfg->shift_dqs_en_when_shift_dqs ? start_dqs_en : -1, new_dqs, mid_min); /* Add delay to bring centre of all DQ windows to the same "level". */ - center_dq_windows(0, left_edge, right_edge, mid_min, orig_mid_min, + center_dq_windows(seq, 0, left_edge, right_edge, mid_min, orig_mid_min, min_index, test_bgn, &dq_margin, &dqs_margin); /* Move DQS-en */ - if (iocfg->shift_dqs_en_when_shift_dqs) { + if (seq->iocfg->shift_dqs_en_when_shift_dqs) { final_dqs_en = start_dqs_en - mid_min; scc_mgr_set_dqs_en_delay(rw_group, final_dqs_en); scc_mgr_load_dqs(rw_group); @@ -2520,7 +2564,8 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn, } /** - * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device + * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the + * device * @rw_group: Read/Write Group * @phase: DQ/DQS phase * @@ -2528,13 +2573,14 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn, * device, the sequencer uses a guaranteed write mechanism to write data into * the memory device. */ -static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group, +static int rw_mgr_mem_calibrate_guaranteed_write(struct socfpga_sdrseq *seq, + const u32 rw_group, const u32 phase) { int ret; /* Set a particular DQ/DQS phase. */ - scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase); + scc_mgr_set_dqdqs_output_phase_all_ranks(seq, rw_group, phase); debug_cond(DLEVEL >= 1, "%s:%d guaranteed write: g=%u p=%u\n", __func__, __LINE__, rw_group, phase); @@ -2544,16 +2590,16 @@ static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group, * Load up the patterns used by read calibration using the * current DQDQS phase. */ - rw_mgr_mem_calibrate_read_load_patterns(0, 1); + rw_mgr_mem_calibrate_read_load_patterns(seq, 0, 1); - if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ) + if (seq->gbl.phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ) return 0; /* * Altera EMI_RM 2015.05.04 :: Figure 1-26 * Back-to-Back reads of the patterns used for calibration. */ - ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1); + ret = rw_mgr_mem_calibrate_read_test_patterns(seq, 0, rw_group, 1); if (ret) debug_cond(DLEVEL >= 1, "%s:%d Guaranteed read test failed: g=%u p=%u\n", @@ -2569,8 +2615,10 @@ static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group, * DQS enable calibration ensures reliable capture of the DQ signal without * glitches on the DQS line. */ -static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group, - const u32 test_bgn) +static int +rw_mgr_mem_calibrate_dqs_enable_calibration(struct socfpga_sdrseq *seq, + const u32 rw_group, + const u32 test_bgn) { /* * Altera EMI_RM 2015.05.04 :: Figure 1-27 @@ -2578,18 +2626,18 @@ static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group, */ /* We start at zero, so have one less dq to devide among */ - const u32 delay_step = iocfg->io_in_delay_max / - (rwcfg->mem_dq_per_read_dqs - 1); + const u32 delay_step = seq->iocfg->io_in_delay_max / + (seq->rwcfg->mem_dq_per_read_dqs - 1); int ret; u32 i, p, d, r; debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn); /* Try different dq_in_delays since the DQ path is shorter than DQS. */ - for (r = 0; r < rwcfg->mem_number_of_ranks; + for (r = 0; r < seq->rwcfg->mem_number_of_ranks; r += NUM_RANKS_PER_SHADOW_REG) { for (i = 0, p = test_bgn, d = 0; - i < rwcfg->mem_dq_per_read_dqs; + i < seq->rwcfg->mem_dq_per_read_dqs; i++, p++, d += delay_step) { debug_cond(DLEVEL >= 1, "%s:%d: g=%u r=%u i=%u p=%u d=%u\n", @@ -2606,15 +2654,15 @@ static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group, * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different * dq_in_delay values */ - ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group); + ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(seq, rw_group); debug_cond(DLEVEL >= 1, "%s:%d: g=%u found=%u; Reseting delay chain to zero\n", __func__, __LINE__, rw_group, !ret); - for (r = 0; r < rwcfg->mem_number_of_ranks; + for (r = 0; r < seq->rwcfg->mem_number_of_ranks; r += NUM_RANKS_PER_SHADOW_REG) { - scc_mgr_apply_group_dq_in_delay(test_bgn, 0); + scc_mgr_apply_group_dq_in_delay(seq, test_bgn, 0); writel(0, &sdr_scc_mgr->update); } @@ -2632,7 +2680,8 @@ static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group, * within a group. */ static int -rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn, +rw_mgr_mem_calibrate_dq_dqs_centering(struct socfpga_sdrseq *seq, + const u32 rw_group, const u32 test_bgn, const int use_read_test, const int update_fom) @@ -2646,9 +2695,9 @@ rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn, */ grp_calibrated = 1; for (rank_bgn = 0, sr = 0; - rank_bgn < rwcfg->mem_number_of_ranks; + rank_bgn < seq->rwcfg->mem_number_of_ranks; rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) { - ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group, + ret = rw_mgr_mem_calibrate_vfifo_center(seq, rank_bgn, rw_group, test_bgn, use_read_test, update_fom); @@ -2679,7 +2728,8 @@ rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn, * - DQS input phase and DQS input delay (DQ/DQS Centering) * - we also do a per-bit deskew on the DQ lines. */ -static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn) +static int rw_mgr_mem_calibrate_vfifo(struct socfpga_sdrseq *seq, + const u32 rw_group, const u32 test_bgn) { u32 p, d; u32 dtaps_per_ptap; @@ -2697,8 +2747,9 @@ static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn) failed_substage = CAL_SUBSTAGE_GUARANTEED_READ; /* USER Determine number of delay taps for each phase tap. */ - dtaps_per_ptap = DIV_ROUND_UP(iocfg->delay_per_opa_tap, - iocfg->delay_per_dqs_en_dchain_tap) - 1; + dtaps_per_ptap = DIV_ROUND_UP(seq->iocfg->delay_per_opa_tap, + seq->iocfg->delay_per_dqs_en_dchain_tap) + - 1; for (d = 0; d <= dtaps_per_ptap; d += 2) { /* @@ -2708,18 +2759,22 @@ static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn) * output side yet. */ if (d > 0) { - scc_mgr_apply_group_all_out_delay_add_all_ranks( - rw_group, d); + scc_mgr_apply_group_all_out_delay_add_all_ranks(seq, + rw_group, + d); } - for (p = 0; p <= iocfg->dqdqs_out_phase_max; p++) { + for (p = 0; p <= seq->iocfg->dqdqs_out_phase_max; p++) { /* 1) Guaranteed Write */ - ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p); + ret = rw_mgr_mem_calibrate_guaranteed_write(seq, + rw_group, + p); if (ret) break; /* 2) DQS Enable Calibration */ - ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group, + ret = rw_mgr_mem_calibrate_dqs_enable_calibration(seq, + rw_group, test_bgn); if (ret) { failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE; @@ -2731,8 +2786,10 @@ static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn) * If doing read after write calibration, do not update * FOM now. Do it then. */ - ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group, - test_bgn, 1, 0); + ret = rw_mgr_mem_calibrate_dq_dqs_centering(seq, + rw_group, + test_bgn, + 1, 0); if (ret) { failed_substage = CAL_SUBSTAGE_VFIFO_CENTER; continue; @@ -2744,7 +2801,8 @@ static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn) } /* Calibration Stage 1 failed. */ - set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage); + set_failing_group_stage(seq, rw_group, CAL_STAGE_VFIFO, + failed_substage); return 0; /* Calibration Stage 1 completed OK. */ @@ -2755,7 +2813,7 @@ cal_done_ok: * first case). */ if (d > 2) - scc_mgr_zero_group(rw_group, 1); + scc_mgr_zero_group(seq, rw_group, 1); return 1; } @@ -2770,7 +2828,8 @@ cal_done_ok: * This function implements UniPHY calibration Stage 3, as explained in * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages". */ -static int rw_mgr_mem_calibrate_vfifo_end(const u32 rw_group, +static int rw_mgr_mem_calibrate_vfifo_end(struct socfpga_sdrseq *seq, + const u32 rw_group, const u32 test_bgn) { int ret; @@ -2782,9 +2841,10 @@ static int rw_mgr_mem_calibrate_vfifo_end(const u32 rw_group, reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES); reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER); - ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group, test_bgn, 0, 1); + ret = rw_mgr_mem_calibrate_dq_dqs_centering(seq, rw_group, test_bgn, 0, + 1); if (ret) - set_failing_group_stage(rw_group, + set_failing_group_stage(seq, rw_group, CAL_STAGE_VFIFO_AFTER_WRITES, CAL_SUBSTAGE_VFIFO_CENTER); return ret; @@ -2799,7 +2859,7 @@ static int rw_mgr_mem_calibrate_vfifo_end(const u32 rw_group, * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages". * Calibrate LFIFO to find smallest read latency. */ -static u32 rw_mgr_mem_calibrate_lfifo(void) +static u32 rw_mgr_mem_calibrate_lfifo(struct socfpga_sdrseq *seq) { int found_one = 0; @@ -2810,14 +2870,15 @@ static u32 rw_mgr_mem_calibrate_lfifo(void) reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY); /* Load up the patterns used by read calibration for all ranks */ - rw_mgr_mem_calibrate_read_load_patterns(0, 1); + rw_mgr_mem_calibrate_read_load_patterns(seq, 0, 1); do { - writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat); + writel(seq->gbl.curr_read_lat, &phy_mgr_cfg->phy_rlat); debug_cond(DLEVEL >= 2, "%s:%d lfifo: read_lat=%u", - __func__, __LINE__, gbl->curr_read_lat); + __func__, __LINE__, seq->gbl.curr_read_lat); - if (!rw_mgr_mem_calibrate_read_test_all_ranks(0, NUM_READ_TESTS, + if (!rw_mgr_mem_calibrate_read_test_all_ranks(seq, 0, + NUM_READ_TESTS, PASS_ALL_BITS, 1)) break; @@ -2826,26 +2887,26 @@ static u32 rw_mgr_mem_calibrate_lfifo(void) * Reduce read latency and see if things are * working correctly. */ - gbl->curr_read_lat--; - } while (gbl->curr_read_lat > 0); + seq->gbl.curr_read_lat--; + } while (seq->gbl.curr_read_lat > 0); /* Reset the fifos to get pointers to known state. */ writel(0, &phy_mgr_cmd->fifo_reset); if (found_one) { /* Add a fudge factor to the read latency that was determined */ - gbl->curr_read_lat += 2; - writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat); + seq->gbl.curr_read_lat += 2; + writel(seq->gbl.curr_read_lat, &phy_mgr_cfg->phy_rlat); debug_cond(DLEVEL >= 2, "%s:%d lfifo: success: using read_lat=%u\n", - __func__, __LINE__, gbl->curr_read_lat); + __func__, __LINE__, seq->gbl.curr_read_lat); } else { - set_failing_group_stage(0xff, CAL_STAGE_LFIFO, + set_failing_group_stage(seq, 0xff, CAL_STAGE_LFIFO, CAL_SUBSTAGE_READ_LATENCY); debug_cond(DLEVEL >= 2, "%s:%d lfifo: failed at initial read_lat=%u\n", - __func__, __LINE__, gbl->curr_read_lat); + __func__, __LINE__, seq->gbl.curr_read_lat); } return found_one; @@ -2853,7 +2914,8 @@ static u32 rw_mgr_mem_calibrate_lfifo(void) /** * search_window() - Search for the/part of the window with DM/DQS shift - * @search_dm: If 1, search for the DM shift, if 0, search for DQS shift + * @search_dm: If 1, search for the DM shift, if 0, search for DQS + * shift * @rank_bgn: Rank number * @write_group: Write Group * @bgn_curr: Current window begin @@ -2865,20 +2927,21 @@ static u32 rw_mgr_mem_calibrate_lfifo(void) * * Search for the/part of the window with DM/DQS shift. */ -static void search_window(const int search_dm, - const u32 rank_bgn, const u32 write_group, - int *bgn_curr, int *end_curr, int *bgn_best, - int *end_best, int *win_best, int new_dqs) +static void search_window(struct socfpga_sdrseq *seq, + const int search_dm, const u32 rank_bgn, + const u32 write_group, int *bgn_curr, int *end_curr, + int *bgn_best, int *end_best, int *win_best, + int new_dqs) { u32 bit_chk; - const int max = iocfg->io_out1_delay_max - new_dqs; + const int max = seq->iocfg->io_out1_delay_max - new_dqs; int d, di; /* Search for the/part of the window with DM/DQS shift. */ for (di = max; di >= 0; di -= DELTA_D) { if (search_dm) { d = di; - scc_mgr_apply_group_dm_out1_delay(d); + scc_mgr_apply_group_dm_out1_delay(seq, d); } else { /* For DQS, we go from 0...max */ d = max - di; @@ -2886,14 +2949,15 @@ static void search_window(const int search_dm, * Note: This only shifts DQS, so are we limiting * ourselves to width of DQ unnecessarily. */ - scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, + scc_mgr_apply_group_dqs_io_and_oct_out1(seq, + write_group, d + new_dqs); } writel(0, &sdr_scc_mgr->update); - if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1, - PASS_ALL_BITS, &bit_chk, + if (rw_mgr_mem_calibrate_write_test(seq, rank_bgn, write_group, + 1, PASS_ALL_BITS, &bit_chk, 0)) { /* Set current end of the window. */ *end_curr = search_dm ? -d : d; @@ -2902,7 +2966,7 @@ static void search_window(const int search_dm, * If a starting edge of our window has not been seen * this is our current start of the DM window. */ - if (*bgn_curr == iocfg->io_out1_delay_max + 1) + if (*bgn_curr == seq->iocfg->io_out1_delay_max + 1) *bgn_curr = search_dm ? -d : d; /* @@ -2916,8 +2980,8 @@ static void search_window(const int search_dm, } } else { /* We just saw a failing test. Reset temp edge. */ - *bgn_curr = iocfg->io_out1_delay_max + 1; - *end_curr = iocfg->io_out1_delay_max + 1; + *bgn_curr = seq->iocfg->io_out1_delay_max + 1; + *end_curr = seq->iocfg->io_out1_delay_max + 1; /* Early exit is only applicable to DQS. */ if (search_dm) @@ -2928,7 +2992,8 @@ static void search_window(const int search_dm, * chain space is less than already seen largest * window we can exit. */ - if (*win_best - 1 > iocfg->io_out1_delay_max - new_dqs - d) + if (*win_best - 1 > seq->iocfg->io_out1_delay_max + - new_dqs - d) break; } } @@ -2944,22 +3009,23 @@ static void search_window(const int search_dm, * certain windows. */ static int -rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group, +rw_mgr_mem_calibrate_writes_center(struct socfpga_sdrseq *seq, + const u32 rank_bgn, const u32 write_group, const u32 test_bgn) { int i; u32 sticky_bit_chk; u32 min_index; - int left_edge[rwcfg->mem_dq_per_write_dqs]; - int right_edge[rwcfg->mem_dq_per_write_dqs]; + int left_edge[seq->rwcfg->mem_dq_per_write_dqs]; + int right_edge[seq->rwcfg->mem_dq_per_write_dqs]; int mid; int mid_min, orig_mid_min; int new_dqs, start_dqs; int dq_margin, dqs_margin, dm_margin; - int bgn_curr = iocfg->io_out1_delay_max + 1; - int end_curr = iocfg->io_out1_delay_max + 1; - int bgn_best = iocfg->io_out1_delay_max + 1; - int end_best = iocfg->io_out1_delay_max + 1; + int bgn_curr = seq->iocfg->io_out1_delay_max + 1; + int end_curr = seq->iocfg->io_out1_delay_max + 1; + int bgn_best = seq->iocfg->io_out1_delay_max + 1; + int end_best = seq->iocfg->io_out1_delay_max + 1; int win_best = 0; int ret; @@ -2970,37 +3036,39 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group, start_dqs = readl((SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET) + - (rwcfg->mem_dq_per_write_dqs << 2)); + (seq->rwcfg->mem_dq_per_write_dqs << 2)); /* Per-bit deskew. */ /* * Set the left and right edge of each bit to an illegal value. - * Use (iocfg->io_out1_delay_max + 1) as an illegal value. + * Use (seq->iocfg->io_out1_delay_max + 1) as an illegal value. */ sticky_bit_chk = 0; - for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) { - left_edge[i] = iocfg->io_out1_delay_max + 1; - right_edge[i] = iocfg->io_out1_delay_max + 1; + for (i = 0; i < seq->rwcfg->mem_dq_per_write_dqs; i++) { + left_edge[i] = seq->iocfg->io_out1_delay_max + 1; + right_edge[i] = seq->iocfg->io_out1_delay_max + 1; } /* Search for the left edge of the window for each bit. */ - search_left_edge(1, rank_bgn, write_group, 0, test_bgn, + search_left_edge(seq, 1, rank_bgn, write_group, 0, test_bgn, &sticky_bit_chk, left_edge, right_edge, 0); /* Search for the right edge of the window for each bit. */ - ret = search_right_edge(1, rank_bgn, write_group, 0, + ret = search_right_edge(seq, 1, rank_bgn, write_group, 0, start_dqs, 0, &sticky_bit_chk, left_edge, right_edge, 0); if (ret) { - set_failing_group_stage(test_bgn + ret - 1, CAL_STAGE_WRITES, + set_failing_group_stage(seq, test_bgn + ret - 1, + CAL_STAGE_WRITES, CAL_SUBSTAGE_WRITES_CENTER); return -EINVAL; } - min_index = get_window_mid_index(1, left_edge, right_edge, &mid_min); + min_index = get_window_mid_index(seq, 1, left_edge, right_edge, + &mid_min); /* Determine the amount we can change DQS (which is -mid_min). */ orig_mid_min = mid_min; @@ -3011,11 +3079,11 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group, __func__, __LINE__, start_dqs, new_dqs, mid_min); /* Add delay to bring centre of all DQ windows to the same "level". */ - center_dq_windows(1, left_edge, right_edge, mid_min, orig_mid_min, + center_dq_windows(seq, 1, left_edge, right_edge, mid_min, orig_mid_min, min_index, 0, &dq_margin, &dqs_margin); /* Move DQS */ - scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs); + scc_mgr_apply_group_dqs_io_and_oct_out1(seq, write_group, new_dqs); writel(0, &sdr_scc_mgr->update); /* Centre DM */ @@ -3023,17 +3091,17 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group, /* * Set the left and right edge of each bit to an illegal value. - * Use (iocfg->io_out1_delay_max + 1) as an illegal value. + * Use (seq->iocfg->io_out1_delay_max + 1) as an illegal value. */ - left_edge[0] = iocfg->io_out1_delay_max + 1; - right_edge[0] = iocfg->io_out1_delay_max + 1; + left_edge[0] = seq->iocfg->io_out1_delay_max + 1; + right_edge[0] = seq->iocfg->io_out1_delay_max + 1; /* Search for the/part of the window with DM shift. */ - search_window(1, rank_bgn, write_group, &bgn_curr, &end_curr, + search_window(seq, 1, rank_bgn, write_group, &bgn_curr, &end_curr, &bgn_best, &end_best, &win_best, 0); /* Reset DM delay chains to 0. */ - scc_mgr_apply_group_dm_out1_delay(0); + scc_mgr_apply_group_dm_out1_delay(seq, 0); /* * Check to see if the current window nudges up aganist 0 delay. @@ -3041,12 +3109,12 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group, * search begins as a new search. */ if (end_curr != 0) { - bgn_curr = iocfg->io_out1_delay_max + 1; - end_curr = iocfg->io_out1_delay_max + 1; + bgn_curr = seq->iocfg->io_out1_delay_max + 1; + end_curr = seq->iocfg->io_out1_delay_max + 1; } /* Search for the/part of the window with DQS shifts. */ - search_window(0, rank_bgn, write_group, &bgn_curr, &end_curr, + search_window(seq, 0, rank_bgn, write_group, &bgn_curr, &end_curr, &bgn_best, &end_best, &win_best, new_dqs); /* Assign left and right edge for cal and reporting. */ @@ -3057,7 +3125,7 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group, __func__, __LINE__, left_edge[0], right_edge[0]); /* Move DQS (back to orig). */ - scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs); + scc_mgr_apply_group_dqs_io_and_oct_out1(seq, write_group, new_dqs); /* Move DM */ @@ -3074,7 +3142,7 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group, else dm_margin = left_edge[0] - mid; - scc_mgr_apply_group_dm_out1_delay(mid); + scc_mgr_apply_group_dm_out1_delay(seq, mid); writel(0, &sdr_scc_mgr->update); debug_cond(DLEVEL >= 2, @@ -3082,7 +3150,7 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group, __func__, __LINE__, left_edge[0], right_edge[0], mid, dm_margin); /* Export values. */ - gbl->fom_out += dq_margin + dqs_margin; + seq->gbl.fom_out += dq_margin + dqs_margin; debug_cond(DLEVEL >= 2, "%s:%d write_center: dq_margin=%d dqs_margin=%d dm_margin=%d\n", @@ -3111,7 +3179,8 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group, * This function implements UniPHY calibration Stage 2, as explained in * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages". */ -static int rw_mgr_mem_calibrate_writes(const u32 rank_bgn, const u32 group, +static int rw_mgr_mem_calibrate_writes(struct socfpga_sdrseq *seq, + const u32 rank_bgn, const u32 group, const u32 test_bgn) { int ret; @@ -3123,9 +3192,10 @@ static int rw_mgr_mem_calibrate_writes(const u32 rank_bgn, const u32 group, reg_file_set_stage(CAL_STAGE_WRITES); reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER); - ret = rw_mgr_mem_calibrate_writes_center(rank_bgn, group, test_bgn); + ret = rw_mgr_mem_calibrate_writes_center(seq, rank_bgn, group, + test_bgn); if (ret) - set_failing_group_stage(group, CAL_STAGE_WRITES, + set_failing_group_stage(seq, group, CAL_STAGE_WRITES, CAL_SUBSTAGE_WRITES_CENTER); return ret; @@ -3136,29 +3206,30 @@ static int rw_mgr_mem_calibrate_writes(const u32 rank_bgn, const u32 group, * * Precharge all banks and activate row 0 in bank "000..." and bank "111...". */ -static void mem_precharge_and_activate(void) +static void mem_precharge_and_activate(struct socfpga_sdrseq *seq) { int r; - for (r = 0; r < rwcfg->mem_number_of_ranks; r++) { + for (r = 0; r < seq->rwcfg->mem_number_of_ranks; r++) { /* Set rank. */ - set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF); + set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_OFF); /* Precharge all banks. */ - writel(rwcfg->precharge_all, SDR_PHYGRP_RWMGRGRP_ADDRESS | + writel(seq->rwcfg->precharge_all, SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET); writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0); - writel(rwcfg->activate_0_and_1_wait1, + writel(seq->rwcfg->activate_0_and_1_wait1, &sdr_rw_load_jump_mgr_regs->load_jump_add0); writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1); - writel(rwcfg->activate_0_and_1_wait2, + writel(seq->rwcfg->activate_0_and_1_wait2, &sdr_rw_load_jump_mgr_regs->load_jump_add1); /* Activate rows. */ - writel(rwcfg->activate_0_and_1, SDR_PHYGRP_RWMGRGRP_ADDRESS | - RW_MGR_RUN_SINGLE_GROUP_OFFSET); + writel(seq->rwcfg->activate_0_and_1, + SDR_PHYGRP_RWMGRGRP_ADDRESS | + RW_MGR_RUN_SINGLE_GROUP_OFFSET); } } @@ -3167,14 +3238,15 @@ static void mem_precharge_and_activate(void) * * Configure memory RLAT and WLAT parameters. */ -static void mem_init_latency(void) +static void mem_init_latency(struct socfpga_sdrseq *seq) { /* * For AV/CV, LFIFO is hardened and always runs at full rate * so max latency in AFI clocks, used here, is correspondingly * smaller. */ - const u32 max_latency = (1 << misccfg->max_latency_count_width) - 1; + const u32 max_latency = (1 << seq->misccfg->max_latency_count_width) + - 1; u32 rlat, wlat; debug("%s:%d\n", __func__, __LINE__); @@ -3186,17 +3258,17 @@ static void mem_init_latency(void) wlat = readl(&data_mgr->t_wl_add); wlat += readl(&data_mgr->mem_t_add); - gbl->rw_wl_nop_cycles = wlat - 1; + seq->gbl.rw_wl_nop_cycles = wlat - 1; /* Read in readl latency. */ rlat = readl(&data_mgr->t_rl_add); /* Set a pretty high read latency initially. */ - gbl->curr_read_lat = rlat + 16; - if (gbl->curr_read_lat > max_latency) - gbl->curr_read_lat = max_latency; + seq->gbl.curr_read_lat = rlat + 16; + if (seq->gbl.curr_read_lat > max_latency) + seq->gbl.curr_read_lat = max_latency; - writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat); + writel(seq->gbl.curr_read_lat, &phy_mgr_cfg->phy_rlat); /* Advertise write latency. */ writel(wlat, &phy_mgr_cfg->afi_wlat); @@ -3207,22 +3279,22 @@ static void mem_init_latency(void) * * Set VFIFO and LFIFO to instant-on settings in skip calibration mode. */ -static void mem_skip_calibrate(void) +static void mem_skip_calibrate(struct socfpga_sdrseq *seq) { u32 vfifo_offset; u32 i, j, r; debug("%s:%d\n", __func__, __LINE__); /* Need to update every shadow register set used by the interface */ - for (r = 0; r < rwcfg->mem_number_of_ranks; + for (r = 0; r < seq->rwcfg->mem_number_of_ranks; r += NUM_RANKS_PER_SHADOW_REG) { /* * Set output phase alignment settings appropriate for * skip calibration. */ - for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) { + for (i = 0; i < seq->rwcfg->mem_if_read_dqs_width; i++) { scc_mgr_set_dqs_en_phase(i, 0); - if (iocfg->dll_chain_length == 6) + if (seq->iocfg->dll_chain_length == 6) scc_mgr_set_dqdqs_output_phase(i, 6); else scc_mgr_set_dqdqs_output_phase(i, 7); @@ -3245,20 +3317,22 @@ static void mem_skip_calibrate(void) * Hence, to make DQS aligned to CK, we need to delay * DQS by: * (720 - 90 - 180 - 2) * - * (360 / iocfg->dll_chain_length) + * (360 / seq->iocfg->dll_chain_length) * - * Dividing the above by (360 / iocfg->dll_chain_length) + * Dividing the above by + (360 / seq->iocfg->dll_chain_length) * gives us the number of ptaps, which simplies to: * - * (1.25 * iocfg->dll_chain_length - 2) + * (1.25 * seq->iocfg->dll_chain_length - 2) */ scc_mgr_set_dqdqs_output_phase(i, - ((125 * iocfg->dll_chain_length) / 100) - 2); + ((125 * seq->iocfg->dll_chain_length) + / 100) - 2); } writel(0xff, &sdr_scc_mgr->dqs_ena); writel(0xff, &sdr_scc_mgr->dqs_io_ena); - for (i = 0; i < rwcfg->mem_if_write_dqs_width; i++) { + for (i = 0; i < seq->rwcfg->mem_if_write_dqs_width; i++) { writel(i, SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_GROUP_COUNTER_OFFSET); } @@ -3268,7 +3342,7 @@ static void mem_skip_calibrate(void) } /* Compensate for simulation model behaviour */ - for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) { + for (i = 0; i < seq->rwcfg->mem_if_read_dqs_width; i++) { scc_mgr_set_dqs_bus_in_delay(i, 10); scc_mgr_load_dqs(i); } @@ -3278,7 +3352,7 @@ static void mem_skip_calibrate(void) * ArriaV has hard FIFOs that can only be initialized by incrementing * in sequencer. */ - vfifo_offset = misccfg->calib_vfifo_offset; + vfifo_offset = seq->misccfg->calib_vfifo_offset; for (j = 0; j < vfifo_offset; j++) writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy); writel(0, &phy_mgr_cmd->fifo_reset); @@ -3287,8 +3361,8 @@ static void mem_skip_calibrate(void) * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal * setting from generation-time constant. */ - gbl->curr_read_lat = misccfg->calib_lfifo_offset; - writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat); + seq->gbl.curr_read_lat = seq->misccfg->calib_lfifo_offset; + writel(seq->gbl.curr_read_lat, &phy_mgr_cfg->phy_rlat); } /** @@ -3296,7 +3370,7 @@ static void mem_skip_calibrate(void) * * Perform memory calibration. */ -static u32 mem_calibrate(void) +static u32 mem_calibrate(struct socfpga_sdrseq *seq) { u32 i; u32 rank_bgn, sr; @@ -3306,25 +3380,25 @@ static u32 mem_calibrate(void) u32 failing_groups = 0; u32 group_failed = 0; - const u32 rwdqs_ratio = rwcfg->mem_if_read_dqs_width / - rwcfg->mem_if_write_dqs_width; + const u32 rwdqs_ratio = seq->rwcfg->mem_if_read_dqs_width / + seq->rwcfg->mem_if_write_dqs_width; debug("%s:%d\n", __func__, __LINE__); /* Initialize the data settings */ - gbl->error_substage = CAL_SUBSTAGE_NIL; - gbl->error_stage = CAL_STAGE_NIL; - gbl->error_group = 0xff; - gbl->fom_in = 0; - gbl->fom_out = 0; + seq->gbl.error_substage = CAL_SUBSTAGE_NIL; + seq->gbl.error_stage = CAL_STAGE_NIL; + seq->gbl.error_group = 0xff; + seq->gbl.fom_in = 0; + seq->gbl.fom_out = 0; /* Initialize WLAT and RLAT. */ - mem_init_latency(); + mem_init_latency(seq); /* Initialize bit slips. */ - mem_precharge_and_activate(); + mem_precharge_and_activate(seq); - for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) { + for (i = 0; i < seq->rwcfg->mem_if_read_dqs_width; i++) { writel(i, SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_GROUP_COUNTER_OFFSET); /* Only needed once to set all groups, pins, DQ, DQS, DM. */ @@ -3335,12 +3409,12 @@ static u32 mem_calibrate(void) } /* Calibration is skipped. */ - if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) { + if ((seq->dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) { /* * Set VFIFO and LFIFO to instant-on settings in skip * calibration mode. */ - mem_skip_calibrate(); + mem_skip_calibrate(seq); /* * Do not remove this line as it makes sure all of our @@ -3356,13 +3430,13 @@ static u32 mem_calibrate(void) * Zero all delay chain/phase settings for all * groups and all shadow register sets. */ - scc_mgr_zero_all(); + scc_mgr_zero_all(seq); run_groups = ~0; for (write_group = 0, write_test_bgn = 0; write_group - < rwcfg->mem_if_write_dqs_width; write_group++, - write_test_bgn += rwcfg->mem_dq_per_write_dqs) { + < seq->rwcfg->mem_if_write_dqs_width; write_group++, + write_test_bgn += seq->rwcfg->mem_dq_per_write_dqs) { /* Initialize the group failure */ group_failed = 0; @@ -3376,22 +3450,22 @@ static u32 mem_calibrate(void) writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_GROUP_COUNTER_OFFSET); - scc_mgr_zero_group(write_group, 0); + scc_mgr_zero_group(seq, write_group, 0); for (read_group = write_group * rwdqs_ratio, read_test_bgn = 0; read_group < (write_group + 1) * rwdqs_ratio; read_group++, - read_test_bgn += rwcfg->mem_dq_per_read_dqs) { + read_test_bgn += seq->rwcfg->mem_dq_per_read_dqs) { if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO) continue; /* Calibrate the VFIFO */ - if (rw_mgr_mem_calibrate_vfifo(read_group, + if (rw_mgr_mem_calibrate_vfifo(seq, read_group, read_test_bgn)) continue; - if (!(gbl->phy_debug_mode_flags & + if (!(seq->gbl.phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS)) return 0; @@ -3401,7 +3475,7 @@ static u32 mem_calibrate(void) /* Calibrate the output side */ for (rank_bgn = 0, sr = 0; - rank_bgn < rwcfg->mem_number_of_ranks; + rank_bgn < seq->rwcfg->mem_number_of_ranks; rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) { if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES) continue; @@ -3412,13 +3486,13 @@ static u32 mem_calibrate(void) continue; /* Calibrate WRITEs */ - if (!rw_mgr_mem_calibrate_writes(rank_bgn, + if (!rw_mgr_mem_calibrate_writes(seq, rank_bgn, write_group, write_test_bgn)) continue; group_failed = 1; - if (!(gbl->phy_debug_mode_flags & + if (!(seq->gbl.phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS)) return 0; } @@ -3431,15 +3505,16 @@ static u32 mem_calibrate(void) read_test_bgn = 0; read_group < (write_group + 1) * rwdqs_ratio; read_group++, - read_test_bgn += rwcfg->mem_dq_per_read_dqs) { + read_test_bgn += seq->rwcfg->mem_dq_per_read_dqs) { if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES) continue; - if (!rw_mgr_mem_calibrate_vfifo_end(read_group, + if (!rw_mgr_mem_calibrate_vfifo_end(seq, + read_group, read_test_bgn)) continue; - if (!(gbl->phy_debug_mode_flags & + if (!(seq->gbl.phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS)) return 0; @@ -3465,7 +3540,7 @@ grp_failed: /* A group failed, increment the counter. */ continue; /* Calibrate the LFIFO */ - if (!rw_mgr_mem_calibrate_lfifo()) + if (!rw_mgr_mem_calibrate_lfifo(seq)) return 0; } @@ -3482,7 +3557,7 @@ grp_failed: /* A group failed, increment the counter. */ * * This function triggers the entire memory calibration procedure. */ -static int run_mem_calibrate(void) +static int run_mem_calibrate(struct socfpga_sdrseq *seq) { int pass; u32 ctrl_cfg; @@ -3497,17 +3572,17 @@ static int run_mem_calibrate(void) writel(ctrl_cfg & ~SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK, &sdr_ctrl->ctrl_cfg); - phy_mgr_initialize(); - rw_mgr_mem_initialize(); + phy_mgr_initialize(seq); + rw_mgr_mem_initialize(seq); /* Perform the actual memory calibration. */ - pass = mem_calibrate(); + pass = mem_calibrate(seq); - mem_precharge_and_activate(); + mem_precharge_and_activate(seq); writel(0, &phy_mgr_cmd->fifo_reset); /* Handoff. */ - rw_mgr_mem_handoff(); + rw_mgr_mem_handoff(seq); /* * In Hard PHY this is a 2-bit control: * 0: AFI Mux Select @@ -3528,25 +3603,25 @@ static int run_mem_calibrate(void) * This function reports the results of the memory calibration * and writes debug information into the register file. */ -static void debug_mem_calibrate(int pass) +static void debug_mem_calibrate(struct socfpga_sdrseq *seq, int pass) { u32 debug_info; if (pass) { debug("%s: CALIBRATION PASSED\n", __FILE__); - gbl->fom_in /= 2; - gbl->fom_out /= 2; + seq->gbl.fom_in /= 2; + seq->gbl.fom_out /= 2; - if (gbl->fom_in > 0xff) - gbl->fom_in = 0xff; + if (seq->gbl.fom_in > 0xff) + seq->gbl.fom_in = 0xff; - if (gbl->fom_out > 0xff) - gbl->fom_out = 0xff; + if (seq->gbl.fom_out > 0xff) + seq->gbl.fom_out = 0xff; /* Update the FOM in the register file */ - debug_info = gbl->fom_in; - debug_info |= gbl->fom_out << 8; + debug_info = seq->gbl.fom_in; + debug_info |= seq->gbl.fom_out << 8; writel(debug_info, &sdr_reg_file->fom); writel(debug_info, &phy_mgr_cfg->cal_debug_info); @@ -3554,18 +3629,18 @@ static void debug_mem_calibrate(int pass) } else { debug("%s: CALIBRATION FAILED\n", __FILE__); - debug_info = gbl->error_stage; - debug_info |= gbl->error_substage << 8; - debug_info |= gbl->error_group << 16; + debug_info = seq->gbl.error_stage; + debug_info |= seq->gbl.error_substage << 8; + debug_info |= seq->gbl.error_group << 16; writel(debug_info, &sdr_reg_file->failing_stage); writel(debug_info, &phy_mgr_cfg->cal_debug_info); writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status); /* Update the failing group/stage in the register file */ - debug_info = gbl->error_stage; - debug_info |= gbl->error_substage << 8; - debug_info |= gbl->error_group << 16; + debug_info = seq->gbl.error_stage; + debug_info |= seq->gbl.error_substage << 8; + debug_info |= seq->gbl.error_group << 16; writel(debug_info, &sdr_reg_file->failing_stage); } @@ -3599,10 +3674,11 @@ static void hc_initialize_rom_data(void) * * Initialize SDR register file. */ -static void initialize_reg_file(void) +static void initialize_reg_file(struct socfpga_sdrseq *seq) { /* Initialize the register file with the correct data */ - writel(misccfg->reg_file_init_seq_signature, &sdr_reg_file->signature); + writel(seq->misccfg->reg_file_init_seq_signature, + &sdr_reg_file->signature); writel(0, &sdr_reg_file->debug_data_addr); writel(0, &sdr_reg_file->cur_stage); writel(0, &sdr_reg_file->fom); @@ -3666,15 +3742,15 @@ static void initialize_hps_phy(void) * * Initialize the register file with usable initial data. */ -static void initialize_tracking(void) +static void initialize_tracking(struct socfpga_sdrseq *seq) { /* * Initialize the register file with the correct data. * Compute usable version of value in case we skip full * computation later. */ - writel(DIV_ROUND_UP(iocfg->delay_per_opa_tap, - iocfg->delay_per_dchain_tap) - 1, + writel(DIV_ROUND_UP(seq->iocfg->delay_per_opa_tap, + seq->iocfg->delay_per_dchain_tap) - 1, &sdr_reg_file->dtaps_per_ptap); /* trk_sample_count */ @@ -3693,23 +3769,22 @@ static void initialize_tracking(void) &sdr_reg_file->delays); /* mux delay */ - writel((rwcfg->idle << 24) | (rwcfg->activate_1 << 16) | - (rwcfg->sgle_read << 8) | (rwcfg->precharge_all << 0), + writel((seq->rwcfg->idle << 24) | (seq->rwcfg->activate_1 << 16) | + (seq->rwcfg->sgle_read << 8) | (seq->rwcfg->precharge_all << 0), &sdr_reg_file->trk_rw_mgr_addr); - writel(rwcfg->mem_if_read_dqs_width, + writel(seq->rwcfg->mem_if_read_dqs_width, &sdr_reg_file->trk_read_dqs_width); /* trefi [7:0] */ - writel((rwcfg->refresh_all << 24) | (1000 << 0), + writel((seq->rwcfg->refresh_all << 24) | (1000 << 0), &sdr_reg_file->trk_rfsh); } int sdram_calibration_full(struct socfpga_sdr *sdr) { - struct param_type my_param; - struct gbl_type my_gbl; u32 pass; + struct socfpga_sdrseq seq; /* * For size reasons, this file uses hard coded addresses. @@ -3718,60 +3793,61 @@ int sdram_calibration_full(struct socfpga_sdr *sdr) if (sdr != (struct socfpga_sdr *)SOCFPGA_SDR_ADDRESS) return -ENODEV; - memset(&my_param, 0, sizeof(my_param)); - memset(&my_gbl, 0, sizeof(my_gbl)); - - param = &my_param; - gbl = &my_gbl; + memset(&seq, 0, sizeof(seq)); - rwcfg = socfpga_get_sdram_rwmgr_config(); - iocfg = socfpga_get_sdram_io_config(); - misccfg = socfpga_get_sdram_misc_config(); + seq.rwcfg = socfpga_get_sdram_rwmgr_config(); + seq.iocfg = socfpga_get_sdram_io_config(); + seq.misccfg = socfpga_get_sdram_misc_config(); /* Set the calibration enabled by default */ - gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT; + seq.gbl.phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT; /* * Only sweep all groups (regardless of fail state) by default * Set enabled read test by default. */ #if DISABLE_GUARANTEED_READ - gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ; + seq.gbl.phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ; #endif /* Initialize the register file */ - initialize_reg_file(); + initialize_reg_file(&seq); /* Initialize any PHY CSR */ initialize_hps_phy(); scc_mgr_initialize(); - initialize_tracking(); + initialize_tracking(&seq); debug("%s: Preparing to start memory calibration\n", __FILE__); debug("%s:%d\n", __func__, __LINE__); debug_cond(DLEVEL >= 1, "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ", - rwcfg->mem_number_of_ranks, rwcfg->mem_number_of_cs_per_dimm, - rwcfg->mem_dq_per_read_dqs, rwcfg->mem_dq_per_write_dqs, - rwcfg->mem_virtual_groups_per_read_dqs, - rwcfg->mem_virtual_groups_per_write_dqs); + seq.rwcfg->mem_number_of_ranks, + seq.rwcfg->mem_number_of_cs_per_dimm, + seq.rwcfg->mem_dq_per_read_dqs, + seq.rwcfg->mem_dq_per_write_dqs, + seq.rwcfg->mem_virtual_groups_per_read_dqs, + seq.rwcfg->mem_virtual_groups_per_write_dqs); debug_cond(DLEVEL >= 1, "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ", - rwcfg->mem_if_read_dqs_width, rwcfg->mem_if_write_dqs_width, - rwcfg->mem_data_width, rwcfg->mem_data_mask_width, - iocfg->delay_per_opa_tap, iocfg->delay_per_dchain_tap); + seq.rwcfg->mem_if_read_dqs_width, + seq.rwcfg->mem_if_write_dqs_width, + seq.rwcfg->mem_data_width, seq.rwcfg->mem_data_mask_width, + seq.iocfg->delay_per_opa_tap, + seq.iocfg->delay_per_dchain_tap); debug_cond(DLEVEL >= 1, "dtap_dqsen_delay=%u, dll=%u", - iocfg->delay_per_dqs_en_dchain_tap, iocfg->dll_chain_length); + seq.iocfg->delay_per_dqs_en_dchain_tap, + seq.iocfg->dll_chain_length); debug_cond(DLEVEL >= 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ", - iocfg->dqs_en_phase_max, iocfg->dqdqs_out_phase_max, - iocfg->dqs_en_delay_max, iocfg->dqs_in_delay_max); + seq.iocfg->dqs_en_phase_max, seq.iocfg->dqdqs_out_phase_max, + seq.iocfg->dqs_en_delay_max, seq.iocfg->dqs_in_delay_max); debug_cond(DLEVEL >= 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ", - iocfg->io_in_delay_max, iocfg->io_out1_delay_max, - iocfg->io_out2_delay_max); + seq.iocfg->io_in_delay_max, seq.iocfg->io_out1_delay_max, + seq.iocfg->io_out2_delay_max); debug_cond(DLEVEL >= 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n", - iocfg->dqs_in_reserve, iocfg->dqs_out_reserve); + seq.iocfg->dqs_in_reserve, seq.iocfg->dqs_out_reserve); hc_initialize_rom_data(); @@ -3783,17 +3859,17 @@ int sdram_calibration_full(struct socfpga_sdr *sdr) * Load global needed for those actions that require * some dynamic calibration support. */ - dyn_calib_steps = STATIC_CALIB_STEPS; + seq.dyn_calib_steps = STATIC_CALIB_STEPS; /* * Load global to allow dynamic selection of delay loop settings * based on calibration mode. */ - if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS)) - skip_delay_mask = 0xff; + if (!(seq.dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS)) + seq.skip_delay_mask = 0xff; else - skip_delay_mask = 0x0; + seq.skip_delay_mask = 0x0; - pass = run_mem_calibrate(); - debug_mem_calibrate(pass); + pass = run_mem_calibrate(&seq); + debug_mem_calibrate(&seq, pass); return pass; } diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h index d7f6935201..4a03c3fdf9 100644 --- a/drivers/ddr/altera/sequencer.h +++ b/drivers/ddr/altera/sequencer.h @@ -6,14 +6,16 @@ #ifndef _SEQUENCER_H_ #define _SEQUENCER_H_ -#define RW_MGR_NUM_DM_PER_WRITE_GROUP (rwcfg->mem_data_mask_width \ - / rwcfg->mem_if_write_dqs_width) -#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (rwcfg->true_mem_data_mask_width \ - / rwcfg->mem_if_write_dqs_width) +#define RW_MGR_NUM_DM_PER_WRITE_GROUP (seq->rwcfg->mem_data_mask_width \ + / seq->rwcfg->mem_if_write_dqs_width) +#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP ( \ + seq->rwcfg->true_mem_data_mask_width \ + / seq->rwcfg->mem_if_write_dqs_width) -#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (rwcfg->mem_if_read_dqs_width \ - / rwcfg->mem_if_write_dqs_width) -#define NUM_RANKS_PER_SHADOW_REG (rwcfg->mem_number_of_ranks / NUM_SHADOW_REGS) +#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (seq->rwcfg->mem_if_read_dqs_width \ + / seq->rwcfg->mem_if_write_dqs_width) +#define NUM_RANKS_PER_SHADOW_REG (seq->rwcfg->mem_number_of_ranks \ + / NUM_SHADOW_REGS) #define RW_MGR_RUN_SINGLE_GROUP_OFFSET 0x0 #define RW_MGR_RUN_ALL_GROUPS_OFFSET 0x0400 @@ -256,6 +258,26 @@ struct socfpga_sdr { u8 _align9[0xea4]; }; +struct socfpga_sdrseq { + const struct socfpga_sdram_rw_mgr_config *rwcfg; + const struct socfpga_sdram_io_config *iocfg; + const struct socfpga_sdram_misc_config *misccfg; + /* calibration steps requested by the rtl */ + u16 dyn_calib_steps; + /* + * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option + * instead of static, we use boolean logic to select between + * non-skip and skip values + * + * The mask is set to include all bits when not-skipping, but is + * zero when skipping + */ + + u16 skip_delay_mask; /* mask off bits when skipping/not-skipping */ + struct gbl_type gbl; + struct param_type param; +}; + int sdram_calibration_full(struct socfpga_sdr *sdr); #endif /* _SEQUENCER_H_ */ diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index 7d8f161b26..873bc8c796 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -1,9 +1,13 @@ config FIRMWARE bool "Enable Firmware driver support" +config SPL_FIRMWARE + bool "Enable Firmware driver support in SPL" + depends on FIRMWARE + config SPL_ARM_PSCI_FW bool - select FIRMWARE + select SPL_FIRMWARE config ARM_PSCI_FW bool @@ -13,6 +17,7 @@ config TI_SCI_PROTOCOL tristate "TI System Control Interface (TISCI) Message Protocol" depends on K3_SEC_PROXY select FIRMWARE + select SPL_FIRMWARE if SPL help TI System Control Interface (TISCI) Message Protocol is used to manage compute systems such as ARM, DSP etc with the system controller in diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 8f59193e3c..105a299812 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -58,9 +58,17 @@ config FPGA_ZYNQMPPL config FPGA_SPARTAN3 bool "Enable Spartan3 FPGA driver" + depends on FPGA_XILINX help Enable Spartan3 FPGA driver for loading in BIT format. +config FPGA_VIRTEX2 + bool "Enable Xilinx Virtex-II and later FPGA driver" + depends on FPGA_XILINX + help + Enable Virtex-II FPGA driver for loading in BIT format. This driver + also supports many newer Xilinx FPGA families. + config FPGA_ZYNQPL bool "Enable Xilinx FPGA for Zynq" depends on ARCH_ZYNQ diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c index 6755956e85..c929cd2cc5 100644 --- a/drivers/fpga/cyclon2.c +++ b/drivers/fpga/cyclon2.c @@ -11,9 +11,9 @@ /* Define FPGA_DEBUG to get debug printf's */ #ifdef FPGA_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) +#define PRINTF(fmt, args...) printf(fmt, ##args) #else -#define PRINTF(fmt,args...) +#define PRINTF(fmt, args...) #endif /* Note: The assumption is that we cannot possibly run fast enough to @@ -26,7 +26,7 @@ #endif #ifndef CONFIG_SYS_FPGA_WAIT -#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */ +#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ / 10 /* 100 ms */ #endif static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize); @@ -41,8 +41,8 @@ int CYC2_load(Altera_desc *desc, const void *buf, size_t bsize) switch (desc->iface) { case passive_serial: - PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__); - ret_val = CYC2_ps_load (desc, buf, bsize); + PRINTF("%s: Launching Passive Serial Loader\n", __func__); + ret_val = CYC2_ps_load(desc, buf, bsize); break; case fast_passive_parallel: @@ -50,16 +50,16 @@ int CYC2_load(Altera_desc *desc, const void *buf, size_t bsize) * done in the write() callback. Use the existing PS load * function for FPP, too. */ - PRINTF ("%s: Launching Fast Passive Parallel Loader\n", - __FUNCTION__); + PRINTF("%s: Launching Fast Passive Parallel Loader\n", + __func__); ret_val = CYC2_ps_load(desc, buf, bsize); break; /* Add new interface types here */ default: - printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); + printf("%s: Unsupported interface type, %d\n", + __func__, desc->iface); } return ret_val; @@ -71,59 +71,58 @@ int CYC2_dump(Altera_desc *desc, const void *buf, size_t bsize) switch (desc->iface) { case passive_serial: - PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__); - ret_val = CYC2_ps_dump (desc, buf, bsize); + PRINTF("%s: Launching Passive Serial Dump\n", __func__); + ret_val = CYC2_ps_dump(desc, buf, bsize); break; /* Add new interface types here */ default: - printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); + printf("%s: Unsupported interface type, %d\n", + __func__, desc->iface); } return ret_val; } -int CYC2_info( Altera_desc *desc ) +int CYC2_info(Altera_desc *desc) { return FPGA_SUCCESS; } /* ------------------------------------------------------------------------- */ -/* CYCLON2 Passive Serial Generic Implementation */ +/* CYCLON2 Passive Serial Generic Implementation */ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ Altera_CYC2_Passive_Serial_fns *fn = desc->iface_fns; int ret = 0; - PRINTF ("%s: start with interface functions @ 0x%p\n", - __FUNCTION__, fn); + PRINTF("%s: start with interface functions @ 0x%p\n", + __func__, fn); if (fn) { int cookie = desc->cookie; /* make a local copy */ unsigned long ts; /* timestamp */ - PRINTF ("%s: Function Table:\n" + PRINTF("%s: Function Table:\n" "ptr:\t0x%p\n" "struct: 0x%p\n" "config:\t0x%p\n" "status:\t0x%p\n" "write:\t0x%p\n" "done:\t0x%p\n\n", - __FUNCTION__, &fn, fn, fn->config, fn->status, + __func__, &fn, fn, fn->config, fn->status, fn->write, fn->done); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - printf ("Loading FPGA Device %d...", cookie); + printf("Loading FPGA Device %d...", cookie); #endif /* * Run the pre configuration function if there is one. */ - if (*fn->pre) { + if (*fn->pre) (*fn->pre) (cookie); - } /* Establish the initial state */ (*fn->config) (false, true, cookie); /* De-assert nCONFIG */ @@ -133,22 +132,23 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize) udelay(2); /* T_cfg > 2us */ /* Wait for nSTATUS to be asserted */ - ts = get_timer (0); /* get current time */ + ts = get_timer(0); /* get current time */ do { - CONFIG_FPGA_DELAY (); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ - puts ("** Timeout waiting for STATUS to go high.\n"); + CONFIG_FPGA_DELAY(); + if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + /* check the time */ + puts("** Timeout waiting for STATUS to go high.\n"); (*fn->abort) (cookie); return FPGA_FAIL; } } while (!(*fn->status) (cookie)); /* Get ready for the burn */ - CONFIG_FPGA_DELAY (); + CONFIG_FPGA_DELAY(); ret = (*fn->write) (buf, bsize, true, cookie); if (ret) { - puts ("** Write failed.\n"); + puts("** Write failed.\n"); (*fn->abort) (cookie); return FPGA_FAIL; } @@ -156,39 +156,41 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize) puts(" OK? ..."); #endif - CONFIG_FPGA_DELAY (); + CONFIG_FPGA_DELAY(); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - putc (' '); /* terminate the dotted line */ + putc(' '); /* terminate the dotted line */ #endif - /* - * Checking FPGA's CONF_DONE signal - correctly booted ? - */ + /* + * Checking FPGA's CONF_DONE signal - correctly booted ? + */ - if ( ! (*fn->done) (cookie) ) { - puts ("** Booting failed! CONF_DONE is still deasserted.\n"); - (*fn->abort) (cookie); - return (FPGA_FAIL); - } + if (!(*fn->done) (cookie)) { + puts("** Booting failed! CONF_DONE is still deasserted.\n"); + (*fn->abort) (cookie); + return FPGA_FAIL; + } #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - puts(" OK\n"); + puts(" OK\n"); #endif - ret_val = FPGA_SUCCESS; + ret_val = FPGA_SUCCESS; #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - if (ret_val == FPGA_SUCCESS) { - puts ("Done.\n"); - } - else { - puts ("Fail.\n"); - } + if (ret_val == FPGA_SUCCESS) + puts("Done.\n"); + else + puts("Fail.\n"); #endif - (*fn->post) (cookie); + /* + * Run the post configuration function if there is one. + */ + if (*fn->post) + (*fn->post) (cookie); } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); + printf("%s: NULL Interface function table!\n", __func__); } return ret_val; @@ -198,7 +200,6 @@ static int CYC2_ps_dump(Altera_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ - printf ("%s: Passive Serial Dumping is unavailable\n", - __FUNCTION__); + printf("%s: Passive Serial Dumping is unavailable\n", __func__); return FPGA_FAIL; } diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c index 285280e507..5fb9d6a191 100644 --- a/drivers/fpga/socfpga_arria10.c +++ b/drivers/fpga/socfpga_arria10.c @@ -936,10 +936,11 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) fpgamgr_program_write(rbf_data, rbf_size); status = fpgamgr_program_finish(); - if (status) { - config_pins(gd->fdt_blob, "fpga"); - puts("FPGA: Enter user mode.\n"); - } + if (status) + return status; + + config_pins(gd->fdt_blob, "fpga"); + puts("FPGA: Enter user mode.\n"); return status; } diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index 02773d6a0e..395736875f 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -3,6 +3,8 @@ * (C) Copyright 2002 * Rich Ireland, Enterasys Networks, rireland@enterasys.com. * Keith Outwater, keith_outwater@mvis.com + * + * Copyright (c) 2019 SED Systems, a division of Calian Ltd. */ /* @@ -19,16 +21,16 @@ #endif #ifdef FPGA_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) +#define PRINTF(fmt, args...) printf(fmt, ##args) #else -#define PRINTF(fmt,args...) +#define PRINTF(fmt, args...) #endif /* * If the SelectMap interface can be overrun by the processor, define - * CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board configuration - * file and add board-specific support for checking BUSY status. By default, - * assume that the SelectMap interface cannot be overrun. + * CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board + * configuration file and add board-specific support for checking BUSY status. + * By default, assume that the SelectMap interface cannot be overrun. */ #ifndef CONFIG_SYS_FPGA_CHECK_BUSY #undef CONFIG_SYS_FPGA_CHECK_BUSY @@ -65,7 +67,7 @@ * an XC2V1000, if anyone can ever get ahold of one. */ #ifndef CONFIG_SYS_FPGA_WAIT_INIT -#define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ/2 /* 500 ms */ +#define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */ #endif /* @@ -74,14 +76,14 @@ * clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary. */ #ifndef CONFIG_SYS_FPGA_WAIT_BUSY -#define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ/200 /* 5 ms*/ +#define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/ #endif /* Default timeout for waiting for FPGA to enter operational mode after * configuration data has been written. */ #ifndef CONFIG_SYS_FPGA_WAIT_CONFIG -#define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */ +#define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */ #endif static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize); @@ -97,18 +99,18 @@ static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize, switch (desc->iface) { case slave_serial: - PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); + PRINTF("%s: Launching Slave Serial Load\n", __func__); ret_val = virtex2_ss_load(desc, buf, bsize); break; case slave_selectmap: - PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); + PRINTF("%s: Launching Slave Parallel Load\n", __func__); ret_val = virtex2_ssm_load(desc, buf, bsize); break; default: - printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); + printf("%s: Unsupported interface type, %d\n", + __func__, desc->iface); } return ret_val; } @@ -119,18 +121,18 @@ static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize) switch (desc->iface) { case slave_serial: - PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__); + PRINTF("%s: Launching Slave Serial Dump\n", __func__); ret_val = virtex2_ss_dump(desc, buf, bsize); break; case slave_parallel: - PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__); + PRINTF("%s: Launching Slave Parallel Dump\n", __func__); ret_val = virtex2_ssm_dump(desc, buf, bsize); break; default: - printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); + printf("%s: Unsupported interface type, %d\n", + __func__, desc->iface); } return ret_val; } @@ -141,8 +143,8 @@ static int virtex2_info(xilinx_desc *desc) } /* - * Virtex-II Slave SelectMap configuration loader. Configuration via - * SelectMap is as follows: + * Virtex-II Slave SelectMap or Serial configuration loader. Configuration + * is as follows: * 1. Set the FPGA's PROG_B line low. * 2. Set the FPGA's PROG_B line high. Wait for INIT_B to go high. * 3. Write data to the SelectMap port. If INIT_B goes low at any time @@ -154,200 +156,236 @@ static int virtex2_info(xilinx_desc *desc) * INIT_B and DONE lines. If both are high, configuration has * succeeded. Congratulations! */ -static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie) { - int ret_val = FPGA_FAIL; - xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns; + unsigned long ts; - PRINTF ("%s:%d: Start with interface functions @ 0x%p\n", - __FUNCTION__, __LINE__, fn); + PRINTF("%s:%d: Start with interface functions @ 0x%p\n", + __func__, __LINE__, fn); - if (fn) { - size_t bytecount = 0; - unsigned char *data = (unsigned char *) buf; - int cookie = desc->cookie; - unsigned long ts; - - /* Gotta split this one up (so the stack won't blow??) */ - PRINTF ("%s:%d: Function Table:\n" - " base 0x%p\n" - " struct 0x%p\n" - " pre 0x%p\n" - " prog 0x%p\n" - " init 0x%p\n" - " error 0x%p\n", - __FUNCTION__, __LINE__, - &fn, fn, fn->pre, fn->pgm, fn->init, fn->err); - PRINTF (" clock 0x%p\n" - " cs 0x%p\n" - " write 0x%p\n" - " rdata 0x%p\n" - " wdata 0x%p\n" - " busy 0x%p\n" - " abort 0x%p\n" - " post 0x%p\n\n", - fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, - fn->busy, fn->abort, fn->post); + if (!fn) { + printf("%s:%d: NULL Interface function table!\n", + __func__, __LINE__); + return FPGA_FAIL; + } + + /* Gotta split this one up (so the stack won't blow??) */ + PRINTF("%s:%d: Function Table:\n" + " base 0x%p\n" + " struct 0x%p\n" + " pre 0x%p\n" + " prog 0x%p\n" + " init 0x%p\n" + " error 0x%p\n", + __func__, __LINE__, + &fn, fn, fn->pre, fn->pgm, fn->init, fn->err); + PRINTF(" clock 0x%p\n" + " cs 0x%p\n" + " write 0x%p\n" + " rdata 0x%p\n" + " wdata 0x%p\n" + " busy 0x%p\n" + " abort 0x%p\n" + " post 0x%p\n\n", + fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, + fn->busy, fn->abort, fn->post); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - printf ("Initializing FPGA Device %d...\n", cookie); + printf("Initializing FPGA Device %d...\n", cookie); #endif - /* - * Run the pre configuration function if there is one. - */ - if (*fn->pre) { - (*fn->pre) (cookie); + /* + * Run the pre configuration function if there is one. + */ + if (*fn->pre) + (*fn->pre)(cookie); + + /* + * Assert the program line. The minimum pulse width for + * Virtex II devices is 300 nS (Tprogram parameter in datasheet). + * There is no maximum value for the pulse width. Check to make + * sure that INIT_B goes low after assertion of PROG_B + */ + (*fn->pgm)(true, true, cookie); + udelay(10); + ts = get_timer(0); + do { + if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) { + printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n", + __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT); + (*fn->abort)(cookie); + return FPGA_FAIL; + } + } while (!(*fn->init)(cookie)); + + (*fn->pgm)(false, true, cookie); + CONFIG_FPGA_DELAY(); + if (fn->clk) + (*fn->clk)(true, true, cookie); + + /* + * Start a timer and wait for INIT_B to go high + */ + ts = get_timer(0); + do { + CONFIG_FPGA_DELAY(); + if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) { + printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n", + __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT); + (*fn->abort)(cookie); + return FPGA_FAIL; } + } while ((*fn->init)(cookie) && (*fn->busy)(cookie)); - /* - * Assert the program line. The minimum pulse width for - * Virtex II devices is 300 nS (Tprogram parameter in datasheet). - * There is no maximum value for the pulse width. Check to make - * sure that INIT_B goes low after assertion of PROG_B - */ - (*fn->pgm) (true, true, cookie); - udelay (10); - ts = get_timer (0); - do { - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_INIT) { - printf ("%s:%d: ** Timeout after %d ticks waiting for INIT" - " to assert.\n", __FUNCTION__, __LINE__, - CONFIG_SYS_FPGA_WAIT_INIT); - (*fn->abort) (cookie); - return FPGA_FAIL; - } - } while (!(*fn->init) (cookie)); + if (fn->wr) + (*fn->wr)(true, true, cookie); + if (fn->cs) + (*fn->cs)(true, true, cookie); - (*fn->pgm) (false, true, cookie); - CONFIG_FPGA_DELAY (); - (*fn->clk) (true, true, cookie); + mdelay(10); + return FPGA_SUCCESS; +} - /* - * Start a timer and wait for INIT_B to go high - */ - ts = get_timer (0); - do { - CONFIG_FPGA_DELAY (); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_INIT) { - printf ("%s:%d: ** Timeout after %d ticks waiting for INIT" - " to deassert.\n", __FUNCTION__, __LINE__, - CONFIG_SYS_FPGA_WAIT_INIT); - (*fn->abort) (cookie); - return FPGA_FAIL; - } - } while ((*fn->init) (cookie) && (*fn->busy) (cookie)); +static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn, + int cookie) +{ + int ret_val = FPGA_SUCCESS; + int num_done = 0; + unsigned long ts; + + /* + * Finished writing the data; deassert FPGA CS_B and WRITE_B signals. + */ + CONFIG_FPGA_DELAY(); + if (fn->cs) + (*fn->cs)(false, true, cookie); + if (fn->wr) + (*fn->wr)(false, true, cookie); - (*fn->wr) (true, true, cookie); - (*fn->cs) (true, true, cookie); +#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK + putc('\n'); +#endif - udelay (10000); + /* + * Check for successful configuration. FPGA INIT_B and DONE + * should both be high upon successful configuration. Continue pulsing + * clock with data set to all ones until DONE is asserted and for 8 + * clock cycles afterwards. + */ + ts = get_timer(0); + while (true) { + if ((*fn->done)(cookie) == FPGA_SUCCESS && + !((*fn->init)(cookie))) { + if (num_done++ >= 8) + break; + } + if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) { + printf("%s:%d: ** Timeout after %d ticks waiting for DONE to assert and INIT to deassert\n", + __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG); + (*fn->abort)(cookie); + ret_val = FPGA_FAIL; + break; + } + if (fn->wbulkdata) { + unsigned char dummy = 0xff; + (*fn->wbulkdata)(&dummy, 1, true, cookie); + } else { + (*fn->wdata)(0xff, true, cookie); + CONFIG_FPGA_DELAY(); + (*fn->clk)(false, true, cookie); + CONFIG_FPGA_DELAY(); + (*fn->clk)(true, true, cookie); + } + } + + if (ret_val == FPGA_SUCCESS) { +#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK + printf("Initialization of FPGA device %d complete\n", cookie); +#endif /* - * Load the data byte by byte + * Run the post configuration function if there is one. */ - while (bytecount < bsize) { -#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC - if (ctrlc ()) { - (*fn->abort) (cookie); - return FPGA_FAIL; - } + if (*fn->post) + (*fn->post)(cookie); + } else { +#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK + printf("** Initialization of FPGA device %d FAILED\n", + cookie); #endif + } + return ret_val; +} - if ((*fn->done) (cookie) == FPGA_SUCCESS) { - PRINTF ("%s:%d:done went active early, bytecount = %d\n", - __FUNCTION__, __LINE__, bytecount); - break; - } - -#ifdef CONFIG_SYS_FPGA_CHECK_ERROR - if ((*fn->init) (cookie)) { - printf ("\n%s:%d: ** Error: INIT asserted during" - " configuration\n", __FUNCTION__, __LINE__); - printf ("%d = buffer offset, %d = buffer size\n", - bytecount, bsize); - (*fn->abort) (cookie); - return FPGA_FAIL; - } +static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; + xilinx_virtex2_slave_fns *fn = desc->iface_fns; + size_t bytecount = 0; + unsigned char *data = (unsigned char *)buf; + int cookie = desc->cookie; + + ret_val = virtex2_slave_pre(fn, cookie); + if (ret_val != FPGA_SUCCESS) + return ret_val; + + /* + * Load the data byte by byte + */ + while (bytecount < bsize) { +#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC + if (ctrlc()) { + (*fn->abort)(cookie); + return FPGA_FAIL; + } #endif - (*fn->wdata) (data[bytecount++], true, cookie); - CONFIG_FPGA_DELAY (); - - /* - * Cycle the clock pin - */ - (*fn->clk) (false, true, cookie); - CONFIG_FPGA_DELAY (); - (*fn->clk) (true, true, cookie); + if ((*fn->done)(cookie) == FPGA_SUCCESS) { + PRINTF("%s:%d:done went active early, bytecount = %d\n", + __func__, __LINE__, bytecount); + break; + } -#ifdef CONFIG_SYS_FPGA_CHECK_BUSY - ts = get_timer (0); - while ((*fn->busy) (cookie)) { - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_BUSY) { - printf ("%s:%d: ** Timeout after %d ticks waiting for" - " BUSY to deassert\n", - __FUNCTION__, __LINE__, CONFIG_SYS_FPGA_WAIT_BUSY); - (*fn->abort) (cookie); - return FPGA_FAIL; - } - } +#ifdef CONFIG_SYS_FPGA_CHECK_ERROR + if ((*fn->init)(cookie)) { + printf("\n%s:%d: ** Error: INIT asserted during configuration\n", + __func__, __LINE__); + printf("%zu = buffer offset, %zu = buffer size\n", + bytecount, bsize); + (*fn->abort)(cookie); + return FPGA_FAIL; + } #endif -#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - if (bytecount % (bsize / 40) == 0) - putc ('.'); -#endif - } + (*fn->wdata)(data[bytecount++], true, cookie); + CONFIG_FPGA_DELAY(); /* - * Finished writing the data; deassert FPGA CS_B and WRITE_B signals. + * Cycle the clock pin */ - CONFIG_FPGA_DELAY (); - (*fn->cs) (false, true, cookie); - (*fn->wr) (false, true, cookie); - -#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - putc ('\n'); -#endif + (*fn->clk)(false, true, cookie); + CONFIG_FPGA_DELAY(); + (*fn->clk)(true, true, cookie); - /* - * Check for successful configuration. FPGA INIT_B and DONE should - * both be high upon successful configuration. - */ - ts = get_timer (0); - ret_val = FPGA_SUCCESS; - while (((*fn->done) (cookie) == FPGA_FAIL) || (*fn->init) (cookie)) { - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) { - printf ("%s:%d: ** Timeout after %d ticks waiting for DONE to" - "assert and INIT to deassert\n", - __FUNCTION__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG); - (*fn->abort) (cookie); - ret_val = FPGA_FAIL; - break; +#ifdef CONFIG_SYS_FPGA_CHECK_BUSY + ts = get_timer(0); + while ((*fn->busy)(cookie)) { + if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_BUSY) { + printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n", + __func__, __LINE__, + CONFIG_SYS_FPGA_WAIT_BUSY); + (*fn->abort)(cookie); + return FPGA_FAIL; } } - - if (ret_val == FPGA_SUCCESS) { -#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - printf ("Initialization of FPGA device %d complete\n", cookie); #endif - /* - * Run the post configuration function if there is one. - */ - if (*fn->post) { - (*fn->post) (cookie); - } - } else { + #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - printf ("** Initialization of FPGA device %d FAILED\n", - cookie); + if (bytecount % (bsize / 40) == 0) + putc('.'); #endif - } - } else { - printf ("%s:%d: NULL Interface function table!\n", - __FUNCTION__, __LINE__); } - return ret_val; + + return virtex2_slave_post(fn, cookie); } /* @@ -356,64 +394,127 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize) static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; - xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns; + xilinx_virtex2_slave_fns *fn = desc->iface_fns; if (fn) { - unsigned char *data = (unsigned char *) buf; + unsigned char *data = (unsigned char *)buf; size_t bytecount = 0; int cookie = desc->cookie; - printf ("Starting Dump of FPGA Device %d...\n", cookie); + printf("Starting Dump of FPGA Device %d...\n", cookie); - (*fn->cs) (true, true, cookie); - (*fn->clk) (true, true, cookie); + (*fn->cs)(true, true, cookie); + (*fn->clk)(true, true, cookie); while (bytecount < bsize) { #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC - if (ctrlc ()) { - (*fn->abort) (cookie); + if (ctrlc()) { + (*fn->abort)(cookie); return FPGA_FAIL; } #endif /* * Cycle the clock and read the data */ - (*fn->clk) (false, true, cookie); - (*fn->clk) (true, true, cookie); - (*fn->rdata) (&(data[bytecount++]), cookie); + (*fn->clk)(false, true, cookie); + (*fn->clk)(true, true, cookie); + (*fn->rdata)(&data[bytecount++], cookie); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK if (bytecount % (bsize / 40) == 0) - putc ('.'); + putc('.'); #endif } /* * Deassert CS_B and cycle the clock to deselect the device. */ - (*fn->cs) (false, false, cookie); - (*fn->clk) (false, true, cookie); - (*fn->clk) (true, true, cookie); + (*fn->cs)(false, false, cookie); + (*fn->clk)(false, true, cookie); + (*fn->clk)(true, true, cookie); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - putc ('\n'); + putc('\n'); #endif - puts ("Done.\n"); + puts("Done.\n"); } else { - printf ("%s:%d: NULL Interface function table!\n", - __FUNCTION__, __LINE__); + printf("%s:%d: NULL Interface function table!\n", + __func__, __LINE__); } return ret_val; } static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) { - printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__); - return FPGA_FAIL; + int ret_val = FPGA_FAIL; + xilinx_virtex2_slave_fns *fn = desc->iface_fns; + unsigned char *data = (unsigned char *)buf; + int cookie = desc->cookie; + + ret_val = virtex2_slave_pre(fn, cookie); + if (ret_val != FPGA_SUCCESS) + return ret_val; + + if (fn->wbulkdata) { + /* Load the data in a single chunk */ + (*fn->wbulkdata)(data, bsize, true, cookie); + } else { + size_t bytecount = 0; + + /* + * Load the data bit by bit + */ + while (bytecount < bsize) { + unsigned char curr_data = data[bytecount++]; + int bit; + +#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC + if (ctrlc()) { + (*fn->abort) (cookie); + return FPGA_FAIL; + } +#endif + + if ((*fn->done)(cookie) == FPGA_SUCCESS) { + PRINTF("%s:%d:done went active early, bytecount = %d\n", + __func__, __LINE__, bytecount); + break; + } + +#ifdef CONFIG_SYS_FPGA_CHECK_ERROR + if ((*fn->init)(cookie)) { + printf("\n%s:%d: ** Error: INIT asserted during configuration\n", + __func__, __LINE__); + printf("%zu = buffer offset, %zu = buffer size\n", + bytecount, bsize); + (*fn->abort)(cookie); + return FPGA_FAIL; + } +#endif + + for (bit = 7; bit >= 0; --bit) { + unsigned char curr_bit = (curr_data >> bit) & 1; + (*fn->wdata)(curr_bit, true, cookie); + CONFIG_FPGA_DELAY(); + (*fn->clk)(false, true, cookie); + CONFIG_FPGA_DELAY(); + (*fn->clk)(true, true, cookie); + } + + /* Slave serial never uses a busy pin */ + +#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK + if (bytecount % (bsize / 40) == 0) + putc('.'); +#endif + } + } + + return virtex2_slave_post(fn, cookie); } static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) { - printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__); + printf("%s: Slave Serial Dumping is unsupported\n", __func__); return FPGA_FAIL; } diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 800584f512..7d9c97f537 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -14,7 +14,7 @@ config DM_GPIO particular GPIOs that they provide. The uclass interface is defined in include/asm-generic/gpio.h. -config DM_GPIO_HOG +config GPIO_HOG bool "Enable GPIO hog support" depends on DM_GPIO default n diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 308d0863ad..01cfa2f788 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -144,7 +144,7 @@ static int gpio_find_and_xlate(struct gpio_desc *desc, return gpio_xlate_offs_flags(desc->dev, desc, args); } -#if defined(CONFIG_DM_GPIO_HOG) +#if defined(CONFIG_GPIO_HOG) struct gpio_hog_priv { struct gpio_desc gpiod; @@ -181,9 +181,8 @@ static int gpio_hog_ofdata_to_platdata(struct udevice *dev) return ret; } nodename = dev_read_string(dev, "line-name"); - if (!nodename) - nodename = dev_read_name(dev); - device_set_name(dev, nodename); + if (nodename) + device_set_name(dev, nodename); return 0; } @@ -202,9 +201,15 @@ static int gpio_hog_probe(struct udevice *dev) dev->name); return ret; } - dm_gpio_set_dir(&priv->gpiod); - if (plat->gpiod_flags == GPIOD_IS_OUT) - dm_gpio_set_value(&priv->gpiod, plat->value); + + if (plat->gpiod_flags == GPIOD_IS_OUT) { + ret = dm_gpio_set_value(&priv->gpiod, plat->value); + if (ret < 0) { + debug("%s: node %s could not set gpio.\n", __func__, + dev->name); + return ret; + } + } return 0; } @@ -213,32 +218,38 @@ int gpio_hog_probe_all(void) { struct udevice *dev; int ret; + int retval = 0; for (uclass_first_device(UCLASS_NOP, &dev); dev; uclass_find_next_device(&dev)) { if (dev->driver == DM_GET_DRIVER(gpio_hog)) { ret = device_probe(dev); - if (ret) - return ret; + if (ret) { + printf("Failed to probe device %s err: %d\n", + dev->name, ret); + retval = ret; + } } } - return 0; + return retval; } -struct gpio_desc *gpio_hog_lookup_name(const char *name) +int gpio_hog_lookup_name(const char *name, struct gpio_desc **desc) { struct udevice *dev; + *desc = NULL; gpio_hog_probe_all(); if (!uclass_get_device_by_name(UCLASS_NOP, name, &dev)) { struct gpio_hog_priv *priv = dev_get_priv(dev); - return &priv->gpiod; + *desc = &priv->gpiod; + return 0; } - return NULL; + return -ENODEV; } U_BOOT_DRIVER(gpio_hog) = { @@ -250,9 +261,9 @@ U_BOOT_DRIVER(gpio_hog) = { .platdata_auto_alloc_size = sizeof(struct gpio_hog_data), }; #else -struct gpio_desc *gpio_hog_lookup_name(const char *name) +int gpio_hog_lookup_name(const char *name, struct gpio_desc **desc) { - return NULL; + return 0; } #endif @@ -755,13 +766,45 @@ int dm_gpio_get_values_as_int(const struct gpio_desc *desc_list, int count) return vector; } +/** + * gpio_request_tail: common work for requesting a gpio. + * + * ret: return value from previous work in function which calls + * this function. + * This seems bogus (why calling this function instead not + * calling it and end caller function instead?). + * Because on error in caller function we want to set some + * default values in gpio desc and have a common error + * debug message, which provides this function. + * nodename: Name of node for which gpio gets requested + * used for gpio label name. + * args: pointer to output arguments structure + * list_name: Name of GPIO list + * used for gpio label name. + * index: gpio index in gpio list + * used for gpio label name. + * desc: pointer to gpio descriptor, filled from this + * function. + * flags: gpio flags to use. + * add_index: should index added to gpio label name + * gpio_dev: pointer to gpio device from which the gpio + * will be requested. If NULL try to get the + * gpio device with uclass_get_device_by_ofnode() + * + * return: In error case this function sets default values in + * gpio descriptor, also emmits a debug message. + * On success it returns 0 else the error code from + * function calls, or the error code passed through + * ret to this function. + * + */ static int gpio_request_tail(int ret, const char *nodename, struct ofnode_phandle_args *args, const char *list_name, int index, struct gpio_desc *desc, int flags, - bool add_index, struct udevice *dev) + bool add_index, struct udevice *gpio_dev) { - desc->dev = dev; + desc->dev = gpio_dev; desc->offset = 0; desc->flags = 0; if (ret) @@ -771,7 +814,8 @@ static int gpio_request_tail(int ret, const char *nodename, ret = uclass_get_device_by_ofnode(UCLASS_GPIO, args->node, &desc->dev); if (ret) { - debug("%s: uclass_get_device_by_ofnode failed\n", __func__); + debug("%s: uclass_get_device_by_ofnode failed\n", + __func__); goto err; } } @@ -989,10 +1033,8 @@ int gpio_dev_request_index(struct udevice *dev, const char *nodename, static int gpio_post_bind(struct udevice *dev) { -#if defined(CONFIG_DM_GPIO_HOG) struct udevice *child; ofnode node; -#endif #if defined(CONFIG_NEEDS_MANUAL_RELOC) struct dm_gpio_ops *ops = (struct dm_gpio_ops *)device_get_ops(dev); @@ -1024,16 +1066,21 @@ static int gpio_post_bind(struct udevice *dev) } #endif -#if defined(CONFIG_DM_GPIO_HOG) - dev_for_each_subnode(node, dev) { - if (ofnode_read_bool(node, "gpio-hog")) { - const char *name = ofnode_get_name(node); - - device_bind_driver_to_node(dev, "gpio_hog", name, - node, &child); + if (IS_ENABLED(CONFIG_GPIO_HOG)) { + dev_for_each_subnode(node, dev) { + if (ofnode_read_bool(node, "gpio-hog")) { + const char *name = ofnode_get_name(node); + int ret; + + ret = device_bind_driver_to_node(dev, + "gpio_hog", + name, node, + &child); + if (ret) + return ret; + } } } -#endif return 0; } diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 4772db3837..03d2fed341 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -12,18 +12,7 @@ config DM_I2C write and speed, is implemented with the bus drivers operations, which provide methods for bus setting and data transfer. Each chip device (bus child) info is kept as parent platdata. The interface - is defined in include/i2c.h. When i2c bus driver supports the i2c - uclass, but the device drivers not, then DM_I2C_COMPAT config can - be used as compatibility layer. - -config DM_I2C_COMPAT - bool "Enable I2C compatibility layer" - depends on DM - help - Enable old-style I2C functions for compatibility with existing code. - This option can be enabled as a temporary measure to avoid needing - to convert all code for a board in a single commit. It should not - be enabled for any board in an official release. + is defined in include/i2c.h. config I2C_CROS_EC_TUNNEL tristate "Chrome OS EC tunnel I2C bus" diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index dc40055efb..c2f75d8755 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -3,7 +3,6 @@ # (C) Copyright 2000-2007 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. obj-$(CONFIG_DM_I2C) += i2c-uclass.o -obj-$(CONFIG_DM_I2C_COMPAT) += i2c-uclass-compat.o obj-$(CONFIG_DM_I2C_GPIO) += i2c-gpio.o obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o diff --git a/drivers/i2c/i2c-uclass-compat.c b/drivers/i2c/i2c-uclass-compat.c deleted file mode 100644 index b3ade88113..0000000000 --- a/drivers/i2c/i2c-uclass-compat.c +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2014 Google, Inc - */ - -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <i2c.h> - -static int cur_busnum __attribute__((section(".data"))); - -static int i2c_compat_get_device(uint chip_addr, int alen, - struct udevice **devp) -{ - struct dm_i2c_chip *chip; - int ret; - - ret = i2c_get_chip_for_busnum(cur_busnum, chip_addr, alen, devp); - if (ret) - return ret; - chip = dev_get_parent_platdata(*devp); - if (chip->offset_len != alen) { - printf("I2C chip %x: requested alen %d does not match chip offset_len %d\n", - chip_addr, alen, chip->offset_len); - return -EADDRNOTAVAIL; - } - - return 0; -} - -int i2c_probe(uint8_t chip_addr) -{ - struct udevice *bus, *dev; - int ret; - - ret = uclass_get_device_by_seq(UCLASS_I2C, cur_busnum, &bus); - if (ret) { - debug("Cannot find I2C bus %d: err=%d\n", cur_busnum, ret); - return ret; - } - - if (!bus) - return -ENOENT; - - return dm_i2c_probe(bus, chip_addr, 0, &dev); -} - -int i2c_read(uint8_t chip_addr, unsigned int addr, int alen, uint8_t *buffer, - int len) -{ - struct udevice *dev; - int ret; - - ret = i2c_compat_get_device(chip_addr, alen, &dev); - if (ret) - return ret; - - return dm_i2c_read(dev, addr, buffer, len); -} - -int i2c_write(uint8_t chip_addr, unsigned int addr, int alen, uint8_t *buffer, - int len) -{ - struct udevice *dev; - int ret; - - ret = i2c_compat_get_device(chip_addr, alen, &dev); - if (ret) - return ret; - - return dm_i2c_write(dev, addr, buffer, len); -} - -int i2c_get_bus_num_fdt(int node) -{ - struct udevice *bus; - int ret; - - ret = uclass_get_device_by_of_offset(UCLASS_I2C, node, &bus); - if (ret) - return ret; - - return bus->seq; -} - -unsigned int i2c_get_bus_num(void) -{ - return cur_busnum; -} - -int i2c_set_bus_num(unsigned int bus) -{ - cur_busnum = bus; - - return 0; -} - -void i2c_init(int speed, int slaveaddr) -{ - /* Nothing to do here - the init happens through driver model */ -} - -void board_i2c_init(const void *blob) -{ - /* Nothing to do here - the init happens through driver model */ -} - -uint8_t i2c_reg_read(uint8_t chip_addr, uint8_t offset) -{ - struct udevice *dev; - int ret; - - ret = i2c_compat_get_device(chip_addr, 1, &dev); - if (ret) - return 0xff; - return dm_i2c_reg_read(dev, offset); -} - -void i2c_reg_write(uint8_t chip_addr, uint8_t offset, uint8_t val) -{ - struct udevice *dev; - int ret; - - ret = i2c_compat_get_device(chip_addr, 1, &dev); - if (!ret) - dm_i2c_reg_write(dev, offset, val); -} diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index c9aa13b409..eecc7d687e 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -2819,12 +2819,12 @@ int mmc_start_init(struct mmc *mmc) MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT; #if !defined(CONFIG_MMC_BROKEN_CD) - /* we pretend there's no card when init is NULL */ no_card = mmc_getcd(mmc) == 0; #else no_card = 0; #endif #if !CONFIG_IS_ENABLED(DM_MMC) + /* we pretend there's no card when init is NULL */ no_card = no_card || (mmc->cfg->ops->init == NULL); #endif if (no_card) { diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c index e0ac3e9d69..49085090c8 100644 --- a/drivers/mmc/mtk-sd.c +++ b/drivers/mmc/mtk-sd.c @@ -13,6 +13,7 @@ #include <errno.h> #include <malloc.h> #include <stdbool.h> +#include <watchdog.h> #include <asm/gpio.h> #include <dm/pinctrl.h> #include <linux/bitops.h> @@ -623,6 +624,8 @@ static int msdc_start_data(struct msdc_host *host, struct mmc_data *data) u32 size; int ret; + WATCHDOG_RESET(); + if (data->flags == MMC_DATA_WRITE) host->last_data_write = 1; diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c index bf26d2e4e2..f5f3e43247 100644 --- a/drivers/mmc/mv_sdhci.c +++ b/drivers/mmc/mv_sdhci.c @@ -114,6 +114,9 @@ static int mv_sdhci_probe(struct udevice *dev) host->name = MVSDH_NAME; host->ioaddr = (void *)devfdt_get_addr(dev); host->quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD; + host->mmc = &plat->mmc; + host->mmc->dev = dev; + host->mmc->priv = host; ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0); if (ret) @@ -124,9 +127,6 @@ static int mv_sdhci_probe(struct udevice *dev) sdhci_mvebu_mbus_config(host->ioaddr); } - host->mmc = &plat->mmc; - host->mmc->dev = dev; - host->mmc->priv = host; upriv->mmc = host->mmc; return sdhci_probe(dev); diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 0a0770cc20..2779bca93f 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -623,7 +623,7 @@ static int sdhci_init(struct mmc *mmc) #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO) struct udevice *dev = mmc->dev; - gpio_request_by_name(dev, "cd-gpio", 0, + gpio_request_by_name(dev, "cd-gpios", 0, &host->cd_gpio, GPIOD_IS_IN); #endif diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c index cfa9b535c8..724bbee752 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -31,6 +31,7 @@ #include <common.h> #include <asm/io.h> #include <nand.h> +#include <dm/uclass.h> #include <asm/ti-common/davinci_nand.h> /* Definitions for 4-bit hardware ECC */ @@ -730,7 +731,7 @@ static int nand_davinci_dev_ready(struct mtd_info *mtd) return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1; } -void davinci_nand_init(struct nand_chip *nand) +static void davinci_nand_init(struct nand_chip *nand) { #if defined CONFIG_KEYSTONE_RBL_NAND int i; @@ -738,8 +739,8 @@ void davinci_nand_init(struct nand_chip *nand) layout = &nand_keystone_rbl_4bit_layout_oobfirst; layout->oobavail = 0; - for (i = 0; layout->oobfree[i].length && - i < ARRAY_SIZE(layout->oobfree); i++) + for (i = 0; i < ARRAY_SIZE(layout->oobfree) && + layout->oobfree[i].length; i++) layout->oobavail += layout->oobfree[i].length; nand->write_page = nand_davinci_write_page; @@ -785,10 +786,53 @@ void davinci_nand_init(struct nand_chip *nand) nand->dev_ready = nand_davinci_dev_ready; } -int board_nand_init(struct nand_chip *chip) __attribute__((weak)); +#ifdef CONFIG_SYS_NAND_SELF_INIT +static int davinci_nand_probe(struct udevice *dev) +{ + struct nand_chip *nand = dev_get_priv(dev); + struct mtd_info *mtd = nand_to_mtd(nand); + int ret; + + nand->IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE; + nand->IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE; + + davinci_nand_init(nand); + + ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS); + if (ret) + return ret; + + return nand_register(0, mtd); +} + +static const struct udevice_id davinci_nand_ids[] = { + { .compatible = "ti,davinci-nand" }, + { } +}; + +U_BOOT_DRIVER(davinci_nand) = { + .name = "davinci-nand", + .id = UCLASS_MTD, + .of_match = davinci_nand_ids, + .probe = davinci_nand_probe, + .priv_auto_alloc_size = sizeof(struct nand_chip), +}; + +void board_nand_init(void) +{ + struct udevice *dev; + int ret; + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_GET_DRIVER(davinci_nand), &dev); + if (ret && ret != -ENODEV) + pr_err("Failed to initialize %s: %d\n", dev->name, ret); +} +#else +int board_nand_init(struct nand_chip *chip) __attribute__((weak)); int board_nand_init(struct nand_chip *chip) { davinci_nand_init(chip); return 0; } +#endif /* CONFIG_SYS_NAND_SELF_INIT */ diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 0a1d228a88..084e095229 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -196,7 +196,7 @@ config ETH_SANDBOX_RAW This driver is a bridge from the bottom of the network stack in U-Boot to the RAW AF_PACKET API in Linux. This allows real network traffic to be tested from within sandbox. See - board/sandbox/README.sandbox for more details. + doc/arch/index.rst for more details. config ETH_DESIGNWARE bool "Synopsys Designware Ethernet MAC" diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 938cc75496..3004335c57 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -14,6 +14,7 @@ #include "pinctrl-mtk-common.h" +#if CONFIG_IS_ENABLED(PINCONF) /** * struct mtk_drive_desc - the structure that holds the information * of the driving current @@ -39,6 +40,7 @@ static const struct mtk_drive_desc mtk_drive[] = { [DRV_GRP3] = { 2, 8, 2, 2 }, [DRV_GRP4] = { 2, 16, 2, 1 }, }; +#endif static const char *mtk_pinctrl_dummy_name = "_dummy"; diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c b/drivers/pinctrl/renesas/pfc-r8a7790.c index ef23ca278a..5e1502ed96 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7790.c +++ b/drivers/pinctrl/renesas/pfc-r8a7790.c @@ -4745,7 +4745,7 @@ static const struct sh_pfc_function pinmux_functions[] = { }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP( GP_0_31_FN, FN_IP3_17_15, GP_0_30_FN, FN_IP3_14_12, GP_0_29_FN, FN_IP3_11_8, @@ -4777,9 +4777,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, FN_IP0_11_9, GP_0_2_FN, FN_IP0_8_6, GP_0_1_FN, FN_IP0_5_3, - GP_0_0_FN, FN_IP0_2_0 } + GP_0_0_FN, FN_IP0_2_0 )) }, - { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP( 0, 0, 0, 0, GP_1_29_FN, FN_IP6_13_11, @@ -4811,9 +4811,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, FN_IP3_28_26, GP_1_2_FN, FN_IP3_25_23, GP_1_1_FN, FN_IP3_22_20, - GP_1_0_FN, FN_IP3_19_18, } + GP_1_0_FN, FN_IP3_19_18, )) }, - { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP( 0, 0, 0, 0, GP_2_29_FN, FN_IP7_15_13, @@ -4845,9 +4845,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, FN_IP8_3_2, GP_2_2_FN, FN_IP8_1_0, GP_2_1_FN, FN_IP7_30_29, - GP_2_0_FN, FN_IP7_28_27 } + GP_2_0_FN, FN_IP7_28_27 )) }, - { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP( GP_3_31_FN, FN_IP11_21_18, GP_3_30_FN, FN_IP11_17_15, GP_3_29_FN, FN_IP11_14_13, @@ -4879,9 +4879,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, FN_IP9_3_2, GP_3_2_FN, FN_IP9_1_0, GP_3_1_FN, FN_IP8_30_29, - GP_3_0_FN, FN_IP8_28 } + GP_3_0_FN, FN_IP8_28 )) }, - { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP( GP_4_31_FN, FN_IP14_18_16, GP_4_30_FN, FN_IP14_15_12, GP_4_29_FN, FN_IP14_11_9, @@ -4913,9 +4913,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, FN_IP11_31_30, GP_4_2_FN, FN_IP11_29_27, GP_4_1_FN, FN_IP11_26_24, - GP_4_0_FN, FN_IP11_23_22 } + GP_4_0_FN, FN_IP11_23_22 )) }, - { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP( GP_5_31_FN, FN_IP7_24_22, GP_5_30_FN, FN_IP7_21_19, GP_5_29_FN, FN_IP7_18_16, @@ -4947,10 +4947,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, FN_IP14_30_28, GP_5_2_FN, FN_IP14_27_25, GP_5_1_FN, FN_IP14_24_22, - GP_5_0_FN, FN_IP14_21_19 } + GP_5_0_FN, FN_IP14_21_19 )) }, { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, - 1, 4, 4, 3, 4, 4, 3, 3, 3, 3) { + GROUP(1, 4, 4, 3, 4, 4, 3, 3, 3, 3), + GROUP( /* IP0_31 [1] */ 0, 0, /* IP0_30_27 [4] */ @@ -4983,10 +4984,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, /* IP0_2_0 [3] */ FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, - 0, 0, 0, } + 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, - 2, 2, 2, 4, 4, 3, 3, 4, 4, 4) { + GROUP(2, 2, 2, 4, 4, 3, 3, 4, 4, 4), + GROUP( /* IP1_31_30 [2] */ 0, 0, 0, 0, /* IP1_29_28 [2] */ @@ -5020,10 +5022,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP1_3_0 [4] */ FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0, FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, - 0, 0, 0, 0, 0, 0, 0, 0, 0, } + 0, 0, 0, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, - 3, 3, 4, 4, 3, 3, 3, 3, 3, 3) { + GROUP(3, 3, 4, 4, 3, 3, 3, 3, 3, 3), + GROUP( /* IP2_31_29 [3] */ 0, 0, 0, 0, 0, 0, 0, 0, /* IP2_28_26 [3] */ @@ -5049,10 +5052,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP2_5_3 [3] */ FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0, /* IP2_2_0 [3] */ - FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, } + FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, - 3, 3, 3, 3, 2, 3, 3, 4, 4, 4) { + GROUP(3, 3, 3, 3, 2, 3, 3, 4, 4, 4), + GROUP( /* IP3_31_29 [3] */ FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, 0, 0, 0, @@ -5082,10 +5086,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP3_3_0 [4] */ FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0, - 0, 0, 0, 0, 0, 0, 0, 0, } + 0, 0, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, - 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3), + GROUP( /* IP4_31_30 [2] */ 0, 0, 0, 0, /* IP4_29_27 [3] */ @@ -5115,10 +5120,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0, /* IP4_2_0 [3] */ FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0, - } + )) }, { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, - 2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) { + GROUP(2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3), + GROUP( /* IP5_31_30 [2] */ 0, 0, 0, 0, /* IP5_29_27 [3] */ @@ -5152,10 +5158,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_INTC_EN0_N, FN_I2C1_SCL, /* IP5_2_0 [3] */ FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, - FN_VI2_R3, 0, 0, } + FN_VI2_R3, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, - 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) { + GROUP(3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3), + GROUP( /* IP6_31_29 [3] */ FN_ETH_REF_CLK, 0, FN_HCTS0_N_E, FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0, @@ -5188,10 +5195,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0, /* IP6_2_0 [3] */ FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, - FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, } + FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, - 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) { + GROUP(1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3), + GROUP( /* IP7_31 [1] */ 0, 0, /* IP7_30_29 [2] */ @@ -5223,11 +5231,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0, /* IP7_2_0 [3] */ FN_ETH_MDIO, 0, FN_HRTS0_N_E, - FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, } + FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, - 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2) { + GROUP(1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2, 2, 2, 2), + GROUP( /* IP8_31 [1] */ 0, 0, /* IP8_30_29 [2] */ @@ -5264,10 +5273,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP8_3_2 [2] */ FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0, /* IP8_1_0 [2] */ - FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, } + FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, - 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) { + GROUP(4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2), + GROUP( /* IP9_31_28 [4] */ FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D, @@ -5299,10 +5309,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP9_3_2 [2] */ FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0, /* IP9_1_0 [2] */ - FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, } + FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, - 2, 4, 3, 4, 4, 4, 4, 3, 4) { + GROUP(2, 4, 3, 4, 4, 4, 4, 3, 4), + GROUP( /* IP10_31_30 [2] */ 0, 0, 0, 0, /* IP10_29_26 [4] */ @@ -5338,10 +5349,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP10_3_0 [4] */ FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D, - FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, } + FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, - 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) { + GROUP(2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4), + GROUP( /* IP11_31_30 [2] */ FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0, /* IP11_29_27 [3] */ @@ -5373,10 +5385,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP11_3_0 [4] */ FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, - FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, } + FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, - 1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) { + GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2), + GROUP( /* IP12_31 [1] */ 0, 0, /* IP12_30_28 [3] */ @@ -5412,10 +5425,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP12_3_2 [2] */ FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0, /* IP12_1_0 [2] */ - FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, } + FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, - 1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) { + GROUP(1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3), + GROUP( /* IP13_31 [1] */ 0, 0, /* IP13_30_29 [2] */ @@ -5448,10 +5462,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0, /* IP13_2_0 [3] */ FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, - FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, } + FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, - 1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) { + GROUP(1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3), + GROUP( /* IP14_30 [1] */ 0, 0, /* IP14_30_28 [3] */ @@ -5486,10 +5501,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP14_2_0 [3] */ FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, - FN_REMOCON, 0, } + FN_REMOCON, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, - 2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) { + GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3), + GROUP( /* IP15_31_30 [2] */ 0, 0, 0, 0, /* IP15_29_28 [2] */ @@ -5521,10 +5537,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_IIC2_SCL, FN_I2C2_SCL, 0, /* IP15_2_0 [3] */ FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7, - FN_LCDOUT15, FN_SCIF_CLK_B, 0, } + FN_LCDOUT15, FN_SCIF_CLK_B, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, - 4, 4, 4, 4, 4, 4, 1, 1, 3, 3) { + GROUP(4, 4, 4, 4, 4, 4, 1, 1, 3, 3), + GROUP( /* IP16_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -5552,11 +5569,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0, /* IP16_2_0 [3] */ FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, - FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, } + FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, - 3, 2, 2, 3, 2, 1, 1, 1, 2, 1, - 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) { + GROUP(3, 2, 2, 3, 2, 1, 1, 1, 2, 1, 2, 1, + 1, 1, 1, 2, 1, 1, 2, 1, 1), + GROUP( /* SEL_SCIF1 [3] */ FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, FN_SEL_SCIF1_4, 0, 0, 0, @@ -5602,11 +5620,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_SOF3 [1] */ FN_SEL_SOF3_0, FN_SEL_SOF3_1, /* SEL_SOF0 [1] */ - FN_SEL_SOF0_0, FN_SEL_SOF0_1, } + FN_SEL_SOF0_0, FN_SEL_SOF0_1, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, - 3, 1, 1, 1, 2, 1, 2, 1, 2, - 1, 1, 1, 3, 3, 2, 3, 2, 2) { + GROUP(3, 1, 1, 1, 2, 1, 2, 1, 2, 1, 1, 1, + 3, 3, 2, 3, 2, 2), + GROUP( /* RESERVED [3] */ 0, 0, 0, 0, 0, 0, 0, 0, /* SEL_TMU1 [1] */ @@ -5644,11 +5663,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_SIM [2] */ FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0, /* SEL_SSI8 [2] */ - FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, } + FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, - 1, 1, 2, 4, 4, 2, 2, - 4, 2, 3, 2, 3, 2) { + GROUP(1, 1, 2, 4, 4, 2, 2, 4, 2, 3, 2, 3, 2), + GROUP( /* SEL_IICDVFS [1] */ FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, /* SEL_IIC0 [1] */ @@ -5679,7 +5698,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, FN_SEL_I2C2_4, 0, 0, 0, /* SEL_I2C1 [2] */ - FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, } + FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, )) }, { }, }; diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c b/drivers/pinctrl/renesas/pfc-r8a7791.c index 8166955459..d6095d6f67 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7791.c +++ b/drivers/pinctrl/renesas/pfc-r8a7791.c @@ -5431,7 +5431,7 @@ static const struct { }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP( GP_0_31_FN, FN_IP1_22_20, GP_0_30_FN, FN_IP1_19_17, GP_0_29_FN, FN_IP1_16_14, @@ -5463,9 +5463,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, FN_IP0_3, GP_0_2_FN, FN_IP0_2, GP_0_1_FN, FN_IP0_1, - GP_0_0_FN, FN_IP0_0, } + GP_0_0_FN, FN_IP0_0, )) }, - { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5497,9 +5497,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, FN_IP2_2_0, GP_1_2_FN, FN_IP1_31_29, GP_1_1_FN, FN_IP1_28_26, - GP_1_0_FN, FN_IP1_25_23, } + GP_1_0_FN, FN_IP1_25_23, )) }, - { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP( GP_2_31_FN, FN_IP6_7_6, GP_2_30_FN, FN_IP6_5_3, GP_2_29_FN, FN_IP6_2_0, @@ -5531,9 +5531,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, FN_IP4_4_2, GP_2_2_FN, FN_IP4_1_0, GP_2_1_FN, FN_IP3_30_28, - GP_2_0_FN, FN_IP3_27_25 } + GP_2_0_FN, FN_IP3_27_25 )) }, - { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP( GP_3_31_FN, FN_IP9_18_17, GP_3_30_FN, FN_IP9_16, GP_3_29_FN, FN_IP9_15_13, @@ -5565,9 +5565,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, FN_IP7_12_11, GP_3_2_FN, FN_IP7_10_9, GP_3_1_FN, FN_IP7_8_6, - GP_3_0_FN, FN_IP7_5_3 } + GP_3_0_FN, FN_IP7_5_3 )) }, - { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP( GP_4_31_FN, FN_IP15_5_4, GP_4_30_FN, FN_IP15_3_2, GP_4_29_FN, FN_IP15_1_0, @@ -5599,9 +5599,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, FN_IP9_24_23, GP_4_2_FN, FN_IP9_22_21, GP_4_1_FN, FN_IP9_20_19, - GP_4_0_FN, FN_VI0_CLK } + GP_4_0_FN, FN_VI0_CLK )) }, - { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP( GP_5_31_FN, FN_IP3_24_22, GP_5_30_FN, FN_IP13_9_7, GP_5_29_FN, FN_IP13_6_5, @@ -5633,9 +5633,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, FN_IP11_18_17, GP_5_2_FN, FN_IP11_16_15, GP_5_1_FN, FN_IP11_14_12, - GP_5_0_FN, FN_IP11_11_9 } + GP_5_0_FN, FN_IP11_11_9 )) }, - { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { + { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP( GP_6_31_FN, FN_DU0_DOTCLKIN, GP_6_30_FN, FN_USB1_OVC, GP_6_29_FN, FN_IP14_31_29, @@ -5667,9 +5667,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_3_FN, FN_IP13_13, GP_6_2_FN, FN_IP13_12, GP_6_1_FN, FN_IP13_11, - GP_6_0_FN, FN_IP13_10 } + GP_6_0_FN, FN_IP13_10 )) }, - { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) { + { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5701,11 +5701,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_7_3_FN, FN_IP15_26_24, GP_7_2_FN, FN_IP15_23_21, GP_7_1_FN, FN_IP15_20_18, - GP_7_0_FN, FN_IP15_17_15 } + GP_7_0_FN, FN_IP15_17_15 )) }, { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, - 1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( /* IP0_31 [1] */ 0, 0, /* IP0_30_29 [2] */ @@ -5760,10 +5761,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP0_1 [1] */ FN_D1, 0, /* IP0_0 [1] */ - FN_D0, 0, } + FN_D0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, - 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) { + GROUP(3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2), + GROUP( /* IP1_31_29 [3] */ FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C, 0, 0, 0, @@ -5796,10 +5798,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 0, /* IP1_1_0 [2] */ FN_A7, FN_MSIOF1_SYNC, - 0, 0, } + 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, - 2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) { + GROUP(2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3), + GROUP( /* IP2_31_30 [2] */ 0, 0, 0, 0, /* IP2_29_27 [3] */ @@ -5832,10 +5835,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_A20, FN_SPCLK, 0, 0, /* IP2_2_0 [3] */ FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0, - FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, } + FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, - 1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) { + GROUP(1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3), + GROUP( /* IP3_31 [1] */ 0, 0, /* IP3_30_28 [3] */ @@ -5870,10 +5874,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0, /* IP3_2_0 [3] */ FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2, - 0, 0, 0, } + 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, - 1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) { + GROUP(1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, + 3, 3, 2), + GROUP( /* IP4_31 [1] */ 0, 0, /* IP4_30_28 [3] */ @@ -5912,10 +5918,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_MSIOF2_SYNC_C, FN_GLO_I0_D, 0, 0, 0, /* IP4_1_0 [2] */ - FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C, } + FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C, + )) }, { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, - 3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) { + GROUP(3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3), + GROUP( /* IP5_31_29 [3] */ FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D, 0, 0, 0, 0, 0, @@ -5950,10 +5958,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP5_2_0 [3] */ FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1, FN_MSIOF2_TXD_D, FN_VI1_R3_B, - 0, 0, } + 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, - 2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) { + GROUP(2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3), + GROUP( /* IP6_31_30 [2] */ 0, 0, 0, 0, /* IP6_29_27 [3] */ @@ -5990,10 +5999,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP6_2_0 [3] */ FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B, FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E, - 0, 0, } + 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, - 2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) { + GROUP(2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3), + GROUP( /* IP7_31_30 [2] */ 0, 0, 0, 0, /* IP7_29_27 [3] */ @@ -6031,10 +6041,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP7_2_0 [3] */ FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C, FN_SCIF_CLK_B, FN_GPS_MAG_D, - 0, 0, } + 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, - 1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) { + GROUP(1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3), + GROUP( /* IP8_31 [1] */ 0, 0, /* IP8_30_28 [3] */ @@ -6074,10 +6085,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, /* IP8_2_0 [3] */ FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B, - 0, 0, 0, } + 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, - 3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) { + GROUP(3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, + 1, 1, 3, 3), + GROUP( /* IP9_31_29 [3] */ FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL, FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0, @@ -6117,10 +6130,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, /* IP9_2_0 [3] */ FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD, - 0, 0, 0, } + 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, - 3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) { + GROUP(3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3), + GROUP( /* IP10_31_29 [3] */ FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D, 0, 0, 0, @@ -6154,11 +6168,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0, /* IP10_2_0 [3] */ FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA, - FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, } + FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, - 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, - 3, 3, 3, 3, 3) { + GROUP(2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, + 2, 3, 3, 3, 3, 3), + GROUP( /* IP11_31_30 [2] */ FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 0, /* IP11_29_28 [2] */ @@ -6201,10 +6216,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, /* IP11_2_0 [3] */ FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, - FN_I2C1_SDA_D, 0, 0, 0, } + FN_I2C1_SDA_D, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, - 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) { + GROUP(2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2), + GROUP( /* IP12_31_30 [2] */ 0, 0, 0, 0, /* IP12_29_27 [3] */ @@ -6242,11 +6258,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP12_3_2 [2] */ FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA, /* IP12_1_0 [2] */ - FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, } + FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, )) }, { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, - 1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1, - 3, 2, 2, 3) { + GROUP(1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, + 1, 1, 1, 3, 2, 2, 3), + GROUP( /* IP13_31 [1] */ 0, 0, /* IP13_30_28 [3] */ @@ -6293,10 +6310,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP13_2_0 [3] */ FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C, FN_ADICLK_B, FN_MSIOF0_SS1_C, - 0, 0, 0, } + 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, - 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) { + GROUP(3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, + 1, 1, 2), + GROUP( /* IP14_31_29 [3] */ FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E, FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 0, @@ -6336,10 +6355,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP14_2 [1] */ FN_SD2_CLK, FN_MMC_CLK, /* IP14_1_0 [2] */ - FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, } + FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, - 2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) { + GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2), + GROUP( /* IP15_31_30 [2] */ 0, 0, 0, 0, /* IP15_29_27 [3] */ @@ -6377,10 +6397,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP15_3_2 [2] */ FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0, /* IP15_1_0 [2] */ - FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, } + FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, - 4, 4, 4, 4, 4, 2, 2, 2, 3, 3) { + GROUP(4, 4, 4, 4, 4, 2, 2, 2, 3, 3), + GROUP( /* IP16_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -6409,11 +6430,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP16_2_0 [3] */ FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C, - 0, 0, 0, } + 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, - 1, 2, 2, 2, 3, 2, 1, 1, 1, 1, - 3, 2, 2, 2, 1, 2, 2, 2) { + GROUP(1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 3, 2, + 2, 2, 1, 2, 2, 2), + GROUP( /* RESERVED [1] */ 0, 0, /* SEL_SCIF1 [2] */ @@ -6454,11 +6476,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_TSIF0 [2] */ FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, /* SEL_SOF0 [2] */ - FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, } + FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, - 3, 1, 1, 3, 2, 1, 1, 2, 2, - 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) { + GROUP(3, 1, 1, 3, 2, 1, 1, 2, 2, 1, 3, 2, + 1, 2, 2, 2, 1, 1, 1), + GROUP( /* SEL_SCIF0 [3] */ FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, FN_SEL_SCIF0_4, @@ -6502,11 +6525,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* RESERVED [1] */ 0, 0, /* SEL_SSI8 [1] */ - FN_SEL_SSI8_0, FN_SEL_SSI8_1, } + FN_SEL_SSI8_0, FN_SEL_SSI8_1, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, - 2, 2, 2, 2, 2, 2, 2, 2, - 1, 1, 2, 2, 3, 2, 2, 2, 1) { + GROUP(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 2, 2, + 3, 2, 2, 2, 1), + GROUP( /* SEL_HSCIF2 [2] */ FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3, @@ -6544,11 +6568,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* RESERVED [2] */ 0, 0, 0, 0, /* RESERVED [1] */ - 0, 0, } + 0, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32, - 3, 2, 2, 1, 1, 1, 1, 3, 2, - 2, 3, 1, 1, 1, 2, 2, 2, 2) { + GROUP(3, 2, 2, 1, 1, 1, 1, 3, 2, 2, 3, 1, + 1, 1, 2, 2, 2, 2), + GROUP( /* SEL_SOF1 [3] */ FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, FN_SEL_SOF1_4, @@ -6590,7 +6615,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* RESERVED [2] */ 0, 0, 0, 0, /* RESERVED [2] */ - 0, 0, 0, 0, } + 0, 0, 0, 0, )) }, { }, }; diff --git a/drivers/pinctrl/renesas/pfc-r8a7792.c b/drivers/pinctrl/renesas/pfc-r8a7792.c index 95bb5237d9..1c90412093 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7792.c +++ b/drivers/pinctrl/renesas/pfc-r8a7792.c @@ -1991,7 +1991,7 @@ static const struct sh_pfc_function pinmux_functions[] = { }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2023,9 +2023,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, FN_IP0_3, GP_0_2_FN, FN_IP0_2, GP_0_1_FN, FN_IP0_1, - GP_0_0_FN, FN_IP0_0 } + GP_0_0_FN, FN_IP0_0 )) }, - { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2057,9 +2057,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, FN_IP1_8, GP_1_2_FN, FN_IP1_7, GP_1_1_FN, FN_IP1_6, - GP_1_0_FN, FN_IP1_5, } + GP_1_0_FN, FN_IP1_5, )) }, - { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP( GP_2_31_FN, FN_A15, GP_2_30_FN, FN_A14, GP_2_29_FN, FN_A13, @@ -2091,9 +2091,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, FN_D3, GP_2_2_FN, FN_D2, GP_2_1_FN, FN_D1, - GP_2_0_FN, FN_D0 } + GP_2_0_FN, FN_D0 )) }, - { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2125,9 +2125,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, FN_A19, GP_3_2_FN, FN_A18, GP_3_1_FN, FN_A17, - GP_3_0_FN, FN_A16 } + GP_3_0_FN, FN_A16 )) }, - { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2159,9 +2159,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, FN_VI0_VSYNC_N, GP_4_2_FN, FN_VI0_HSYNC_N, GP_4_1_FN, FN_VI0_CLKENB, - GP_4_0_FN, FN_VI0_CLK } + GP_4_0_FN, FN_VI0_CLK )) }, - { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2193,9 +2193,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, FN_VI1_VSYNC_N, GP_5_2_FN, FN_VI1_HSYNC_N, GP_5_1_FN, FN_VI1_CLKENB, - GP_5_0_FN, FN_VI1_CLK } + GP_5_0_FN, FN_VI1_CLK )) }, - { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { + { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2227,9 +2227,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_3_FN, FN_IP2_3, GP_6_2_FN, FN_IP2_2, GP_6_1_FN, FN_IP2_1, - GP_6_0_FN, FN_IP2_0 } + GP_6_0_FN, FN_IP2_0 )) }, - { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1) { + { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2261,9 +2261,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_7_3_FN, FN_IP3_3, GP_7_2_FN, FN_IP3_2, GP_7_1_FN, FN_IP3_1, - GP_7_0_FN, FN_IP3_0 } + GP_7_0_FN, FN_IP3_0 )) }, - { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1) { + { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2295,9 +2295,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_8_3_FN, FN_IP4_3_2, GP_8_2_FN, FN_IP4_1, GP_8_1_FN, FN_IP4_0, - GP_8_0_FN, FN_VI4_CLK } + GP_8_0_FN, FN_VI4_CLK )) }, - { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1) { + { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2329,9 +2329,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_9_3_FN, FN_IP5_2, GP_9_2_FN, FN_IP5_1, GP_9_1_FN, FN_IP5_0, - GP_9_0_FN, FN_VI5_CLK } + GP_9_0_FN, FN_VI5_CLK )) }, - { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1) { + { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1, GROUP( GP_10_31_FN, FN_CAN1_RX, GP_10_30_FN, FN_CAN1_TX, GP_10_29_FN, FN_CAN_CLK, @@ -2363,9 +2363,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_10_3_FN, FN_IP6_2, GP_10_2_FN, FN_HRTS0_N, GP_10_1_FN, FN_IP6_1, - GP_10_0_FN, FN_IP6_0 } + GP_10_0_FN, FN_IP6_0 )) }, - { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1) { + { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1, GROUP( 0, 0, 0, 0, GP_11_29_FN, FN_AVS2, @@ -2397,13 +2397,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_11_3_FN, FN_IP7_6, GP_11_2_FN, FN_IP7_5_4, GP_11_1_FN, FN_IP7_3_2, - GP_11_0_FN, FN_IP7_1_0 } + GP_11_0_FN, FN_IP7_1_0 )) }, { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32, - 4, 4, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(4, 4, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( /* IP0_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP0_27_24 [4] */ @@ -2455,13 +2456,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP0_1 [1] */ FN_DU0_DR1_DATA1, 0, /* IP0_0 [1] */ - FN_DU0_DR0_DATA0, 0 } + FN_DU0_DR0_DATA0, 0 )) }, { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32, - 4, 4, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(4, 4, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( /* IP1_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP1_27_24 [4] */ @@ -2513,13 +2515,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP1_1 [1] */ FN_DU0_EXVSYNC_DU0_VSYNC, 0, /* IP1_0 [1] */ - FN_DU0_EXHSYNC_DU0_HSYNC, 0 } + FN_DU0_EXHSYNC_DU0_HSYNC, 0 )) }, { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32, - 4, 4, - 4, 3, 1, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(4, 4, + 4, 3, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( /* IP2_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP2_27_24 [4] */ @@ -2561,13 +2564,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP2_1 [1] */ FN_VI2_CLKENB, FN_AVB_RX_DV, /* IP2_0 [1] */ - FN_VI2_CLK, FN_AVB_RX_CLK } + FN_VI2_CLK, FN_AVB_RX_CLK )) }, { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32, - 4, 4, - 4, 4, - 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(4, 4, + 4, 4, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( /* IP3_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP3_27_24 [4] */ @@ -2607,12 +2611,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP3_1 [1] */ FN_VI3_CLKENB, FN_AVB_TXD4, /* IP3_0 [1] */ - FN_VI3_CLK, FN_AVB_TX_CLK } + FN_VI3_CLK, FN_AVB_TX_CLK )) }, { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32, - 4, 3, 1, - 1, 1, 1, 2, 2, 2, - 2, 2, 2, 2, 2, 1, 2, 1, 1) { + GROUP(4, 3, 1, + 1, 1, 1, 2, 2, 2, + 2, 2, 2, 2, 2, 1, 2, 1, 1), + GROUP( /* IP4_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP4_27_25 [3] */ @@ -2648,13 +2653,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP4_1 [1] */ FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5, /* IP4_0 [1] */ - FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 } + FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 )) }, { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32, - 4, 4, - 4, 4, - 4, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(4, 4, + 4, 4, + 4, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( /* IP5_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP5_27_24 [4] */ @@ -2688,13 +2694,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP5_1 [1] */ FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B, /* IP5_0 [1] */ - FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B } + FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B )) }, { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32, - 4, 4, - 4, 1, 2, 1, - 2, 2, 2, 2, - 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(4, 4, + 4, 1, 2, 1, + 2, 2, 2, 2, + 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( /* IP6_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP6_27_24 [4] */ @@ -2730,13 +2737,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP6_1 [1] */ FN_MSIOF0_SYNC, FN_HCTS0_N, /* IP6_0 [1] */ - FN_MSIOF0_SCK, FN_HSCK0 } + FN_MSIOF0_SCK, FN_HSCK0 )) }, { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32, - 4, 4, - 3, 1, 1, 1, 1, 1, - 2, 2, 2, 2, - 1, 1, 2, 2, 2) { + GROUP(4, 4, + 3, 1, 1, 1, 1, 1, + 2, 2, 2, 2, + 1, 1, 2, 2, 2), + GROUP( /* IP7_31_28 [4] */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP7_27_24 [4] */ @@ -2770,7 +2778,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP7_3_2 [2] */ FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0, /* IP7_1_0 [2] */ - FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 } + FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 )) }, { }, }; diff --git a/drivers/pinctrl/renesas/pfc-r8a7794.c b/drivers/pinctrl/renesas/pfc-r8a7794.c index 657ebca783..91ac815f3d 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7794.c +++ b/drivers/pinctrl/renesas/pfc-r8a7794.c @@ -4619,7 +4619,7 @@ static const struct sh_pfc_function pinmux_functions[] = { }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP( GP_0_31_FN, FN_IP2_17_16, GP_0_30_FN, FN_IP2_15_14, GP_0_29_FN, FN_IP2_13_12, @@ -4651,9 +4651,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, FN_IP0_27_26, GP_0_2_FN, FN_IP0_25, GP_0_1_FN, FN_IP0_24, - GP_0_0_FN, FN_IP0_23_22, } + GP_0_0_FN, FN_IP0_23_22, )) }, - { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4685,9 +4685,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, FN_IP2_29_27, GP_1_2_FN, FN_IP2_26_24, GP_1_1_FN, FN_IP2_23_21, - GP_1_0_FN, FN_IP2_20_18, } + GP_1_0_FN, FN_IP2_20_18, )) }, - { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP( GP_2_31_FN, FN_IP6_7_6, GP_2_30_FN, FN_IP6_5_4, GP_2_29_FN, FN_IP6_3_2, @@ -4719,9 +4719,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, FN_IP4_11_10, GP_2_2_FN, FN_IP4_9_8, GP_2_1_FN, FN_IP4_7_5, - GP_2_0_FN, FN_IP4_4_2 } + GP_2_0_FN, FN_IP4_4_2 )) }, - { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP( GP_3_31_FN, FN_IP8_22_20, GP_3_30_FN, FN_IP8_19_17, GP_3_29_FN, FN_IP8_16_15, @@ -4753,9 +4753,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, FN_IP6_11, GP_3_2_FN, FN_IP6_10, GP_3_1_FN, FN_IP6_9, - GP_3_0_FN, FN_IP6_8 } + GP_3_0_FN, FN_IP6_8 )) }, - { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP( GP_4_31_FN, FN_IP11_17_16, GP_4_30_FN, FN_IP11_15_14, GP_4_29_FN, FN_IP11_13_11, @@ -4787,9 +4787,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, FN_IP9_2_0, GP_4_2_FN, FN_IP8_31_29, GP_4_1_FN, FN_IP8_28_26, - GP_4_0_FN, FN_IP8_25_23 } + GP_4_0_FN, FN_IP8_25_23 )) }, - { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4821,9 +4821,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, FN_IP11_29_27, GP_5_2_FN, FN_IP11_26_24, GP_5_1_FN, FN_IP11_23_21, - GP_5_0_FN, FN_IP11_20_18 } + GP_5_0_FN, FN_IP11_20_18 )) }, - { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { + { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4855,11 +4855,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_3_FN, FN_SD0_DATA1, GP_6_2_FN, FN_SD0_DATA0, GP_6_1_FN, FN_SD0_CMD, - GP_6_0_FN, FN_SD0_CLK } + GP_6_0_FN, FN_SD0_CLK )) }, { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, - 2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, - 2, 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, + 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( /* IP0_31_30 [2] */ FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0, /* IP0_29_28 [2] */ @@ -4909,11 +4910,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP0_1 [1] */ 0, 0, /* IP0_0 [1] */ - FN_SD1_CD, FN_CAN0_RX, } + FN_SD1_CD, FN_CAN0_RX, )) }, { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, - 2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2, 3, 2, 2, - 2, 2) { + GROUP(2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2, + 3, 2, 2, 2, 2), + GROUP( /* IP1_31_30 [2] */ FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C, /* IP1_29_28 [2] */ @@ -4949,10 +4951,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP1_3_2 [2] */ FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B, /* IP1_1_0 [2] */ - FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, } + FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, - 2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2) { + GROUP(2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2), + GROUP( /* IP2_31_30 [2] */ FN_A20, FN_SPCLK, 0, 0, /* IP2_29_27 [3] */ @@ -4984,10 +4987,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP2_3_2 [2] */ FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0, /* IP2_1_0 [2] */ - FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, } + FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, - 1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2, 2, 2, 2, 2) { + GROUP(1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2, + 2, 2, 2, 2), + GROUP( /* IP3_31 [1] */ FN_RD_WR_N, FN_ATAG1_N, /* IP3_30 [1] */ @@ -5024,10 +5029,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP3_3_2 [2] */ FN_A22, FN_MISO_IO1, 0, FN_ATADIR1_N, /* IP3_1_0 [2] */ - FN_A21, FN_MOSI_IO0, 0, 0, } + FN_A21, FN_MOSI_IO0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, - 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2) { + GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2), + GROUP( /* IP4_31_30 [2] */ FN_DU0_DG4, FN_LCDOUT12, 0, 0, /* IP4_29_28 [2] */ @@ -5059,10 +5065,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, 0, 0, 0, 0, /* IP4_1_0 [2] */ - FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, } + FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, - 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2) { + GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, + 2, 2, 2), + GROUP( /* IP5_31_30 [2] */ FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 0, 0, /* IP5_29_28 [2] */ @@ -5094,11 +5102,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP5_3_2 [2] */ FN_DU0_DG6, FN_LCDOUT14, 0, 0, /* IP5_1_0 [2] */ - FN_DU0_DG5, FN_LCDOUT13, 0, 0, } + FN_DU0_DG5, FN_LCDOUT13, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, - 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, - 2, 2) { + GROUP(3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 2, 2, 2, 2), + GROUP( /* IP6_31_29 [3] */ FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, FN_AVB_TX_CLK, FN_ADIDATA, 0, 0, @@ -5140,10 +5149,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, /* IP6_1_0 [2] */ - FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, } + FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, - 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3), + GROUP( /* IP7_31 [1] */ FN_DREQ0_N, FN_SCIFB1_RXD, /* IP7_30 [1] */ @@ -5177,10 +5187,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_AVB_TXD1, FN_ADICLK, 0, 0, /* IP7_2_0 [3] */ FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, - FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, } + FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, - 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) { + GROUP(3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3), + GROUP( /* IP8_31_29 [3] */ FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, 0, FN_TS_SDEN_D, FN_FMCLK_C, 0, @@ -5212,10 +5223,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0, /* IP8_2_0 [3] */ FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, - FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, } + FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, - 1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3) { + GROUP(1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3), + GROUP( /* IP9_31 [1] */ 0, 0, /* IP9_30_28 [3] */ @@ -5248,10 +5260,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, FN_TPUTO1_C, 0, 0, /* IP9_2_0 [3] */ FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, - 0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, } + 0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, - 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3), + GROUP( /* IP10_31_30 [2] */ FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, 0, /* IP10_29_27 [3] */ @@ -5283,10 +5296,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, /* IP10_2_0 [3] */ FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, - 0, 0, 0, 0, } + 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, - 2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) { + GROUP(2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3), + GROUP( /* IP11_31_30 [2] */ 0, 0, 0, 0, /* IP11_29_27 [3] */ @@ -5318,10 +5332,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, /* IP11_2_0 [3] */ FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, - 0, 0, 0, 0, } + 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, - 2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3) { + GROUP(2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3), + GROUP( /* IP12_31_30 [2] */ 0, 0, 0, 0, /* IP12_29_27 [3] */ @@ -5353,10 +5368,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_CAN1_RX_C, FN_DACK1_B, 0, 0, /* IP12_2_0 [3] */ FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B, - 0, FN_DREQ1_N_B, 0, 0, } + 0, FN_DREQ1_N_B, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, - 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + GROUP(1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3), + GROUP( /* IP13_31 [1] */ 0, 0, /* IP13_30 [1] */ @@ -5393,11 +5409,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_VI1_DATA4, 0, FN_ATACS10_N, FN_ETH_REFCLK_B, 0, /* IP13_2_0 [3] */ FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, - 0, FN_ATACS00_N, FN_ETH_LINK_B, 0, } + 0, FN_ATACS00_N, FN_ETH_LINK_B, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, - 2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3, - 2, 1) { + GROUP(2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3, 2, 1), + GROUP( /* SEL_ADG [2] */ FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, /* RESERVED [1] */ @@ -5431,11 +5447,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_I2C05 [2] */ FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3, /* RESERVED [1] */ - 0, 0, } + 0, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, - 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, - 2, 2, 2, 1, 1, 2) { + GROUP(2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, + 2, 2, 1, 1, 2, 2, 2, 1, 1, 2), + GROUP( /* SEL_IEB [2] */ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, /* SEL_IIC0 [2] */ @@ -5482,11 +5499,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_HSCIF1 [1] */ FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, /* RESERVED [2] */ - 0, 0, 0, 0, } + 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, - 2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( /* SEL_SCIF0 [2] */ FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, /* SEL_SCIF1 [2] */ @@ -5539,7 +5557,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* RESERVED [1] */ 0, 0, /* RESERVED [1] */ - 0, 0, } + 0, 0, )) }, { }, }; diff --git a/drivers/pinctrl/renesas/pfc-r8a7795.c b/drivers/pinctrl/renesas/pfc-r8a7795.c index 89ae6f6ed7..ba17a55775 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7795.c +++ b/drivers/pinctrl/renesas/pfc-r8a7795.c @@ -2,7 +2,7 @@ /* * R8A7795 ES2.0+ processor support - PFC hardware block. * - * Copyright (C) 2015-2017 Renesas Electronics Corporation + * Copyright (C) 2015-2019 Renesas Electronics Corporation */ #include <common.h> @@ -202,8 +202,8 @@ #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20) /* GPSR7 */ -#define GPSR7_3 FM(HDMI1_CEC) -#define GPSR7_2 FM(HDMI0_CEC) +#define GPSR7_3 FM(GP7_03) +#define GPSR7_2 FM(GP7_02) #define GPSR7_1 FM(AVS2) #define GPSR7_0 FM(AVS1) @@ -352,7 +352,7 @@ #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) @@ -463,7 +463,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) -#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3) +#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3) /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) @@ -499,8 +499,8 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) -#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1) -#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1) +#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1) +#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1) #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) #define PINMUX_MOD_SELS \ @@ -592,8 +592,8 @@ static const u16 pinmux_data[] = { PINMUX_SINGLE(AVS1), PINMUX_SINGLE(AVS2), PINMUX_SINGLE(CLKOUT), - PINMUX_SINGLE(HDMI0_CEC), - PINMUX_SINGLE(HDMI1_CEC), + PINMUX_SINGLE(GP7_02), + PINMUX_SINGLE(GP7_03), PINMUX_SINGLE(MSIOF0_RXD), PINMUX_SINGLE(MSIOF0_SCK), PINMUX_SINGLE(MSIOF0_TXD), @@ -1131,7 +1131,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP11_27_24, SCK0), PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), - PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1), + PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1), PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), @@ -1164,7 +1164,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N), PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), - PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1), + PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1), PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), @@ -1223,7 +1223,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0), + PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0), PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), @@ -1270,7 +1270,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A), - PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2), + PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2), PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), @@ -1279,7 +1279,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0), + PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0), PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0), PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), @@ -1410,10 +1410,9 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), /* IPSR17 */ - PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0), - PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT), + PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0), - PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1), + PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1), PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), @@ -2133,22 +2132,6 @@ static const unsigned int du_disp_mux[] = { DU_DISP_MARK, }; -/* - HDMI ------------------------------------------------------------------- */ -static const unsigned int hdmi0_cec_pins[] = { - /* HDMI0_CEC */ - RCAR_GP_PIN(7, 2), -}; -static const unsigned int hdmi0_cec_mux[] = { - HDMI0_CEC_MARK, -}; -static const unsigned int hdmi1_cec_pins[] = { - /* HDMI1_CEC */ - RCAR_GP_PIN(7, 3), -}; -static const unsigned int hdmi1_cec_mux[] = { - HDMI1_CEC_MARK, -}; - /* - HSCIF0 ----------------------------------------------------------------- */ static const unsigned int hscif0_data_pins[] = { /* RX, TX */ @@ -4227,8 +4210,6 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du_oddf), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), - SH_PFC_PIN_GROUP(hdmi0_cec), - SH_PFC_PIN_GROUP(hdmi1_cec), SH_PFC_PIN_GROUP(hscif0_data), SH_PFC_PIN_GROUP(hscif0_clk), SH_PFC_PIN_GROUP(hscif0_ctrl), @@ -4613,14 +4594,6 @@ static const char * const du_groups[] = { "du_disp", }; -static const char * const hdmi0_groups[] = { - "hdmi0_cec", -}; - -static const char * const hdmi1_groups[] = { - "hdmi1_cec", -}; - static const char * const hscif0_groups[] = { "hscif0_data", "hscif0_clk", @@ -5039,8 +5012,6 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(drif3), SH_PFC_FUNCTION(du), - SH_PFC_FUNCTION(hdmi0), - SH_PFC_FUNCTION(hdmi1), SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), SH_PFC_FUNCTION(hscif2), @@ -5090,7 +5061,7 @@ static const struct sh_pfc_function pinmux_functions[] = { static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) FN_##y #define FM(x) FN_##x - { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5122,9 +5093,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, GPSR0_3, GP_0_2_FN, GPSR0_2, GP_0_1_FN, GPSR0_1, - GP_0_0_FN, GPSR0_0, } + GP_0_0_FN, GPSR0_0, )) }, - { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5156,9 +5127,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, GPSR1_3, GP_1_2_FN, GPSR1_2, GP_1_1_FN, GPSR1_1, - GP_1_0_FN, GPSR1_0, } + GP_1_0_FN, GPSR1_0, )) }, - { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5190,9 +5161,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, GPSR2_3, GP_2_2_FN, GPSR2_2, GP_2_1_FN, GPSR2_1, - GP_2_0_FN, GPSR2_0, } + GP_2_0_FN, GPSR2_0, )) }, - { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5224,9 +5195,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, GPSR3_3, GP_3_2_FN, GPSR3_2, GP_3_1_FN, GPSR3_1, - GP_3_0_FN, GPSR3_0, } + GP_3_0_FN, GPSR3_0, )) }, - { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5258,9 +5229,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, GPSR4_3, GP_4_2_FN, GPSR4_2, GP_4_1_FN, GPSR4_1, - GP_4_0_FN, GPSR4_0, } + GP_4_0_FN, GPSR4_0, )) }, - { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5292,9 +5263,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, GPSR5_3, GP_5_2_FN, GPSR5_2, GP_5_1_FN, GPSR5_1, - GP_5_0_FN, GPSR5_0, } + GP_5_0_FN, GPSR5_0, )) }, - { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { + { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( GP_6_31_FN, GPSR6_31, GP_6_30_FN, GPSR6_30, GP_6_29_FN, GPSR6_29, @@ -5326,9 +5297,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_3_FN, GPSR6_3, GP_6_2_FN, GPSR6_2, GP_6_1_FN, GPSR6_1, - GP_6_0_FN, GPSR6_0, } + GP_6_0_FN, GPSR6_0, )) }, - { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) { + { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5360,14 +5331,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_7_3_FN, GPSR7_3, GP_7_2_FN, GPSR7_2, GP_7_1_FN, GPSR7_1, - GP_7_0_FN, GPSR7_0, } + GP_7_0_FN, GPSR7_0, )) }, #undef F_ #undef FM #define F_(x, y) x, #define FM(x) FN_##x, - { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { + { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( IP0_31_28 IP0_27_24 IP0_23_20 @@ -5375,9 +5346,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP0_15_12 IP0_11_8 IP0_7_4 - IP0_3_0 } + IP0_3_0 )) }, - { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { + { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( IP1_31_28 IP1_27_24 IP1_23_20 @@ -5385,9 +5356,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP1_15_12 IP1_11_8 IP1_7_4 - IP1_3_0 } + IP1_3_0 )) }, - { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { + { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( IP2_31_28 IP2_27_24 IP2_23_20 @@ -5395,9 +5366,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP2_15_12 IP2_11_8 IP2_7_4 - IP2_3_0 } + IP2_3_0 )) }, - { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { + { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( IP3_31_28 IP3_27_24 IP3_23_20 @@ -5405,9 +5376,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP3_15_12 IP3_11_8 IP3_7_4 - IP3_3_0 } + IP3_3_0 )) }, - { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { + { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( IP4_31_28 IP4_27_24 IP4_23_20 @@ -5415,9 +5386,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP4_15_12 IP4_11_8 IP4_7_4 - IP4_3_0 } + IP4_3_0 )) }, - { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { + { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( IP5_31_28 IP5_27_24 IP5_23_20 @@ -5425,9 +5396,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP5_15_12 IP5_11_8 IP5_7_4 - IP5_3_0 } + IP5_3_0 )) }, - { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { + { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( IP6_31_28 IP6_27_24 IP6_23_20 @@ -5435,9 +5406,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP6_15_12 IP6_11_8 IP6_7_4 - IP6_3_0 } + IP6_3_0 )) }, - { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { + { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( IP7_31_28 IP7_27_24 IP7_23_20 @@ -5445,9 +5416,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, IP7_11_8 IP7_7_4 - IP7_3_0 } + IP7_3_0 )) }, - { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { + { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( IP8_31_28 IP8_27_24 IP8_23_20 @@ -5455,9 +5426,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP8_15_12 IP8_11_8 IP8_7_4 - IP8_3_0 } + IP8_3_0 )) }, - { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { + { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( IP9_31_28 IP9_27_24 IP9_23_20 @@ -5465,9 +5436,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP9_15_12 IP9_11_8 IP9_7_4 - IP9_3_0 } + IP9_3_0 )) }, - { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { + { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( IP10_31_28 IP10_27_24 IP10_23_20 @@ -5475,9 +5446,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP10_15_12 IP10_11_8 IP10_7_4 - IP10_3_0 } + IP10_3_0 )) }, - { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { + { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( IP11_31_28 IP11_27_24 IP11_23_20 @@ -5485,9 +5456,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP11_15_12 IP11_11_8 IP11_7_4 - IP11_3_0 } + IP11_3_0 )) }, - { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { + { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( IP12_31_28 IP12_27_24 IP12_23_20 @@ -5495,9 +5466,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP12_15_12 IP12_11_8 IP12_7_4 - IP12_3_0 } + IP12_3_0 )) }, - { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { + { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( IP13_31_28 IP13_27_24 IP13_23_20 @@ -5505,9 +5476,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP13_15_12 IP13_11_8 IP13_7_4 - IP13_3_0 } + IP13_3_0 )) }, - { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) { + { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( IP14_31_28 IP14_27_24 IP14_23_20 @@ -5515,9 +5486,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP14_15_12 IP14_11_8 IP14_7_4 - IP14_3_0 } + IP14_3_0 )) }, - { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) { + { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( IP15_31_28 IP15_27_24 IP15_23_20 @@ -5525,9 +5496,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP15_15_12 IP15_11_8 IP15_7_4 - IP15_3_0 } + IP15_3_0 )) }, - { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) { + { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP( IP16_31_28 IP16_27_24 IP16_23_20 @@ -5535,9 +5506,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP16_15_12 IP16_11_8 IP16_7_4 - IP16_3_0 } + IP16_3_0 )) }, - { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) { + { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP( IP17_31_28 IP17_27_24 IP17_23_20 @@ -5545,9 +5516,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP17_15_12 IP17_11_8 IP17_7_4 - IP17_3_0 } + IP17_3_0 )) }, - { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) { + { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP( /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -5555,7 +5526,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, IP18_7_4 - IP18_3_0 } + IP18_3_0 )) }, #undef F_ #undef FM @@ -5563,8 +5534,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, - 3, 2, 3, 1, 1, 1, 1, 1, 2, 1, - 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) { + GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2, + 1, 1, 1, 2, 2, 1, 2, 3), + GROUP( MOD_SEL0_31_30_29 MOD_SEL0_28_27 MOD_SEL0_26_25_24 @@ -5585,11 +5557,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_5 MOD_SEL0_4_3 /* RESERVED 2, 1, 0 */ - 0, 0, 0, 0, 0, 0, 0, 0 } + 0, 0, 0, 0, 0, 0, 0, 0 )) }, { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, - 2, 3, 1, 2, 3, 1, 1, 2, 1, - 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) { + GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1, + 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1), + GROUP( MOD_SEL1_31_30 MOD_SEL1_29_28_27 MOD_SEL1_26 @@ -5612,11 +5585,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL1_3 MOD_SEL1_2 MOD_SEL1_1 - MOD_SEL1_0 } + MOD_SEL1_0 )) }, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, - 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1, - 4, 4, 4, 3, 1) { + GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, + 1, 4, 4, 4, 3, 1), + GROUP( MOD_SEL2_31 MOD_SEL2_30 MOD_SEL2_29 @@ -5643,7 +5617,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, /* RESERVED 3, 2, 1 */ 0, 0, 0, 0, 0, 0, 0, 0, - MOD_SEL2_0 } + MOD_SEL2_0 )) }, { }, }; @@ -5764,8 +5738,8 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ - { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */ - { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */ + { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ + { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ } }, @@ -5899,10 +5873,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { enum ioctrl_regs { POCCTRL, + TDSELCTRL, }; static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { [POCCTRL] = { 0xe6060380, }, + [TDSELCTRL] = { 0xe60603c0, }, { /* sentinel */ }, }; @@ -6019,8 +5995,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [25] = RCAR_GP_PIN(0, 15), /* D15 */ [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ - [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */ - [29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */ + [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ + [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ } }, diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c index 24fbbf19aa..a92c8ad18c 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7796.c +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c @@ -2,7 +2,7 @@ /* * R8A7796 processor support - PFC hardware block. * - * Copyright (C) 2016-2017 Renesas Electronics Corp. + * Copyright (C) 2016-2019 Renesas Electronics Corp. * * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c * @@ -209,7 +209,7 @@ /* GPSR7 */ #define GPSR7_3 FM(GP7_03) -#define GPSR7_2 FM(HDMI0_CEC) +#define GPSR7_2 FM(GP7_02) #define GPSR7_1 FM(AVS2) #define GPSR7_0 FM(AVS1) @@ -358,7 +358,7 @@ #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) @@ -469,7 +469,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) -#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3) +#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3) /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) @@ -502,12 +502,12 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1) +#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1) #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) -#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1) -#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1) +#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1) +#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1) #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) #define PINMUX_MOD_SELS \ @@ -600,7 +600,7 @@ static const u16 pinmux_data[] = { PINMUX_SINGLE(AVS2), PINMUX_SINGLE(CLKOUT), PINMUX_SINGLE(GP7_03), - PINMUX_SINGLE(HDMI0_CEC), + PINMUX_SINGLE(GP7_02), PINMUX_SINGLE(MSIOF0_RXD), PINMUX_SINGLE(MSIOF0_SCK), PINMUX_SINGLE(MSIOF0_TXD), @@ -1024,35 +1024,35 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), @@ -1118,28 +1118,28 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP11_7_4, NFCLE), PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD), - PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0), PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1), PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0), PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), - PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0), PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0), - PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDFC_0), + PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0), PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1), PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0), - PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDFC_0), + PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0), PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1), PINMUX_IPSR_GPSR(IP11_27_24, SCK0), PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), - PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1), + PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1), PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), @@ -1172,7 +1172,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N), PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), - PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1), + PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1), PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), @@ -1231,7 +1231,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0), + PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0), PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), @@ -1277,8 +1277,8 @@ static const u16 pinmux_data[] = { /* IPSR14 */ PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), - PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0), - PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2), + PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0), + PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2), PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), @@ -1287,7 +1287,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0), + PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0), PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0), PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), @@ -1415,10 +1415,9 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), /* IPSR17 */ - PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0), - PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT), + PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0), - PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1), + PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1), PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), @@ -1502,11 +1501,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2), PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3), - /* I2C */ - PINMUX_IPSR_NOGP(0, I2C_SEL_0_1), - PINMUX_IPSR_NOGP(0, I2C_SEL_3_1), - PINMUX_IPSR_NOGP(0, I2C_SEL_5_1), - /* * Static pins can not be muxed between different functions but * still need mark entries in the pinmux list. Add each static @@ -2143,15 +2137,6 @@ static const unsigned int du_disp_mux[] = { DU_DISP_MARK, }; -/* - HDMI ------------------------------------------------------------------- */ -static const unsigned int hdmi0_cec_pins[] = { - /* HDMI0_CEC */ - RCAR_GP_PIN(7, 2), -}; -static const unsigned int hdmi0_cec_mux[] = { - HDMI0_CEC_MARK, -}; - /* - HSCIF0 ----------------------------------------------------------------- */ static const unsigned int hscif0_data_pins[] = { /* RX, TX */ @@ -4127,8 +4112,8 @@ static const unsigned int vin5_clk_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[310]; - struct sh_pfc_pin_group automotive[33]; + struct sh_pfc_pin_group common[312]; + struct sh_pfc_pin_group automotive[30]; } pinmux_groups = { .common = { SH_PFC_PIN_GROUP(audio_clk_a_a), @@ -4163,6 +4148,9 @@ static const struct { SH_PFC_PIN_GROUP(can0_data_b), SH_PFC_PIN_GROUP(can1_data), SH_PFC_PIN_GROUP(can_clk), + SH_PFC_PIN_GROUP(canfd0_data_a), + SH_PFC_PIN_GROUP(canfd0_data_b), + SH_PFC_PIN_GROUP(canfd1_data), SH_PFC_PIN_GROUP(du_rgb666), SH_PFC_PIN_GROUP(du_rgb888), SH_PFC_PIN_GROUP(du_clk_out_0), @@ -4171,7 +4159,6 @@ static const struct { SH_PFC_PIN_GROUP(du_oddf), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), - SH_PFC_PIN_GROUP(hdmi0_cec), SH_PFC_PIN_GROUP(hscif0_data), SH_PFC_PIN_GROUP(hscif0_clk), SH_PFC_PIN_GROUP(hscif0_ctrl), @@ -4443,9 +4430,6 @@ static const struct { SH_PFC_PIN_GROUP(vin5_clk), }, .automotive = { - SH_PFC_PIN_GROUP(canfd0_data_a), - SH_PFC_PIN_GROUP(canfd0_data_b), - SH_PFC_PIN_GROUP(canfd1_data), SH_PFC_PIN_GROUP(drif0_ctrl_a), SH_PFC_PIN_GROUP(drif0_data0_a), SH_PFC_PIN_GROUP(drif0_data1_a), @@ -4588,10 +4572,6 @@ static const char * const du_groups[] = { "du_disp", }; -static const char * const hdmi0_groups[] = { - "hdmi0_cec", -}; - static const char * const hscif0_groups[] = { "hscif0_data", "hscif0_clk", @@ -4985,8 +4965,8 @@ static const char * const vin5_groups[] = { }; static const struct { - struct sh_pfc_function common[48]; - struct sh_pfc_function automotive[6]; + struct sh_pfc_function common[49]; + struct sh_pfc_function automotive[4]; } pinmux_functions = { .common = { SH_PFC_FUNCTION(audio_clk), @@ -4994,8 +4974,9 @@ static const struct { SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(can_clk), + SH_PFC_FUNCTION(canfd0), + SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(du), - SH_PFC_FUNCTION(hdmi0), SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), SH_PFC_FUNCTION(hscif2), @@ -5039,8 +5020,6 @@ static const struct { SH_PFC_FUNCTION(vin5), }, .automotive = { - SH_PFC_FUNCTION(canfd0), - SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(drif0), SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), @@ -5051,7 +5030,7 @@ static const struct { static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) FN_##y #define FM(x) FN_##x - { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5083,9 +5062,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, GPSR0_3, GP_0_2_FN, GPSR0_2, GP_0_1_FN, GPSR0_1, - GP_0_0_FN, GPSR0_0, } + GP_0_0_FN, GPSR0_0, )) }, - { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5117,9 +5096,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, GPSR1_3, GP_1_2_FN, GPSR1_2, GP_1_1_FN, GPSR1_1, - GP_1_0_FN, GPSR1_0, } + GP_1_0_FN, GPSR1_0, )) }, - { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5151,9 +5130,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, GPSR2_3, GP_2_2_FN, GPSR2_2, GP_2_1_FN, GPSR2_1, - GP_2_0_FN, GPSR2_0, } + GP_2_0_FN, GPSR2_0, )) }, - { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5185,9 +5164,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, GPSR3_3, GP_3_2_FN, GPSR3_2, GP_3_1_FN, GPSR3_1, - GP_3_0_FN, GPSR3_0, } + GP_3_0_FN, GPSR3_0, )) }, - { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5219,9 +5198,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, GPSR4_3, GP_4_2_FN, GPSR4_2, GP_4_1_FN, GPSR4_1, - GP_4_0_FN, GPSR4_0, } + GP_4_0_FN, GPSR4_0, )) }, - { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5253,9 +5232,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, GPSR5_3, GP_5_2_FN, GPSR5_2, GP_5_1_FN, GPSR5_1, - GP_5_0_FN, GPSR5_0, } + GP_5_0_FN, GPSR5_0, )) }, - { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { + { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( GP_6_31_FN, GPSR6_31, GP_6_30_FN, GPSR6_30, GP_6_29_FN, GPSR6_29, @@ -5287,9 +5266,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_3_FN, GPSR6_3, GP_6_2_FN, GPSR6_2, GP_6_1_FN, GPSR6_1, - GP_6_0_FN, GPSR6_0, } + GP_6_0_FN, GPSR6_0, )) }, - { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) { + { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5321,14 +5300,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_7_3_FN, GPSR7_3, GP_7_2_FN, GPSR7_2, GP_7_1_FN, GPSR7_1, - GP_7_0_FN, GPSR7_0, } + GP_7_0_FN, GPSR7_0, )) }, #undef F_ #undef FM #define F_(x, y) x, #define FM(x) FN_##x, - { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { + { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( IP0_31_28 IP0_27_24 IP0_23_20 @@ -5336,9 +5315,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP0_15_12 IP0_11_8 IP0_7_4 - IP0_3_0 } + IP0_3_0 )) }, - { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { + { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( IP1_31_28 IP1_27_24 IP1_23_20 @@ -5346,9 +5325,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP1_15_12 IP1_11_8 IP1_7_4 - IP1_3_0 } + IP1_3_0 )) }, - { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { + { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( IP2_31_28 IP2_27_24 IP2_23_20 @@ -5356,9 +5335,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP2_15_12 IP2_11_8 IP2_7_4 - IP2_3_0 } + IP2_3_0 )) }, - { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { + { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( IP3_31_28 IP3_27_24 IP3_23_20 @@ -5366,9 +5345,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP3_15_12 IP3_11_8 IP3_7_4 - IP3_3_0 } + IP3_3_0 )) }, - { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { + { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( IP4_31_28 IP4_27_24 IP4_23_20 @@ -5376,9 +5355,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP4_15_12 IP4_11_8 IP4_7_4 - IP4_3_0 } + IP4_3_0 )) }, - { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { + { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( IP5_31_28 IP5_27_24 IP5_23_20 @@ -5386,9 +5365,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP5_15_12 IP5_11_8 IP5_7_4 - IP5_3_0 } + IP5_3_0 )) }, - { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { + { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( IP6_31_28 IP6_27_24 IP6_23_20 @@ -5396,9 +5375,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP6_15_12 IP6_11_8 IP6_7_4 - IP6_3_0 } + IP6_3_0 )) }, - { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { + { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( IP7_31_28 IP7_27_24 IP7_23_20 @@ -5406,9 +5385,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, IP7_11_8 IP7_7_4 - IP7_3_0 } + IP7_3_0 )) }, - { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { + { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( IP8_31_28 IP8_27_24 IP8_23_20 @@ -5416,9 +5395,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP8_15_12 IP8_11_8 IP8_7_4 - IP8_3_0 } + IP8_3_0 )) }, - { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { + { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( IP9_31_28 IP9_27_24 IP9_23_20 @@ -5426,9 +5405,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP9_15_12 IP9_11_8 IP9_7_4 - IP9_3_0 } + IP9_3_0 )) }, - { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { + { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( IP10_31_28 IP10_27_24 IP10_23_20 @@ -5436,9 +5415,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP10_15_12 IP10_11_8 IP10_7_4 - IP10_3_0 } + IP10_3_0 )) }, - { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { + { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( IP11_31_28 IP11_27_24 IP11_23_20 @@ -5446,9 +5425,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP11_15_12 IP11_11_8 IP11_7_4 - IP11_3_0 } + IP11_3_0 )) }, - { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { + { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( IP12_31_28 IP12_27_24 IP12_23_20 @@ -5456,9 +5435,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP12_15_12 IP12_11_8 IP12_7_4 - IP12_3_0 } + IP12_3_0 )) }, - { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { + { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( IP13_31_28 IP13_27_24 IP13_23_20 @@ -5466,9 +5445,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP13_15_12 IP13_11_8 IP13_7_4 - IP13_3_0 } + IP13_3_0 )) }, - { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) { + { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( IP14_31_28 IP14_27_24 IP14_23_20 @@ -5476,9 +5455,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP14_15_12 IP14_11_8 IP14_7_4 - IP14_3_0 } + IP14_3_0 )) }, - { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) { + { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( IP15_31_28 IP15_27_24 IP15_23_20 @@ -5486,9 +5465,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP15_15_12 IP15_11_8 IP15_7_4 - IP15_3_0 } + IP15_3_0 )) }, - { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) { + { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP( IP16_31_28 IP16_27_24 IP16_23_20 @@ -5496,9 +5475,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP16_15_12 IP16_11_8 IP16_7_4 - IP16_3_0 } + IP16_3_0 )) }, - { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) { + { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP( IP17_31_28 IP17_27_24 IP17_23_20 @@ -5506,9 +5485,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP17_15_12 IP17_11_8 IP17_7_4 - IP17_3_0 } + IP17_3_0 )) }, - { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) { + { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP( /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -5516,7 +5495,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, IP18_7_4 - IP18_3_0 } + IP18_3_0 )) }, #undef F_ #undef FM @@ -5524,8 +5503,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, - 3, 2, 3, 1, 1, 1, 1, 1, 2, 1, - 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) { + GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2, + 1, 1, 1, 2, 2, 1, 2, 3), + GROUP( MOD_SEL0_31_30_29 MOD_SEL0_28_27 MOD_SEL0_26_25_24 @@ -5546,11 +5526,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_5 MOD_SEL0_4_3 /* RESERVED 2, 1, 0 */ - 0, 0, 0, 0, 0, 0, 0, 0 } + 0, 0, 0, 0, 0, 0, 0, 0 )) }, { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, - 2, 3, 1, 2, 3, 1, 1, 2, 1, - 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) { + GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1, + 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1), + GROUP( MOD_SEL1_31_30 MOD_SEL1_29_28_27 MOD_SEL1_26 @@ -5573,11 +5554,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL1_3 MOD_SEL1_2 MOD_SEL1_1 - MOD_SEL1_0 } + MOD_SEL1_0 )) }, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, - 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1, - 4, 4, 4, 3, 1) { + GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, + 1, 4, 4, 4, 3, 1), + GROUP( MOD_SEL2_31 MOD_SEL2_30 MOD_SEL2_29 @@ -5603,7 +5585,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, /* RESERVED 3, 2, 1 */ 0, 0, 0, 0, 0, 0, 0, 0, - MOD_SEL2_0 } + MOD_SEL2_0 )) }, { }, }; @@ -5724,7 +5706,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ - { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */ + { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ @@ -5858,10 +5840,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { enum ioctrl_regs { POCCTRL, + TDSELCTRL, }; static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { [POCCTRL] = { 0xe6060380, }, + [TDSELCTRL] = { 0xe60603c0, }, { /* sentinel */ }, }; @@ -5978,7 +5962,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [25] = RCAR_GP_PIN(0, 15), /* D15 */ [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ - [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */ + [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c index 7c24836d2c..2523904aec 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77965.c +++ b/drivers/pinctrl/renesas/pfc-r8a77965.c @@ -3,7 +3,7 @@ * R8A77965 processor support - PFC hardware block. * * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org> - * Copyright (C) 2016 Renesas Electronics Corp. + * Copyright (C) 2016-2019 Renesas Electronics Corp. * * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c * @@ -210,7 +210,7 @@ /* GPSR7 */ #define GPSR7_3 FM(GP7_03) -#define GPSR7_2 FM(HDMI0_CEC) +#define GPSR7_2 FM(GP7_02) #define GPSR7_1 FM(AVS2) #define GPSR7_0 FM(AVS1) @@ -359,7 +359,7 @@ #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0) #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0) @@ -470,7 +470,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0) #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0) #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) -#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3) +#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3) /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3) @@ -503,12 +503,12 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3) #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1) +#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1) #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1) #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1) #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1) -#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1) -#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1) +#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1) +#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1) #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1) #define PINMUX_MOD_SELS \ @@ -560,6 +560,9 @@ MOD_SEL0_4_3 MOD_SEL1_4 \ FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \ FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) +#define PINMUX_PHYS \ + FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5) + enum { PINMUX_RESERVED = 0, @@ -585,6 +588,7 @@ enum { PINMUX_IPSR PINMUX_MOD_SELS PINMUX_STATIC + PINMUX_PHYS PINMUX_MARK_END, #undef F_ #undef FM @@ -597,7 +601,7 @@ static const u16 pinmux_data[] = { PINMUX_SINGLE(AVS2), PINMUX_SINGLE(CLKOUT), PINMUX_SINGLE(GP7_03), - PINMUX_SINGLE(HDMI0_CEC), + PINMUX_SINGLE(GP7_02), PINMUX_SINGLE(MSIOF0_RXD), PINMUX_SINGLE(MSIOF0_SCK), PINMUX_SINGLE(MSIOF0_TXD), @@ -622,13 +626,15 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A), - PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0), - PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2), - PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), + PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1), - PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0), - PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2), - PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), + PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), @@ -681,14 +687,16 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), - PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0), - PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3), - PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1), - PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), + PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1), - PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0), - PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3), - PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1), + PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1), PINMUX_IPSR_GPSR(IP1_31_28, A0), PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), @@ -1019,35 +1027,35 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD), PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0), PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0), PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4), PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1), PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5), PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2), PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6), PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1), PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3), PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7), PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6), - PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1), PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1), PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1), @@ -1114,26 +1122,28 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP11_7_4, NFCLE), PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD), - PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0), PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1), PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0), PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), - PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0), PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), - PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD), - PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0), - PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1), + PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0), + PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0), + PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), + PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1), - PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP), - PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0), - PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1), + PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0), + PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0), + PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), + PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1), PINMUX_IPSR_GPSR(IP11_27_24, SCK0), PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1), - PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1), + PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1), PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1), PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2), @@ -1166,7 +1176,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N), PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1), - PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1), + PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1), PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0), PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2), PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1), @@ -1225,7 +1235,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP13_11_8, HSCK0), PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0), + PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0), PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1), PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3), PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3), @@ -1271,8 +1281,8 @@ static const u16 pinmux_data[] = { /* IPSR14 */ PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1), PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0), - PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0), - PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2), + PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0), + PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2), PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0), PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2), PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A), @@ -1281,7 +1291,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2), PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0), PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3), - PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0), + PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0), PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0), PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3), PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D), @@ -1410,10 +1420,9 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0), /* IPSR17 */ - PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0), - PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT), + PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0), - PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1), + PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1), PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0), PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3), PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0), @@ -1497,11 +1506,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2), PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3), - /* I2C */ - PINMUX_IPSR_NOGP(0, I2C_SEL_0_1), - PINMUX_IPSR_NOGP(0, I2C_SEL_3_1), - PINMUX_IPSR_NOGP(0, I2C_SEL_5_1), - /* * Static pins can not be muxed between different functions but * still need mark entries in the pinmux list. Add each static @@ -2481,52 +2485,92 @@ static const unsigned int hscif4_data_b_mux[] = { }; /* - I2C -------------------------------------------------------------------- */ +static const unsigned int i2c0_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), +}; + +static const unsigned int i2c0_mux[] = { + SCL0_MARK, SDA0_MARK, +}; + static const unsigned int i2c1_a_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), }; + static const unsigned int i2c1_a_mux[] = { SDA1_A_MARK, SCL1_A_MARK, }; + static const unsigned int i2c1_b_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), }; + static const unsigned int i2c1_b_mux[] = { SDA1_B_MARK, SCL1_B_MARK, }; + static const unsigned int i2c2_a_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), }; + static const unsigned int i2c2_a_mux[] = { SDA2_A_MARK, SCL2_A_MARK, }; + static const unsigned int i2c2_b_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), }; + static const unsigned int i2c2_b_mux[] = { SDA2_B_MARK, SCL2_B_MARK, }; + +static const unsigned int i2c3_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), +}; + +static const unsigned int i2c3_mux[] = { + SCL3_MARK, SDA3_MARK, +}; + +static const unsigned int i2c5_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), +}; + +static const unsigned int i2c5_mux[] = { + SCL5_MARK, SDA5_MARK, +}; + static const unsigned int i2c6_a_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), }; + static const unsigned int i2c6_a_mux[] = { SDA6_A_MARK, SCL6_A_MARK, }; + static const unsigned int i2c6_b_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), }; + static const unsigned int i2c6_b_mux[] = { SDA6_B_MARK, SCL6_B_MARK, }; + static const unsigned int i2c6_c_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), }; + static const unsigned int i2c6_c_mux[] = { SDA6_C_MARK, SCL6_C_MARK, }; @@ -4416,10 +4460,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(hscif4_clk), SH_PFC_PIN_GROUP(hscif4_ctrl), SH_PFC_PIN_GROUP(hscif4_data_b), + SH_PFC_PIN_GROUP(i2c0), SH_PFC_PIN_GROUP(i2c1_a), SH_PFC_PIN_GROUP(i2c1_b), SH_PFC_PIN_GROUP(i2c2_a), SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(i2c5), SH_PFC_PIN_GROUP(i2c6_a), SH_PFC_PIN_GROUP(i2c6_b), SH_PFC_PIN_GROUP(i2c6_c), @@ -4810,6 +4857,10 @@ static const char * const hscif4_groups[] = { "hscif4_data_b", }; +static const char * const i2c0_groups[] = { + "i2c0", +}; + static const char * const i2c1_groups[] = { "i2c1_a", "i2c1_b", @@ -4820,6 +4871,14 @@ static const char * const i2c2_groups[] = { "i2c2_b", }; +static const char * const i2c3_groups[] = { + "i2c3", +}; + +static const char * const i2c5_groups[] = { + "i2c5", +}; + static const char * const i2c6_groups[] = { "i2c6_a", "i2c6_b", @@ -5169,8 +5228,11 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(hscif2), SH_PFC_FUNCTION(hscif3), SH_PFC_FUNCTION(hscif4), + SH_PFC_FUNCTION(i2c0), SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(i2c5), SH_PFC_FUNCTION(i2c6), SH_PFC_FUNCTION(intc_ex), SH_PFC_FUNCTION(msiof0), @@ -5208,7 +5270,7 @@ static const struct sh_pfc_function pinmux_functions[] = { static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) FN_##y #define FM(x) FN_##x - { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5240,9 +5302,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, GPSR0_3, GP_0_2_FN, GPSR0_2, GP_0_1_FN, GPSR0_1, - GP_0_0_FN, GPSR0_0, } + GP_0_0_FN, GPSR0_0, )) }, - { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5274,9 +5336,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, GPSR1_3, GP_1_2_FN, GPSR1_2, GP_1_1_FN, GPSR1_1, - GP_1_0_FN, GPSR1_0, } + GP_1_0_FN, GPSR1_0, )) }, - { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5308,9 +5370,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, GPSR2_3, GP_2_2_FN, GPSR2_2, GP_2_1_FN, GPSR2_1, - GP_2_0_FN, GPSR2_0, } + GP_2_0_FN, GPSR2_0, )) }, - { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5342,9 +5404,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, GPSR3_3, GP_3_2_FN, GPSR3_2, GP_3_1_FN, GPSR3_1, - GP_3_0_FN, GPSR3_0, } + GP_3_0_FN, GPSR3_0, )) }, - { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5376,9 +5438,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, GPSR4_3, GP_4_2_FN, GPSR4_2, GP_4_1_FN, GPSR4_1, - GP_4_0_FN, GPSR4_0, } + GP_4_0_FN, GPSR4_0, )) }, - { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5410,9 +5472,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, GPSR5_3, GP_5_2_FN, GPSR5_2, GP_5_1_FN, GPSR5_1, - GP_5_0_FN, GPSR5_0, } + GP_5_0_FN, GPSR5_0, )) }, - { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { + { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( GP_6_31_FN, GPSR6_31, GP_6_30_FN, GPSR6_30, GP_6_29_FN, GPSR6_29, @@ -5444,9 +5506,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_3_FN, GPSR6_3, GP_6_2_FN, GPSR6_2, GP_6_1_FN, GPSR6_1, - GP_6_0_FN, GPSR6_0, } + GP_6_0_FN, GPSR6_0, )) }, - { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) { + { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5478,14 +5540,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_7_3_FN, GPSR7_3, GP_7_2_FN, GPSR7_2, GP_7_1_FN, GPSR7_1, - GP_7_0_FN, GPSR7_0, } + GP_7_0_FN, GPSR7_0, )) }, #undef F_ #undef FM #define F_(x, y) x, #define FM(x) FN_##x, - { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { + { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( IP0_31_28 IP0_27_24 IP0_23_20 @@ -5493,9 +5555,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP0_15_12 IP0_11_8 IP0_7_4 - IP0_3_0 } + IP0_3_0 )) }, - { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { + { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( IP1_31_28 IP1_27_24 IP1_23_20 @@ -5503,9 +5565,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP1_15_12 IP1_11_8 IP1_7_4 - IP1_3_0 } + IP1_3_0 )) }, - { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { + { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( IP2_31_28 IP2_27_24 IP2_23_20 @@ -5513,9 +5575,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP2_15_12 IP2_11_8 IP2_7_4 - IP2_3_0 } + IP2_3_0 )) }, - { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { + { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( IP3_31_28 IP3_27_24 IP3_23_20 @@ -5523,9 +5585,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP3_15_12 IP3_11_8 IP3_7_4 - IP3_3_0 } + IP3_3_0 )) }, - { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { + { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( IP4_31_28 IP4_27_24 IP4_23_20 @@ -5533,9 +5595,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP4_15_12 IP4_11_8 IP4_7_4 - IP4_3_0 } + IP4_3_0 )) }, - { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { + { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( IP5_31_28 IP5_27_24 IP5_23_20 @@ -5543,9 +5605,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP5_15_12 IP5_11_8 IP5_7_4 - IP5_3_0 } + IP5_3_0 )) }, - { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { + { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( IP6_31_28 IP6_27_24 IP6_23_20 @@ -5553,9 +5615,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP6_15_12 IP6_11_8 IP6_7_4 - IP6_3_0 } + IP6_3_0 )) }, - { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { + { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( IP7_31_28 IP7_27_24 IP7_23_20 @@ -5563,9 +5625,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, IP7_11_8 IP7_7_4 - IP7_3_0 } + IP7_3_0 )) }, - { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { + { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( IP8_31_28 IP8_27_24 IP8_23_20 @@ -5573,9 +5635,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP8_15_12 IP8_11_8 IP8_7_4 - IP8_3_0 } + IP8_3_0 )) }, - { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { + { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( IP9_31_28 IP9_27_24 IP9_23_20 @@ -5583,9 +5645,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP9_15_12 IP9_11_8 IP9_7_4 - IP9_3_0 } + IP9_3_0 )) }, - { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { + { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( IP10_31_28 IP10_27_24 IP10_23_20 @@ -5593,9 +5655,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP10_15_12 IP10_11_8 IP10_7_4 - IP10_3_0 } + IP10_3_0 )) }, - { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { + { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( IP11_31_28 IP11_27_24 IP11_23_20 @@ -5603,9 +5665,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP11_15_12 IP11_11_8 IP11_7_4 - IP11_3_0 } + IP11_3_0 )) }, - { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { + { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( IP12_31_28 IP12_27_24 IP12_23_20 @@ -5613,9 +5675,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP12_15_12 IP12_11_8 IP12_7_4 - IP12_3_0 } + IP12_3_0 )) }, - { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { + { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( IP13_31_28 IP13_27_24 IP13_23_20 @@ -5623,9 +5685,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP13_15_12 IP13_11_8 IP13_7_4 - IP13_3_0 } + IP13_3_0 )) }, - { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) { + { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( IP14_31_28 IP14_27_24 IP14_23_20 @@ -5633,9 +5695,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP14_15_12 IP14_11_8 IP14_7_4 - IP14_3_0 } + IP14_3_0 )) }, - { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) { + { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( IP15_31_28 IP15_27_24 IP15_23_20 @@ -5643,9 +5705,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP15_15_12 IP15_11_8 IP15_7_4 - IP15_3_0 } + IP15_3_0 )) }, - { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) { + { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP( IP16_31_28 IP16_27_24 IP16_23_20 @@ -5653,9 +5715,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP16_15_12 IP16_11_8 IP16_7_4 - IP16_3_0 } + IP16_3_0 )) }, - { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) { + { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP( IP17_31_28 IP17_27_24 IP17_23_20 @@ -5663,9 +5725,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP17_15_12 IP17_11_8 IP17_7_4 - IP17_3_0 } + IP17_3_0 )) }, - { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) { + { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP( /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -5673,7 +5735,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, IP18_7_4 - IP18_3_0 } + IP18_3_0 )) }, #undef F_ #undef FM @@ -5681,8 +5743,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, - 3, 2, 3, 1, 1, 1, 1, 1, 2, 1, - 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) { + GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2, + 1, 1, 1, 2, 2, 1, 2, 3), + GROUP( MOD_SEL0_31_30_29 MOD_SEL0_28_27 MOD_SEL0_26_25_24 @@ -5703,11 +5766,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_5 MOD_SEL0_4_3 /* RESERVED 2, 1, 0 */ - 0, 0, 0, 0, 0, 0, 0, 0 } + 0, 0, 0, 0, 0, 0, 0, 0 )) }, { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, - 2, 3, 1, 2, 3, 1, 1, 2, 1, - 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) { + GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1, + 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1), + GROUP( MOD_SEL1_31_30 MOD_SEL1_29_28_27 MOD_SEL1_26 @@ -5730,11 +5794,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL1_3 MOD_SEL1_2 MOD_SEL1_1 - MOD_SEL1_0 } + MOD_SEL1_0 )) }, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, - 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1, - 4, 4, 4, 3, 1) { + GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, + 1, 4, 4, 4, 3, 1), + GROUP( MOD_SEL2_31 MOD_SEL2_30 MOD_SEL2_29 @@ -5760,7 +5825,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, /* RESERVED 3, 2, 1 */ 0, 0, 0, 0, 0, 0, 0, 0, - MOD_SEL2_0 } + MOD_SEL2_0 )) }, { }, }; @@ -5881,7 +5946,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ - { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */ + { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */ { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */ @@ -6015,10 +6080,12 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { enum ioctrl_regs { POCCTRL, + TDSELCTRL, }; static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { [POCCTRL] = { 0xe6060380, }, + [TDSELCTRL] = { 0xe60603c0, }, { /* sentinel */ }, }; @@ -6135,7 +6202,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [25] = RCAR_GP_PIN(0, 15), /* D15 */ [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ - [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */ + [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c b/drivers/pinctrl/renesas/pfc-r8a77970.c index 823edb559d..33ecd93398 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77970.c +++ b/drivers/pinctrl/renesas/pfc-r8a77970.c @@ -173,19 +173,19 @@ #define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(HRX0) F_(0, 0) FM(A19) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2_27_24 FM(IRQ0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N_TANS) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_23_20 FM(VI0_DATA2) FM(AVB0_AVTP_PPS) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) FM(PWM0_A) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) FM(A23) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) FM(A24) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -200,18 +200,18 @@ #define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_7_4 FM(VI1_DATA5) F_(0,0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_11_8 FM(VI1_DATA6) F_(0,0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_15_12 FM(VI1_DATA7) F_(0,0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_19_16 FM(VI1_DATA8) F_(0,0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_23_20 FM(VI1_DATA9) F_(0,0) FM(RTS4_N_TANS) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_27_24 FM(VI1_DATA10) F_(0,0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_7_4 FM(VI1_DATA5) F_(0, 0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_11_8 FM(VI1_DATA6) F_(0, 0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_15_12 FM(VI1_DATA7) F_(0, 0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_19_16 FM(VI1_DATA8) F_(0, 0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_23_20 FM(VI1_DATA9) F_(0, 0) FM(RTS4_N) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_27_24 FM(VI1_DATA10) F_(0, 0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N_TANS) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_23_20 FM(SCL2) FM(DU_DB0) FM(TCLK1_A) FM(WE1_N) FM(RX0) FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_27_24 FM(SDA2) FM(DU_DB1) FM(TCLK2_A) FM(EX_WAIT0) FM(TX0) FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP7_31_28 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSCLKST2_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -472,7 +472,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC), PINMUX_IPSR_GPSR(IP2_27_24, IRQ0), - PINMUX_IPSR_GPSR(IP2_27_24, CC5_OSCOUT), PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK), PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK), @@ -498,7 +497,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0), PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1), - PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N_TANS), + PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N), PINMUX_IPSR_GPSR(IP3_15_12, HRX3), PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1), @@ -529,7 +528,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7), PINMUX_IPSR_GPSR(IP4_11_8, HRX1), - PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N_TANS), + PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N), PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8), PINMUX_IPSR_GPSR(IP4_15_12, HSCK2), @@ -619,7 +618,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP6_19_16, MMC_D5), PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9), - PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N_TANS), + PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N), PINMUX_IPSR_GPSR(IP6_23_20, D12), PINMUX_IPSR_GPSR(IP6_23_20, MMC_D6), PINMUX_IPSR_MSEL(IP6_23_20, SCL3_B, SEL_I2C3_1), @@ -666,7 +665,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP7_19_16, DU_DG1), PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3), PINMUX_IPSR_GPSR(IP7_19_16, WE0_N), - PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N_TANS), + PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N), PINMUX_IPSR_GPSR(IP7_19_16, MSIOF0_SYNC), PINMUX_IPSR_GPSR(IP7_23_20, SCL2), @@ -1470,7 +1469,7 @@ static const unsigned int scif0_ctrl_pins[] = { RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2), }; static const unsigned int scif0_ctrl_mux[] = { - RTS0_N_TANS_MARK, CTS0_N_MARK, + RTS0_N_MARK, CTS0_N_MARK, }; /* - SCIF1 ------------------------------------------------------------------ */ @@ -1493,7 +1492,7 @@ static const unsigned int scif1_ctrl_pins[] = { RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10), }; static const unsigned int scif1_ctrl_mux[] = { - RTS1_N_TANS_MARK, CTS1_N_MARK, + RTS1_N_MARK, CTS1_N_MARK, }; static const unsigned int scif1_data_b_pins[] = { /* RX, TX */ @@ -1523,7 +1522,7 @@ static const unsigned int scif3_ctrl_pins[] = { RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), }; static const unsigned int scif3_ctrl_mux[] = { - RTS3_N_TANS_MARK, CTS3_N_MARK, + RTS3_N_MARK, CTS3_N_MARK, }; /* - SCIF4 ------------------------------------------------------------------ */ @@ -1546,7 +1545,7 @@ static const unsigned int scif4_ctrl_pins[] = { RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), }; static const unsigned int scif4_ctrl_mux[] = { - RTS4_N_TANS_MARK, CTS4_N_MARK, + RTS4_N_MARK, CTS4_N_MARK, }; /* - TMU -------------------------------------------------------------------- */ @@ -2074,7 +2073,7 @@ static const struct sh_pfc_function pinmux_functions[] = { static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) FN_##y #define FM(x) FN_##x - { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2106,9 +2105,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, GPSR0_3, GP_0_2_FN, GPSR0_2, GP_0_1_FN, GPSR0_1, - GP_0_0_FN, GPSR0_0, } + GP_0_0_FN, GPSR0_0, )) }, - { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2140,9 +2139,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, GPSR1_3, GP_1_2_FN, GPSR1_2, GP_1_1_FN, GPSR1_1, - GP_1_0_FN, GPSR1_0, } + GP_1_0_FN, GPSR1_0, )) }, - { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2174,9 +2173,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, GPSR2_3, GP_2_2_FN, GPSR2_2, GP_2_1_FN, GPSR2_1, - GP_2_0_FN, GPSR2_0, } + GP_2_0_FN, GPSR2_0, )) }, - { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2208,9 +2207,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, GPSR3_3, GP_3_2_FN, GPSR3_2, GP_3_1_FN, GPSR3_1, - GP_3_0_FN, GPSR3_0, } + GP_3_0_FN, GPSR3_0, )) }, - { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2242,9 +2241,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, GPSR4_3, GP_4_2_FN, GPSR4_2, GP_4_1_FN, GPSR4_1, - GP_4_0_FN, GPSR4_0, } + GP_4_0_FN, GPSR4_0, )) }, - { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2276,14 +2275,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, GPSR5_3, GP_5_2_FN, GPSR5_2, GP_5_1_FN, GPSR5_1, - GP_5_0_FN, GPSR5_0, } + GP_5_0_FN, GPSR5_0, )) }, #undef F_ #undef FM #define F_(x, y) x, #define FM(x) FN_##x, - { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { + { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( IP0_31_28 IP0_27_24 IP0_23_20 @@ -2291,9 +2290,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP0_15_12 IP0_11_8 IP0_7_4 - IP0_3_0 } + IP0_3_0 )) }, - { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { + { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( IP1_31_28 IP1_27_24 IP1_23_20 @@ -2301,9 +2300,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP1_15_12 IP1_11_8 IP1_7_4 - IP1_3_0 } + IP1_3_0 )) }, - { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { + { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( IP2_31_28 IP2_27_24 IP2_23_20 @@ -2311,9 +2310,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP2_15_12 IP2_11_8 IP2_7_4 - IP2_3_0 } + IP2_3_0 )) }, - { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { + { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( IP3_31_28 IP3_27_24 IP3_23_20 @@ -2321,9 +2320,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP3_15_12 IP3_11_8 IP3_7_4 - IP3_3_0 } + IP3_3_0 )) }, - { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { + { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( IP4_31_28 IP4_27_24 IP4_23_20 @@ -2331,9 +2330,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP4_15_12 IP4_11_8 IP4_7_4 - IP4_3_0 } + IP4_3_0 )) }, - { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { + { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( IP5_31_28 IP5_27_24 IP5_23_20 @@ -2341,9 +2340,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP5_15_12 IP5_11_8 IP5_7_4 - IP5_3_0 } + IP5_3_0 )) }, - { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { + { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( IP6_31_28 IP6_27_24 IP6_23_20 @@ -2351,9 +2350,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP6_15_12 IP6_11_8 IP6_7_4 - IP6_3_0 } + IP6_3_0 )) }, - { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { + { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( IP7_31_28 IP7_27_24 IP7_23_20 @@ -2361,9 +2360,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP7_15_12 IP7_11_8 IP7_7_4 - IP7_3_0 } + IP7_3_0 )) }, - { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { + { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( IP8_31_28 IP8_27_24 IP8_23_20 @@ -2371,7 +2370,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP8_15_12 IP8_11_8 IP8_7_4 - IP8_3_0 } + IP8_3_0 )) }, #undef F_ #undef FM @@ -2379,8 +2378,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, - 4, 4, 4, 4, 4, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) { + GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1), + GROUP( /* RESERVED 31, 30, 29, 28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* RESERVED 27, 26, 25, 24 */ @@ -2402,21 +2402,23 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_3 MOD_SEL0_2 MOD_SEL0_1 - MOD_SEL0_0 } + MOD_SEL0_0 )) }, { }, }; enum ioctrl_regs { - IOCTRL30, - IOCTRL31, - IOCTRL32, + POCCTRL0, + POCCTRL1, + POCCTRL2, + TDSELCTRL, }; static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { - [IOCTRL30] = { 0xe6060380 }, - [IOCTRL31] = { 0xe6060384 }, - [IOCTRL32] = { 0xe6060388 }, + [POCCTRL0] = { 0xe6060380 }, + [POCCTRL1] = { 0xe6060384 }, + [POCCTRL2] = { 0xe6060388 }, + [TDSELCTRL] = { 0xe60603c0, }, { /* sentinel */ }, }; @@ -2425,13 +2427,13 @@ static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, { int bit = pin & 0x1f; - *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg; + *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21)) return bit; if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9)) return bit + 22; - *pocctrl = pinmux_ioctrl_regs[IOCTRL31].reg; + *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg; if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16)) return bit - 10; if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16)) diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index 1cf08ae471..5313f2f509 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -2,7 +2,7 @@ /* * R8A77990 processor support - PFC hardware block. * - * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018-2019 Renesas Electronics Corp. * * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c * @@ -168,7 +168,7 @@ #define GPSR5_7 F_(SCK2_A, IP12_7_4) #define GPSR5_6 F_(TX1, IP12_3_0) #define GPSR5_5 F_(RX1, IP11_31_28) -#define GPSR5_4 F_(RTS0_N_TANS_A, IP11_23_20) +#define GPSR5_4 F_(RTS0_N_A, IP11_23_20) #define GPSR5_3 F_(CTS0_N_A, IP11_19_16) #define GPSR5_2 F_(TX0_A, IP11_15_12) #define GPSR5_1 F_(RX0_A, IP11_11_8) @@ -222,7 +222,7 @@ #define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_11_8 FM(A3) FM(CTS4_N_A) FM(PWM4_A) FM(VI4_DATA12) F_(0, 0) FM(DU_DOTCLKOUT0) FM(HTX3_D) FM(IECLK) FM(LCDOUT12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3_15_12 FM(A4) FM(RTS4_N_TANS_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP3_15_12 FM(A4) FM(RTS4_N_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_19_16 FM(A5) FM(SCK4_A) FM(MSIOF3_SCK_B) FM(VI4_DATA9) FM(PWM3_B) F_(0, 0) FM(RIF2_SYNC_B) F_(0, 0) FM(QPOLA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_23_20 FM(A6) FM(RX4_A) FM(MSIOF3_RXD_B) FM(VI4_DATA10) F_(0, 0) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3_27_24 FM(A7) FM(TX4_A) FM(MSIOF3_TXD_B) FM(VI4_DATA11) F_(0, 0) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -243,10 +243,10 @@ #define IP5_15_12 FM(CS0_N) FM(SCL5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR0) FM(VI4_DATA2_B) F_(0, 0) FM(LCDOUT16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP5_19_16 FM(WE0_N) FM(SDA5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR1) FM(VI4_DATA3_B) F_(0, 0) FM(LCDOUT17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP5_23_20 FM(D0) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(CTS4_N_C) F_(0, 0) FM(LCDOUT18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_TANS_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4_C) F_(0, 0) FM(LCDOUT19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_3_0 FM(D3) FM(MSIOF3_TXD_A) FM(TX5_C) F_(0, 0) FM(VI5_DATA15_A) FM(DU_DR4) FM(TX4_C) F_(0, 0) FM(LCDOUT20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_TANS_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_11_8 FM(D5) FM(RX3_A) FM(HRX3_B) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(VI4_DATA4_B) F_(0, 0) FM(LCDOUT21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_15_12 FM(D6) FM(TX3_A) FM(HTX3_B) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(VI4_DATA5_B) F_(0, 0) FM(LCDOUT22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP6_19_16 FM(D7) FM(CANFD1_RX) FM(IRQ5) FM(CAN1_RX) FM(CTS3_N_A) F_(0, 0) F_(0, 0) FM(VI5_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -292,8 +292,8 @@ #define IP11_11_8 FM(RX0_A) FM(HRX1_A) FM(SSI_SCK2_A) FM(RIF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_19_16 FM(CTS0_N_A) FM(NFDATA14_A) FM(AUDIO_CLKOUT_A) FM(RIF1_D1) FM(SCIF_CLK_A) FM(FMCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP11_23_20 FM(RTS0_N_TANS_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N_TANS) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_23_20 FM(RTS0_N_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_31_28 FM(RX1) FM(HRX2_B) FM(SSI_SCK9_B) FM(AUDIO_CLKOUT1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */ @@ -417,7 +417,7 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM #define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) #define MOD_SEL0_21_20 REV4(FM(SEL_I2C1_0), FM(SEL_I2C1_1), FM(SEL_I2C1_2), FM(SEL_I2C1_3)) #define MOD_SEL0_19_18_17 REV8(FM(SEL_I2C2_0), FM(SEL_I2C2_1), FM(SEL_I2C2_2), FM(SEL_I2C2_3), FM(SEL_I2C2_4), F_(0, 0), F_(0, 0), F_(0, 0)) -#define MOD_SEL0_16 FM(SEL_NDFC_0) FM(SEL_NDFC_1) +#define MOD_SEL0_16 FM(SEL_NDF_0) FM(SEL_NDF_1) #define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1) #define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1) #define MOD_SEL0_13_12 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0)) @@ -432,8 +432,6 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM #define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0), FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0)) /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ -#define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) -#define MOD_SEL1_30 FM(SEL_SSI2_0) FM(SEL_SSI2_1) #define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1) #define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1) #define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) @@ -454,8 +452,7 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM #define PINMUX_MOD_SELS \ \ - MOD_SEL1_31 \ -MOD_SEL0_30_29 MOD_SEL1_30 \ +MOD_SEL0_30_29 \ MOD_SEL1_29 \ MOD_SEL0_28 MOD_SEL1_28 \ MOD_SEL0_27_26 \ @@ -674,7 +671,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT12), PINMUX_IPSR_GPSR(IP3_15_12, A4), - PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_TANS_A, SEL_SCIF4_0), + PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_A, SEL_SCIF4_0), PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SYNC_B, SEL_MSIOF3_1), PINMUX_IPSR_GPSR(IP3_15_12, VI4_DATA8), PINMUX_IPSR_MSEL(IP3_15_12, PWM2_B, SEL_PWM2_1), @@ -824,7 +821,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23), PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0), PINMUX_IPSR_GPSR(IP5_27_24, DU_DB7), - PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_TANS_C, SEL_SCIF4_2), + PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_C, SEL_SCIF4_2), PINMUX_IPSR_GPSR(IP5_27_24, LCDOUT7), PINMUX_IPSR_GPSR(IP5_31_28, D2), @@ -848,7 +845,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP6_7_4, CANFD1_TX), PINMUX_IPSR_MSEL(IP6_7_4, HSCK3_B, SEL_HSCIF3_1), PINMUX_IPSR_GPSR(IP6_7_4, CAN1_TX), - PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_TANS_A, SEL_SCIF3_0), + PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_A, SEL_SCIF3_0), PINMUX_IPSR_GPSR(IP6_7_4, MSIOF3_SS2_A), PINMUX_IPSR_MSEL(IP6_7_4, VI5_DATA1_B, SEL_VIN5_1), @@ -987,23 +984,23 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP8_19_16, REMOCON_C, SEL_REMOCON_2), PINMUX_IPSR_GPSR(IP8_23_20, SD1_CLK), - PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1), PINMUX_IPSR_GPSR(IP8_27_24, SD1_CMD), - PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1), PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT0), - PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDF_1), /* IPSR9 */ PINMUX_IPSR_GPSR(IP9_3_0, SD1_DAT1), - PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDF_1), PINMUX_IPSR_GPSR(IP9_7_4, SD1_DAT2), - PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDF_1), PINMUX_IPSR_GPSR(IP9_11_8, SD1_DAT3), - PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDFC_1), + PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDF_1), PINMUX_IPSR_GPSR(IP9_15_12, SD3_CLK), PINMUX_IPSR_GPSR(IP9_15_12, NFWE_N), @@ -1040,57 +1037,57 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP10_23_20, NFCLE), PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD), - PINMUX_IPSR_GPSR(IP10_27_24, NFALE_A), + PINMUX_IPSR_MSEL(IP10_27_24, NFALE_A, SEL_NDF_0), PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD), PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1), PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1), PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0), - PINMUX_IPSR_MSEL(IP10_27_24, SSI_SCK2_B, SEL_SSI2_1), + PINMUX_IPSR_GPSR(IP10_27_24, SSI_SCK2_B), PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0), PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP), - PINMUX_IPSR_GPSR(IP10_31_28, NFRB_N_A), + PINMUX_IPSR_MSEL(IP10_31_28, NFRB_N_A, SEL_NDF_0), PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP), PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1), PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1), PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0), - PINMUX_IPSR_MSEL(IP10_31_28, SSI_WS2_B, SEL_SSI2_1), + PINMUX_IPSR_GPSR(IP10_31_28, SSI_WS2_B), PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0), /* IPSR11 */ PINMUX_IPSR_GPSR(IP11_3_0, SD1_CD), - PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDF_0), PINMUX_IPSR_GPSR(IP11_3_0, SSI_SCK1), PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1), PINMUX_IPSR_GPSR(IP11_3_0, TS_SDEN0), PINMUX_IPSR_GPSR(IP11_7_4, SD1_WP), - PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDF_0), PINMUX_IPSR_GPSR(IP11_7_4, SSI_WS1), PINMUX_IPSR_MSEL(IP11_7_4, RIF0_SYNC_B, SEL_DRIF0_1), PINMUX_IPSR_GPSR(IP11_7_4, TS_SPSYNC0), PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0), PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0), - PINMUX_IPSR_MSEL(IP11_11_8, SSI_SCK2_A, SEL_SSI2_0), + PINMUX_IPSR_GPSR(IP11_11_8, SSI_SCK2_A), PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC), PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1), PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0), PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A), - PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0), + PINMUX_IPSR_GPSR(IP11_15_12, SSI_WS2_A), PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0), PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1), PINMUX_IPSR_MSEL(IP11_19_16, CTS0_N_A, SEL_SCIF0_0), - PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDF_0), PINMUX_IPSR_GPSR(IP11_19_16, AUDIO_CLKOUT_A), PINMUX_IPSR_GPSR(IP11_19_16, RIF1_D1), PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0), PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0), - PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_TANS_A, SEL_SCIF0_0), - PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDFC_0), + PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_A, SEL_SCIF0_0), + PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDF_0), PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A), PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK), PINMUX_IPSR_MSEL(IP11_23_20, SCL2_A, SEL_I2C2_0), @@ -1099,7 +1096,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP11_27_24, SCK0_A, SEL_SCIF0_0), PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_A, SEL_HSCIF1_0), PINMUX_IPSR_GPSR(IP11_27_24, USB3HS0_ID), - PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS), + PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N), PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0), PINMUX_IPSR_MSEL(IP11_27_24, FMCLK_C, SEL_FM_2), PINMUX_IPSR_GPSR(IP11_27_24, USB0_ID), @@ -1183,7 +1180,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0), PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1), PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1), - PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0), + PINMUX_IPSR_GPSR(IP13_19_16, SIM0_D_A), PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT), PINMUX_IPSR_MSEL(IP13_23_20, TX0_B, SEL_SCIF0_1), @@ -1251,7 +1248,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2), PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3), PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1), - PINMUX_IPSR_MSEL(IP15_15_12, SIM0_D_B, SEL_SIMCARD_1), + PINMUX_IPSR_GPSR(IP15_15_12, SIM0_D_B), PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6), PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0), @@ -2842,7 +2839,7 @@ static const unsigned int scif0_ctrl_a_pins[] = { }; static const unsigned int scif0_ctrl_a_mux[] = { - RTS0_N_TANS_A_MARK, CTS0_N_A_MARK, + RTS0_N_A_MARK, CTS0_N_A_MARK, }; static const unsigned int scif0_data_b_pins[] = { @@ -2888,7 +2885,7 @@ static const unsigned int scif1_ctrl_pins[] = { }; static const unsigned int scif1_ctrl_mux[] = { - RTS1_N_TANS_MARK, CTS1_N_MARK, + RTS1_N_MARK, CTS1_N_MARK, }; /* - SCIF2 ------------------------------------------------------------------ */ @@ -2944,7 +2941,7 @@ static const unsigned int scif3_ctrl_a_pins[] = { }; static const unsigned int scif3_ctrl_a_mux[] = { - RTS3_N_TANS_A_MARK, CTS3_N_A_MARK, + RTS3_N_A_MARK, CTS3_N_A_MARK, }; static const unsigned int scif3_data_b_pins[] = { @@ -2999,7 +2996,7 @@ static const unsigned int scif4_ctrl_a_pins[] = { }; static const unsigned int scif4_ctrl_a_mux[] = { - RTS4_N_TANS_A_MARK, CTS4_N_A_MARK, + RTS4_N_A_MARK, CTS4_N_A_MARK, }; static const unsigned int scif4_data_b_pins[] = { @@ -3035,7 +3032,7 @@ static const unsigned int scif4_ctrl_c_pins[] = { }; static const unsigned int scif4_ctrl_c_mux[] = { - RTS4_N_TANS_C_MARK, CTS4_N_C_MARK, + RTS4_N_C_MARK, CTS4_N_C_MARK, }; /* - SCIF5 ------------------------------------------------------------------ */ @@ -3769,8 +3766,8 @@ static const unsigned int vin5_clk_b_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[245]; - struct sh_pfc_pin_group automotive[23]; + struct sh_pfc_pin_group common[247]; + struct sh_pfc_pin_group automotive[21]; } pinmux_groups = { .common = { SH_PFC_PIN_GROUP(audio_clk_a), @@ -3801,6 +3798,8 @@ static const struct { SH_PFC_PIN_GROUP(can0_data), SH_PFC_PIN_GROUP(can1_data), SH_PFC_PIN_GROUP(can_clk), + SH_PFC_PIN_GROUP(canfd0_data), + SH_PFC_PIN_GROUP(canfd1_data), SH_PFC_PIN_GROUP(du_rgb666), SH_PFC_PIN_GROUP(du_rgb888), SH_PFC_PIN_GROUP(du_clk_in_0), @@ -4020,8 +4019,6 @@ static const struct { SH_PFC_PIN_GROUP(vin5_clk_b), }, .automotive = { - SH_PFC_PIN_GROUP(canfd0_data), - SH_PFC_PIN_GROUP(canfd1_data), SH_PFC_PIN_GROUP(drif0_ctrl_a), SH_PFC_PIN_GROUP(drif0_data0_a), SH_PFC_PIN_GROUP(drif0_data1_a), @@ -4468,8 +4465,8 @@ static const char * const vin5_groups[] = { }; static const struct { - struct sh_pfc_function common[45]; - struct sh_pfc_function automotive[6]; + struct sh_pfc_function common[47]; + struct sh_pfc_function automotive[4]; } pinmux_functions = { .common = { SH_PFC_FUNCTION(audio_clk), @@ -4477,6 +4474,8 @@ static const struct { SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(can_clk), + SH_PFC_FUNCTION(canfd0), + SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(du), SH_PFC_FUNCTION(hscif0), SH_PFC_FUNCTION(hscif1), @@ -4519,8 +4518,6 @@ static const struct { SH_PFC_FUNCTION(vin5), }, .automotive = { - SH_PFC_FUNCTION(canfd0), - SH_PFC_FUNCTION(canfd1), SH_PFC_FUNCTION(drif0), SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), @@ -4531,7 +4528,7 @@ static const struct { static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) FN_##y #define FM(x) FN_##x - { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4563,9 +4560,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, GPSR0_3, GP_0_2_FN, GPSR0_2, GP_0_1_FN, GPSR0_1, - GP_0_0_FN, GPSR0_0, } + GP_0_0_FN, GPSR0_0, )) }, - { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4597,9 +4594,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, GPSR1_3, GP_1_2_FN, GPSR1_2, GP_1_1_FN, GPSR1_1, - GP_1_0_FN, GPSR1_0, } + GP_1_0_FN, GPSR1_0, )) }, - { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4631,9 +4628,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, GPSR2_3, GP_2_2_FN, GPSR2_2, GP_2_1_FN, GPSR2_1, - GP_2_0_FN, GPSR2_0, } + GP_2_0_FN, GPSR2_0, )) }, - { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4665,9 +4662,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, GPSR3_3, GP_3_2_FN, GPSR3_2, GP_3_1_FN, GPSR3_1, - GP_3_0_FN, GPSR3_0, } + GP_3_0_FN, GPSR3_0, )) }, - { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4699,9 +4696,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, GPSR4_3, GP_4_2_FN, GPSR4_2, GP_4_1_FN, GPSR4_1, - GP_4_0_FN, GPSR4_0, } + GP_4_0_FN, GPSR4_0, )) }, - { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4733,9 +4730,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, GPSR5_3, GP_5_2_FN, GPSR5_2, GP_5_1_FN, GPSR5_1, - GP_5_0_FN, GPSR5_0, } + GP_5_0_FN, GPSR5_0, )) }, - { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { + { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -4767,14 +4764,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_3_FN, GPSR6_3, GP_6_2_FN, GPSR6_2, GP_6_1_FN, GPSR6_1, - GP_6_0_FN, GPSR6_0, } + GP_6_0_FN, GPSR6_0, )) }, #undef F_ #undef FM #define F_(x, y) x, #define FM(x) FN_##x, - { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { + { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( IP0_31_28 IP0_27_24 IP0_23_20 @@ -4782,9 +4779,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP0_15_12 IP0_11_8 IP0_7_4 - IP0_3_0 } + IP0_3_0 )) }, - { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { + { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( IP1_31_28 IP1_27_24 IP1_23_20 @@ -4792,9 +4789,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP1_15_12 IP1_11_8 IP1_7_4 - IP1_3_0 } + IP1_3_0 )) }, - { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { + { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( IP2_31_28 IP2_27_24 IP2_23_20 @@ -4802,9 +4799,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP2_15_12 IP2_11_8 IP2_7_4 - IP2_3_0 } + IP2_3_0 )) }, - { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { + { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( IP3_31_28 IP3_27_24 IP3_23_20 @@ -4812,9 +4809,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP3_15_12 IP3_11_8 IP3_7_4 - IP3_3_0 } + IP3_3_0 )) }, - { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { + { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( IP4_31_28 IP4_27_24 IP4_23_20 @@ -4822,9 +4819,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP4_15_12 IP4_11_8 IP4_7_4 - IP4_3_0 } + IP4_3_0 )) }, - { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { + { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( IP5_31_28 IP5_27_24 IP5_23_20 @@ -4832,9 +4829,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP5_15_12 IP5_11_8 IP5_7_4 - IP5_3_0 } + IP5_3_0 )) }, - { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { + { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( IP6_31_28 IP6_27_24 IP6_23_20 @@ -4842,9 +4839,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP6_15_12 IP6_11_8 IP6_7_4 - IP6_3_0 } + IP6_3_0 )) }, - { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { + { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( IP7_31_28 IP7_27_24 IP7_23_20 @@ -4852,9 +4849,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP7_15_12 IP7_11_8 IP7_7_4 - IP7_3_0 } + IP7_3_0 )) }, - { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { + { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( IP8_31_28 IP8_27_24 IP8_23_20 @@ -4862,9 +4859,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP8_15_12 IP8_11_8 IP8_7_4 - IP8_3_0 } + IP8_3_0 )) }, - { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { + { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( IP9_31_28 IP9_27_24 IP9_23_20 @@ -4872,9 +4869,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP9_15_12 IP9_11_8 IP9_7_4 - IP9_3_0 } + IP9_3_0 )) }, - { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { + { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( IP10_31_28 IP10_27_24 IP10_23_20 @@ -4882,9 +4879,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP10_15_12 IP10_11_8 IP10_7_4 - IP10_3_0 } + IP10_3_0 )) }, - { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { + { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( IP11_31_28 IP11_27_24 IP11_23_20 @@ -4892,9 +4889,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP11_15_12 IP11_11_8 IP11_7_4 - IP11_3_0 } + IP11_3_0 )) }, - { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { + { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( IP12_31_28 IP12_27_24 IP12_23_20 @@ -4902,9 +4899,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP12_15_12 IP12_11_8 IP12_7_4 - IP12_3_0 } + IP12_3_0 )) }, - { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { + { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( IP13_31_28 IP13_27_24 IP13_23_20 @@ -4912,9 +4909,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP13_15_12 IP13_11_8 IP13_7_4 - IP13_3_0 } + IP13_3_0 )) }, - { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) { + { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP( IP14_31_28 IP14_27_24 IP14_23_20 @@ -4922,9 +4919,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP14_15_12 IP14_11_8 IP14_7_4 - IP14_3_0 } + IP14_3_0 )) }, - { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) { + { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP( IP15_31_28 IP15_27_24 IP15_23_20 @@ -4932,7 +4929,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP15_15_12 IP15_11_8 IP15_7_4 - IP15_3_0 } + IP15_3_0 )) }, #undef F_ #undef FM @@ -4940,8 +4937,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, - 1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, - 1, 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2) { + GROUP(1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, 1, + 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2), + GROUP( /* RESERVED 31 */ 0, 0, MOD_SEL0_30_29 @@ -4965,13 +4963,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_4 MOD_SEL0_3 MOD_SEL0_2 - MOD_SEL0_1_0 } + MOD_SEL0_1_0 )) }, { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, - 1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, - 1, 2, 2, 2, 1, 1, 2, 1, 4) { - MOD_SEL1_31 - MOD_SEL1_30 + GROUP(2, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, 1, + 2, 2, 2, 1, 1, 2, 1, 4), + GROUP( + /* RESERVED 31, 30 */ + 0, 0, 0, 0, MOD_SEL1_29 MOD_SEL1_28 /* RESERVED 27 */ @@ -4992,17 +4991,19 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL1_6_5 MOD_SEL1_4 /* RESERVED 3, 2, 1, 0 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 )) }, { }, }; enum ioctrl_regs { - IOCTRL30, + POCCTRL0, + TDSELCTRL, }; static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { - [IOCTRL30] = { 0xe6060380, }, + [POCCTRL0] = { 0xe6060380, }, + [TDSELCTRL] = { 0xe60603c0, }, { /* sentinel */ }, }; @@ -5011,7 +5012,7 @@ static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, { int bit = -EINVAL; - *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg; + *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) bit = pin & 0x1f; @@ -5127,7 +5128,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { } }, { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { [0] = RCAR_GP_PIN(5, 0), /* SCK0_A */ - [1] = RCAR_GP_PIN(5, 4), /* RTS0#/TANS_A */ + [1] = RCAR_GP_PIN(5, 4), /* RTS0#_A */ [2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */ [3] = RCAR_GP_PIN(5, 2), /* TX0_A */ [4] = RCAR_GP_PIN(5, 1), /* RX0_A */ diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c index ed678584cb..724cf4ae3c 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77995.c +++ b/drivers/pinctrl/renesas/pfc-r8a77995.c @@ -290,7 +290,7 @@ #define IP10_23_20 FM(SSI_SDATA4_A) FM(HTX0) FM(SCL2_A) FM(CAN1_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP10_27_24 FM(SSI_WS4_A) FM(HRX0) FM(SDA2_A) FM(CAN1_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP10_31_28 FM(SCL1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP11_3_0 FM(SDA1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP11_3_0 FM(SDA1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_7_4 FM(MSIOF1_SCK) FM(AVB0_AVTP_PPS_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_11_8 FM(MSIOF1_TXD) FM(AVB0_AVTP_CAPTURE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP11_15_12 FM(MSIOF1_RXD) FM(AVB0_AVTP_MATCH_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -301,7 +301,7 @@ /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ #define IP12_3_0 FM(RX1_A) FM(CTS0_N) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP12_7_4 FM(TX1_A) FM(RTS0_N_TANS) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP12_7_4 FM(TX1_A) FM(RTS0_N) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_11_8 FM(SCK2) FM(MSIOF1_SS1) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_15_12 FM(TPU0TO0_A) FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP12_19_16 FM(TPU0TO1_A) FM(AVB0_AVTP_MATCH_A) FM(HRTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -860,7 +860,7 @@ static const u16 pinmux_data[] = { /* IPSR11 */ PINMUX_IPSR_GPSR(IP11_3_0, SDA1), - PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N_TANS), + PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N), PINMUX_IPSR_GPSR(IP11_7_4, MSIOF1_SCK), PINMUX_IPSR_MSEL(IP11_7_4, AVB0_AVTP_PPS_B, SEL_ETHERAVB_1), @@ -895,7 +895,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP12_3_0, TPU0TO0_B), PINMUX_IPSR_MSEL(IP12_7_4, TX1_A, SEL_SCIF1_0), - PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N_TANS), + PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N), PINMUX_IPSR_GPSR(IP12_7_4, TPU0TO1_B), PINMUX_IPSR_GPSR(IP12_11_8, SCK2), @@ -1707,7 +1707,7 @@ static const unsigned int scif0_ctrl_pins[] = { RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23), }; static const unsigned int scif0_ctrl_mux[] = { - RTS0_N_TANS_MARK, CTS0_N_MARK, + RTS0_N_MARK, CTS0_N_MARK, }; /* - SCIF1 ------------------------------------------------------------------ */ static const unsigned int scif1_data_a_pins[] = { @@ -1743,7 +1743,7 @@ static const unsigned int scif1_ctrl_pins[] = { RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10), }; static const unsigned int scif1_ctrl_mux[] = { - RTS1_N_TANS_MARK, CTS1_N_MARK, + RTS1_N_MARK, CTS1_N_MARK, }; /* - SCIF2 ------------------------------------------------------------------ */ @@ -2377,7 +2377,7 @@ static const struct sh_pfc_function pinmux_functions[] = { static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) FN_##y #define FM(x) FN_##x - { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2409,9 +2409,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, GPSR0_3, GP_0_2_FN, GPSR0_2, GP_0_1_FN, GPSR0_1, - GP_0_0_FN, GPSR0_0, } + GP_0_0_FN, GPSR0_0, )) }, - { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( GP_1_31_FN, GPSR1_31, GP_1_30_FN, GPSR1_30, GP_1_29_FN, GPSR1_29, @@ -2443,9 +2443,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, GPSR1_3, GP_1_2_FN, GPSR1_2, GP_1_1_FN, GPSR1_1, - GP_1_0_FN, GPSR1_0, } + GP_1_0_FN, GPSR1_0, )) }, - { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( GP_2_31_FN, GPSR2_31, GP_2_30_FN, GPSR2_30, GP_2_29_FN, GPSR2_29, @@ -2477,9 +2477,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, GPSR2_3, GP_2_2_FN, GPSR2_2, GP_2_1_FN, GPSR2_1, - GP_2_0_FN, GPSR2_0, } + GP_2_0_FN, GPSR2_0, )) }, - { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2511,9 +2511,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, GPSR3_3, GP_3_2_FN, GPSR3_2, GP_3_1_FN, GPSR3_1, - GP_3_0_FN, GPSR3_0, } + GP_3_0_FN, GPSR3_0, )) }, - { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( GP_4_31_FN, GPSR4_31, GP_4_30_FN, GPSR4_30, GP_4_29_FN, GPSR4_29, @@ -2545,9 +2545,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, GPSR4_3, GP_4_2_FN, GPSR4_2, GP_4_1_FN, GPSR4_1, - GP_4_0_FN, GPSR4_0, } + GP_4_0_FN, GPSR4_0, )) }, - { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2579,9 +2579,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, GPSR5_3, GP_5_2_FN, GPSR5_2, GP_5_1_FN, GPSR5_1, - GP_5_0_FN, GPSR5_0, } + GP_5_0_FN, GPSR5_0, )) }, - { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) { + { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2613,14 +2613,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_3_FN, GPSR6_3, GP_6_2_FN, GPSR6_2, GP_6_1_FN, GPSR6_1, - GP_6_0_FN, GPSR6_0, } + GP_6_0_FN, GPSR6_0, )) }, #undef F_ #undef FM #define F_(x, y) x, #define FM(x) FN_##x, - { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) { + { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( IP0_31_28 IP0_27_24 IP0_23_20 @@ -2628,9 +2628,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP0_15_12 IP0_11_8 IP0_7_4 - IP0_3_0 } + IP0_3_0 )) }, - { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) { + { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( IP1_31_28 IP1_27_24 IP1_23_20 @@ -2638,9 +2638,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP1_15_12 IP1_11_8 IP1_7_4 - IP1_3_0 } + IP1_3_0 )) }, - { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) { + { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( IP2_31_28 IP2_27_24 IP2_23_20 @@ -2648,9 +2648,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP2_15_12 IP2_11_8 IP2_7_4 - IP2_3_0 } + IP2_3_0 )) }, - { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) { + { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( IP3_31_28 IP3_27_24 IP3_23_20 @@ -2658,9 +2658,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP3_15_12 IP3_11_8 IP3_7_4 - IP3_3_0 } + IP3_3_0 )) }, - { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) { + { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( IP4_31_28 IP4_27_24 IP4_23_20 @@ -2668,9 +2668,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP4_15_12 IP4_11_8 IP4_7_4 - IP4_3_0 } + IP4_3_0 )) }, - { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) { + { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( IP5_31_28 IP5_27_24 IP5_23_20 @@ -2678,9 +2678,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP5_15_12 IP5_11_8 IP5_7_4 - IP5_3_0 } + IP5_3_0 )) }, - { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) { + { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( IP6_31_28 IP6_27_24 IP6_23_20 @@ -2688,9 +2688,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP6_15_12 IP6_11_8 IP6_7_4 - IP6_3_0 } + IP6_3_0 )) }, - { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) { + { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( IP7_31_28 IP7_27_24 IP7_23_20 @@ -2698,9 +2698,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP7_15_12 IP7_11_8 IP7_7_4 - IP7_3_0 } + IP7_3_0 )) }, - { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) { + { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( IP8_31_28 IP8_27_24 IP8_23_20 @@ -2708,9 +2708,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP8_15_12 IP8_11_8 IP8_7_4 - IP8_3_0 } + IP8_3_0 )) }, - { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) { + { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( IP9_31_28 IP9_27_24 IP9_23_20 @@ -2718,9 +2718,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP9_15_12 IP9_11_8 IP9_7_4 - IP9_3_0 } + IP9_3_0 )) }, - { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) { + { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( IP10_31_28 IP10_27_24 IP10_23_20 @@ -2728,9 +2728,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP10_15_12 IP10_11_8 IP10_7_4 - IP10_3_0 } + IP10_3_0 )) }, - { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) { + { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( IP11_31_28 IP11_27_24 IP11_23_20 @@ -2738,9 +2738,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP11_15_12 IP11_11_8 IP11_7_4 - IP11_3_0 } + IP11_3_0 )) }, - { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) { + { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( IP12_31_28 IP12_27_24 IP12_23_20 @@ -2748,9 +2748,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP12_15_12 IP12_11_8 IP12_7_4 - IP12_3_0 } + IP12_3_0 )) }, - { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) { + { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( /* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -2758,7 +2758,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* IP13_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, IP13_7_4 - IP13_3_0 } + IP13_3_0 )) }, #undef F_ #undef FM @@ -2766,8 +2766,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, - 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1, - 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1) { + GROUP(1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1, + 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1), + GROUP( /* RESERVED 31 */ 0, 0, MOD_SEL0_30 @@ -2795,11 +2796,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_3 MOD_SEL0_2 MOD_SEL0_1 - MOD_SEL0_0 } + MOD_SEL0_0 )) }, { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, - 1, 1, 1, 1, 1, 1, 2, 4, 4, - 4, 4, 4, 4) { + GROUP(1, 1, 1, 1, 1, 1, 2, 4, 4, 4, 4, 4, 4), + GROUP( MOD_SEL1_31 MOD_SEL1_30 MOD_SEL1_29 @@ -2819,7 +2820,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* RESERVED 7, 6, 5, 4 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* RESERVED 3, 2, 1, 0 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 )) }, { }, }; @@ -2836,6 +2837,15 @@ static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *po return bit; } +enum ioctrl_regs { + TDSELCTRL, +}; + +static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { + [TDSELCTRL] = { 0xe60603c0, }, + { /* sentinel */ }, +}; + static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = { .pin_to_pocctrl = r8a77995_pin_to_pocctrl, }; @@ -2855,6 +2865,7 @@ const struct sh_pfc_soc_info r8a77995_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions), .cfg_regs = pinmux_config_regs, + .ioctrl_regs = pinmux_ioctrl_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c index d1271dad44..f2973bebef 100644 --- a/drivers/pinctrl/renesas/pfc.c +++ b/drivers/pinctrl/renesas/pfc.c @@ -469,7 +469,7 @@ static int sh_pfc_gpio_request_enable(struct udevice *dev, const struct sh_pfc_pin *pin = NULL; int i, ret, idx; - for (i = 1; i < pfc->info->nr_pins; i++) { + for (i = 0; i < pfc->info->nr_pins; i++) { if (priv->pfc.info->pins[i].pin != pin_selector) continue; @@ -505,7 +505,7 @@ static int sh_pfc_gpio_disable_free(struct udevice *dev, const struct sh_pfc_pin *pin = NULL; int i, idx; - for (i = 1; i < pfc->info->nr_pins; i++) { + for (i = 0; i < pfc->info->nr_pins; i++) { if (priv->pfc.info->pins[i].pin != pin_selector) continue; diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index 6629e1f772..f6159b8a3a 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -41,7 +41,8 @@ struct sh_pfc_pin { .name = #alias, \ .pins = n##_pins, \ .mux = n##_mux, \ - .nr_pins = ARRAY_SIZE(n##_pins), \ + .nr_pins = ARRAY_SIZE(n##_pins) + \ + BUILD_BUG_ON_ZERO(sizeof(n##_pins) != sizeof(n##_mux)), \ } #define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n) @@ -110,40 +111,54 @@ struct pinmux_func { struct pinmux_cfg_reg { u32 reg; u8 reg_width, field_width; +#ifdef DEBUG + u16 nr_enum_ids; /* for variable width regs only */ +#define SET_NR_ENUM_IDS(n) .nr_enum_ids = n, +#else +#define SET_NR_ENUM_IDS(n) +#endif const u16 *enum_ids; const u8 *var_field_width; }; +#define GROUP(...) __VA_ARGS__ + /* * Describe a config register consisting of several fields of the same width * - name: Register name (unused, for documentation purposes only) * - r: Physical register address * - r_width: Width of the register (in bits) * - f_width: Width of the fixed-width register fields (in bits) - * This macro must be followed by initialization data: For each register field - * (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified, - * one for each possible combination of the register field bit values. + * - ids: For each register field (from left to right, i.e. MSB to LSB), + * 2^f_width enum IDs must be specified, one for each possible + * combination of the register field bit values, all wrapped using + * the GROUP() macro. */ -#define PINMUX_CFG_REG(name, r, r_width, f_width) \ - .reg = r, .reg_width = r_width, .field_width = f_width, \ - .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) +#define PINMUX_CFG_REG(name, r, r_width, f_width, ids) \ + .reg = r, .reg_width = r_width, \ + .field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) + \ + BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \ + (r_width / f_width) * (1 << f_width)), \ + .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) \ + { ids } /* * Describe a config register consisting of several fields of different widths * - name: Register name (unused, for documentation purposes only) * - r: Physical register address * - r_width: Width of the register (in bits) - * - var_fw0, var_fwn...: List of widths of the register fields (in bits), - * From left to right (i.e. MSB to LSB) - * This macro must be followed by initialization data: For each register field - * (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified, - * one for each possible combination of the register field bit values. + * - f_widths: List of widths of the register fields (in bits), from left + * to right (i.e. MSB to LSB), wrapped using the GROUP() macro. + * - ids: For each register field (from left to right, i.e. MSB to LSB), + * 2^f_widths[i] enum IDs must be specified, one for each possible + * combination of the register field bit values, all wrapped using + * the GROUP() macro. */ -#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ - .reg = r, .reg_width = r_width, \ - .var_field_width = (const u8 [r_width]) \ - { var_fw0, var_fwn, 0 }, \ - .enum_ids = (const u16 []) +#define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \ + .reg = r, .reg_width = r_width, \ + .var_field_width = (const u8 []) { f_widths, 0 }, \ + SET_NR_ENUM_IDS(sizeof((const u16 []) { ids }) / sizeof(u16)) \ + .enum_ids = (const u16 []) { ids } struct pinmux_drive_reg_field { u16 pin; @@ -186,12 +201,14 @@ struct pinmux_data_reg { * - name: Register name (unused, for documentation purposes only) * - r: Physical register address * - r_width: Width of the register (in bits) - * This macro must be followed by initialization data: For each register bit - * (from left to right, i.e. MSB to LSB), one enum ID must be specified. + * - ids: For each register bit (from left to right, i.e. MSB to LSB), one + * enum ID must be specified, all wrapped using the GROUP() macro. */ -#define PINMUX_DATA_REG(name, r, r_width) \ - .reg = r, .reg_width = r_width, \ - .enum_ids = (const u16 [r_width]) \ +#define PINMUX_DATA_REG(name, r, r_width, ids) \ + .reg = r, .reg_width = r_width + \ + BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \ + r_width), \ + .enum_ids = (const u16 [r_width]) { ids } struct pinmux_irq { const short *gpios; @@ -371,8 +388,8 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; /* * Describe a pinmux configuration in which a pin is physically multiplexed * with other pins. - * - ipsr: IPSR field - * - fn: Function name, also referring to the IPSR field + * - ipsr: IPSR field (unused, for documentation purposes only) + * - fn: Function name * - psel: Physical multiplexing selector */ #define PINMUX_IPSR_PHYS(ipsr, fn, psel) \ @@ -632,7 +649,9 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; */ #define PORTCR(nr, reg) \ { \ - PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\ + PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, \ + GROUP(2, 2, 1, 3), \ + GROUP( \ /* PULMD[1:0], handled by .set_bias() */ \ 0, 0, 0, 0, \ /* IE and OE */ \ @@ -644,7 +663,7 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info; PORT##nr##_FN2, PORT##nr##_FN3, \ PORT##nr##_FN4, PORT##nr##_FN5, \ PORT##nr##_FN6, PORT##nr##_FN7 \ - } \ + )) \ } /* diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index ee4cbcb02f..822a3fe265 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -14,6 +14,7 @@ #include <common.h> #include <dm.h> +#include <dm/lists.h> #include <dm/of_access.h> #include <reset-uclass.h> #include <linux/bitops.h> @@ -130,6 +131,23 @@ static int socfpga_reset_remove(struct udevice *dev) return 0; } +static int socfpga_reset_bind(struct udevice *dev) +{ + int ret; + struct udevice *sys_child; + + /* + * The sysreset driver does not have a device node, so bind it here. + * Bind it to the node, too, so that it can get its base address. + */ + ret = device_bind_driver_to_node(dev, "socfpga_sysreset", "sysreset", + dev->node, &sys_child); + if (ret) + debug("Warning: No sysreset driver: ret=%d\n", ret); + + return 0; +} + static const struct udevice_id socfpga_reset_match[] = { { .compatible = "altr,rst-mgr" }, { /* sentinel */ }, @@ -139,6 +157,7 @@ U_BOOT_DRIVER(socfpga_reset) = { .name = "socfpga-reset", .id = UCLASS_RESET, .of_match = socfpga_reset_match, + .bind = socfpga_reset_bind, .probe = socfpga_reset_probe, .priv_auto_alloc_size = sizeof(struct socfpga_reset_data), .ops = &socfpga_reset_ops, diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 0b58a18f5f..860b73d369 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -86,6 +86,11 @@ config RTC_RX8010SJ help Support for Epson RX8010SJ Real Time Clock devices. +config RTC_RX8025 + bool "Enable RX8025 driver" + help + Support for Epson RX8025 Real Time Clock devices. + config RTC_PL031 bool "Enable ARM AMBA PL031 RTC driver" help diff --git a/drivers/rtc/rx8025.c b/drivers/rtc/rx8025.c index 7bd9f8b42a..e717dcbbfe 100644 --- a/drivers/rtc/rx8025.c +++ b/drivers/rtc/rx8025.c @@ -10,8 +10,9 @@ #include <common.h> #include <command.h> -#include <rtc.h> +#include <dm.h> #include <i2c.h> +#include <rtc.h> /*---------------------------------------------------------------------*/ #undef DEBUG_RTC @@ -27,6 +28,18 @@ # define CONFIG_SYS_I2C_RTC_ADDR 0x32 #endif +#ifdef CONFIG_DM_RTC +#define DEV_TYPE struct udevice +#else +/* Local udevice */ +struct ludevice { + u8 chip; +}; + +#define DEV_TYPE struct ludevice + +#endif + /* * RTC register addresses */ @@ -68,21 +81,35 @@ */ /* static uchar rtc_read (uchar reg); */ +#ifdef CONFIG_DM_RTC +/* + * on mpc85xx based board with DM and offset len 1 + * accessing rtc works fine. May we can drop this ? + */ +#define rtc_read(reg) buf[(reg) & 0xf] +#else #define rtc_read(reg) buf[((reg) + 1) & 0xf] +#endif -static void rtc_write (uchar reg, uchar val); +static int rtc_write(DEV_TYPE *dev, uchar reg, uchar val); /* * Get the current time from the RTC */ -int rtc_get (struct rtc_time *tmp) +static int rx8025_rtc_get(DEV_TYPE *dev, struct rtc_time *tmp) { int rel = 0; uchar sec, min, hour, mday, wday, mon, year, ctl2; uchar buf[16]; - if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 16)) +#ifdef CONFIG_DM_RTC + if (dm_i2c_read(dev, 0, buf, sizeof(buf))) { +#else + if (i2c_read(dev->chip, 0, 0, buf, 16)) { +#endif printf("Error reading from RTC\n"); + return -EIO; + } sec = rtc_read(RTC_SEC_REG_ADDR); min = rtc_read(RTC_MIN_REG_ADDR); @@ -92,9 +119,9 @@ int rtc_get (struct rtc_time *tmp) mon = rtc_read(RTC_MON_REG_ADDR); year = rtc_read(RTC_YR_REG_ADDR); - DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x " - "hr: %02x min: %02x sec: %02x\n", - year, mon, mday, wday, hour, min, sec); + DEBUGR("Get RTC year: %02x mon: %02x mday: %02x wday: %02x " + "hr: %02x min: %02x sec: %02x\n", + year, mon, mday, wday, hour, min, sec); /* dump status */ ctl2 = rtc_read(RTC_CTL2_REG_ADDR); @@ -113,13 +140,14 @@ int rtc_get (struct rtc_time *tmp) rel = -1; } - tmp->tm_sec = bcd2bin (sec & 0x7F); - tmp->tm_min = bcd2bin (min & 0x7F); + tmp->tm_sec = bcd2bin(sec & 0x7F); + tmp->tm_min = bcd2bin(min & 0x7F); if (rtc_read(RTC_CTL1_REG_ADDR) & RTC_CTL1_BIT_2412) - tmp->tm_hour = bcd2bin (hour & 0x3F); + tmp->tm_hour = bcd2bin(hour & 0x3F); else - tmp->tm_hour = bcd2bin (hour & 0x1F) % 12 + + tmp->tm_hour = bcd2bin(hour & 0x1F) % 12 + ((hour & 0x20) ? 12 : 0); + tmp->tm_mday = bcd2bin (mday & 0x3F); tmp->tm_mon = bcd2bin (mon & 0x1F); tmp->tm_year = bcd2bin (year) + ( bcd2bin (year) >= 70 ? 1900 : 2000); @@ -127,9 +155,9 @@ int rtc_get (struct rtc_time *tmp) tmp->tm_yday = 0; tmp->tm_isdst= 0; - DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + DEBUGR("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); return rel; } @@ -137,54 +165,142 @@ int rtc_get (struct rtc_time *tmp) /* * Set the RTC */ -int rtc_set (struct rtc_time *tmp) +static int rx8025_rtc_set(DEV_TYPE *dev, const struct rtc_time *tmp) { - DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + DEBUGR("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); if (tmp->tm_year < 1970 || tmp->tm_year > 2069) printf("WARNING: year should be between 1970 and 2069!\n"); - rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100)); - rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon)); - rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday)); - rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday)); - rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour)); - rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min)); - rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec)); + if (rtc_write(dev, RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100))) + return -EIO; - rtc_write (RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412); + if (rtc_write(dev, RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon))) + return -EIO; - return 0; + if (rtc_write(dev, RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday))) + return -EIO; + + if (rtc_write(dev, RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday))) + return -EIO; + + if (rtc_write(dev, RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour))) + return -EIO; + + if (rtc_write(dev, RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min))) + return -EIO; + + if (rtc_write(dev, RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec))) + return -EIO; + + return rtc_write(dev, RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412); } /* * Reset the RTC */ -void rtc_reset (void) +static int rx8025_rtc_reset(DEV_TYPE *dev) { uchar buf[16]; uchar ctl2; - if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 16)) +#ifdef CONFIG_DM_RTC + if (dm_i2c_read(dev, 0, buf, sizeof(buf))) { +#else + if (i2c_read(dev->chip, 0, 0, buf, 16)) { +#endif printf("Error reading from RTC\n"); + return -EIO; + } ctl2 = rtc_read(RTC_CTL2_REG_ADDR); ctl2 &= ~(RTC_CTL2_BIT_PON | RTC_CTL2_BIT_VDET); ctl2 |= RTC_CTL2_BIT_XST | RTC_CTL2_BIT_VDSL; - rtc_write (RTC_CTL2_REG_ADDR, ctl2); + + return rtc_write(dev, RTC_CTL2_REG_ADDR, ctl2); } /* * Helper functions */ -static void rtc_write (uchar reg, uchar val) +static int rtc_write(DEV_TYPE *dev, uchar reg, uchar val) { uchar buf[2]; buf[0] = reg << 4; buf[1] = val; - if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 2) != 0) + +#ifdef CONFIG_DM_RTC + if (dm_i2c_write(dev, 0, buf, 2)) { +#else + if (i2c_write(dev->chip, 0, 0, buf, 2) != 0) { +#endif printf("Error writing to RTC\n"); + return -EIO; + } + return 0; } + +#ifdef CONFIG_DM_RTC +static int rx8025_probe(struct udevice *dev) +{ + uchar buf[16]; + int ret = 0; + + if (i2c_get_chip_offset_len(dev) != 1) + ret = i2c_set_chip_offset_len(dev, 1); + + if (ret) + return ret; + + return dm_i2c_read(dev, 0, buf, sizeof(buf)); +} + +static const struct rtc_ops rx8025_rtc_ops = { + .get = rx8025_rtc_get, + .set = rx8025_rtc_set, + .reset = rx8025_rtc_reset, +}; + +static const struct udevice_id rx8025_rtc_ids[] = { + { .compatible = "epson,rx8025" }, + { } +}; + +U_BOOT_DRIVER(rx8010sj_rtc) = { + .name = "rx8025_rtc", + .id = UCLASS_RTC, + .probe = rx8025_probe, + .of_match = rx8025_rtc_ids, + .ops = &rx8025_rtc_ops, +}; +#else +int rtc_get(struct rtc_time *tm) +{ + struct ludevice dev = { + .chip = CONFIG_SYS_I2C_RTC_ADDR, + }; + + return rx8025_rtc_get(&dev, tm); +} + +int rtc_set(struct rtc_time *tm) +{ + struct ludevice dev = { + .chip = CONFIG_SYS_I2C_RTC_ADDR, + }; + + return rx8025_rtc_set(&dev, tm); +} + +void rtc_reset(void) +{ + struct ludevice dev = { + .chip = CONFIG_SYS_I2C_RTC_ADDR, + }; + + rx8025_rtc_reset(&dev); +} +#endif diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 30aed2c4c1..90c41ab44d 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -50,10 +50,25 @@ config SYSRESET_MICROBLAZE config SYSRESET_PSCI bool "Enable support for PSCI System Reset" depends on ARM_PSCI_FW + select SPL_ARM_PSCI_FW if SPL help Enable PSCI SYSTEM_RESET function call. To use this, PSCI firmware must be running on your system. +config SYSRESET_SOCFPGA + bool "Enable support for Intel SOCFPGA family" + depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10) + help + This enables the system reset driver support for Intel SOCFPGA SoCs + (Cyclone 5, Arria 5 and Arria 10). + +config SYSRESET_SOCFPGA_S10 + bool "Enable support for Intel SOCFPGA Stratix 10" + depends on ARCH_SOCFPGA && TARGET_SOCFPGA_STRATIX10 + help + This enables the system reset driver support for Intel SOCFPGA + Stratix SoCs. + config SYSRESET_TI_SCI bool "TI System Control Interface (TI SCI) system reset driver" depends on TI_SCI_PROTOCOL diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index 8e1c845dfe..cf01492295 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -11,6 +11,8 @@ obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o obj-$(CONFIG_SYSRESET_MCP83XX) += sysreset_mpc83xx.o obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o +obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o +obj-$(CONFIG_SYSRESET_SOCFPGA_S10) += sysreset_socfpga_s10.o obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o diff --git a/drivers/sysreset/sysreset_socfpga.c b/drivers/sysreset/sysreset_socfpga.c new file mode 100644 index 0000000000..d6c26a5b23 --- /dev/null +++ b/drivers/sysreset/sysreset_socfpga.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Pepperl+Fuchs + * Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <sysreset.h> +#include <asm/io.h> +#include <asm/arch/reset_manager.h> + +struct socfpga_sysreset_data { + struct socfpga_reset_manager *rstmgr_base; +}; + +static int socfpga_sysreset_request(struct udevice *dev, + enum sysreset_t type) +{ + struct socfpga_sysreset_data *data = dev_get_priv(dev); + + switch (type) { + case SYSRESET_WARM: + writel(BIT(RSTMGR_CTRL_SWWARMRSTREQ_LSB), + &data->rstmgr_base->ctrl); + break; + case SYSRESET_COLD: + writel(BIT(RSTMGR_CTRL_SWCOLDRSTREQ_LSB), + &data->rstmgr_base->ctrl); + break; + default: + return -EPROTONOSUPPORT; + } + return -EINPROGRESS; +} + +static int socfpga_sysreset_probe(struct udevice *dev) +{ + struct socfpga_sysreset_data *data = dev_get_priv(dev); + + data->rstmgr_base = devfdt_get_addr_ptr(dev); + return 0; +} + +static struct sysreset_ops socfpga_sysreset = { + .request = socfpga_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_socfpga) = { + .id = UCLASS_SYSRESET, + .name = "socfpga_sysreset", + .priv_auto_alloc_size = sizeof(struct socfpga_sysreset_data), + .ops = &socfpga_sysreset, + .probe = socfpga_sysreset_probe, +}; diff --git a/drivers/sysreset/sysreset_socfpga_s10.c b/drivers/sysreset/sysreset_socfpga_s10.c new file mode 100644 index 0000000000..9837aadf64 --- /dev/null +++ b/drivers/sysreset/sysreset_socfpga_s10.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Pepperl+Fuchs + * Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <sysreset.h> +#include <asm/arch/mailbox_s10.h> + +static int socfpga_sysreset_request(struct udevice *dev, + enum sysreset_t type) +{ + puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n"); + mbox_reset_cold(); + return -EINPROGRESS; +} + +static struct sysreset_ops socfpga_sysreset = { + .request = socfpga_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_socfpga) = { + .id = UCLASS_SYSRESET, + .name = "socfpga_sysreset", + .ops = &socfpga_sysreset, +}; diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index c3781b160d..261fa98517 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -484,7 +484,7 @@ config VIDEO_IVYBRIDGE_IGD config VIDEO_FSL_DCU_FB bool "Enable Freescale Display Control Unit" - depends on VIDEO + depends on VIDEO || DM_VIDEO help This enables support for Freescale Display Control Unit (DCU4) module found on Freescale Vybrid and QorIQ family of SoCs. diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c index bc41090aed..1d2eda084c 100644 --- a/drivers/video/bcm2835.c +++ b/drivers/video/bcm2835.c @@ -19,13 +19,15 @@ static int bcm2835_video_probe(struct udevice *dev) debug("bcm2835: Query resolution...\n"); ret = bcm2835_get_video_size(&w, &h); - if (ret) + if (ret || w == 0 || h == 0) return -EIO; debug("bcm2835: Setting up display for %d x %d\n", w, h); ret = bcm2835_set_video_params(&w, &h, 32, BCM2835_MBOX_PIXEL_ORDER_RGB, BCM2835_MBOX_ALPHA_MODE_IGNORED, &fb_base, &fb_size, &pitch); + if (ret) + return -EIO; debug("bcm2835: Final resolution is %d x %d\n", w, h); diff --git a/drivers/video/display-uclass.c b/drivers/video/display-uclass.c index 99ef5e76f5..1a29ce5d85 100644 --- a/drivers/video/display-uclass.c +++ b/drivers/video/display-uclass.c @@ -37,6 +37,17 @@ int display_enable(struct udevice *dev, int panel_bpp, return 0; } +static bool display_mode_valid(void *priv, const struct display_timing *timing) +{ + struct udevice *dev = priv; + struct dm_display_ops *ops = display_get_ops(dev); + + if (ops && ops->mode_valid) + return ops->mode_valid(dev, timing); + + return true; +} + int display_read_timing(struct udevice *dev, struct display_timing *timing) { struct dm_display_ops *ops = display_get_ops(dev); @@ -53,7 +64,9 @@ int display_read_timing(struct udevice *dev, struct display_timing *timing) if (ret < 0) return ret; - return edid_get_timing(buf, ret, timing, &panel_bits_per_colour); + return edid_get_timing_validate(buf, ret, timing, + &panel_bits_per_colour, + display_mode_valid, dev); } bool display_in_use(struct udevice *dev) diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c index 463436edf3..bf74d6adf2 100644 --- a/drivers/video/dw_hdmi.c +++ b/drivers/video/dw_hdmi.c @@ -8,6 +8,7 @@ #include <common.h> #include <fdtdec.h> #include <asm/io.h> +#include <i2c.h> #include <media_bus_format.h> #include "dw_hdmi.h" @@ -812,6 +813,18 @@ static int hdmi_read_edid(struct dw_hdmi *hdmi, int block, u8 *buff) u32 trytime = 5; u32 n; + if (CONFIG_IS_ENABLED(DM_I2C) && hdmi->ddc_bus) { + struct udevice *chip; + + edid_read_err = i2c_get_chip(hdmi->ddc_bus, + HDMI_I2CM_SLAVE_DDC_ADDR, + 1, &chip); + if (edid_read_err) + return edid_read_err; + + return dm_i2c_read(chip, shift, buff, HDMI_EDID_BLOCK_SIZE); + } + /* set ddc i2c clk which devided from ddc_clk to 100khz */ hdmi_write(hdmi, hdmi->i2c_clk_high, HDMI_I2CM_SS_SCL_HCNT_0_ADDR); hdmi_write(hdmi, hdmi->i2c_clk_low, HDMI_I2CM_SS_SCL_LCNT_0_ADDR); diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c index 9f6e7f83b0..add64b85b5 100644 --- a/drivers/video/fsl_dcu_fb.c +++ b/drivers/video/fsl_dcu_fb.c @@ -1,16 +1,19 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2019 Toradex AG * * FSL DCU Framebuffer driver */ #include <asm/io.h> #include <common.h> +#include <dm.h> #include <fdt_support.h> #include <fsl_dcu_fb.h> #include <linux/fb.h> #include <malloc.h> +#include <video.h> #include <video_fb.h> #include "videomodes.h" @@ -218,8 +221,6 @@ struct dcu_reg { u32 ctrldescl[DCU_LAYER_MAX_NUM][16]; }; -static struct fb_info info; - static void reset_total_layers(void) { struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR; @@ -240,20 +241,22 @@ static void reset_total_layers(void) } } -static int layer_ctrldesc_init(int index, u32 pixel_format) +static int layer_ctrldesc_init(struct fb_info fbinfo, + int index, u32 pixel_format) { struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR; unsigned int bpp = BPP_24_RGB888; dcu_write32(®s->ctrldescl[index][0], - DCU_CTRLDESCLN_1_HEIGHT(info.var.yres) | - DCU_CTRLDESCLN_1_WIDTH(info.var.xres)); + DCU_CTRLDESCLN_1_HEIGHT(fbinfo.var.yres) | + DCU_CTRLDESCLN_1_WIDTH(fbinfo.var.xres)); dcu_write32(®s->ctrldescl[index][1], DCU_CTRLDESCLN_2_POSY(0) | DCU_CTRLDESCLN_2_POSX(0)); - dcu_write32(®s->ctrldescl[index][2], (unsigned int)info.screen_base); + dcu_write32(®s->ctrldescl[index][2], + (unsigned int)fbinfo.screen_base); switch (pixel_format) { case 16: @@ -294,42 +297,46 @@ static int layer_ctrldesc_init(int index, u32 pixel_format) return 0; } -int fsl_dcu_init(unsigned int xres, unsigned int yres, - unsigned int pixel_format) +int fsl_dcu_init(struct fb_info *fbinfo, unsigned int xres, + unsigned int yres, unsigned int pixel_format) { struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR; unsigned int div, mode; +/* + * When DM_VIDEO is enabled reservation of framebuffer is done + * in advance during bind() call. + */ +#if !CONFIG_IS_ENABLED(DM_VIDEO) + fbinfo->screen_size = fbinfo->var.xres * fbinfo->var.yres * + (fbinfo->var.bits_per_pixel / 8); - info.screen_size = - info.var.xres * info.var.yres * (info.var.bits_per_pixel / 8); - - if (info.screen_size > CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB) { - info.screen_size = 0; + if (fbinfo->screen_size > CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB) { + fbinfo->screen_size = 0; return -ENOMEM; } - /* Reserve framebuffer at the end of memory */ gd->fb_base = gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size - info.screen_size; - info.screen_base = (char *)gd->fb_base; + gd->bd->bi_dram[0].size - fbinfo->screen_size; + fbinfo->screen_base = (char *)gd->fb_base; - memset(info.screen_base, 0, info.screen_size); + memset(fbinfo->screen_base, 0, fbinfo->screen_size); +#endif reset_total_layers(); dcu_write32(®s->disp_size, - DCU_DISP_SIZE_DELTA_Y(info.var.yres) | - DCU_DISP_SIZE_DELTA_X(info.var.xres / 16)); + DCU_DISP_SIZE_DELTA_Y(fbinfo->var.yres) | + DCU_DISP_SIZE_DELTA_X(fbinfo->var.xres / 16)); dcu_write32(®s->hsyn_para, - DCU_HSYN_PARA_BP(info.var.left_margin) | - DCU_HSYN_PARA_PW(info.var.hsync_len) | - DCU_HSYN_PARA_FP(info.var.right_margin)); + DCU_HSYN_PARA_BP(fbinfo->var.left_margin) | + DCU_HSYN_PARA_PW(fbinfo->var.hsync_len) | + DCU_HSYN_PARA_FP(fbinfo->var.right_margin)); dcu_write32(®s->vsyn_para, - DCU_VSYN_PARA_BP(info.var.upper_margin) | - DCU_VSYN_PARA_PW(info.var.vsync_len) | - DCU_VSYN_PARA_FP(info.var.lower_margin)); + DCU_VSYN_PARA_BP(fbinfo->var.upper_margin) | + DCU_VSYN_PARA_PW(fbinfo->var.vsync_len) | + DCU_VSYN_PARA_FP(fbinfo->var.lower_margin)); dcu_write32(®s->synpol, DCU_SYN_POL_INV_PXCK_FALL | @@ -352,9 +359,9 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres, mode = dcu_read32(®s->mode); dcu_write32(®s->mode, mode | DCU_MODE_NORMAL); - layer_ctrldesc_init(0, pixel_format); + layer_ctrldesc_init(*fbinfo, 0, pixel_format); - div = dcu_set_pixel_clock(info.var.pixclock); + div = dcu_set_pixel_clock(fbinfo->var.pixclock); dcu_write32(®s->div_ratio, (div - 1)); dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG); @@ -367,24 +374,26 @@ ulong board_get_usable_ram_top(ulong total_size) return gd->ram_top - CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB; } -void *video_hw_init(void) +int fsl_probe_common(struct fb_info *fbinfo, unsigned int *win_x, + unsigned int *win_y) { - static GraphicDevice ctfb; const char *options; unsigned int depth = 0, freq = 0; + struct fb_videomode *fsl_dcu_mode_db = &fsl_dcu_mode_480_272; - if (!video_get_video_mode(&ctfb.winSizeX, &ctfb.winSizeY, &depth, &freq, + if (!video_get_video_mode(win_x, win_y, &depth, &freq, &options)) - return NULL; + return -EINVAL; /* Find the monitor port, which is a required option */ if (!options) - return NULL; + return -EINVAL; + if (strncmp(options, "monitor=", 8) != 0) - return NULL; + return -EINVAL; - switch (RESOLUTION(ctfb.winSizeX, ctfb.winSizeY)) { + switch (RESOLUTION(*win_x, *win_y)) { case RESOLUTION(480, 272): fsl_dcu_mode_db = &fsl_dcu_mode_480_272; break; @@ -402,39 +411,31 @@ void *video_hw_init(void) break; default: printf("unsupported resolution %ux%u\n", - ctfb.winSizeX, ctfb.winSizeY); + *win_x, *win_y); } - info.var.xres = fsl_dcu_mode_db->xres; - info.var.yres = fsl_dcu_mode_db->yres; - info.var.bits_per_pixel = 32; - info.var.pixclock = fsl_dcu_mode_db->pixclock; - info.var.left_margin = fsl_dcu_mode_db->left_margin; - info.var.right_margin = fsl_dcu_mode_db->right_margin; - info.var.upper_margin = fsl_dcu_mode_db->upper_margin; - info.var.lower_margin = fsl_dcu_mode_db->lower_margin; - info.var.hsync_len = fsl_dcu_mode_db->hsync_len; - info.var.vsync_len = fsl_dcu_mode_db->vsync_len; - info.var.sync = fsl_dcu_mode_db->sync; - info.var.vmode = fsl_dcu_mode_db->vmode; - info.fix.line_length = info.var.xres * info.var.bits_per_pixel / 8; - - if (platform_dcu_init(ctfb.winSizeX, ctfb.winSizeY, - options + 8, fsl_dcu_mode_db) < 0) - return NULL; - - ctfb.frameAdrs = (unsigned int)info.screen_base; - ctfb.plnSizeX = ctfb.winSizeX; - ctfb.plnSizeY = ctfb.winSizeY; - - ctfb.gdfBytesPP = 4; - ctfb.gdfIndex = GDF_32BIT_X888RGB; - - ctfb.memSize = info.screen_size; - - return &ctfb; + fbinfo->var.xres = fsl_dcu_mode_db->xres; + fbinfo->var.yres = fsl_dcu_mode_db->yres; + fbinfo->var.bits_per_pixel = 32; + fbinfo->var.pixclock = fsl_dcu_mode_db->pixclock; + fbinfo->var.left_margin = fsl_dcu_mode_db->left_margin; + fbinfo->var.right_margin = fsl_dcu_mode_db->right_margin; + fbinfo->var.upper_margin = fsl_dcu_mode_db->upper_margin; + fbinfo->var.lower_margin = fsl_dcu_mode_db->lower_margin; + fbinfo->var.hsync_len = fsl_dcu_mode_db->hsync_len; + fbinfo->var.vsync_len = fsl_dcu_mode_db->vsync_len; + fbinfo->var.sync = fsl_dcu_mode_db->sync; + fbinfo->var.vmode = fsl_dcu_mode_db->vmode; + fbinfo->fix.line_length = fbinfo->var.xres * + fbinfo->var.bits_per_pixel / 8; + + return platform_dcu_init(fbinfo, *win_x, *win_y, + options + 8, fsl_dcu_mode_db); } +#ifndef CONFIG_DM_VIDEO +static struct fb_info info; + #if defined(CONFIG_OF_BOARD_SETUP) int fsl_dcu_fixedfb_setup(void *blob) { @@ -457,3 +458,89 @@ int fsl_dcu_fixedfb_setup(void *blob) return 0; } #endif + +void *video_hw_init(void) +{ + static GraphicDevice ctfb; + + if (fsl_probe_common(&info, &ctfb.winSizeX, &ctfb.winSizeY) < 0) + return NULL; + + ctfb.frameAdrs = (unsigned int)info.screen_base; + ctfb.plnSizeX = ctfb.winSizeX; + ctfb.plnSizeY = ctfb.winSizeY; + + ctfb.gdfBytesPP = 4; + ctfb.gdfIndex = GDF_32BIT_X888RGB; + + ctfb.memSize = info.screen_size; + + return &ctfb; +} + +#else /* ifndef CONFIG_DM_VIDEO */ + +static int fsl_dcu_video_probe(struct udevice *dev) +{ + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + struct fb_info fbinfo = { 0 }; + unsigned int win_x; + unsigned int win_y; + u32 fb_start, fb_end; + int ret = 0; + + fb_start = plat->base & ~(MMU_SECTION_SIZE - 1); + fb_end = plat->base + plat->size; + fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT); + + fbinfo.screen_base = (char *)fb_start; + fbinfo.screen_size = plat->size; + + ret = fsl_probe_common(&fbinfo, &win_x, &win_y); + if (ret < 0) + return ret; + + uc_priv->bpix = VIDEO_BPP32; + uc_priv->xsize = win_x; + uc_priv->ysize = win_y; + + /* Enable dcache for the frame buffer */ + mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start, + DCACHE_WRITEBACK); + video_set_flush_dcache(dev, true); + return ret; +} + +static int fsl_dcu_video_bind(struct udevice *dev) +{ + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + unsigned int win_x; + unsigned int win_y; + unsigned int depth = 0, freq = 0; + const char *options; + int ret = 0; + + ret = video_get_video_mode(&win_x, &win_y, &depth, &freq, &options); + if (ret < 0) + return ret; + + plat->size = win_x * win_y * 32; + + return 0; +} + +static const struct udevice_id fsl_dcu_video_ids[] = { + { .compatible = "fsl,vf610-dcu" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(fsl_dcu_video) = { + .name = "fsl_dcu_video", + .id = UCLASS_VIDEO, + .of_match = fsl_dcu_video_ids, + .bind = fsl_dcu_video_bind, + .probe = fsl_dcu_video_probe, + .flags = DM_FLAG_PRE_RELOC, +}; +#endif /* ifndef CONFIG_DM_VIDEO */ diff --git a/drivers/video/imx/mxc_ipuv3_fb.c b/drivers/video/imx/mxc_ipuv3_fb.c index 29ecac40a2..c64be38e49 100644 --- a/drivers/video/imx/mxc_ipuv3_fb.c +++ b/drivers/video/imx/mxc_ipuv3_fb.c @@ -24,6 +24,8 @@ #include "ipu.h" #include "mxcfb.h" #include "ipu_regs.h" +#include "display.h" +#include <panel.h> #include <dm.h> #include <video.h> @@ -609,6 +611,7 @@ void *video_hw_init(void) ret = mxcfb_probe(gpixfmt, gdisp, gmode); debug("Framebuffer at 0x%x\n", (unsigned int)panel.frameAdrs); + gd->fb_base = panel.frameAdrs; return (void *)&panel; } @@ -636,6 +639,10 @@ static int ipuv3_video_probe(struct udevice *dev) { struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); struct video_priv *uc_priv = dev_get_uclass_priv(dev); +#if defined(CONFIG_DISPLAY) + struct udevice *disp_dev; +#endif + struct udevice *panel_dev; u32 fb_start, fb_end; int ret; @@ -654,6 +661,18 @@ static int ipuv3_video_probe(struct udevice *dev) if (ret < 0) return ret; +#if defined(CONFIG_DISPLAY) + ret = uclass_first_device(UCLASS_DISPLAY, &disp_dev); + if (disp_dev) { + ret = display_enable(disp_dev, 16, NULL); + if (ret < 0) + return ret; + } +#endif + ret = uclass_get_device(UCLASS_PANEL, 0, &panel_dev); + if (panel_dev) + panel_enable_backlight(panel_dev); + uc_priv->xsize = gmode->xres; uc_priv->ysize = gmode->yres; uc_priv->bpix = LCD_MAX_LOG2_BPP; @@ -665,6 +684,7 @@ static int ipuv3_video_probe(struct udevice *dev) mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start, DCACHE_WRITEBACK); video_set_flush_dcache(dev, true); + gd->fb_base = fb_start; return 0; } diff --git a/drivers/video/meson/meson_dw_hdmi.c b/drivers/video/meson/meson_dw_hdmi.c index 483c93f6b6..9831d978fc 100644 --- a/drivers/video/meson/meson_dw_hdmi.c +++ b/drivers/video/meson/meson_dw_hdmi.c @@ -375,6 +375,9 @@ static int meson_dw_hdmi_probe(struct udevice *dev) } #endif + uclass_get_device_by_phandle(UCLASS_I2C, dev, "ddc-i2c-bus", + &priv->hdmi.ddc_bus); + ret = reset_get_bulk(dev, &resets); if (ret) return ret; @@ -426,9 +429,16 @@ static int meson_dw_hdmi_probe(struct udevice *dev) return ret; } +static bool meson_dw_hdmi_mode_valid(struct udevice *dev, + const struct display_timing *timing) +{ + return meson_venc_hdmi_supported_mode(timing); +} + static const struct dm_display_ops meson_dw_hdmi_ops = { .read_edid = meson_dw_hdmi_read_edid, .enable = meson_dw_hdmi_enable, + .mode_valid = meson_dw_hdmi_mode_valid, }; static const struct udevice_id meson_dw_hdmi_ids[] = { diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index f02ba20138..6c9a7c05e8 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -271,6 +271,42 @@ dealloc_fb: } #else /* ifndef CONFIG_DM_VIDEO */ +static int mxs_of_get_timings(struct udevice *dev, + struct display_timing *timings, + u32 *bpp) +{ + int ret = 0; + u32 display_phandle; + ofnode display_node; + + ret = ofnode_read_u32(dev_ofnode(dev), "display", &display_phandle); + if (ret) { + dev_err(dev, "required display property isn't provided\n"); + return -EINVAL; + } + + display_node = ofnode_get_by_phandle(display_phandle); + if (!ofnode_valid(display_node)) { + dev_err(dev, "failed to find display subnode\n"); + return -EINVAL; + } + + ret = ofnode_read_u32(display_node, "bits-per-pixel", bpp); + if (ret) { + dev_err(dev, + "required bits-per-pixel property isn't provided\n"); + return -EINVAL; + } + + ret = ofnode_decode_display_timing(display_node, 0, timings); + if (ret) { + dev_err(dev, "failed to get any display timings\n"); + return -EINVAL; + } + + return ret; +} + static int mxs_video_probe(struct udevice *dev) { struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); @@ -278,18 +314,16 @@ static int mxs_video_probe(struct udevice *dev) struct ctfb_res_modes mode; struct display_timing timings; - int bpp = -1; + u32 bpp = 0; u32 fb_start, fb_end; int ret; debug("%s() plat: base 0x%lx, size 0x%x\n", __func__, plat->base, plat->size); - ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, &timings); - if (ret) { - dev_err(dev, "failed to get any display timings\n"); - return -EINVAL; - } + ret = mxs_of_get_timings(dev, &timings, &bpp); + if (ret) + return ret; mode.xres = timings.hactive.typ; mode.yres = timings.vactive.typ; @@ -301,13 +335,12 @@ static int mxs_video_probe(struct udevice *dev) mode.vsync_len = timings.vsync_len.typ; mode.pixclock = HZ2PS(timings.pixelclock.typ); - bpp = BITS_PP; - ret = mxs_probe_common(&mode, bpp, plat->base); if (ret) return ret; switch (bpp) { + case 32: case 24: case 18: uc_priv->bpix = VIDEO_BPP32; @@ -341,15 +374,32 @@ static int mxs_video_bind(struct udevice *dev) { struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); struct display_timing timings; + u32 bpp = 0; + u32 bytes_pp = 0; int ret; - ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, &timings); - if (ret) { - dev_err(dev, "failed to get any display timings\n"); + ret = mxs_of_get_timings(dev, &timings, &bpp); + if (ret) + return ret; + + switch (bpp) { + case 32: + case 24: + case 18: + bytes_pp = 4; + break; + case 16: + bytes_pp = 2; + break; + case 8: + bytes_pp = 1; + break; + default: + dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp); return -EINVAL; } - plat->size = timings.hactive.typ * timings.vactive.typ * BYTES_PP; + plat->size = timings.hactive.typ * timings.vactive.typ * bytes_pp; return 0; } diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c index 51931ceefa..5b44a7e8c9 100644 --- a/drivers/video/rockchip/rk_hdmi.c +++ b/drivers/video/rockchip/rk_hdmi.c @@ -93,6 +93,9 @@ int rk_hdmi_ofdata_to_platdata(struct udevice *dev) priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + uclass_get_device_by_phandle(UCLASS_I2C, dev, "ddc-i2c-bus", + &hdmi->ddc_bus); + return 0; } diff --git a/drivers/video/simple_panel.c b/drivers/video/simple_panel.c index 7a968e740c..c3c0e84732 100644 --- a/drivers/video/simple_panel.c +++ b/drivers/video/simple_panel.c @@ -105,6 +105,7 @@ static const struct udevice_id simple_panel_ids[] = { { .compatible = "auo,b133xtn01" }, { .compatible = "auo,b116xw03" }, { .compatible = "auo,b133htn01" }, + { .compatible = "lg,lb070wv8" }, { } }; diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index 6fe1aa7ee4..cec23295b5 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -373,6 +373,9 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev) priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg; priv->mux = uc_plat->source_id; + uclass_get_device_by_phandle(UCLASS_I2C, dev, "ddc-i2c-bus", + &priv->hdmi.ddc_bus); + dw_hdmi_init(&priv->hdmi); return 0; |