diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_training.c | 6 | ||||
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr_topology_def.h | 9 |
2 files changed, 15 insertions, 0 deletions
diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c index 7e0749fde3..e70ca4b425 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training.c +++ b/drivers/ddr/marvell/a38x/ddr3_training.c @@ -308,6 +308,7 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ enum hws_speed_bin speed_bin_index = SPEED_BIN_DDR_2133N; enum hws_mem_size memory_size = MEM_2G; enum hws_ddr_freq freq = init_freq; + enum hws_timing timing; u32 cs_mask = 0; u32 cl_value = 0, cwl_val = 0; u32 refresh_interval_cnt = 0, bus_cnt = 0, adll_tap = 0; @@ -569,8 +570,13 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ DUNIT_CONTROL_HIGH_REG, (init_cntr_prm->msys_init << 7), (1 << 7))); + timing = tm->interface_params[if_id].timing; + if (mode2_t != 0xff) { t2t = mode2_t; + } else if (timing != HWS_TIM_DEFAULT) { + /* Board topology map is forcing timing */ + t2t = (timing == HWS_TIM_2T) ? 1 : 0; } else { /* calculate number of CS (per interface) */ CHECK_STATUS(calc_cs_num diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h index f8894e828a..229c3a127a 100644 --- a/drivers/ddr/marvell/a38x/ddr_topology_def.h +++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h @@ -37,6 +37,12 @@ enum hws_mem_size { MEM_SIZE_LAST }; +enum hws_timing { + HWS_TIM_DEFAULT, + HWS_TIM_1T, + HWS_TIM_2T +}; + struct bus_params { /* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */ u8 cs_bitmask; @@ -84,6 +90,9 @@ struct if_params { /* operation temperature */ enum hws_temperature interface_temp; + + /* 2T vs 1T mode (by default computed from number of CSs) */ + enum hws_timing timing; }; struct hws_topology_map { |