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-rw-r--r--drivers/block/blkcache.c2
-rw-r--r--drivers/clk/mediatek/clk-mt7623.c15
-rw-r--r--drivers/clk/mediatek/clk-mt7629.c15
-rw-r--r--drivers/clk/mediatek/clk-mtk.h2
-rw-r--r--drivers/i2c/Kconfig7
-rw-r--r--drivers/i2c/Makefile1
-rw-r--r--drivers/i2c/i2c-cdns.c9
-rw-r--r--drivers/i2c/muxes/i2c-mux-uclass.c4
-rw-r--r--drivers/i2c/muxes/pca954x.c2
-rw-r--r--drivers/i2c/xilinx_xiic.c340
-rw-r--r--drivers/misc/fs_loader.c108
-rw-r--r--drivers/mmc/hi6220_dw_mmc.c100
-rw-r--r--drivers/mmc/mmc.c39
-rw-r--r--drivers/net/Kconfig10
-rw-r--r--drivers/net/Makefile1
-rw-r--r--drivers/net/mtk_eth.c1175
-rw-r--r--drivers/net/mtk_eth.h286
-rw-r--r--drivers/reset/Kconfig7
-rw-r--r--drivers/reset/Makefile1
-rw-r--r--drivers/reset/reset-mediatek.c102
-rw-r--r--drivers/serial/Kconfig13
-rw-r--r--drivers/serial/ns16550.c20
22 files changed, 2151 insertions, 108 deletions
diff --git a/drivers/block/blkcache.c b/drivers/block/blkcache.c
index 294511fcdb..1fa64989d3 100644
--- a/drivers/block/blkcache.c
+++ b/drivers/block/blkcache.c
@@ -24,7 +24,7 @@ struct block_cache_node {
static LIST_HEAD(block_cache);
static struct block_cache_stats _stats = {
- .max_blocks_per_entry = 2,
+ .max_blocks_per_entry = 8,
.max_entries = 32
};
diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c
index c6b09d8e18..87ad4f79ce 100644
--- a/drivers/clk/mediatek/clk-mt7623.c
+++ b/drivers/clk/mediatek/clk-mt7623.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <dm.h>
+#include <asm/arch-mediatek/reset.h>
#include <asm/io.h>
#include <dt-bindings/clock/mt7623-clk.h>
@@ -782,6 +783,19 @@ static int mt7623_ethsys_probe(struct udevice *dev)
return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, eth_cgs);
}
+static int mt7623_ethsys_bind(struct udevice *dev)
+{
+ int ret = 0;
+
+#if CONFIG_IS_ENABLED(RESET_MEDIATEK)
+ ret = mediatek_reset_bind(dev, ETHSYS_RST_CTRL_OFS, 1);
+ if (ret)
+ debug("Warning: failed to bind ethsys reset controller\n");
+#endif
+
+ return ret;
+}
+
static const struct udevice_id mt7623_apmixed_compat[] = {
{ .compatible = "mediatek,mt7623-apmixedsys" },
{ }
@@ -865,6 +879,7 @@ U_BOOT_DRIVER(mtk_clk_ethsys) = {
.id = UCLASS_CLK,
.of_match = mt7623_ethsys_compat,
.probe = mt7623_ethsys_probe,
+ .bind = mt7623_ethsys_bind,
.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c
index 2601b6cf30..6a9f60139c 100644
--- a/drivers/clk/mediatek/clk-mt7629.c
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <dm.h>
+#include <asm/arch-mediatek/reset.h>
#include <asm/io.h>
#include <dt-bindings/clock/mt7629-clk.h>
@@ -602,6 +603,19 @@ static int mt7629_ethsys_probe(struct udevice *dev)
return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, eth_cgs);
}
+static int mt7629_ethsys_bind(struct udevice *dev)
+{
+ int ret = 0;
+
+#if CONFIG_IS_ENABLED(RESET_MEDIATEK)
+ ret = mediatek_reset_bind(dev, ETHSYS_RST_CTRL_OFS, 1);
+ if (ret)
+ debug("Warning: failed to bind ethsys reset controller\n");
+#endif
+
+ return ret;
+}
+
static int mt7629_sgmiisys_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, sgmii_cgs);
@@ -695,6 +709,7 @@ U_BOOT_DRIVER(mtk_clk_ethsys) = {
.id = UCLASS_CLK,
.of_match = mt7629_ethsys_compat,
.probe = mt7629_ethsys_probe,
+ .bind = mt7629_ethsys_bind,
.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
.ops = &mtk_clk_gate_ops,
};
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 74152ed9c6..7847388b2a 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -23,6 +23,8 @@
#define CLK_PARENT_TOPCKGEN BIT(5)
#define CLK_PARENT_MASK GENMASK(5, 4)
+#define ETHSYS_RST_CTRL_OFS 0x34
+
/* struct mtk_pll_data - hardware-specific PLLs data */
struct mtk_pll_data {
const int id;
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 1ef22e6bcd..7579eb8755 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -450,9 +450,16 @@ config SYS_I2C_BUS_MAX
help
Define the maximum number of available I2C buses.
+config SYS_I2C_XILINX_XIIC
+ bool "Xilinx AXI I2C driver"
+ depends on DM_I2C
+ help
+ Support for Xilinx AXI I2C controller.
+
config SYS_I2C_ZYNQ
bool "Xilinx I2C driver"
depends on ARCH_ZYNQMP || ARCH_ZYNQ
+ depends on !DM_I2C
help
Support for Xilinx I2C controller.
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index d3637bcd8d..ec2d1964c3 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o
obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o
obj-$(CONFIG_SYS_I2C_VERSATILE) += i2c-versatile.o
+obj-$(CONFIG_SYS_I2C_XILINX_XIIC) += xilinx_xiic.o
obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o
obj-$(CONFIG_TEGRA186_BPMP_I2C) += tegra186_bpmp_i2c.o
diff --git a/drivers/i2c/i2c-cdns.c b/drivers/i2c/i2c-cdns.c
index 30be173343..f2c4b2073c 100644
--- a/drivers/i2c/i2c-cdns.c
+++ b/drivers/i2c/i2c-cdns.c
@@ -17,6 +17,7 @@
#include <fdtdec.h>
#include <mapmem.h>
#include <wait_bit.h>
+#include <clk.h>
/* i2c register set */
struct cdns_i2c_regs {
@@ -415,6 +416,8 @@ static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
struct cdns_i2c_platform_data *pdata =
(struct cdns_i2c_platform_data *)dev_get_driver_data(dev);
+ struct clk clk;
+ int ret;
i2c_bus->regs = (struct cdns_i2c_regs *)devfdt_get_addr(dev);
if (!i2c_bus->regs)
@@ -423,7 +426,11 @@ static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
if (pdata)
i2c_bus->quirks = pdata->quirks;
- i2c_bus->input_freq = 100000000; /* TODO hardcode input freq for now */
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret)
+ return ret;
+
+ i2c_bus->input_freq = clk_get_rate(&clk);
return 0;
}
diff --git a/drivers/i2c/muxes/i2c-mux-uclass.c b/drivers/i2c/muxes/i2c-mux-uclass.c
index 10336919ad..a680ee1762 100644
--- a/drivers/i2c/muxes/i2c-mux-uclass.c
+++ b/drivers/i2c/muxes/i2c-mux-uclass.c
@@ -11,8 +11,6 @@
#include <dm/lists.h>
#include <dm/root.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/**
* struct i2c_mux: Information the uclass stores about an I2C mux
*
@@ -39,7 +37,7 @@ static int i2c_mux_child_post_bind(struct udevice *dev)
struct i2c_mux_bus *plat = dev_get_parent_platdata(dev);
int channel;
- channel = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1);
+ channel = dev_read_u32_default(dev, "reg", -1);
if (channel < 0)
return -EINVAL;
plat->channel = channel;
diff --git a/drivers/i2c/muxes/pca954x.c b/drivers/i2c/muxes/pca954x.c
index ab8b4000af..bd4e9abe5f 100644
--- a/drivers/i2c/muxes/pca954x.c
+++ b/drivers/i2c/muxes/pca954x.c
@@ -101,7 +101,7 @@ static int pca954x_ofdata_to_platdata(struct udevice *dev)
struct pca954x_priv *priv = dev_get_priv(dev);
const struct chip_desc *chip = &chips[dev_get_driver_data(dev)];
- priv->addr = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", 0);
+ priv->addr = dev_read_u32_default(dev, "reg", 0);
if (!priv->addr) {
debug("MUX not found\n");
return -ENODEV;
diff --git a/drivers/i2c/xilinx_xiic.c b/drivers/i2c/xilinx_xiic.c
new file mode 100644
index 0000000000..83114ed510
--- /dev/null
+++ b/drivers/i2c/xilinx_xiic.c
@@ -0,0 +1,340 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Xilinx AXI I2C driver
+ *
+ * Copyright (C) 2018 Marek Vasut <marex@denx.de>
+ *
+ * Based on Linux 4.14.y i2c-xiic.c
+ * Copyright (c) 2002-2007 Xilinx Inc.
+ * Copyright (c) 2009-2010 Intel Corporation
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <i2c.h>
+#include <wait_bit.h>
+#include <asm/io.h>
+
+struct xilinx_xiic_priv {
+ void __iomem *base;
+ struct clk clk;
+};
+
+#define XIIC_MSB_OFFSET 0
+#define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)
+
+/*
+ * Register offsets in bytes from RegisterBase. Three is added to the
+ * base offset to access LSB (IBM style) of the word
+ */
+#define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */
+#define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */
+#define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */
+#define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */
+#define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */
+#define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */
+#define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */
+#define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */
+#define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
+#define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */
+
+/* Control Register masks */
+#define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */
+#define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
+#define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
+#define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */
+#define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
+#define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
+#define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
+
+/* Status Register masks */
+#define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
+#define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */
+#define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */
+#define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
+#define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
+#define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
+#define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */
+#define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */
+
+/* Interrupt Status Register masks Interrupt occurs when... */
+#define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */
+#define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */
+#define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */
+#define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */
+#define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */
+#define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */
+#define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */
+#define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */
+
+/* The following constants specify the depth of the FIFOs */
+#define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */
+#define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */
+
+/*
+ * Tx Fifo upper bit masks.
+ */
+#define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */
+#define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */
+
+/*
+ * The following constants define the register offsets for the Interrupt
+ * registers. There are some holes in the memory map for reserved addresses
+ * to allow other registers to be added and still match the memory map of the
+ * interrupt controller registers
+ */
+#define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */
+#define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */
+#define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */
+#define XIIC_RESETR_OFFSET 0x40 /* Reset Register */
+
+#define XIIC_RESET_MASK 0xAUL
+
+static u8 i2c_8bit_addr_from_flags(uint addr, u16 flags)
+{
+ return (addr << 1) | (flags & I2C_M_RD ? 1 : 0);
+}
+
+static void xiic_irq_clr(struct xilinx_xiic_priv *priv, u32 mask)
+{
+ u32 isr = readl(priv->base + XIIC_IISR_OFFSET);
+
+ writel(isr & mask, priv->base + XIIC_IISR_OFFSET);
+}
+
+static int xiic_read_rx(struct xilinx_xiic_priv *priv,
+ struct i2c_msg *msg, int nmsgs)
+{
+ u8 bytes_in_fifo;
+ u32 pos = 0;
+ int i, ret;
+
+ while (pos < msg->len) {
+ ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET,
+ XIIC_SR_RX_FIFO_EMPTY_MASK, false,
+ 1000, true);
+ if (ret)
+ return ret;
+
+ bytes_in_fifo = readb(priv->base + XIIC_RFO_REG_OFFSET) + 1;
+
+ if (bytes_in_fifo > msg->len)
+ bytes_in_fifo = msg->len;
+
+ for (i = 0; i < bytes_in_fifo; i++) {
+ msg->buf[pos++] = readb(priv->base +
+ XIIC_DRR_REG_OFFSET);
+ }
+ }
+
+ return 0;
+}
+
+static int xiic_tx_fifo_space(struct xilinx_xiic_priv *priv)
+{
+ /* return the actual space left in the FIFO */
+ return IIC_TX_FIFO_DEPTH - readb(priv->base + XIIC_TFO_REG_OFFSET) - 1;
+}
+
+static void xiic_fill_tx_fifo(struct xilinx_xiic_priv *priv,
+ struct i2c_msg *msg, int nmsgs)
+{
+ u8 fifo_space = xiic_tx_fifo_space(priv);
+ int len = msg->len;
+ u32 pos = 0;
+
+ len = (len > fifo_space) ? fifo_space : len;
+
+ while (len--) {
+ u16 data = msg->buf[pos++];
+
+ if (pos == len && nmsgs == 1) {
+ /* last message in transfer -> STOP */
+ data |= XIIC_TX_DYN_STOP_MASK;
+ }
+ writew(data, priv->base + XIIC_DTR_REG_OFFSET);
+ }
+}
+
+static void xilinx_xiic_set_addr(struct udevice *dev, u8 addr,
+ u16 flags, u32 len, u32 nmsgs)
+{
+ struct xilinx_xiic_priv *priv = dev_get_priv(dev);
+
+ xiic_irq_clr(priv, XIIC_INTR_TX_ERROR_MASK);
+
+ if (!(flags & I2C_M_NOSTART)) {
+ /* write the address */
+ u16 data = i2c_8bit_addr_from_flags(addr, flags) |
+ XIIC_TX_DYN_START_MASK;
+ if (nmsgs == 1 && len == 0)
+ /* no data and last message -> add STOP */
+ data |= XIIC_TX_DYN_STOP_MASK;
+
+ writew(data, priv->base + XIIC_DTR_REG_OFFSET);
+ }
+}
+
+static int xilinx_xiic_read_common(struct udevice *dev, struct i2c_msg *msg,
+ u32 nmsgs)
+{
+ struct xilinx_xiic_priv *priv = dev_get_priv(dev);
+ u8 rx_watermark;
+
+ /* Clear and enable Rx full interrupt. */
+ xiic_irq_clr(priv, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK);
+
+ /* we want to get all but last byte, because the TX_ERROR IRQ is used
+ * to inidicate error ACK on the address, and negative ack on the last
+ * received byte, so to not mix them receive all but last.
+ * In the case where there is only one byte to receive
+ * we can check if ERROR and RX full is set at the same time
+ */
+ rx_watermark = msg->len;
+ if (rx_watermark > IIC_RX_FIFO_DEPTH)
+ rx_watermark = IIC_RX_FIFO_DEPTH;
+
+ writeb(rx_watermark - 1, priv->base + XIIC_RFD_REG_OFFSET);
+
+ xilinx_xiic_set_addr(dev, msg->addr, msg->flags, msg->len, nmsgs);
+
+ xiic_irq_clr(priv, XIIC_INTR_BNB_MASK);
+
+ writew((msg->len & 0xff) | ((nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0),
+ priv->base + XIIC_DTR_REG_OFFSET);
+
+ if (nmsgs == 1)
+ /* very last, enable bus not busy as well */
+ xiic_irq_clr(priv, XIIC_INTR_BNB_MASK);
+
+ return xiic_read_rx(priv, msg, nmsgs);
+}
+
+static int xilinx_xiic_write_common(struct udevice *dev, struct i2c_msg *msg,
+ int nmsgs)
+{
+ struct xilinx_xiic_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ xilinx_xiic_set_addr(dev, msg->addr, msg->flags, msg->len, nmsgs);
+ xiic_fill_tx_fifo(priv, msg, nmsgs);
+
+ ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET,
+ XIIC_SR_TX_FIFO_EMPTY_MASK, false, 1000, true);
+ if (ret)
+ return ret;
+
+ /* Clear any pending Tx empty, Tx Error and then enable them. */
+ xiic_irq_clr(priv, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK |
+ XIIC_INTR_BNB_MASK);
+
+ return 0;
+}
+
+static void xiic_clear_rx_fifo(struct xilinx_xiic_priv *priv)
+{
+ u8 sr;
+
+ for (sr = readb(priv->base + XIIC_SR_REG_OFFSET);
+ !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
+ sr = readb(priv->base + XIIC_SR_REG_OFFSET))
+ readb(priv->base + XIIC_DRR_REG_OFFSET);
+}
+
+static void xiic_reinit(struct xilinx_xiic_priv *priv)
+{
+ writel(XIIC_RESET_MASK, priv->base + XIIC_RESETR_OFFSET);
+
+ /* Set receive Fifo depth to maximum (zero based). */
+ writeb(IIC_RX_FIFO_DEPTH - 1, priv->base + XIIC_RFD_REG_OFFSET);
+
+ /* Reset Tx Fifo. */
+ writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET);
+
+ /* Enable IIC Device, remove Tx Fifo reset & disable general call. */
+ writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET);
+
+ /* make sure RX fifo is empty */
+ xiic_clear_rx_fifo(priv);
+
+ /* Disable interrupts */
+ writel(0, priv->base + XIIC_DGIER_OFFSET);
+
+ xiic_irq_clr(priv, XIIC_INTR_ARB_LOST_MASK);
+}
+
+static int xilinx_xiic_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
+{
+ int ret = 0;
+
+ for (; nmsgs > 0; nmsgs--, msg++) {
+ if (msg->flags & I2C_M_RD)
+ ret = xilinx_xiic_read_common(dev, msg, nmsgs);
+ else
+ ret = xilinx_xiic_write_common(dev, msg, nmsgs);
+
+ if (ret)
+ return -EREMOTEIO;
+ }
+
+ return ret;
+}
+
+static int xilinx_xiic_probe_chip(struct udevice *dev, uint addr, uint flags)
+{
+ struct xilinx_xiic_priv *priv = dev_get_priv(dev);
+ u32 reg;
+ int ret;
+
+ xiic_reinit(priv);
+
+ xilinx_xiic_set_addr(dev, addr, 0, 0, 1);
+ ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET,
+ XIIC_SR_BUS_BUSY_MASK, false, 1000, true);
+ if (ret)
+ return ret;
+
+ reg = readl(priv->base + XIIC_IISR_OFFSET);
+ if (reg & XIIC_INTR_TX_ERROR_MASK)
+ return -ENODEV;
+
+ return 0;
+}
+
+static int xilinx_xiic_set_speed(struct udevice *dev, uint speed)
+{
+ return 0;
+}
+
+static int xilinx_xiic_probe(struct udevice *dev)
+{
+ struct xilinx_xiic_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr_ptr(dev);
+
+ writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET);
+ xiic_reinit(priv);
+
+ return 0;
+}
+
+static const struct dm_i2c_ops xilinx_xiic_ops = {
+ .xfer = xilinx_xiic_xfer,
+ .probe_chip = xilinx_xiic_probe_chip,
+ .set_bus_speed = xilinx_xiic_set_speed,
+};
+
+static const struct udevice_id xilinx_xiic_ids[] = {
+ { .compatible = "xlnx,xps-iic-2.00.a" },
+ { }
+};
+
+U_BOOT_DRIVER(xilinx_xiic) = {
+ .name = "xilinx_axi_i2c",
+ .id = UCLASS_I2C,
+ .of_match = xilinx_xiic_ids,
+ .probe = xilinx_xiic_probe,
+ .priv_auto_alloc_size = sizeof(struct xilinx_xiic_priv),
+ .ops = &xilinx_xiic_ops,
+};
diff --git a/drivers/misc/fs_loader.c b/drivers/misc/fs_loader.c
index baa5f8302a..57a14a3479 100644
--- a/drivers/misc/fs_loader.c
+++ b/drivers/misc/fs_loader.c
@@ -16,9 +16,22 @@
DECLARE_GLOBAL_DATA_PTR;
-struct firmware_priv {
- const char *name; /* Filename */
- u32 offset; /* Offset of reading a file */
+/**
+ * struct firmware - A place for storing firmware and its attribute data.
+ *
+ * This holds information about a firmware and its content.
+ *
+ * @size: Size of a file
+ * @data: Buffer for file
+ * @priv: Firmware loader private fields
+ * @name: Filename
+ * @offset: Offset of reading a file
+ */
+struct firmware {
+ size_t size;
+ const u8 *data;
+ const char *name;
+ u32 offset;
};
#ifdef CONFIG_CMD_UBIFS
@@ -88,74 +101,42 @@ static int select_fs_dev(struct device_platdata *plat)
/**
* _request_firmware_prepare - Prepare firmware struct.
*
+ * @dev: An instance of a driver.
* @name: Name of firmware file.
* @dbuf: Address of buffer to load firmware into.
* @size: Size of buffer.
* @offset: Offset of a file for start reading into buffer.
- * @firmwarep: Pointer to pointer to firmware image.
*
* Return: Negative value if fail, 0 for successful.
*/
-static int _request_firmware_prepare(const char *name, void *dbuf,
- size_t size, u32 offset,
- struct firmware **firmwarep)
+static int _request_firmware_prepare(struct udevice *dev,
+ const char *name, void *dbuf,
+ size_t size, u32 offset)
{
if (!name || name[0] == '\0')
return -EINVAL;
- /* No memory allocation is required if *firmwarep is allocated */
- if (!(*firmwarep)) {
- (*firmwarep) = calloc(1, sizeof(struct firmware));
- if (!(*firmwarep))
- return -ENOMEM;
+ struct firmware *firmwarep = dev_get_priv(dev);
- (*firmwarep)->priv = calloc(1, sizeof(struct firmware_priv));
- if (!(*firmwarep)->priv) {
- free(*firmwarep);
- return -ENOMEM;
- }
- } else if (!(*firmwarep)->priv) {
- (*firmwarep)->priv = calloc(1, sizeof(struct firmware_priv));
- if (!(*firmwarep)->priv) {
- free(*firmwarep);
- return -ENOMEM;
- }
- }
+ if (!firmwarep)
+ return -ENOMEM;
- ((struct firmware_priv *)((*firmwarep)->priv))->name = name;
- ((struct firmware_priv *)((*firmwarep)->priv))->offset = offset;
- (*firmwarep)->data = dbuf;
- (*firmwarep)->size = size;
+ firmwarep->name = name;
+ firmwarep->offset = offset;
+ firmwarep->data = dbuf;
+ firmwarep->size = size;
return 0;
}
/**
- * release_firmware - Release the resource associated with a firmware image
- * @firmware: Firmware resource to release
- */
-void release_firmware(struct firmware *firmware)
-{
- if (firmware) {
- if (firmware->priv) {
- free(firmware->priv);
- firmware->priv = NULL;
- }
- free(firmware);
- }
-}
-
-/**
* fw_get_filesystem_firmware - load firmware into an allocated buffer.
- * @plat: Platform data such as storage and partition firmware loading from.
- * @firmware: pointer to firmware image.
+ * @dev: An instance of a driver.
*
* Return: Size of total read, negative value when error.
*/
-static int fw_get_filesystem_firmware(struct device_platdata *plat,
- struct firmware *firmware)
+static int fw_get_filesystem_firmware(struct udevice *dev)
{
- struct firmware_priv *fw_priv = NULL;
loff_t actread;
char *storage_interface, *dev_part, *ubi_mtdpart, *ubi_volume;
int ret;
@@ -178,20 +159,23 @@ static int fw_get_filesystem_firmware(struct device_platdata *plat,
else
ret = -ENODEV;
} else {
- ret = select_fs_dev(plat);
+ ret = select_fs_dev(dev->platdata);
}
if (ret)
goto out;
- fw_priv = firmware->priv;
+ struct firmware *firmwarep = dev_get_priv(dev);
+
+ if (!firmwarep)
+ return -ENOMEM;
- ret = fs_read(fw_priv->name, (ulong)map_to_sysmem(firmware->data),
- fw_priv->offset, firmware->size, &actread);
+ ret = fs_read(firmwarep->name, (ulong)map_to_sysmem(firmwarep->data),
+ firmwarep->offset, firmwarep->size, &actread);
if (ret) {
debug("Error: %d Failed to read %s from flash %lld != %zu.\n",
- ret, fw_priv->name, actread, firmware->size);
+ ret, firmwarep->name, actread, firmwarep->size);
} else {
ret = actread;
}
@@ -205,33 +189,30 @@ out:
/**
* request_firmware_into_buf - Load firmware into a previously allocated buffer.
- * @plat: Platform data such as storage and partition firmware loading from.
+ * @dev: An instance of a driver.
* @name: Name of firmware file.
* @buf: Address of buffer to load firmware into.
* @size: Size of buffer.
* @offset: Offset of a file for start reading into buffer.
- * @firmwarep: Pointer to firmware image.
*
- * The firmware is loaded directly into the buffer pointed to by @buf and
- * the @firmwarep data member is pointed at @buf.
+ * The firmware is loaded directly into the buffer pointed to by @buf.
*
* Return: Size of total read, negative value when error.
*/
-int request_firmware_into_buf(struct device_platdata *plat,
+int request_firmware_into_buf(struct udevice *dev,
const char *name,
- void *buf, size_t size, u32 offset,
- struct firmware **firmwarep)
+ void *buf, size_t size, u32 offset)
{
int ret;
- if (!plat)
+ if (!dev)
return -EINVAL;
- ret = _request_firmware_prepare(name, buf, size, offset, firmwarep);
+ ret = _request_firmware_prepare(dev, name, buf, size, offset);
if (ret < 0) /* error */
return ret;
- ret = fw_get_filesystem_firmware(plat, *firmwarep);
+ ret = fw_get_filesystem_firmware(dev);
return ret;
}
@@ -286,6 +267,7 @@ U_BOOT_DRIVER(fs_loader) = {
.probe = fs_loader_probe,
.ofdata_to_platdata = fs_loader_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct device_platdata),
+ .priv_auto_alloc_size = sizeof(struct firmware),
};
UCLASS_DRIVER(fs_loader) = {
diff --git a/drivers/mmc/hi6220_dw_mmc.c b/drivers/mmc/hi6220_dw_mmc.c
index ce395d53c9..cc58aff38c 100644
--- a/drivers/mmc/hi6220_dw_mmc.c
+++ b/drivers/mmc/hi6220_dw_mmc.c
@@ -5,51 +5,89 @@
*/
#include <common.h>
+#include <dm.h>
#include <dwmmc.h>
+#include <errno.h>
+#include <fdtdec.h>
#include <malloc.h>
-#include <linux/errno.h>
-#define DWMMC_MAX_CH_NUM 4
+DECLARE_GLOBAL_DATA_PTR;
-#define DWMMC_MAX_FREQ 50000000
-#define DWMMC_MIN_FREQ 400000
+struct hi6220_dwmmc_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
-/* Source clock is configured to 100MHz by ATF bl1*/
-#define MMC0_DEFAULT_FREQ 100000000
+struct hi6220_dwmmc_priv_data {
+ struct dwmci_host host;
+};
-static int hi6220_dwmci_core_init(struct dwmci_host *host, int index)
+static int hi6220_dwmmc_ofdata_to_platdata(struct udevice *dev)
{
- host->name = "Hisilicon DWMMC";
+ struct hi6220_dwmmc_priv_data *priv = dev_get_priv(dev);
+ struct dwmci_host *host = &priv->host;
- host->dev_index = index;
+ host->name = dev->name;
+ host->ioaddr = (void *)devfdt_get_addr(dev);
+ host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "bus-width", 4);
+
+ /* use non-removable property for differentiating SD card and eMMC */
+ if (dev_read_bool(dev, "non-removable"))
+ host->dev_index = 0;
+ else
+ host->dev_index = 1;
+
+ host->priv = priv;
- /* Add the mmc channel to be registered with mmc core */
- if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
- printf("DWMMC%d registration failed\n", index);
- return -1;
- }
return 0;
}
-/*
- * This function adds the mmc channel to be registered with mmc core.
- * index - mmc channel number.
- * regbase - register base address of mmc channel specified in 'index'.
- * bus_width - operating bus width of mmc channel specified in 'index'.
- */
-int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width)
+static int hi6220_dwmmc_probe(struct udevice *dev)
{
- struct dwmci_host *host = NULL;
+ struct hi6220_dwmmc_plat *plat = dev_get_platdata(dev);
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct hi6220_dwmmc_priv_data *priv = dev_get_priv(dev);
+ struct dwmci_host *host = &priv->host;
- host = calloc(1, sizeof(struct dwmci_host));
- if (!host) {
- pr_err("dwmci_host calloc failed!\n");
- return -ENOMEM;
- }
+ /* Use default bus speed due to absence of clk driver */
+ host->bus_hz = 50000000;
- host->ioaddr = (void *)(ulong)regbase;
- host->buswidth = bus_width;
- host->bus_hz = MMC0_DEFAULT_FREQ;
+ dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
+ host->mmc = &plat->mmc;
- return hi6220_dwmci_core_init(host, index);
+ host->mmc->priv = &priv->host;
+ upriv->mmc = host->mmc;
+ host->mmc->dev = dev;
+
+ return dwmci_probe(dev);
}
+
+static int hi6220_dwmmc_bind(struct udevice *dev)
+{
+ struct hi6220_dwmmc_plat *plat = dev_get_platdata(dev);
+ int ret;
+
+ ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static const struct udevice_id hi6220_dwmmc_ids[] = {
+ { .compatible = "hisilicon,hi6220-dw-mshc" },
+ { }
+};
+
+U_BOOT_DRIVER(hi6220_dwmmc_drv) = {
+ .name = "hi6220_dwmmc",
+ .id = UCLASS_MMC,
+ .of_match = hi6220_dwmmc_ids,
+ .ofdata_to_platdata = hi6220_dwmmc_ofdata_to_platdata,
+ .ops = &dm_dwmci_ops,
+ .bind = hi6220_dwmmc_bind,
+ .probe = hi6220_dwmmc_probe,
+ .priv_auto_alloc_size = sizeof(struct hi6220_dwmmc_priv_data),
+ .platdata_auto_alloc_size = sizeof(struct hi6220_dwmmc_plat),
+};
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index d858127132..84d157ff40 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -754,7 +754,8 @@ int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
}
#if !CONFIG_IS_ENABLED(MMC_TINY)
-static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode)
+static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode,
+ bool hsdowngrade)
{
int err;
int speed_bits;
@@ -788,6 +789,20 @@ static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode)
if (err)
return err;
+#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
+ CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
+ /*
+ * In case the eMMC is in HS200/HS400 mode and we are downgrading
+ * to HS mode, the card clock are still running much faster than
+ * the supported HS mode clock, so we can not reliably read out
+ * Extended CSD. Reconfigure the controller to run at HS mode.
+ */
+ if (hsdowngrade) {
+ mmc_select_mode(mmc, MMC_HS);
+ mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false);
+ }
+#endif
+
if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
/* Now check to see that it worked */
err = mmc_send_ext_csd(mmc, test_csd);
@@ -1849,7 +1864,7 @@ static int mmc_select_hs400(struct mmc *mmc)
int err;
/* Set timing to HS200 for tuning */
- err = mmc_set_card_speed(mmc, MMC_HS_200);
+ err = mmc_set_card_speed(mmc, MMC_HS_200, false);
if (err)
return err;
@@ -1865,7 +1880,7 @@ static int mmc_select_hs400(struct mmc *mmc)
}
/* Set back to HS */
- mmc_set_card_speed(mmc, MMC_HS);
+ mmc_set_card_speed(mmc, MMC_HS, false);
mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false);
err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
@@ -1873,7 +1888,7 @@ static int mmc_select_hs400(struct mmc *mmc)
if (err)
return err;
- err = mmc_set_card_speed(mmc, MMC_HS_400);
+ err = mmc_set_card_speed(mmc, MMC_HS_400, false);
if (err)
return err;
@@ -1920,7 +1935,19 @@ static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
return -ENOTSUPP;
}
- mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
+#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
+ CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
+ /*
+ * In case the eMMC is in HS200/HS400 mode, downgrade to HS mode
+ * before doing anything else, since a transition from either of
+ * the HS200/HS400 mode directly to legacy mode is not supported.
+ */
+ if (mmc->selected_mode == MMC_HS_200 ||
+ mmc->selected_mode == MMC_HS_400)
+ mmc_set_card_speed(mmc, MMC_HS, true);
+ else
+#endif
+ mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
for_each_mmc_mode_by_pref(card_caps, mwt) {
for_each_supported_width(card_caps & mwt->widths,
@@ -1952,7 +1979,7 @@ static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
}
} else {
/* configure the bus speed (card) */
- err = mmc_set_card_speed(mmc, mwt->mode);
+ err = mmc_set_card_speed(mmc, mwt->mode, false);
if (err)
goto error;
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 7044c6adf3..ff55e03d3f 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -513,4 +513,14 @@ config TSEC_ENET
This driver implements support for the (Enhanced) Three-Speed
Ethernet Controller found on Freescale SoCs.
+config MEDIATEK_ETH
+ bool "MediaTek Ethernet GMAC Driver"
+ depends on DM_ETH
+ select PHYLIB
+ select DM_GPIO
+ select DM_RESET
+ help
+ This Driver support MediaTek Ethernet GMAC
+ Say Y to enable support for the MediaTek Ethernet GMAC.
+
endif # NETDEVICES
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 0dbfa03306..ee7f3e71a8 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -74,3 +74,4 @@ obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
obj-$(CONFIG_FSL_PFE) += pfe_eth/
obj-$(CONFIG_SNI_AVE) += sni_ave.o
obj-y += ti/
+obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o
diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c
new file mode 100644
index 0000000000..cc09404830
--- /dev/null
+++ b/drivers/net/mtk_eth.c
@@ -0,0 +1,1175 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ * Author: Mark Lee <mark-mc.lee@mediatek.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <regmap.h>
+#include <reset.h>
+#include <syscon.h>
+#include <wait_bit.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <linux/err.h>
+#include <linux/ioport.h>
+#include <linux/mdio.h>
+#include <linux/mii.h>
+
+#include "mtk_eth.h"
+
+#define NUM_TX_DESC 24
+#define NUM_RX_DESC 24
+#define TX_TOTAL_BUF_SIZE (NUM_TX_DESC * PKTSIZE_ALIGN)
+#define RX_TOTAL_BUF_SIZE (NUM_RX_DESC * PKTSIZE_ALIGN)
+#define TOTAL_PKT_BUF_SIZE (TX_TOTAL_BUF_SIZE + RX_TOTAL_BUF_SIZE)
+
+#define MT7530_NUM_PHYS 5
+#define MT7530_DFL_SMI_ADDR 31
+
+#define MT7530_PHY_ADDR(base, addr) \
+ (((base) + (addr)) & 0x1f)
+
+#define GDMA_FWD_TO_CPU \
+ (0x20000000 | \
+ GDM_ICS_EN | \
+ GDM_TCS_EN | \
+ GDM_UCS_EN | \
+ STRP_CRC | \
+ (DP_PDMA << MYMAC_DP_S) | \
+ (DP_PDMA << BC_DP_S) | \
+ (DP_PDMA << MC_DP_S) | \
+ (DP_PDMA << UN_DP_S))
+
+#define GDMA_FWD_DISCARD \
+ (0x20000000 | \
+ GDM_ICS_EN | \
+ GDM_TCS_EN | \
+ GDM_UCS_EN | \
+ STRP_CRC | \
+ (DP_DISCARD << MYMAC_DP_S) | \
+ (DP_DISCARD << BC_DP_S) | \
+ (DP_DISCARD << MC_DP_S) | \
+ (DP_DISCARD << UN_DP_S))
+
+struct pdma_rxd_info1 {
+ u32 PDP0;
+};
+
+struct pdma_rxd_info2 {
+ u32 PLEN1 : 14;
+ u32 LS1 : 1;
+ u32 UN_USED : 1;
+ u32 PLEN0 : 14;
+ u32 LS0 : 1;
+ u32 DDONE : 1;
+};
+
+struct pdma_rxd_info3 {
+ u32 PDP1;
+};
+
+struct pdma_rxd_info4 {
+ u32 FOE_ENTRY : 14;
+ u32 CRSN : 5;
+ u32 SP : 3;
+ u32 L4F : 1;
+ u32 L4VLD : 1;
+ u32 TACK : 1;
+ u32 IP4F : 1;
+ u32 IP4 : 1;
+ u32 IP6 : 1;
+ u32 UN_USED : 4;
+};
+
+struct pdma_rxdesc {
+ struct pdma_rxd_info1 rxd_info1;
+ struct pdma_rxd_info2 rxd_info2;
+ struct pdma_rxd_info3 rxd_info3;
+ struct pdma_rxd_info4 rxd_info4;
+};
+
+struct pdma_txd_info1 {
+ u32 SDP0;
+};
+
+struct pdma_txd_info2 {
+ u32 SDL1 : 14;
+ u32 LS1 : 1;
+ u32 BURST : 1;
+ u32 SDL0 : 14;
+ u32 LS0 : 1;
+ u32 DDONE : 1;
+};
+
+struct pdma_txd_info3 {
+ u32 SDP1;
+};
+
+struct pdma_txd_info4 {
+ u32 VLAN_TAG : 16;
+ u32 INS : 1;
+ u32 RESV : 2;
+ u32 UDF : 6;
+ u32 FPORT : 3;
+ u32 TSO : 1;
+ u32 TUI_CO : 3;
+};
+
+struct pdma_txdesc {
+ struct pdma_txd_info1 txd_info1;
+ struct pdma_txd_info2 txd_info2;
+ struct pdma_txd_info3 txd_info3;
+ struct pdma_txd_info4 txd_info4;
+};
+
+enum mtk_switch {
+ SW_NONE,
+ SW_MT7530
+};
+
+enum mtk_soc {
+ SOC_MT7623,
+ SOC_MT7629
+};
+
+struct mtk_eth_priv {
+ char pkt_pool[TOTAL_PKT_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
+
+ struct pdma_txdesc *tx_ring_noc;
+ struct pdma_rxdesc *rx_ring_noc;
+
+ int rx_dma_owner_idx0;
+ int tx_cpu_owner_idx0;
+
+ void __iomem *fe_base;
+ void __iomem *gmac_base;
+ void __iomem *ethsys_base;
+
+ struct mii_dev *mdio_bus;
+ int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg);
+ int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val);
+ int (*mmd_read)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg);
+ int (*mmd_write)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg,
+ u16 val);
+
+ enum mtk_soc soc;
+ int gmac_id;
+ int force_mode;
+ int speed;
+ int duplex;
+
+ struct phy_device *phydev;
+ int phy_interface;
+ int phy_addr;
+
+ enum mtk_switch sw;
+ int (*switch_init)(struct mtk_eth_priv *priv);
+ u32 mt7530_smi_addr;
+ u32 mt7530_phy_base;
+
+ struct gpio_desc rst_gpio;
+ int mcm;
+
+ struct reset_ctl rst_fe;
+ struct reset_ctl rst_mcm;
+};
+
+static void mtk_pdma_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
+{
+ writel(val, priv->fe_base + PDMA_BASE + reg);
+}
+
+static void mtk_pdma_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
+ u32 set)
+{
+ clrsetbits_le32(priv->fe_base + PDMA_BASE + reg, clr, set);
+}
+
+static void mtk_gdma_write(struct mtk_eth_priv *priv, int no, u32 reg,
+ u32 val)
+{
+ u32 gdma_base;
+
+ if (no == 1)
+ gdma_base = GDMA2_BASE;
+ else
+ gdma_base = GDMA1_BASE;
+
+ writel(val, priv->fe_base + gdma_base + reg);
+}
+
+static u32 mtk_gmac_read(struct mtk_eth_priv *priv, u32 reg)
+{
+ return readl(priv->gmac_base + reg);
+}
+
+static void mtk_gmac_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
+{
+ writel(val, priv->gmac_base + reg);
+}
+
+static void mtk_gmac_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set)
+{
+ clrsetbits_le32(priv->gmac_base + reg, clr, set);
+}
+
+static void mtk_ethsys_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
+ u32 set)
+{
+ clrsetbits_le32(priv->ethsys_base + reg, clr, set);
+}
+
+/* Direct MDIO clause 22/45 access via SoC */
+static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data,
+ u32 cmd, u32 st)
+{
+ int ret;
+ u32 val;
+
+ val = (st << MDIO_ST_S) |
+ ((cmd << MDIO_CMD_S) & MDIO_CMD_M) |
+ (((u32)phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) |
+ (((u32)reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M);
+
+ if (cmd == MDIO_CMD_WRITE)
+ val |= data & MDIO_RW_DATA_M;
+
+ mtk_gmac_write(priv, GMAC_PIAC_REG, val | PHY_ACS_ST);
+
+ ret = wait_for_bit_le32(priv->gmac_base + GMAC_PIAC_REG,
+ PHY_ACS_ST, 0, 5000, 0);
+ if (ret) {
+ pr_warn("MDIO access timeout\n");
+ return ret;
+ }
+
+ if (cmd == MDIO_CMD_READ) {
+ val = mtk_gmac_read(priv, GMAC_PIAC_REG);
+ return val & MDIO_RW_DATA_M;
+ }
+
+ return 0;
+}
+
+/* Direct MDIO clause 22 read via SoC */
+static int mtk_mii_read(struct mtk_eth_priv *priv, u8 phy, u8 reg)
+{
+ return mtk_mii_rw(priv, phy, reg, 0, MDIO_CMD_READ, MDIO_ST_C22);
+}
+
+/* Direct MDIO clause 22 write via SoC */
+static int mtk_mii_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data)
+{
+ return mtk_mii_rw(priv, phy, reg, data, MDIO_CMD_WRITE, MDIO_ST_C22);
+}
+
+/* Direct MDIO clause 45 read via SoC */
+static int mtk_mmd_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg)
+{
+ int ret;
+
+ ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45);
+ if (ret)
+ return ret;
+
+ return mtk_mii_rw(priv, addr, devad, 0, MDIO_CMD_READ_C45,
+ MDIO_ST_C45);
+}
+
+/* Direct MDIO clause 45 write via SoC */
+static int mtk_mmd_write(struct mtk_eth_priv *priv, u8 addr, u8 devad,
+ u16 reg, u16 val)
+{
+ int ret;
+
+ ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45);
+ if (ret)
+ return ret;
+
+ return mtk_mii_rw(priv, addr, devad, val, MDIO_CMD_WRITE,
+ MDIO_ST_C45);
+}
+
+/* Indirect MDIO clause 45 read via MII registers */
+static int mtk_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad,
+ u16 reg)
+{
+ int ret;
+
+ ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
+ (MMD_ADDR << MMD_CMD_S) |
+ ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
+ if (ret)
+ return ret;
+
+ ret = priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg);
+ if (ret)
+ return ret;
+
+ ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
+ (MMD_DATA << MMD_CMD_S) |
+ ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
+ if (ret)
+ return ret;
+
+ return priv->mii_read(priv, addr, MII_MMD_ADDR_DATA_REG);
+}
+
+/* Indirect MDIO clause 45 write via MII registers */
+static int mtk_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad,
+ u16 reg, u16 val)
+{
+ int ret;
+
+ ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
+ (MMD_ADDR << MMD_CMD_S) |
+ ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
+ if (ret)
+ return ret;
+
+ ret = priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg);
+ if (ret)
+ return ret;
+
+ ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG,
+ (MMD_DATA << MMD_CMD_S) |
+ ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));
+ if (ret)
+ return ret;
+
+ return priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, val);
+}
+
+static int mtk_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+ struct mtk_eth_priv *priv = bus->priv;
+
+ if (devad < 0)
+ return priv->mii_read(priv, addr, reg);
+ else
+ return priv->mmd_read(priv, addr, devad, reg);
+}
+
+static int mtk_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
+ u16 val)
+{
+ struct mtk_eth_priv *priv = bus->priv;
+
+ if (devad < 0)
+ return priv->mii_write(priv, addr, reg, val);
+ else
+ return priv->mmd_write(priv, addr, devad, reg, val);
+}
+
+static int mtk_mdio_register(struct udevice *dev)
+{
+ struct mtk_eth_priv *priv = dev_get_priv(dev);
+ struct mii_dev *mdio_bus = mdio_alloc();
+ int ret;
+
+ if (!mdio_bus)
+ return -ENOMEM;
+
+ /* Assign MDIO access APIs according to the switch/phy */
+ switch (priv->sw) {
+ case SW_MT7530:
+ priv->mii_read = mtk_mii_read;
+ priv->mii_write = mtk_mii_write;
+ priv->mmd_read = mtk_mmd_ind_read;
+ priv->mmd_write = mtk_mmd_ind_write;
+ break;
+ default:
+ priv->mii_read = mtk_mii_read;
+ priv->mii_write = mtk_mii_write;
+ priv->mmd_read = mtk_mmd_read;
+ priv->mmd_write = mtk_mmd_write;
+ }
+
+ mdio_bus->read = mtk_mdio_read;
+ mdio_bus->write = mtk_mdio_write;
+ snprintf(mdio_bus->name, sizeof(mdio_bus->name), dev->name);
+
+ mdio_bus->priv = (void *)priv;
+
+ ret = mdio_register(mdio_bus);
+
+ if (ret)
+ return ret;
+
+ priv->mdio_bus = mdio_bus;
+
+ return 0;
+}
+
+/*
+ * MT7530 Internal Register Address Bits
+ * -------------------------------------------------------------------
+ * | 15 14 13 12 11 10 9 8 7 6 | 5 4 3 2 | 1 0 |
+ * |----------------------------------------|---------------|--------|
+ * | Page Address | Reg Address | Unused |
+ * -------------------------------------------------------------------
+ */
+
+static int mt7530_reg_read(struct mtk_eth_priv *priv, u32 reg, u32 *data)
+{
+ int ret, low_word, high_word;
+
+ /* Write page address */
+ ret = mtk_mii_write(priv, priv->mt7530_smi_addr, 0x1f, reg >> 6);
+ if (ret)
+ return ret;
+
+ /* Read low word */
+ low_word = mtk_mii_read(priv, priv->mt7530_smi_addr, (reg >> 2) & 0xf);
+ if (low_word < 0)
+ return low_word;
+
+ /* Read high word */
+ high_word = mtk_mii_read(priv, priv->mt7530_smi_addr, 0x10);
+ if (high_word < 0)
+ return high_word;
+
+ if (data)
+ *data = ((u32)high_word << 16) | (low_word & 0xffff);
+
+ return 0;
+}
+
+static int mt7530_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 data)
+{
+ int ret;
+
+ /* Write page address */
+ ret = mtk_mii_write(priv, priv->mt7530_smi_addr, 0x1f, reg >> 6);
+ if (ret)
+ return ret;
+
+ /* Write low word */
+ ret = mtk_mii_write(priv, priv->mt7530_smi_addr, (reg >> 2) & 0xf,
+ data & 0xffff);
+ if (ret)
+ return ret;
+
+ /* Write high word */
+ return mtk_mii_write(priv, priv->mt7530_smi_addr, 0x10, data >> 16);
+}
+
+static void mt7530_reg_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
+ u32 set)
+{
+ u32 val;
+
+ mt7530_reg_read(priv, reg, &val);
+ val &= ~clr;
+ val |= set;
+ mt7530_reg_write(priv, reg, val);
+}
+
+static void mt7530_core_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 val)
+{
+ u8 phy_addr = MT7530_PHY_ADDR(priv->mt7530_phy_base, 0);
+
+ mtk_mmd_ind_write(priv, phy_addr, 0x1f, reg, val);
+}
+
+static int mt7530_pad_clk_setup(struct mtk_eth_priv *priv, int mode)
+{
+ u32 ncpo1, ssc_delta;
+
+ switch (mode) {
+ case PHY_INTERFACE_MODE_RGMII:
+ ncpo1 = 0x0c80;
+ ssc_delta = 0x87;
+ break;
+ default:
+ printf("error: xMII mode %d not supported\n", mode);
+ return -EINVAL;
+ }
+
+ /* Disable MT7530 core clock */
+ mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, 0);
+
+ /* Disable MT7530 PLL */
+ mt7530_core_reg_write(priv, CORE_GSWPLL_GRP1,
+ (2 << RG_GSWPLL_POSDIV_200M_S) |
+ (32 << RG_GSWPLL_FBKDIV_200M_S));
+
+ /* For MT7530 core clock = 500Mhz */
+ mt7530_core_reg_write(priv, CORE_GSWPLL_GRP2,
+ (1 << RG_GSWPLL_POSDIV_500M_S) |
+ (25 << RG_GSWPLL_FBKDIV_500M_S));
+
+ /* Enable MT7530 PLL */
+ mt7530_core_reg_write(priv, CORE_GSWPLL_GRP1,
+ (2 << RG_GSWPLL_POSDIV_200M_S) |
+ (32 << RG_GSWPLL_FBKDIV_200M_S) |
+ RG_GSWPLL_EN_PRE);
+
+ udelay(20);
+
+ mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
+
+ /* Setup the MT7530 TRGMII Tx Clock */
+ mt7530_core_reg_write(priv, CORE_PLL_GROUP5, ncpo1);
+ mt7530_core_reg_write(priv, CORE_PLL_GROUP6, 0);
+ mt7530_core_reg_write(priv, CORE_PLL_GROUP10, ssc_delta);
+ mt7530_core_reg_write(priv, CORE_PLL_GROUP11, ssc_delta);
+ mt7530_core_reg_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN |
+ RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN);
+
+ mt7530_core_reg_write(priv, CORE_PLL_GROUP2,
+ RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
+ (1 << RG_SYSPLL_POSDIV_S));
+
+ mt7530_core_reg_write(priv, CORE_PLL_GROUP7,
+ RG_LCDDS_PCW_NCPO_CHG | (3 << RG_LCCDS_C_S) |
+ RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
+
+ /* Enable MT7530 core clock */
+ mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG,
+ REG_GSWCK_EN | REG_TRGMIICK_EN);
+
+ return 0;
+}
+
+static int mt7530_setup(struct mtk_eth_priv *priv)
+{
+ u16 phy_addr, phy_val;
+ u32 val;
+ int i;
+
+ /* Select 250MHz clk for RGMII mode */
+ mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG,
+ ETHSYS_TRGMII_CLK_SEL362_5, 0);
+
+ /* Global reset switch */
+ if (priv->mcm) {
+ reset_assert(&priv->rst_mcm);
+ udelay(1000);
+ reset_deassert(&priv->rst_mcm);
+ mdelay(1000);
+ } else if (dm_gpio_is_valid(&priv->rst_gpio)) {
+ dm_gpio_set_value(&priv->rst_gpio, 0);
+ udelay(1000);
+ dm_gpio_set_value(&priv->rst_gpio, 1);
+ mdelay(1000);
+ }
+
+ /* Modify HWTRAP first to allow direct access to internal PHYs */
+ mt7530_reg_read(priv, HWTRAP_REG, &val);
+ val |= CHG_TRAP;
+ val &= ~C_MDIO_BPS;
+ mt7530_reg_write(priv, MHWTRAP_REG, val);
+
+ /* Calculate the phy base address */
+ val = ((val & SMI_ADDR_M) >> SMI_ADDR_S) << 3;
+ priv->mt7530_phy_base = (val | 0x7) + 1;
+
+ /* Turn off PHYs */
+ for (i = 0; i < MT7530_NUM_PHYS; i++) {
+ phy_addr = MT7530_PHY_ADDR(priv->mt7530_phy_base, i);
+ phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
+ phy_val |= BMCR_PDOWN;
+ priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
+ }
+
+ /* Force MAC link down before reset */
+ mt7530_reg_write(priv, PCMR_REG(5), FORCE_MODE);
+ mt7530_reg_write(priv, PCMR_REG(6), FORCE_MODE);
+
+ /* MT7530 reset */
+ mt7530_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST);
+ udelay(100);
+
+ val = (1 << IPG_CFG_S) |
+ MAC_MODE | FORCE_MODE |
+ MAC_TX_EN | MAC_RX_EN |
+ BKOFF_EN | BACKPR_EN |
+ (SPEED_1000M << FORCE_SPD_S) |
+ FORCE_DPX | FORCE_LINK;
+
+ /* MT7530 Port6: Forced 1000M/FD, FC disabled */
+ mt7530_reg_write(priv, PCMR_REG(6), val);
+
+ /* MT7530 Port5: Forced link down */
+ mt7530_reg_write(priv, PCMR_REG(5), FORCE_MODE);
+
+ /* MT7530 Port6: Set to RGMII */
+ mt7530_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII);
+
+ /* Hardware Trap: Enable Port6, Disable Port5 */
+ mt7530_reg_read(priv, HWTRAP_REG, &val);
+ val |= CHG_TRAP | LOOPDET_DIS | P5_INTF_DIS |
+ (P5_INTF_SEL_GMAC5 << P5_INTF_SEL_S) |
+ (P5_INTF_MODE_RGMII << P5_INTF_MODE_S);
+ val &= ~(C_MDIO_BPS | P6_INTF_DIS);
+ mt7530_reg_write(priv, MHWTRAP_REG, val);
+
+ /* Setup switch core pll */
+ mt7530_pad_clk_setup(priv, priv->phy_interface);
+
+ /* Lower Tx Driving for TRGMII path */
+ for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
+ mt7530_reg_write(priv, MT7530_TRGMII_TD_ODT(i),
+ (8 << TD_DM_DRVP_S) | (8 << TD_DM_DRVN_S));
+
+ for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
+ mt7530_reg_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_M, 16);
+
+ /* Turn on PHYs */
+ for (i = 0; i < MT7530_NUM_PHYS; i++) {
+ phy_addr = MT7530_PHY_ADDR(priv->mt7530_phy_base, i);
+ phy_val = priv->mii_read(priv, phy_addr, MII_BMCR);
+ phy_val &= ~BMCR_PDOWN;
+ priv->mii_write(priv, phy_addr, MII_BMCR, phy_val);
+ }
+
+ /* Set port isolation */
+ for (i = 0; i < 8; i++) {
+ /* Set port matrix mode */
+ if (i != 6)
+ mt7530_reg_write(priv, PCR_REG(i),
+ (0x40 << PORT_MATRIX_S));
+ else
+ mt7530_reg_write(priv, PCR_REG(i),
+ (0x3f << PORT_MATRIX_S));
+
+ /* Set port mode to user port */
+ mt7530_reg_write(priv, PVC_REG(i),
+ (0x8100 << STAG_VPID_S) |
+ (VLAN_ATTR_USER << VLAN_ATTR_S));
+ }
+
+ return 0;
+}
+
+static void mtk_phy_link_adjust(struct mtk_eth_priv *priv)
+{
+ u16 lcl_adv = 0, rmt_adv = 0;
+ u8 flowctrl;
+ u32 mcr;
+
+ mcr = (1 << IPG_CFG_S) |
+ (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) |
+ MAC_MODE | FORCE_MODE |
+ MAC_TX_EN | MAC_RX_EN |
+ BKOFF_EN | BACKPR_EN;
+
+ switch (priv->phydev->speed) {
+ case SPEED_10:
+ mcr |= (SPEED_10M << FORCE_SPD_S);
+ break;
+ case SPEED_100:
+ mcr |= (SPEED_100M << FORCE_SPD_S);
+ break;
+ case SPEED_1000:
+ mcr |= (SPEED_1000M << FORCE_SPD_S);
+ break;
+ };
+
+ if (priv->phydev->link)
+ mcr |= FORCE_LINK;
+
+ if (priv->phydev->duplex) {
+ mcr |= FORCE_DPX;
+
+ if (priv->phydev->pause)
+ rmt_adv = LPA_PAUSE_CAP;
+ if (priv->phydev->asym_pause)
+ rmt_adv |= LPA_PAUSE_ASYM;
+
+ if (priv->phydev->advertising & ADVERTISED_Pause)
+ lcl_adv |= ADVERTISE_PAUSE_CAP;
+ if (priv->phydev->advertising & ADVERTISED_Asym_Pause)
+ lcl_adv |= ADVERTISE_PAUSE_ASYM;
+
+ flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
+
+ if (flowctrl & FLOW_CTRL_TX)
+ mcr |= FORCE_TX_FC;
+ if (flowctrl & FLOW_CTRL_RX)
+ mcr |= FORCE_RX_FC;
+
+ debug("rx pause %s, tx pause %s\n",
+ flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
+ flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
+ }
+
+ mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr);
+}
+
+static int mtk_phy_start(struct mtk_eth_priv *priv)
+{
+ struct phy_device *phydev = priv->phydev;
+ int ret;
+
+ ret = phy_startup(phydev);
+
+ if (ret) {
+ debug("Could not initialize PHY %s\n", phydev->dev->name);
+ return ret;
+ }
+
+ if (!phydev->link) {
+ debug("%s: link down.\n", phydev->dev->name);
+ return 0;
+ }
+
+ mtk_phy_link_adjust(priv);
+
+ debug("Speed: %d, %s duplex%s\n", phydev->speed,
+ (phydev->duplex) ? "full" : "half",
+ (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
+
+ return 0;
+}
+
+static int mtk_phy_probe(struct udevice *dev)
+{
+ struct mtk_eth_priv *priv = dev_get_priv(dev);
+ struct phy_device *phydev;
+
+ phydev = phy_connect(priv->mdio_bus, priv->phy_addr, dev,
+ priv->phy_interface);
+ if (!phydev)
+ return -ENODEV;
+
+ phydev->supported &= PHY_GBIT_FEATURES;
+ phydev->advertising = phydev->supported;
+
+ priv->phydev = phydev;
+ phy_config(phydev);
+
+ return 0;
+}
+
+static void mtk_mac_init(struct mtk_eth_priv *priv)
+{
+ int i, ge_mode = 0;
+ u32 mcr;
+
+ switch (priv->phy_interface) {
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_SGMII:
+ ge_mode = GE_MODE_RGMII;
+ break;
+ case PHY_INTERFACE_MODE_MII:
+ case PHY_INTERFACE_MODE_GMII:
+ ge_mode = GE_MODE_MII;
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ ge_mode = GE_MODE_RMII;
+ break;
+ default:
+ break;
+ }
+
+ /* set the gmac to the right mode */
+ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG,
+ SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id),
+ ge_mode << SYSCFG0_GE_MODE_S(priv->gmac_id));
+
+ if (priv->force_mode) {
+ mcr = (1 << IPG_CFG_S) |
+ (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) |
+ MAC_MODE | FORCE_MODE |
+ MAC_TX_EN | MAC_RX_EN |
+ BKOFF_EN | BACKPR_EN |
+ FORCE_LINK;
+
+ switch (priv->speed) {
+ case SPEED_10:
+ mcr |= SPEED_10M << FORCE_SPD_S;
+ break;
+ case SPEED_100:
+ mcr |= SPEED_100M << FORCE_SPD_S;
+ break;
+ case SPEED_1000:
+ mcr |= SPEED_1000M << FORCE_SPD_S;
+ break;
+ }
+
+ if (priv->duplex)
+ mcr |= FORCE_DPX;
+
+ mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr);
+ }
+
+ if (priv->soc == SOC_MT7623) {
+ /* Lower Tx Driving for TRGMII path */
+ for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
+ mtk_gmac_write(priv, GMAC_TRGMII_TD_ODT(i),
+ (8 << TD_DM_DRVP_S) |
+ (8 << TD_DM_DRVN_S));
+
+ mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, 0,
+ RX_RST | RXC_DQSISEL);
+ mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, RX_RST, 0);
+ }
+}
+
+static void mtk_eth_fifo_init(struct mtk_eth_priv *priv)
+{
+ char *pkt_base = priv->pkt_pool;
+ int i;
+
+ mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0xffff0000, 0);
+ udelay(500);
+
+ memset(priv->tx_ring_noc, 0, NUM_TX_DESC * sizeof(struct pdma_txdesc));
+ memset(priv->rx_ring_noc, 0, NUM_RX_DESC * sizeof(struct pdma_rxdesc));
+ memset(priv->pkt_pool, 0, TOTAL_PKT_BUF_SIZE);
+
+ flush_dcache_range((u32)pkt_base, (u32)(pkt_base + TOTAL_PKT_BUF_SIZE));
+
+ priv->rx_dma_owner_idx0 = 0;
+ priv->tx_cpu_owner_idx0 = 0;
+
+ for (i = 0; i < NUM_TX_DESC; i++) {
+ priv->tx_ring_noc[i].txd_info2.LS0 = 1;
+ priv->tx_ring_noc[i].txd_info2.DDONE = 1;
+ priv->tx_ring_noc[i].txd_info4.FPORT = priv->gmac_id + 1;
+
+ priv->tx_ring_noc[i].txd_info1.SDP0 = virt_to_phys(pkt_base);
+ pkt_base += PKTSIZE_ALIGN;
+ }
+
+ for (i = 0; i < NUM_RX_DESC; i++) {
+ priv->rx_ring_noc[i].rxd_info2.PLEN0 = PKTSIZE_ALIGN;
+ priv->rx_ring_noc[i].rxd_info1.PDP0 = virt_to_phys(pkt_base);
+ pkt_base += PKTSIZE_ALIGN;
+ }
+
+ mtk_pdma_write(priv, TX_BASE_PTR_REG(0),
+ virt_to_phys(priv->tx_ring_noc));
+ mtk_pdma_write(priv, TX_MAX_CNT_REG(0), NUM_TX_DESC);
+ mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0);
+
+ mtk_pdma_write(priv, RX_BASE_PTR_REG(0),
+ virt_to_phys(priv->rx_ring_noc));
+ mtk_pdma_write(priv, RX_MAX_CNT_REG(0), NUM_RX_DESC);
+ mtk_pdma_write(priv, RX_CRX_IDX_REG(0), NUM_RX_DESC - 1);
+
+ mtk_pdma_write(priv, PDMA_RST_IDX_REG, RST_DTX_IDX0 | RST_DRX_IDX0);
+}
+
+static int mtk_eth_start(struct udevice *dev)
+{
+ struct mtk_eth_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ /* Reset FE */
+ reset_assert(&priv->rst_fe);
+ udelay(1000);
+ reset_deassert(&priv->rst_fe);
+ mdelay(10);
+
+ /* Packets forward to PDMA */
+ mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_FWD_TO_CPU);
+
+ if (priv->gmac_id == 0)
+ mtk_gdma_write(priv, 1, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
+ else
+ mtk_gdma_write(priv, 0, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
+
+ udelay(500);
+
+ mtk_eth_fifo_init(priv);
+
+ /* Start PHY */
+ if (priv->sw == SW_NONE) {
+ ret = mtk_phy_start(priv);
+ if (ret)
+ return ret;
+ }
+
+ mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0,
+ TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN);
+ udelay(500);
+
+ return 0;
+}
+
+static void mtk_eth_stop(struct udevice *dev)
+{
+ struct mtk_eth_priv *priv = dev_get_priv(dev);
+
+ mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG,
+ TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN, 0);
+ udelay(500);
+
+ wait_for_bit_le32(priv->fe_base + PDMA_BASE + PDMA_GLO_CFG_REG,
+ RX_DMA_BUSY | TX_DMA_BUSY, 0, 5000, 0);
+}
+
+static int mtk_eth_write_hwaddr(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct mtk_eth_priv *priv = dev_get_priv(dev);
+ unsigned char *mac = pdata->enetaddr;
+ u32 macaddr_lsb, macaddr_msb;
+
+ macaddr_msb = ((u32)mac[0] << 8) | (u32)mac[1];
+ macaddr_lsb = ((u32)mac[2] << 24) | ((u32)mac[3] << 16) |
+ ((u32)mac[4] << 8) | (u32)mac[5];
+
+ mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_MSB_REG, macaddr_msb);
+ mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_LSB_REG, macaddr_lsb);
+
+ return 0;
+}
+
+static int mtk_eth_send(struct udevice *dev, void *packet, int length)
+{
+ struct mtk_eth_priv *priv = dev_get_priv(dev);
+ u32 idx = priv->tx_cpu_owner_idx0;
+ void *pkt_base;
+
+ if (!priv->tx_ring_noc[idx].txd_info2.DDONE) {
+ debug("mtk-eth: TX DMA descriptor ring is full\n");
+ return -EPERM;
+ }
+
+ pkt_base = (void *)phys_to_virt(priv->tx_ring_noc[idx].txd_info1.SDP0);
+ memcpy(pkt_base, packet, length);
+ flush_dcache_range((u32)pkt_base, (u32)pkt_base +
+ roundup(length, ARCH_DMA_MINALIGN));
+
+ priv->tx_ring_noc[idx].txd_info2.SDL0 = length;
+ priv->tx_ring_noc[idx].txd_info2.DDONE = 0;
+
+ priv->tx_cpu_owner_idx0 = (priv->tx_cpu_owner_idx0 + 1) % NUM_TX_DESC;
+ mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0);
+
+ return 0;
+}
+
+static int mtk_eth_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct mtk_eth_priv *priv = dev_get_priv(dev);
+ u32 idx = priv->rx_dma_owner_idx0;
+ uchar *pkt_base;
+ u32 length;
+
+ if (!priv->rx_ring_noc[idx].rxd_info2.DDONE) {
+ debug("mtk-eth: RX DMA descriptor ring is empty\n");
+ return -EAGAIN;
+ }
+
+ length = priv->rx_ring_noc[idx].rxd_info2.PLEN0;
+ pkt_base = (void *)phys_to_virt(priv->rx_ring_noc[idx].rxd_info1.PDP0);
+ invalidate_dcache_range((u32)pkt_base, (u32)pkt_base +
+ roundup(length, ARCH_DMA_MINALIGN));
+
+ if (packetp)
+ *packetp = pkt_base;
+
+ return length;
+}
+
+static int mtk_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct mtk_eth_priv *priv = dev_get_priv(dev);
+ u32 idx = priv->rx_dma_owner_idx0;
+
+ priv->rx_ring_noc[idx].rxd_info2.DDONE = 0;
+ priv->rx_ring_noc[idx].rxd_info2.LS0 = 0;
+ priv->rx_ring_noc[idx].rxd_info2.PLEN0 = PKTSIZE_ALIGN;
+
+ mtk_pdma_write(priv, RX_CRX_IDX_REG(0), idx);
+ priv->rx_dma_owner_idx0 = (priv->rx_dma_owner_idx0 + 1) % NUM_RX_DESC;
+
+ return 0;
+}
+
+static int mtk_eth_probe(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct mtk_eth_priv *priv = dev_get_priv(dev);
+ u32 iobase = pdata->iobase;
+ int ret;
+
+ /* Frame Engine Register Base */
+ priv->fe_base = (void *)iobase;
+
+ /* GMAC Register Base */
+ priv->gmac_base = (void *)(iobase + GMAC_BASE);
+
+ /* MDIO register */
+ ret = mtk_mdio_register(dev);
+ if (ret)
+ return ret;
+
+ /* Prepare for tx/rx rings */
+ priv->tx_ring_noc = (struct pdma_txdesc *)
+ noncached_alloc(sizeof(struct pdma_txdesc) * NUM_TX_DESC,
+ ARCH_DMA_MINALIGN);
+ priv->rx_ring_noc = (struct pdma_rxdesc *)
+ noncached_alloc(sizeof(struct pdma_rxdesc) * NUM_RX_DESC,
+ ARCH_DMA_MINALIGN);
+
+ /* Set MAC mode */
+ mtk_mac_init(priv);
+
+ /* Probe phy if switch is not specified */
+ if (priv->sw == SW_NONE)
+ return mtk_phy_probe(dev);
+
+ /* Initialize switch */
+ return priv->switch_init(priv);
+}
+
+static int mtk_eth_remove(struct udevice *dev)
+{
+ struct mtk_eth_priv *priv = dev_get_priv(dev);
+
+ /* MDIO unregister */
+ mdio_unregister(priv->mdio_bus);
+ mdio_free(priv->mdio_bus);
+
+ /* Stop possibly started DMA */
+ mtk_eth_stop(dev);
+
+ return 0;
+}
+
+static int mtk_eth_ofdata_to_platdata(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct mtk_eth_priv *priv = dev_get_priv(dev);
+ struct ofnode_phandle_args args;
+ struct regmap *regmap;
+ const char *str;
+ ofnode subnode;
+ int ret;
+
+ priv->soc = dev_get_driver_data(dev);
+
+ pdata->iobase = devfdt_get_addr(dev);
+
+ /* get corresponding ethsys phandle */
+ ret = dev_read_phandle_with_args(dev, "mediatek,ethsys", NULL, 0, 0,
+ &args);
+ if (ret)
+ return ret;
+
+ regmap = syscon_node_to_regmap(args.node);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ priv->ethsys_base = regmap_get_range(regmap, 0);
+ if (!priv->ethsys_base) {
+ dev_err(dev, "Unable to find ethsys\n");
+ return -ENODEV;
+ }
+
+ /* Reset controllers */
+ ret = reset_get_by_name(dev, "fe", &priv->rst_fe);
+ if (ret) {
+ printf("error: Unable to get reset ctrl for frame engine\n");
+ return ret;
+ }
+
+ priv->gmac_id = dev_read_u32_default(dev, "mediatek,gmac-id", 0);
+
+ /* Interface mode is required */
+ str = dev_read_string(dev, "phy-mode");
+ if (str) {
+ pdata->phy_interface = phy_get_interface_by_name(str);
+ priv->phy_interface = pdata->phy_interface;
+ } else {
+ printf("error: phy-mode is not set\n");
+ return -EINVAL;
+ }
+
+ /* Force mode or autoneg */
+ subnode = ofnode_find_subnode(dev_ofnode(dev), "fixed-link");
+ if (ofnode_valid(subnode)) {
+ priv->force_mode = 1;
+ priv->speed = ofnode_read_u32_default(subnode, "speed", 0);
+ priv->duplex = ofnode_read_bool(subnode, "full-duplex");
+
+ if (priv->speed != SPEED_10 && priv->speed != SPEED_100 &&
+ priv->speed != SPEED_1000) {
+ printf("error: no valid speed set in fixed-link\n");
+ return -EINVAL;
+ }
+ }
+
+ /* check for switch first, otherwise phy will be used */
+ priv->sw = SW_NONE;
+ priv->switch_init = NULL;
+ str = dev_read_string(dev, "mediatek,switch");
+
+ if (str) {
+ if (!strcmp(str, "mt7530")) {
+ priv->sw = SW_MT7530;
+ priv->switch_init = mt7530_setup;
+ priv->mt7530_smi_addr = MT7530_DFL_SMI_ADDR;
+ } else {
+ printf("error: unsupported switch\n");
+ return -EINVAL;
+ }
+
+ priv->mcm = dev_read_bool(dev, "mediatek,mcm");
+ if (priv->mcm) {
+ ret = reset_get_by_name(dev, "mcm", &priv->rst_mcm);
+ if (ret) {
+ printf("error: no reset ctrl for mcm\n");
+ return ret;
+ }
+ } else {
+ gpio_request_by_name(dev, "reset-gpios", 0,
+ &priv->rst_gpio, GPIOD_IS_OUT);
+ }
+ } else {
+ subnode = ofnode_find_subnode(dev_ofnode(dev), "phy-handle");
+ if (!ofnode_valid(subnode)) {
+ printf("error: phy-handle is not specified\n");
+ return ret;
+ }
+
+ priv->phy_addr = ofnode_read_s32_default(subnode, "reg", -1);
+ if (priv->phy_addr < 0) {
+ printf("error: phy address is not specified\n");
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static const struct udevice_id mtk_eth_ids[] = {
+ { .compatible = "mediatek,mt7629-eth", .data = SOC_MT7629 },
+ { .compatible = "mediatek,mt7623-eth", .data = SOC_MT7623 },
+ {}
+};
+
+static const struct eth_ops mtk_eth_ops = {
+ .start = mtk_eth_start,
+ .stop = mtk_eth_stop,
+ .send = mtk_eth_send,
+ .recv = mtk_eth_recv,
+ .free_pkt = mtk_eth_free_pkt,
+ .write_hwaddr = mtk_eth_write_hwaddr,
+};
+
+U_BOOT_DRIVER(mtk_eth) = {
+ .name = "mtk-eth",
+ .id = UCLASS_ETH,
+ .of_match = mtk_eth_ids,
+ .ofdata_to_platdata = mtk_eth_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+ .probe = mtk_eth_probe,
+ .remove = mtk_eth_remove,
+ .ops = &mtk_eth_ops,
+ .priv_auto_alloc_size = sizeof(struct mtk_eth_priv),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth.h
new file mode 100644
index 0000000000..fe89a03739
--- /dev/null
+++ b/drivers/net/mtk_eth.h
@@ -0,0 +1,286 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ * Author: Mark Lee <mark-mc.lee@mediatek.com>
+ */
+
+#ifndef _MTK_ETH_H_
+#define _MTK_ETH_H_
+
+/* Frame Engine Register Bases */
+#define PDMA_BASE 0x0800
+#define GDMA1_BASE 0x0500
+#define GDMA2_BASE 0x1500
+#define GMAC_BASE 0x10000
+
+/* Ethernet subsystem registers */
+
+#define ETHSYS_SYSCFG0_REG 0x14
+#define SYSCFG0_GE_MODE_S(n) (12 + ((n) * 2))
+#define SYSCFG0_GE_MODE_M 0x3
+
+#define ETHSYS_CLKCFG0_REG 0x2c
+#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
+
+/* SYSCFG0_GE_MODE: GE Modes */
+#define GE_MODE_RGMII 0
+#define GE_MODE_MII 1
+#define GE_MODE_MII_PHY 2
+#define GE_MODE_RMII 3
+
+/* Frame Engine Registers */
+
+/* PDMA */
+#define TX_BASE_PTR_REG(n) (0x000 + (n) * 0x10)
+#define TX_MAX_CNT_REG(n) (0x004 + (n) * 0x10)
+#define TX_CTX_IDX_REG(n) (0x008 + (n) * 0x10)
+#define TX_DTX_IDX_REG(n) (0x00c + (n) * 0x10)
+
+#define RX_BASE_PTR_REG(n) (0x100 + (n) * 0x10)
+#define RX_MAX_CNT_REG(n) (0x104 + (n) * 0x10)
+#define RX_CRX_IDX_REG(n) (0x108 + (n) * 0x10)
+#define RX_DRX_IDX_REG(n) (0x10c + (n) * 0x10)
+
+#define PDMA_GLO_CFG_REG 0x204
+#define TX_WB_DDONE BIT(6)
+#define RX_DMA_BUSY BIT(3)
+#define RX_DMA_EN BIT(2)
+#define TX_DMA_BUSY BIT(1)
+#define TX_DMA_EN BIT(0)
+
+#define PDMA_RST_IDX_REG 0x208
+#define RST_DRX_IDX0 BIT(16)
+#define RST_DTX_IDX0 BIT(0)
+
+/* GDMA */
+#define GDMA_IG_CTRL_REG 0x000
+#define GDM_ICS_EN BIT(22)
+#define GDM_TCS_EN BIT(21)
+#define GDM_UCS_EN BIT(20)
+#define STRP_CRC BIT(16)
+#define MYMAC_DP_S 12
+#define MYMAC_DP_M 0xf000
+#define BC_DP_S 8
+#define BC_DP_M 0xf00
+#define MC_DP_S 4
+#define MC_DP_M 0xf0
+#define UN_DP_S 0
+#define UN_DP_M 0x0f
+
+#define GDMA_MAC_LSB_REG 0x008
+
+#define GDMA_MAC_MSB_REG 0x00c
+
+/* MYMAC_DP/BC_DP/MC_DP/UN_DP: Destination ports */
+#define DP_PDMA 0
+#define DP_GDMA1 1
+#define DP_GDMA2 2
+#define DP_PPE 4
+#define DP_QDMA 5
+#define DP_DISCARD 7
+
+/* GMAC Registers */
+
+#define GMAC_PIAC_REG 0x0004
+#define PHY_ACS_ST BIT(31)
+#define MDIO_REG_ADDR_S 25
+#define MDIO_REG_ADDR_M 0x3e000000
+#define MDIO_PHY_ADDR_S 20
+#define MDIO_PHY_ADDR_M 0x1f00000
+#define MDIO_CMD_S 18
+#define MDIO_CMD_M 0xc0000
+#define MDIO_ST_S 16
+#define MDIO_ST_M 0x30000
+#define MDIO_RW_DATA_S 0
+#define MDIO_RW_DATA_M 0xffff
+
+/* MDIO_CMD: MDIO commands */
+#define MDIO_CMD_ADDR 0
+#define MDIO_CMD_WRITE 1
+#define MDIO_CMD_READ 2
+#define MDIO_CMD_READ_C45 3
+
+/* MDIO_ST: MDIO start field */
+#define MDIO_ST_C45 0
+#define MDIO_ST_C22 1
+
+#define GMAC_PORT_MCR(p) (0x0100 + (p) * 0x100)
+#define MAC_RX_PKT_LEN_S 24
+#define MAC_RX_PKT_LEN_M 0x3000000
+#define IPG_CFG_S 18
+#define IPG_CFG_M 0xc0000
+#define MAC_MODE BIT(16)
+#define FORCE_MODE BIT(15)
+#define MAC_TX_EN BIT(14)
+#define MAC_RX_EN BIT(13)
+#define BKOFF_EN BIT(9)
+#define BACKPR_EN BIT(8)
+#define FORCE_RX_FC BIT(5)
+#define FORCE_TX_FC BIT(4)
+#define FORCE_SPD_S 2
+#define FORCE_SPD_M 0x0c
+#define FORCE_DPX BIT(1)
+#define FORCE_LINK BIT(0)
+
+/* MAC_RX_PKT_LEN: Max RX packet length */
+#define MAC_RX_PKT_LEN_1518 0
+#define MAC_RX_PKT_LEN_1536 1
+#define MAC_RX_PKT_LEN_1552 2
+#define MAC_RX_PKT_LEN_JUMBO 3
+
+/* FORCE_SPD: Forced link speed */
+#define SPEED_10M 0
+#define SPEED_100M 1
+#define SPEED_1000M 2
+
+#define GMAC_TRGMII_RCK_CTRL 0x300
+#define RX_RST BIT(31)
+#define RXC_DQSISEL BIT(30)
+
+#define GMAC_TRGMII_TD_ODT(n) (0x354 + (n) * 8)
+#define TD_DM_DRVN_S 4
+#define TD_DM_DRVN_M 0xf0
+#define TD_DM_DRVP_S 0
+#define TD_DM_DRVP_M 0x0f
+
+/* MT7530 Registers */
+
+#define PCR_REG(p) (0x2004 + (p) * 0x100)
+#define PORT_MATRIX_S 16
+#define PORT_MATRIX_M 0xff0000
+
+#define PVC_REG(p) (0x2010 + (p) * 0x100)
+#define STAG_VPID_S 16
+#define STAG_VPID_M 0xffff0000
+#define VLAN_ATTR_S 6
+#define VLAN_ATTR_M 0xc0
+
+/* VLAN_ATTR: VLAN attributes */
+#define VLAN_ATTR_USER 0
+#define VLAN_ATTR_STACK 1
+#define VLAN_ATTR_TRANSLATION 2
+#define VLAN_ATTR_TRANSPARENT 3
+
+#define PCMR_REG(p) (0x3000 + (p) * 0x100)
+/* XXX: all fields are defined under GMAC_PORT_MCR */
+
+#define SYS_CTRL_REG 0x7000
+#define SW_PHY_RST BIT(2)
+#define SW_SYS_RST BIT(1)
+#define SW_REG_RST BIT(0)
+
+#define NUM_TRGMII_CTRL 5
+
+#define HWTRAP_REG 0x7800
+#define MHWTRAP_REG 0x7804
+#define CHG_TRAP BIT(16)
+#define LOOPDET_DIS BIT(14)
+#define P5_INTF_SEL_S 13
+#define P5_INTF_SEL_M 0x2000
+#define SMI_ADDR_S 11
+#define SMI_ADDR_M 0x1800
+#define XTAL_FSEL_S 9
+#define XTAL_FSEL_M 0x600
+#define P6_INTF_DIS BIT(8)
+#define P5_INTF_MODE_S 7
+#define P5_INTF_MODE_M 0x80
+#define P5_INTF_DIS BIT(6)
+#define C_MDIO_BPS BIT(5)
+#define CHIP_MODE_S 0
+#define CHIP_MODE_M 0x0f
+
+/* P5_INTF_SEL: Interface type of Port5 */
+#define P5_INTF_SEL_GPHY 0
+#define P5_INTF_SEL_GMAC5 1
+
+/* P5_INTF_MODE: Interface mode of Port5 */
+#define P5_INTF_MODE_GMII_MII 0
+#define P5_INTF_MODE_RGMII 1
+
+#define MT7530_P6ECR 0x7830
+#define P6_INTF_MODE_M 0x3
+#define P6_INTF_MODE_S 0
+
+/* P6_INTF_MODE: Interface mode of Port6 */
+#define P6_INTF_MODE_RGMII 0
+#define P6_INTF_MODE_TRGMII 1
+
+#define MT7530_TRGMII_RD(n) (0x7a10 + (n) * 8)
+#define RD_TAP_S 0
+#define RD_TAP_M 0x7f
+
+#define MT7530_TRGMII_TD_ODT(n) (0x7a54 + (n) * 8)
+/* XXX: all fields are defined under GMAC_TRGMII_TD_ODT */
+
+/* MT7530 GPHY MDIO Indirect Access Registers */
+
+#define MII_MMD_ACC_CTL_REG 0x0d
+#define MMD_CMD_S 14
+#define MMD_CMD_M 0xc000
+#define MMD_DEVAD_S 0
+#define MMD_DEVAD_M 0x1f
+
+/* MMD_CMD: MMD commands */
+#define MMD_ADDR 0
+#define MMD_DATA 1
+#define MMD_DATA_RW_POST_INC 2
+#define MMD_DATA_W_POST_INC 3
+
+#define MII_MMD_ADDR_DATA_REG 0x0e
+
+/* MT7530 GPHY MDIO MMD Registers */
+
+#define CORE_PLL_GROUP2 0x401
+#define RG_SYSPLL_EN_NORMAL BIT(15)
+#define RG_SYSPLL_VODEN BIT(14)
+#define RG_SYSPLL_POSDIV_S 5
+#define RG_SYSPLL_POSDIV_M 0x60
+
+#define CORE_PLL_GROUP4 0x403
+#define RG_SYSPLL_DDSFBK_EN BIT(12)
+#define RG_SYSPLL_BIAS_EN BIT(11)
+#define RG_SYSPLL_BIAS_LPF_EN BIT(10)
+
+#define CORE_PLL_GROUP5 0x404
+#define RG_LCDDS_PCW_NCPO1_S 0
+#define RG_LCDDS_PCW_NCPO1_M 0xffff
+
+#define CORE_PLL_GROUP6 0x405
+#define RG_LCDDS_PCW_NCPO0_S 0
+#define RG_LCDDS_PCW_NCPO0_M 0xffff
+
+#define CORE_PLL_GROUP7 0x406
+#define RG_LCDDS_PWDB BIT(15)
+#define RG_LCDDS_ISO_EN BIT(13)
+#define RG_LCCDS_C_S 4
+#define RG_LCCDS_C_M 0x70
+#define RG_LCDDS_PCW_NCPO_CHG BIT(3)
+
+#define CORE_PLL_GROUP10 0x409
+#define RG_LCDDS_SSC_DELTA_S 0
+#define RG_LCDDS_SSC_DELTA_M 0xfff
+
+#define CORE_PLL_GROUP11 0x40a
+#define RG_LCDDS_SSC_DELTA1_S 0
+#define RG_LCDDS_SSC_DELTA1_M 0xfff
+
+#define CORE_GSWPLL_GRP1 0x40d
+#define RG_GSWPLL_POSDIV_200M_S 12
+#define RG_GSWPLL_POSDIV_200M_M 0x3000
+#define RG_GSWPLL_EN_PRE BIT(11)
+#define RG_GSWPLL_FBKDIV_200M_S 0
+#define RG_GSWPLL_FBKDIV_200M_M 0xff
+
+#define CORE_GSWPLL_GRP2 0x40e
+#define RG_GSWPLL_POSDIV_500M_S 8
+#define RG_GSWPLL_POSDIV_500M_M 0x300
+#define RG_GSWPLL_FBKDIV_500M_S 0
+#define RG_GSWPLL_FBKDIV_500M_M 0xff
+
+#define CORE_TRGMII_GSW_CLK_CG 0x410
+#define REG_GSWCK_EN BIT(0)
+#define REG_TRGMIICK_EN BIT(1)
+
+#endif /* _MTK_ETH_H_ */
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 9c5208b7da..3a6d61f440 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -106,4 +106,11 @@ config RESET_SOCFPGA
help
Support for reset controller on SoCFPGA platform.
+config RESET_MEDIATEK
+ bool "Reset controller driver for MediaTek SoCs"
+ depends on DM_RESET && ARCH_MEDIATEK && CLK
+ default y
+ help
+ Support for reset controller on MediaTek SoCs.
+
endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index f4520878b7..8a4dcab8f6 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
+obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
diff --git a/drivers/reset/reset-mediatek.c b/drivers/reset/reset-mediatek.c
new file mode 100644
index 0000000000..e3614e6e2a
--- /dev/null
+++ b/drivers/reset/reset-mediatek.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ *
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ * Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/lists.h>
+#include <regmap.h>
+#include <reset-uclass.h>
+#include <syscon.h>
+
+struct mediatek_reset_priv {
+ struct regmap *regmap;
+ u32 regofs;
+ u32 nr_resets;
+};
+
+static int mediatek_reset_request(struct reset_ctl *reset_ctl)
+{
+ return 0;
+}
+
+static int mediatek_reset_free(struct reset_ctl *reset_ctl)
+{
+ return 0;
+}
+
+static int mediatek_reset_assert(struct reset_ctl *reset_ctl)
+{
+ struct mediatek_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+ int id = reset_ctl->id;
+
+ if (id >= priv->nr_resets)
+ return -EINVAL;
+
+ return regmap_update_bits(priv->regmap,
+ priv->regofs + ((id / 32) << 2), BIT(id % 32), BIT(id % 32));
+}
+
+static int mediatek_reset_deassert(struct reset_ctl *reset_ctl)
+{
+ struct mediatek_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+ int id = reset_ctl->id;
+
+ if (id >= priv->nr_resets)
+ return -EINVAL;
+
+ return regmap_update_bits(priv->regmap,
+ priv->regofs + ((id / 32) << 2), BIT(id % 32), 0);
+}
+
+struct reset_ops mediatek_reset_ops = {
+ .request = mediatek_reset_request,
+ .free = mediatek_reset_free,
+ .rst_assert = mediatek_reset_assert,
+ .rst_deassert = mediatek_reset_deassert,
+};
+
+static int mediatek_reset_probe(struct udevice *dev)
+{
+ struct mediatek_reset_priv *priv = dev_get_priv(dev);
+
+ if (!priv->regofs && !priv->nr_resets)
+ return -EINVAL;
+
+ priv->regmap = syscon_node_to_regmap(dev_ofnode(dev));
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+ return 0;
+}
+
+int mediatek_reset_bind(struct udevice *pdev, u32 regofs, u32 num_regs)
+{
+ struct udevice *rst_dev;
+ struct mediatek_reset_priv *priv;
+ int ret;
+
+ ret = device_bind_driver_to_node(pdev, "mediatek_reset", "reset",
+ dev_ofnode(pdev), &rst_dev);
+ if (ret)
+ return ret;
+
+ priv = malloc(sizeof(struct mediatek_reset_priv));
+ priv->regofs = regofs;
+ priv->nr_resets = num_regs * 32;
+ rst_dev->priv = priv;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(mediatek_reset) = {
+ .name = "mediatek_reset",
+ .id = UCLASS_RESET,
+ .probe = mediatek_reset_probe,
+ .ops = &mediatek_reset_ops,
+ .priv_auto_alloc_size = sizeof(struct mediatek_reset_priv),
+};
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index b7ff2960ab..887cd687c0 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -442,10 +442,23 @@ config DEBUG_UART_ANNOUNCE
config DEBUG_UART_SKIP_INIT
bool "Skip UART initialization"
+ depends on DEBUG_UART
help
Select this if the UART you want to use for debug output is already
initialized by the time U-Boot starts its execution.
+config DEBUG_UART_NS16550_CHECK_ENABLED
+ bool "Check if UART is enabled on output"
+ depends on DEBUG_UART
+ depends on DEBUG_UART_NS16550
+ help
+ Select this if puts()/putc() might be called before the debug UART
+ has been initialized. If this is disabled, putc() might sit in a
+ tight loop if it is called before debug_uart_init() has been called.
+
+ Note that this does not work for every ns16550-compatible UART and
+ so has to be enabled carefully or you might notice lost characters.
+
config ALTERA_JTAG_UART
bool "Altera JTAG UART support"
depends on DM_SERIAL
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 560ca2ae34..6cf2be8f2b 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -272,12 +272,28 @@ static inline void _debug_uart_init(void)
serial_dout(&com_port->lcr, UART_LCRVAL);
}
+static inline int NS16550_read_baud_divisor(struct NS16550 *com_port)
+{
+ int ret;
+
+ serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
+ ret = serial_din(&com_port->dll) & 0xff;
+ ret |= (serial_din(&com_port->dlm) & 0xff) << 8;
+ serial_dout(&com_port->lcr, UART_LCRVAL);
+
+ return ret;
+}
+
static inline void _debug_uart_putc(int ch)
{
struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE;
- while (!(serial_din(&com_port->lsr) & UART_LSR_THRE))
- ;
+ while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) {
+#ifdef CONFIG_DEBUG_UART_NS16550_CHECK_ENABLED
+ if (!NS16550_read_baud_divisor(com_port))
+ return;
+#endif
+ }
serial_dout(&com_port->thr, ch);
}
generated by cgit (git 2.34.1) at 2025-01-18 05:59:13 +0000