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-rw-r--r--drivers/fpga/socfpga.c14
-rw-r--r--drivers/gpio/gpio-uniphier.c3
-rw-r--r--drivers/gpio/kw_gpio.c2
-rw-r--r--drivers/mtd/mtdcore.c360
-rw-r--r--drivers/mtd/nand/Kconfig11
-rw-r--r--drivers/mtd/nand/davinci_nand.c10
-rw-r--r--drivers/mtd/nand/denali.c2027
-rw-r--r--drivers/mtd/nand/denali.h473
-rw-r--r--drivers/mtd/nand/denali_dt.c17
-rw-r--r--drivers/mtd/nand/denali_spl.c14
-rw-r--r--drivers/mtd/nand/nand_base.c530
-rw-r--r--drivers/mtd/nand/nand_timings.c494
-rw-r--r--drivers/pci/pci_msc01.c2
-rw-r--r--drivers/usb/gadget/f_sdp.c4
-rw-r--r--drivers/usb/gadget/storage_common.c2
-rw-r--r--drivers/usb/host/Kconfig8
-rw-r--r--drivers/usb/host/Makefile1
-rw-r--r--drivers/usb/host/ehci-hcd.c15
-rw-r--r--drivers/usb/host/ehci.h8
-rw-r--r--drivers/usb/host/r8a66597-hcd.c47
-rw-r--r--drivers/usb/host/r8a66597.h21
-rw-r--r--drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h643
-rw-r--r--drivers/usb/host/xhci-rcar.c159
23 files changed, 3280 insertions, 1585 deletions
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index 28fa16b944..6e14ebd26d 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -55,18 +55,20 @@ void fpgamgr_program_write(const void *rbf_data, size_t rbf_size)
uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4);
asm volatile(
+ " cmp %2, #0\n"
+ " beq 2f\n"
"1: ldmia %0!, {r0-r7}\n"
" stmia %1!, {r0-r7}\n"
" sub %1, #32\n"
" subs %2, #1\n"
" bne 1b\n"
- " cmp %3, #0\n"
- " beq 3f\n"
- "2: ldr %2, [%0], #4\n"
+ "2: cmp %3, #0\n"
+ " beq 4f\n"
+ "3: ldr %2, [%0], #4\n"
" str %2, [%1]\n"
" subs %3, #1\n"
- " bne 2b\n"
- "3: nop\n"
+ " bne 3b\n"
+ "4: nop\n"
: "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) :
: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc");
}
diff --git a/drivers/gpio/gpio-uniphier.c b/drivers/gpio/gpio-uniphier.c
index 107c3fcb10..8d72ab8c4a 100644
--- a/drivers/gpio/gpio-uniphier.c
+++ b/drivers/gpio/gpio-uniphier.c
@@ -13,8 +13,7 @@
#include <linux/errno.h>
#include <asm/global_data.h>
#include <asm/gpio.h>
-
-#define UNIPHIER_GPIO_LINES_PER_BANK 8
+#include <dt-bindings/gpio/uniphier-gpio.h>
#define UNIPHIER_GPIO_PORT_DATA 0x0 /* data */
#define UNIPHIER_GPIO_PORT_DIR 0x4 /* direction (1:in, 0:out) */
diff --git a/drivers/gpio/kw_gpio.c b/drivers/gpio/kw_gpio.c
index 43b27e3fea..cc26cc1658 100644
--- a/drivers/gpio/kw_gpio.c
+++ b/drivers/gpio/kw_gpio.c
@@ -14,7 +14,7 @@
*/
#include <common.h>
-#include <asm/bitops.h>
+#include <linux/bitops.h>
#include <asm/io.h>
#include <asm/arch/soc.h>
#include <asm/arch/gpio.h>
diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c
index e3f56e5424..2cda0511e8 100644
--- a/drivers/mtd/mtdcore.c
+++ b/drivers/mtd/mtdcore.c
@@ -1005,6 +1005,366 @@ int mtd_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops)
}
EXPORT_SYMBOL_GPL(mtd_read_oob);
+/**
+ * mtd_ooblayout_ecc - Get the OOB region definition of a specific ECC section
+ * @mtd: MTD device structure
+ * @section: ECC section. Depending on the layout you may have all the ECC
+ * bytes stored in a single contiguous section, or one section
+ * per ECC chunk (and sometime several sections for a single ECC
+ * ECC chunk)
+ * @oobecc: OOB region struct filled with the appropriate ECC position
+ * information
+ *
+ * This function returns ECC section information in the OOB area. If you want
+ * to get all the ECC bytes information, then you should call
+ * mtd_ooblayout_ecc(mtd, section++, oobecc) until it returns -ERANGE.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobecc)
+{
+ memset(oobecc, 0, sizeof(*oobecc));
+
+ if (!mtd || section < 0)
+ return -EINVAL;
+
+ if (!mtd->ooblayout || !mtd->ooblayout->ecc)
+ return -ENOTSUPP;
+
+ return mtd->ooblayout->ecc(mtd, section, oobecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_ecc);
+
+/**
+ * mtd_ooblayout_free - Get the OOB region definition of a specific free
+ * section
+ * @mtd: MTD device structure
+ * @section: Free section you are interested in. Depending on the layout
+ * you may have all the free bytes stored in a single contiguous
+ * section, or one section per ECC chunk plus an extra section
+ * for the remaining bytes (or other funky layout).
+ * @oobfree: OOB region struct filled with the appropriate free position
+ * information
+ *
+ * This function returns free bytes position in the OOB area. If you want
+ * to get all the free bytes information, then you should call
+ * mtd_ooblayout_free(mtd, section++, oobfree) until it returns -ERANGE.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobfree)
+{
+ memset(oobfree, 0, sizeof(*oobfree));
+
+ if (!mtd || section < 0)
+ return -EINVAL;
+
+ if (!mtd->ooblayout || !mtd->ooblayout->free)
+ return -ENOTSUPP;
+
+ return mtd->ooblayout->free(mtd, section, oobfree);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_free);
+
+/**
+ * mtd_ooblayout_find_region - Find the region attached to a specific byte
+ * @mtd: mtd info structure
+ * @byte: the byte we are searching for
+ * @sectionp: pointer where the section id will be stored
+ * @oobregion: used to retrieve the ECC position
+ * @iter: iterator function. Should be either mtd_ooblayout_free or
+ * mtd_ooblayout_ecc depending on the region type you're searching for
+ *
+ * This function returns the section id and oobregion information of a
+ * specific byte. For example, say you want to know where the 4th ECC byte is
+ * stored, you'll use:
+ *
+ * mtd_ooblayout_find_region(mtd, 3, &section, &oobregion, mtd_ooblayout_ecc);
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+static int mtd_ooblayout_find_region(struct mtd_info *mtd, int byte,
+ int *sectionp, struct mtd_oob_region *oobregion,
+ int (*iter)(struct mtd_info *,
+ int section,
+ struct mtd_oob_region *oobregion))
+{
+ int pos = 0, ret, section = 0;
+
+ memset(oobregion, 0, sizeof(*oobregion));
+
+ while (1) {
+ ret = iter(mtd, section, oobregion);
+ if (ret)
+ return ret;
+
+ if (pos + oobregion->length > byte)
+ break;
+
+ pos += oobregion->length;
+ section++;
+ }
+
+ /*
+ * Adjust region info to make it start at the beginning at the
+ * 'start' ECC byte.
+ */
+ oobregion->offset += byte - pos;
+ oobregion->length -= byte - pos;
+ *sectionp = section;
+
+ return 0;
+}
+
+/**
+ * mtd_ooblayout_find_eccregion - Find the ECC region attached to a specific
+ * ECC byte
+ * @mtd: mtd info structure
+ * @eccbyte: the byte we are searching for
+ * @sectionp: pointer where the section id will be stored
+ * @oobregion: OOB region information
+ *
+ * Works like mtd_ooblayout_find_region() except it searches for a specific ECC
+ * byte.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_find_eccregion(struct mtd_info *mtd, int eccbyte,
+ int *section,
+ struct mtd_oob_region *oobregion)
+{
+ return mtd_ooblayout_find_region(mtd, eccbyte, section, oobregion,
+ mtd_ooblayout_ecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_find_eccregion);
+
+/**
+ * mtd_ooblayout_get_bytes - Extract OOB bytes from the oob buffer
+ * @mtd: mtd info structure
+ * @buf: destination buffer to store OOB bytes
+ * @oobbuf: OOB buffer
+ * @start: first byte to retrieve
+ * @nbytes: number of bytes to retrieve
+ * @iter: section iterator
+ *
+ * Extract bytes attached to a specific category (ECC or free)
+ * from the OOB buffer and copy them into buf.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+static int mtd_ooblayout_get_bytes(struct mtd_info *mtd, u8 *buf,
+ const u8 *oobbuf, int start, int nbytes,
+ int (*iter)(struct mtd_info *,
+ int section,
+ struct mtd_oob_region *oobregion))
+{
+ struct mtd_oob_region oobregion;
+ int section, ret;
+
+ ret = mtd_ooblayout_find_region(mtd, start, &section,
+ &oobregion, iter);
+
+ while (!ret) {
+ int cnt;
+
+ cnt = min_t(int, nbytes, oobregion.length);
+ memcpy(buf, oobbuf + oobregion.offset, cnt);
+ buf += cnt;
+ nbytes -= cnt;
+
+ if (!nbytes)
+ break;
+
+ ret = iter(mtd, ++section, &oobregion);
+ }
+
+ return ret;
+}
+
+/**
+ * mtd_ooblayout_set_bytes - put OOB bytes into the oob buffer
+ * @mtd: mtd info structure
+ * @buf: source buffer to get OOB bytes from
+ * @oobbuf: OOB buffer
+ * @start: first OOB byte to set
+ * @nbytes: number of OOB bytes to set
+ * @iter: section iterator
+ *
+ * Fill the OOB buffer with data provided in buf. The category (ECC or free)
+ * is selected by passing the appropriate iterator.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+static int mtd_ooblayout_set_bytes(struct mtd_info *mtd, const u8 *buf,
+ u8 *oobbuf, int start, int nbytes,
+ int (*iter)(struct mtd_info *,
+ int section,
+ struct mtd_oob_region *oobregion))
+{
+ struct mtd_oob_region oobregion;
+ int section, ret;
+
+ ret = mtd_ooblayout_find_region(mtd, start, &section,
+ &oobregion, iter);
+
+ while (!ret) {
+ int cnt;
+
+ cnt = min_t(int, nbytes, oobregion.length);
+ memcpy(oobbuf + oobregion.offset, buf, cnt);
+ buf += cnt;
+ nbytes -= cnt;
+
+ if (!nbytes)
+ break;
+
+ ret = iter(mtd, ++section, &oobregion);
+ }
+
+ return ret;
+}
+
+/**
+ * mtd_ooblayout_count_bytes - count the number of bytes in a OOB category
+ * @mtd: mtd info structure
+ * @iter: category iterator
+ *
+ * Count the number of bytes in a given category.
+ *
+ * Returns a positive value on success, a negative error code otherwise.
+ */
+static int mtd_ooblayout_count_bytes(struct mtd_info *mtd,
+ int (*iter)(struct mtd_info *,
+ int section,
+ struct mtd_oob_region *oobregion))
+{
+ struct mtd_oob_region oobregion;
+ int section = 0, ret, nbytes = 0;
+
+ while (1) {
+ ret = iter(mtd, section++, &oobregion);
+ if (ret) {
+ if (ret == -ERANGE)
+ ret = nbytes;
+ break;
+ }
+
+ nbytes += oobregion.length;
+ }
+
+ return ret;
+}
+
+/**
+ * mtd_ooblayout_get_eccbytes - extract ECC bytes from the oob buffer
+ * @mtd: mtd info structure
+ * @eccbuf: destination buffer to store ECC bytes
+ * @oobbuf: OOB buffer
+ * @start: first ECC byte to retrieve
+ * @nbytes: number of ECC bytes to retrieve
+ *
+ * Works like mtd_ooblayout_get_bytes(), except it acts on ECC bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_get_eccbytes(struct mtd_info *mtd, u8 *eccbuf,
+ const u8 *oobbuf, int start, int nbytes)
+{
+ return mtd_ooblayout_get_bytes(mtd, eccbuf, oobbuf, start, nbytes,
+ mtd_ooblayout_ecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_get_eccbytes);
+
+/**
+ * mtd_ooblayout_set_eccbytes - set ECC bytes into the oob buffer
+ * @mtd: mtd info structure
+ * @eccbuf: source buffer to get ECC bytes from
+ * @oobbuf: OOB buffer
+ * @start: first ECC byte to set
+ * @nbytes: number of ECC bytes to set
+ *
+ * Works like mtd_ooblayout_set_bytes(), except it acts on ECC bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_set_eccbytes(struct mtd_info *mtd, const u8 *eccbuf,
+ u8 *oobbuf, int start, int nbytes)
+{
+ return mtd_ooblayout_set_bytes(mtd, eccbuf, oobbuf, start, nbytes,
+ mtd_ooblayout_ecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_set_eccbytes);
+
+/**
+ * mtd_ooblayout_get_databytes - extract data bytes from the oob buffer
+ * @mtd: mtd info structure
+ * @databuf: destination buffer to store ECC bytes
+ * @oobbuf: OOB buffer
+ * @start: first ECC byte to retrieve
+ * @nbytes: number of ECC bytes to retrieve
+ *
+ * Works like mtd_ooblayout_get_bytes(), except it acts on free bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_get_databytes(struct mtd_info *mtd, u8 *databuf,
+ const u8 *oobbuf, int start, int nbytes)
+{
+ return mtd_ooblayout_get_bytes(mtd, databuf, oobbuf, start, nbytes,
+ mtd_ooblayout_free);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_get_databytes);
+
+/**
+ * mtd_ooblayout_get_eccbytes - set data bytes into the oob buffer
+ * @mtd: mtd info structure
+ * @eccbuf: source buffer to get data bytes from
+ * @oobbuf: OOB buffer
+ * @start: first ECC byte to set
+ * @nbytes: number of ECC bytes to set
+ *
+ * Works like mtd_ooblayout_get_bytes(), except it acts on free bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_set_databytes(struct mtd_info *mtd, const u8 *databuf,
+ u8 *oobbuf, int start, int nbytes)
+{
+ return mtd_ooblayout_set_bytes(mtd, databuf, oobbuf, start, nbytes,
+ mtd_ooblayout_free);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_set_databytes);
+
+/**
+ * mtd_ooblayout_count_freebytes - count the number of free bytes in OOB
+ * @mtd: mtd info structure
+ *
+ * Works like mtd_ooblayout_count_bytes(), except it count free bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_count_freebytes(struct mtd_info *mtd)
+{
+ return mtd_ooblayout_count_bytes(mtd, mtd_ooblayout_free);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_count_freebytes);
+
+/**
+ * mtd_ooblayout_count_freebytes - count the number of ECC bytes in OOB
+ * @mtd: mtd info structure
+ *
+ * Works like mtd_ooblayout_count_bytes(), except it count ECC bytes.
+ *
+ * Returns zero on success, a negative error code otherwise.
+ */
+int mtd_ooblayout_count_eccbytes(struct mtd_info *mtd)
+{
+ return mtd_ooblayout_count_bytes(mtd, mtd_ooblayout_ecc);
+}
+EXPORT_SYMBOL_GPL(mtd_ooblayout_count_eccbytes);
+
/*
* Method to access the protection register area, present in some flash
* devices. The user data is one time programmable but the factory data is read
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 75023dc06b..47ec43500c 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -23,17 +23,6 @@ config NAND_DENALI_DT
Enable the driver for NAND flash on platforms using a Denali NAND
controller as a DT device.
-config SYS_NAND_DENALI_64BIT
- bool "Use 64-bit variant of Denali NAND controller"
- depends on NAND_DENALI
- help
- The Denali NAND controller IP has some variations in terms of
- the bus interface. The DMA setup sequence is completely differenct
- between 32bit / 64bit AXI bus variants.
-
- If your Denali NAND controller is the 64-bit variant, say Y.
- Otherwise (32 bit), say N.
-
config NAND_DENALI_SPARE_AREA_SKIP_BYTES
int "Number of bytes skipped in OOB area"
depends on NAND_DENALI
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index 2a01fd34e9..65104c6cf4 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -358,13 +358,12 @@ static struct nand_ecclayout nand_keystone_rbl_4bit_layout_oobfirst = {
* @buf: the data to write
* @oob_required: must write chip->oob_poi to OOB
* @page: page number to write
- * @cached: cached programming
* @raw: use _raw version of write_page
*/
static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip,
uint32_t offset, int data_len,
const uint8_t *buf, int oob_required,
- int page, int cached, int raw)
+ int page, int raw)
{
int status;
int ret = 0;
@@ -395,13 +394,6 @@ static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip,
chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
status = chip->waitfunc(mtd, chip);
- /*
- * See if operation failed and additional status checks are
- * available.
- */
- if ((status & NAND_STATUS_FAIL) && (chip->errstat))
- status = chip->errstat(mtd, chip, FL_WRITING, status, page);
-
if (status & NAND_STATUS_FAIL) {
ret = -EIO;
goto err;
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index 54718f418c..b116d3a17c 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@@ -9,1144 +9,1076 @@
#include <common.h>
#include <malloc.h>
#include <nand.h>
+#include <dm.h>
+#include <linux/bitfield.h>
+#include <linux/dma-direction.h>
#include <linux/errno.h>
#include <linux/io.h>
#include "denali.h"
-#define NAND_DEFAULT_TIMINGS -1
-
-static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
-
-/*
- * We define a macro here that combines all interrupts this driver uses into
- * a single constant value, for convenience.
- */
-#define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \
- INTR_STATUS__ECC_TRANSACTION_DONE | \
- INTR_STATUS__ECC_ERR | \
- INTR_STATUS__PROGRAM_FAIL | \
- INTR_STATUS__LOAD_COMP | \
- INTR_STATUS__PROGRAM_COMP | \
- INTR_STATUS__TIME_OUT | \
- INTR_STATUS__ERASE_FAIL | \
- INTR_STATUS__RST_COMP | \
- INTR_STATUS__ERASE_COMP | \
- INTR_STATUS__ECC_UNCOR_ERR | \
- INTR_STATUS__INT_ACT | \
- INTR_STATUS__LOCKED_BLK)
+static dma_addr_t dma_map_single(void *dev, void *ptr, size_t size,
+ enum dma_data_direction dir)
+{
+ unsigned long addr = (unsigned long)ptr;
-/*
- * indicates whether or not the internal value for the flash bank is
- * valid or not
- */
-#define CHIP_SELECT_INVALID -1
+ if (dir == DMA_FROM_DEVICE)
+ invalidate_dcache_range(addr, addr + size);
+ else
+ flush_dcache_range(addr, addr + size);
-#define SUPPORT_8BITECC 1
+ return addr;
+}
-/*
- * this macro allows us to convert from an MTD structure to our own
- * device context (denali) structure.
- */
-static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
+static void dma_unmap_single(void *dev, dma_addr_t addr, size_t size,
+ enum dma_data_direction dir)
{
- return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand);
+ if (dir != DMA_TO_DEVICE)
+ invalidate_dcache_range(addr, addr + size);
}
-/*
- * These constants are defined by the driver to enable common driver
- * configuration options.
- */
-#define SPARE_ACCESS 0x41
-#define MAIN_ACCESS 0x42
-#define MAIN_SPARE_ACCESS 0x43
-#define PIPELINE_ACCESS 0x2000
-
-#define DENALI_UNLOCK_START 0x10
-#define DENALI_UNLOCK_END 0x11
-#define DENALI_LOCK 0x21
-#define DENALI_LOCK_TIGHT 0x31
-#define DENALI_BUFFER_LOAD 0x60
-#define DENALI_BUFFER_WRITE 0x62
-
-#define DENALI_READ 0
-#define DENALI_WRITE 0x100
-
-/* types of device accesses. We can issue commands and get status */
-#define COMMAND_CYCLE 0
-#define ADDR_CYCLE 1
-#define STATUS_CYCLE 2
-
-/*
- * this is a helper macro that allows us to
- * format the bank into the proper bits for the controller
- */
-#define BANK(x) ((x) << 24)
-
-/* Interrupts are cleared by writing a 1 to the appropriate status bit */
-static inline void clear_interrupt(struct denali_nand_info *denali,
- uint32_t irq_mask)
+static int dma_mapping_error(void *dev, dma_addr_t addr)
{
- uint32_t intr_status_reg;
-
- intr_status_reg = INTR_STATUS(denali->flash_bank);
-
- writel(irq_mask, denali->flash_reg + intr_status_reg);
+ return 0;
}
-static uint32_t read_interrupt_status(struct denali_nand_info *denali)
-{
- uint32_t intr_status_reg;
+#define DENALI_NAND_NAME "denali-nand"
- intr_status_reg = INTR_STATUS(denali->flash_bank);
+/* for Indexed Addressing */
+#define DENALI_INDEXED_CTRL 0x00
+#define DENALI_INDEXED_DATA 0x10
- return readl(denali->flash_reg + intr_status_reg);
-}
+#define DENALI_MAP00 (0 << 26) /* direct access to buffer */
+#define DENALI_MAP01 (1 << 26) /* read/write pages in PIO */
+#define DENALI_MAP10 (2 << 26) /* high-level control plane */
+#define DENALI_MAP11 (3 << 26) /* direct controller access */
-static void clear_interrupts(struct denali_nand_info *denali)
-{
- uint32_t status;
+/* MAP11 access cycle type */
+#define DENALI_MAP11_CMD ((DENALI_MAP11) | 0) /* command cycle */
+#define DENALI_MAP11_ADDR ((DENALI_MAP11) | 1) /* address cycle */
+#define DENALI_MAP11_DATA ((DENALI_MAP11) | 2) /* data cycle */
- status = read_interrupt_status(denali);
- clear_interrupt(denali, status);
+/* MAP10 commands */
+#define DENALI_ERASE 0x01
- denali->irq_status = 0;
-}
+#define DENALI_BANK(denali) ((denali)->active_bank << 24)
-static void denali_irq_enable(struct denali_nand_info *denali,
- uint32_t int_mask)
-{
- int i;
+#define DENALI_INVALID_BANK -1
+#define DENALI_NR_BANKS 4
- for (i = 0; i < denali->max_banks; ++i)
- writel(int_mask, denali->flash_reg + INTR_EN(i));
-}
+/*
+ * The bus interface clock, clk_x, is phase aligned with the core clock. The
+ * clk_x is an integral multiple N of the core clk. The value N is configured
+ * at IP delivery time, and its available value is 4, 5, or 6. We need to align
+ * to the largest value to make it work with any possible configuration.
+ */
+#define DENALI_CLK_X_MULT 6
-static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
+static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
{
- unsigned long timeout = 1000000;
- uint32_t intr_status;
-
- do {
- intr_status = read_interrupt_status(denali) & DENALI_IRQ_ALL;
- if (intr_status & irq_mask) {
- denali->irq_status &= ~irq_mask;
- /* our interrupt was detected */
- break;
- }
- udelay(1);
- timeout--;
- } while (timeout != 0);
-
- if (timeout == 0) {
- /* timeout */
- printf("Denali timeout with interrupt status %08x\n",
- read_interrupt_status(denali));
- intr_status = 0;
- }
- return intr_status;
+ return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand);
}
/*
- * Certain operations for the denali NAND controller use an indexed mode to
- * read/write data. The operation is performed by writing the address value
- * of the command to the device memory followed by the data. This function
- * abstracts this common operation.
+ * Direct Addressing - the slave address forms the control information (command
+ * type, bank, block, and page address). The slave data is the actual data to
+ * be transferred. This mode requires 28 bits of address region allocated.
*/
-static void index_addr(struct denali_nand_info *denali,
- uint32_t address, uint32_t data)
+static u32 denali_direct_read(struct denali_nand_info *denali, u32 addr)
{
- writel(address, denali->flash_mem + INDEX_CTRL_REG);
- writel(data, denali->flash_mem + INDEX_DATA_REG);
+ return ioread32(denali->host + addr);
}
-/* Perform an indexed read of the device */
-static void index_addr_read_data(struct denali_nand_info *denali,
- uint32_t address, uint32_t *pdata)
+static void denali_direct_write(struct denali_nand_info *denali, u32 addr,
+ u32 data)
{
- writel(address, denali->flash_mem + INDEX_CTRL_REG);
- *pdata = readl(denali->flash_mem + INDEX_DATA_REG);
+ iowrite32(data, denali->host + addr);
}
/*
- * We need to buffer some data for some of the NAND core routines.
- * The operations manage buffering that data.
+ * Indexed Addressing - address translation module intervenes in passing the
+ * control information. This mode reduces the required address range. The
+ * control information and transferred data are latched by the registers in
+ * the translation module.
*/
-static void reset_buf(struct denali_nand_info *denali)
+static u32 denali_indexed_read(struct denali_nand_info *denali, u32 addr)
{
- denali->buf.head = 0;
- denali->buf.tail = 0;
+ iowrite32(addr, denali->host + DENALI_INDEXED_CTRL);
+ return ioread32(denali->host + DENALI_INDEXED_DATA);
}
-static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte)
+static void denali_indexed_write(struct denali_nand_info *denali, u32 addr,
+ u32 data)
{
- denali->buf.buf[denali->buf.tail++] = byte;
+ iowrite32(addr, denali->host + DENALI_INDEXED_CTRL);
+ iowrite32(data, denali->host + DENALI_INDEXED_DATA);
}
-/* resets a specific device connected to the core */
-static void reset_bank(struct denali_nand_info *denali)
+/*
+ * Use the configuration feature register to determine the maximum number of
+ * banks that the hardware supports.
+ */
+static void denali_detect_max_banks(struct denali_nand_info *denali)
{
- uint32_t irq_status;
- uint32_t irq_mask = INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT;
-
- clear_interrupts(denali);
+ uint32_t features = ioread32(denali->reg + FEATURES);
- writel(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET);
+ denali->max_banks = 1 << FIELD_GET(FEATURES__N_BANKS, features);
- irq_status = wait_for_irq(denali, irq_mask);
- if (irq_status & INTR_STATUS__TIME_OUT)
- debug("reset bank failed.\n");
+ /* the encoding changed from rev 5.0 to 5.1 */
+ if (denali->revision < 0x0501)
+ denali->max_banks <<= 1;
}
-/* Reset the flash controller */
-static uint32_t denali_nand_reset(struct denali_nand_info *denali)
+static void __maybe_unused denali_enable_irq(struct denali_nand_info *denali)
{
int i;
- for (i = 0; i < denali->max_banks; i++)
- writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
- denali->flash_reg + INTR_STATUS(i));
+ for (i = 0; i < DENALI_NR_BANKS; i++)
+ iowrite32(U32_MAX, denali->reg + INTR_EN(i));
+ iowrite32(GLOBAL_INT_EN_FLAG, denali->reg + GLOBAL_INT_ENABLE);
+}
- for (i = 0; i < denali->max_banks; i++) {
- writel(1 << i, denali->flash_reg + DEVICE_RESET);
- while (!(readl(denali->flash_reg + INTR_STATUS(i)) &
- (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT)))
- if (readl(denali->flash_reg + INTR_STATUS(i)) &
- INTR_STATUS__TIME_OUT)
- debug("NAND Reset operation timed out on bank"
- " %d\n", i);
- }
+static void __maybe_unused denali_disable_irq(struct denali_nand_info *denali)
+{
+ int i;
- for (i = 0; i < denali->max_banks; i++)
- writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
- denali->flash_reg + INTR_STATUS(i));
+ for (i = 0; i < DENALI_NR_BANKS; i++)
+ iowrite32(0, denali->reg + INTR_EN(i));
+ iowrite32(0, denali->reg + GLOBAL_INT_ENABLE);
+}
- return 0;
+static void denali_clear_irq(struct denali_nand_info *denali,
+ int bank, uint32_t irq_status)
+{
+ /* write one to clear bits */
+ iowrite32(irq_status, denali->reg + INTR_STATUS(bank));
}
-/*
- * this routine calculates the ONFI timing values for a given mode and
- * programs the clocking register accordingly. The mode is determined by
- * the get_onfi_nand_para routine.
- */
-static void nand_onfi_timing_set(struct denali_nand_info *denali,
- uint16_t mode)
+static void denali_clear_irq_all(struct denali_nand_info *denali)
{
- uint32_t trea[6] = {40, 30, 25, 20, 20, 16};
- uint32_t trp[6] = {50, 25, 17, 15, 12, 10};
- uint32_t treh[6] = {30, 15, 15, 10, 10, 7};
- uint32_t trc[6] = {100, 50, 35, 30, 25, 20};
- uint32_t trhoh[6] = {0, 15, 15, 15, 15, 15};
- uint32_t trloh[6] = {0, 0, 0, 0, 5, 5};
- uint32_t tcea[6] = {100, 45, 30, 25, 25, 25};
- uint32_t tadl[6] = {200, 100, 100, 100, 70, 70};
- uint32_t trhw[6] = {200, 100, 100, 100, 100, 100};
- uint32_t trhz[6] = {200, 100, 100, 100, 100, 100};
- uint32_t twhr[6] = {120, 80, 80, 60, 60, 60};
- uint32_t tcs[6] = {70, 35, 25, 25, 20, 15};
-
- uint32_t data_invalid_rhoh, data_invalid_rloh, data_invalid;
- uint32_t dv_window = 0;
- uint32_t en_lo, en_hi;
- uint32_t acc_clks;
- uint32_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
-
- en_lo = DIV_ROUND_UP(trp[mode], CLK_X);
- en_hi = DIV_ROUND_UP(treh[mode], CLK_X);
- if ((en_hi * CLK_X) < (treh[mode] + 2))
- en_hi++;
-
- if ((en_lo + en_hi) * CLK_X < trc[mode])
- en_lo += DIV_ROUND_UP((trc[mode] - (en_lo + en_hi) * CLK_X),
- CLK_X);
-
- if ((en_lo + en_hi) < CLK_MULTI)
- en_lo += CLK_MULTI - en_lo - en_hi;
-
- while (dv_window < 8) {
- data_invalid_rhoh = en_lo * CLK_X + trhoh[mode];
-
- data_invalid_rloh = (en_lo + en_hi) * CLK_X + trloh[mode];
-
- data_invalid = data_invalid_rhoh < data_invalid_rloh ?
- data_invalid_rhoh : data_invalid_rloh;
-
- dv_window = data_invalid - trea[mode];
-
- if (dv_window < 8)
- en_lo++;
- }
+ int i;
- acc_clks = DIV_ROUND_UP(trea[mode], CLK_X);
+ for (i = 0; i < DENALI_NR_BANKS; i++)
+ denali_clear_irq(denali, i, U32_MAX);
+}
- while (acc_clks * CLK_X - trea[mode] < 3)
- acc_clks++;
+static void __denali_check_irq(struct denali_nand_info *denali)
+{
+ uint32_t irq_status;
+ int i;
- if (data_invalid - acc_clks * CLK_X < 2)
- debug("%s, Line %d: Warning!\n", __FILE__, __LINE__);
+ for (i = 0; i < DENALI_NR_BANKS; i++) {
+ irq_status = ioread32(denali->reg + INTR_STATUS(i));
+ denali_clear_irq(denali, i, irq_status);
- addr_2_data = DIV_ROUND_UP(tadl[mode], CLK_X);
- re_2_we = DIV_ROUND_UP(trhw[mode], CLK_X);
- re_2_re = DIV_ROUND_UP(trhz[mode], CLK_X);
- we_2_re = DIV_ROUND_UP(twhr[mode], CLK_X);
- cs_cnt = DIV_ROUND_UP((tcs[mode] - trp[mode]), CLK_X);
- if (cs_cnt == 0)
- cs_cnt = 1;
+ if (i != denali->active_bank)
+ continue;
- if (tcea[mode]) {
- while (cs_cnt * CLK_X + trea[mode] < tcea[mode])
- cs_cnt++;
+ denali->irq_status |= irq_status;
}
+}
- /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */
- if (readl(denali->flash_reg + MANUFACTURER_ID) == 0 &&
- readl(denali->flash_reg + DEVICE_ID) == 0x88)
- acc_clks = 6;
-
- writel(acc_clks, denali->flash_reg + ACC_CLKS);
- writel(re_2_we, denali->flash_reg + RE_2_WE);
- writel(re_2_re, denali->flash_reg + RE_2_RE);
- writel(we_2_re, denali->flash_reg + WE_2_RE);
- writel(addr_2_data, denali->flash_reg + ADDR_2_DATA);
- writel(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
- writel(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
- writel(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
+static void denali_reset_irq(struct denali_nand_info *denali)
+{
+ denali->irq_status = 0;
+ denali->irq_mask = 0;
}
-/* queries the NAND device to see what ONFI modes it supports. */
-static uint32_t get_onfi_nand_para(struct denali_nand_info *denali)
+static uint32_t denali_wait_for_irq(struct denali_nand_info *denali,
+ uint32_t irq_mask)
{
- int i;
+ unsigned long time_left = 1000000;
- /*
- * we needn't to do a reset here because driver has already
- * reset all the banks before
- */
- if (!(readl(denali->flash_reg + ONFI_TIMING_MODE) &
- ONFI_TIMING_MODE__VALUE))
- return -EIO;
+ while (time_left) {
+ __denali_check_irq(denali);
- for (i = 5; i > 0; i--) {
- if (readl(denali->flash_reg + ONFI_TIMING_MODE) &
- (0x01 << i))
- break;
+ if (irq_mask & denali->irq_status)
+ return denali->irq_status;
+ udelay(1);
+ time_left--;
}
- nand_onfi_timing_set(denali, i);
-
- /*
- * By now, all the ONFI devices we know support the page cache
- * rw feature. So here we enable the pipeline_rw_ahead feature
- */
+ if (!time_left) {
+ dev_err(denali->dev, "timeout while waiting for irq 0x%x\n",
+ irq_mask);
+ return 0;
+ }
- return 0;
+ return denali->irq_status;
}
-static void get_samsung_nand_para(struct denali_nand_info *denali,
- uint8_t device_id)
+static uint32_t denali_check_irq(struct denali_nand_info *denali)
{
- if (device_id == 0xd3) { /* Samsung K9WAG08U1A */
- /* Set timing register values according to datasheet */
- writel(5, denali->flash_reg + ACC_CLKS);
- writel(20, denali->flash_reg + RE_2_WE);
- writel(12, denali->flash_reg + WE_2_RE);
- writel(14, denali->flash_reg + ADDR_2_DATA);
- writel(3, denali->flash_reg + RDWR_EN_LO_CNT);
- writel(2, denali->flash_reg + RDWR_EN_HI_CNT);
- writel(2, denali->flash_reg + CS_SETUP_CNT);
- }
+ __denali_check_irq(denali);
+
+ return denali->irq_status;
}
-static void get_toshiba_nand_para(struct denali_nand_info *denali)
+static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
- uint32_t tmp;
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
+ int i;
- /*
- * Workaround to fix a controller bug which reports a wrong
- * spare area size for some kind of Toshiba NAND device
- */
- if ((readl(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
- (readl(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {
- writel(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
- tmp = readl(denali->flash_reg + DEVICES_CONNECTED) *
- readl(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
- writel(tmp, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
- }
+ for (i = 0; i < len; i++)
+ buf[i] = denali->host_read(denali, addr);
}
-static void get_hynix_nand_para(struct denali_nand_info *denali,
- uint8_t device_id)
+static void denali_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
{
- uint32_t main_size, spare_size;
-
- switch (device_id) {
- case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
- case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
- writel(128, denali->flash_reg + PAGES_PER_BLOCK);
- writel(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
- writel(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
- main_size = 4096 *
- readl(denali->flash_reg + DEVICES_CONNECTED);
- spare_size = 224 *
- readl(denali->flash_reg + DEVICES_CONNECTED);
- writel(main_size, denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
- writel(spare_size, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
- writel(0, denali->flash_reg + DEVICE_WIDTH);
- break;
- default:
- debug("Spectra: Unknown Hynix NAND (Device ID: 0x%x).\n"
- "Will use default parameter values instead.\n",
- device_id);
- }
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
+ int i;
+
+ for (i = 0; i < len; i++)
+ denali->host_write(denali, addr, buf[i]);
}
-/*
- * determines how many NAND chips are connected to the controller. Note for
- * Intel CE4100 devices we don't support more than one device.
- */
-static void find_valid_banks(struct denali_nand_info *denali)
+static void denali_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
{
- uint32_t id[denali->max_banks];
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
+ uint16_t *buf16 = (uint16_t *)buf;
int i;
- denali->total_used_banks = 1;
- for (i = 0; i < denali->max_banks; i++) {
- index_addr(denali, MODE_11 | (i << 24) | 0, 0x90);
- index_addr(denali, MODE_11 | (i << 24) | 1, 0);
- index_addr_read_data(denali, MODE_11 | (i << 24) | 2, &id[i]);
+ for (i = 0; i < len / 2; i++)
+ buf16[i] = denali->host_read(denali, addr);
+}
- if (i == 0) {
- if (!(id[i] & 0x0ff))
- break;
- } else {
- if ((id[i] & 0x0ff) == (id[0] & 0x0ff))
- denali->total_used_banks++;
- else
- break;
- }
- }
+static void denali_write_buf16(struct mtd_info *mtd, const uint8_t *buf,
+ int len)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
+ const uint16_t *buf16 = (const uint16_t *)buf;
+ int i;
+
+ for (i = 0; i < len / 2; i++)
+ denali->host_write(denali, addr, buf16[i]);
}
-/*
- * Use the configuration feature register to determine the maximum number of
- * banks that the hardware supports.
- */
-static void detect_max_banks(struct denali_nand_info *denali)
+static uint8_t denali_read_byte(struct mtd_info *mtd)
{
- uint32_t features = ioread32(denali->flash_reg + FEATURES);
+ uint8_t byte;
- denali->max_banks = 1 << (features & FEATURES__N_BANKS);
+ denali_read_buf(mtd, &byte, 1);
- /* the encoding changed from rev 5.0 to 5.1 */
- if (denali->revision < 0x0501)
- denali->max_banks <<= 1;
+ return byte;
}
-static void detect_partition_feature(struct denali_nand_info *denali)
+static void denali_write_byte(struct mtd_info *mtd, uint8_t byte)
{
- /*
- * For MRST platform, denali->fwblks represent the
- * number of blocks firmware is taken,
- * FW is in protect partition and MTD driver has no
- * permission to access it. So let driver know how many
- * blocks it can't touch.
- */
- if (readl(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {
- if ((readl(denali->flash_reg + PERM_SRC_ID(1)) &
- PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) {
- denali->fwblks =
- ((readl(denali->flash_reg + MIN_MAX_BANK(1)) &
- MIN_MAX_BANK__MIN_VALUE) *
- denali->blksperchip)
- +
- (readl(denali->flash_reg + MIN_BLK_ADDR(1)) &
- MIN_BLK_ADDR__VALUE);
- } else {
- denali->fwblks = SPECTRA_START_BLOCK;
- }
- } else {
- denali->fwblks = SPECTRA_START_BLOCK;
- }
+ denali_write_buf(mtd, &byte, 1);
}
-static uint32_t denali_nand_timing_set(struct denali_nand_info *denali)
+static uint16_t denali_read_word(struct mtd_info *mtd)
{
- uint32_t id_bytes[8], addr;
- uint8_t maf_id, device_id;
- int i;
+ uint16_t word;
- /*
- * Use read id method to get device ID and other params.
- * For some NAND chips, controller can't report the correct
- * device ID by reading from DEVICE_ID register
- */
- addr = MODE_11 | BANK(denali->flash_bank);
- index_addr(denali, addr | 0, 0x90);
- index_addr(denali, addr | 1, 0);
- for (i = 0; i < 8; i++)
- index_addr_read_data(denali, addr | 2, &id_bytes[i]);
- maf_id = id_bytes[0];
- device_id = id_bytes[1];
-
- if (readl(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
- ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */
- if (get_onfi_nand_para(denali))
- return -EIO;
- } else if (maf_id == 0xEC) { /* Samsung NAND */
- get_samsung_nand_para(denali, device_id);
- } else if (maf_id == 0x98) { /* Toshiba NAND */
- get_toshiba_nand_para(denali);
- } else if (maf_id == 0xAD) { /* Hynix NAND */
- get_hynix_nand_para(denali, device_id);
- }
+ denali_read_buf16(mtd, (uint8_t *)&word, 2);
- find_valid_banks(denali);
+ return word;
+}
- detect_partition_feature(denali);
+static void denali_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ uint32_t type;
+
+ if (ctrl & NAND_CLE)
+ type = DENALI_MAP11_CMD;
+ else if (ctrl & NAND_ALE)
+ type = DENALI_MAP11_ADDR;
+ else
+ return;
/*
- * If the user specified to override the default timings
- * with a specific ONFI mode, we apply those changes here.
+ * Some commands are followed by chip->dev_ready or chip->waitfunc.
+ * irq_status must be cleared here to catch the R/B# interrupt later.
*/
- if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
- nand_onfi_timing_set(denali, onfi_timing_mode);
+ if (ctrl & NAND_CTRL_CHANGE)
+ denali_reset_irq(denali);
- return 0;
+ denali->host_write(denali, DENALI_BANK(denali) | type, dat);
}
-/*
- * validation function to verify that the controlling software is making
- * a valid request
- */
-static inline bool is_flash_bank_valid(int flash_bank)
-{
- return flash_bank >= 0 && flash_bank < 4;
-}
-
-static void denali_irq_init(struct denali_nand_info *denali)
+static int denali_dev_ready(struct mtd_info *mtd)
{
- uint32_t int_mask;
- int i;
-
- /* Disable global interrupts */
- writel(0, denali->flash_reg + GLOBAL_INT_ENABLE);
-
- int_mask = DENALI_IRQ_ALL;
-
- /* Clear all status bits */
- for (i = 0; i < denali->max_banks; ++i)
- writel(0xFFFF, denali->flash_reg + INTR_STATUS(i));
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
- denali_irq_enable(denali, int_mask);
+ return !!(denali_check_irq(denali) & INTR__INT_ACT);
}
-/*
- * This helper function setups the registers for ECC and whether or not
- * the spare area will be transferred.
- */
-static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
- bool transfer_spare)
+static int denali_check_erased_page(struct mtd_info *mtd,
+ struct nand_chip *chip, uint8_t *buf,
+ unsigned long uncor_ecc_flags,
+ unsigned int max_bitflips)
{
- int ecc_en_flag, transfer_spare_flag;
+ uint8_t *ecc_code = chip->buffers->ecccode;
+ int ecc_steps = chip->ecc.steps;
+ int ecc_size = chip->ecc.size;
+ int ecc_bytes = chip->ecc.bytes;
+ int i, ret, stat;
+
+ ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
+ chip->ecc.total);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < ecc_steps; i++) {
+ if (!(uncor_ecc_flags & BIT(i)))
+ continue;
+
+ stat = nand_check_erased_ecc_chunk(buf, ecc_size,
+ ecc_code, ecc_bytes,
+ NULL, 0,
+ chip->ecc.strength);
+ if (stat < 0) {
+ mtd->ecc_stats.failed++;
+ } else {
+ mtd->ecc_stats.corrected += stat;
+ max_bitflips = max_t(unsigned int, max_bitflips, stat);
+ }
- /* set ECC, transfer spare bits if needed */
- ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;
- transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;
+ buf += ecc_size;
+ ecc_code += ecc_bytes;
+ }
- /* Enable spare area/ECC per user's request. */
- writel(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
- /* applicable for MAP01 only */
- writel(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG);
+ return max_bitflips;
}
-/*
- * sends a pipeline command operation to the controller. See the Denali NAND
- * controller's user guide for more information (section 4.2.3.6).
- */
-static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
- bool ecc_en, bool transfer_spare,
- int access_type, int op)
+static int denali_hw_ecc_fixup(struct mtd_info *mtd,
+ struct denali_nand_info *denali,
+ unsigned long *uncor_ecc_flags)
{
- uint32_t addr, cmd, irq_status;
- static uint32_t page_count = 1;
-
- setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ int bank = denali->active_bank;
+ uint32_t ecc_cor;
+ unsigned int max_bitflips;
- clear_interrupts(denali);
+ ecc_cor = ioread32(denali->reg + ECC_COR_INFO(bank));
+ ecc_cor >>= ECC_COR_INFO__SHIFT(bank);
- addr = BANK(denali->flash_bank) | denali->page;
+ if (ecc_cor & ECC_COR_INFO__UNCOR_ERR) {
+ /*
+ * This flag is set when uncorrectable error occurs at least in
+ * one ECC sector. We can not know "how many sectors", or
+ * "which sector(s)". We need erase-page check for all sectors.
+ */
+ *uncor_ecc_flags = GENMASK(chip->ecc.steps - 1, 0);
+ return 0;
+ }
- /* setup the acccess type */
- cmd = MODE_10 | addr;
- index_addr(denali, cmd, access_type);
+ max_bitflips = FIELD_GET(ECC_COR_INFO__MAX_ERRORS, ecc_cor);
- /* setup the pipeline command */
- index_addr(denali, cmd, 0x2000 | op | page_count);
+ /*
+ * The register holds the maximum of per-sector corrected bitflips.
+ * This is suitable for the return value of the ->read_page() callback.
+ * Unfortunately, we can not know the total number of corrected bits in
+ * the page. Increase the stats by max_bitflips. (compromised solution)
+ */
+ mtd->ecc_stats.corrected += max_bitflips;
- cmd = MODE_01 | addr;
- writel(cmd, denali->flash_mem + INDEX_CTRL_REG);
+ return max_bitflips;
+}
- if (op == DENALI_READ) {
- /* wait for command to be accepted */
- irq_status = wait_for_irq(denali, INTR_STATUS__LOAD_COMP);
+static int denali_sw_ecc_fixup(struct mtd_info *mtd,
+ struct denali_nand_info *denali,
+ unsigned long *uncor_ecc_flags, uint8_t *buf)
+{
+ unsigned int ecc_size = denali->nand.ecc.size;
+ unsigned int bitflips = 0;
+ unsigned int max_bitflips = 0;
+ uint32_t err_addr, err_cor_info;
+ unsigned int err_byte, err_sector, err_device;
+ uint8_t err_cor_value;
+ unsigned int prev_sector = 0;
+ uint32_t irq_status;
- if (irq_status == 0)
- return -EIO;
- }
+ denali_reset_irq(denali);
- return 0;
-}
+ do {
+ err_addr = ioread32(denali->reg + ECC_ERROR_ADDRESS);
+ err_sector = FIELD_GET(ECC_ERROR_ADDRESS__SECTOR, err_addr);
+ err_byte = FIELD_GET(ECC_ERROR_ADDRESS__OFFSET, err_addr);
+
+ err_cor_info = ioread32(denali->reg + ERR_CORRECTION_INFO);
+ err_cor_value = FIELD_GET(ERR_CORRECTION_INFO__BYTE,
+ err_cor_info);
+ err_device = FIELD_GET(ERR_CORRECTION_INFO__DEVICE,
+ err_cor_info);
+
+ /* reset the bitflip counter when crossing ECC sector */
+ if (err_sector != prev_sector)
+ bitflips = 0;
+
+ if (err_cor_info & ERR_CORRECTION_INFO__UNCOR) {
+ /*
+ * Check later if this is a real ECC error, or
+ * an erased sector.
+ */
+ *uncor_ecc_flags |= BIT(err_sector);
+ } else if (err_byte < ecc_size) {
+ /*
+ * If err_byte is larger than ecc_size, means error
+ * happened in OOB, so we ignore it. It's no need for
+ * us to correct it err_device is represented the NAND
+ * error bits are happened in if there are more than
+ * one NAND connected.
+ */
+ int offset;
+ unsigned int flips_in_byte;
+
+ offset = (err_sector * ecc_size + err_byte) *
+ denali->devs_per_cs + err_device;
+
+ /* correct the ECC error */
+ flips_in_byte = hweight8(buf[offset] ^ err_cor_value);
+ buf[offset] ^= err_cor_value;
+ mtd->ecc_stats.corrected += flips_in_byte;
+ bitflips += flips_in_byte;
+
+ max_bitflips = max(max_bitflips, bitflips);
+ }
-/* helper function that simply writes a buffer to the flash */
-static int write_data_to_flash_mem(struct denali_nand_info *denali,
- const uint8_t *buf, int len)
-{
- uint32_t *buf32;
- int i;
+ prev_sector = err_sector;
+ } while (!(err_cor_info & ERR_CORRECTION_INFO__LAST_ERR));
/*
- * verify that the len is a multiple of 4.
- * see comment in read_data_from_flash_mem()
+ * Once handle all ECC errors, controller will trigger an
+ * ECC_TRANSACTION_DONE interrupt.
*/
- BUG_ON((len % 4) != 0);
+ irq_status = denali_wait_for_irq(denali, INTR__ECC_TRANSACTION_DONE);
+ if (!(irq_status & INTR__ECC_TRANSACTION_DONE))
+ return -EIO;
- /* write the data to the flash memory */
- buf32 = (uint32_t *)buf;
- for (i = 0; i < len / 4; i++)
- writel(*buf32++, denali->flash_mem + INDEX_DATA_REG);
- return i * 4; /* intent is to return the number of bytes read */
+ return max_bitflips;
}
-/* helper function that simply reads a buffer from the flash */
-static int read_data_from_flash_mem(struct denali_nand_info *denali,
- uint8_t *buf, int len)
+static void denali_setup_dma64(struct denali_nand_info *denali,
+ dma_addr_t dma_addr, int page, int write)
{
- uint32_t *buf32;
- int i;
+ uint32_t mode;
+ const int page_count = 1;
- /*
- * we assume that len will be a multiple of 4, if not it would be nice
- * to know about it ASAP rather than have random failures...
- * This assumption is based on the fact that this function is designed
- * to be used to read flash pages, which are typically multiples of 4.
- */
- BUG_ON((len % 4) != 0);
+ mode = DENALI_MAP10 | DENALI_BANK(denali) | page;
- /* transfer the data from the flash */
- buf32 = (uint32_t *)buf;
- for (i = 0; i < len / 4; i++)
- *buf32++ = readl(denali->flash_mem + INDEX_DATA_REG);
+ /* DMA is a three step process */
- return i * 4; /* intent is to return the number of bytes read */
-}
+ /*
+ * 1. setup transfer type, interrupt when complete,
+ * burst len = 64 bytes, the number of pages
+ */
+ denali->host_write(denali, mode,
+ 0x01002000 | (64 << 16) | (write << 8) | page_count);
-static void denali_mode_main_access(struct denali_nand_info *denali)
-{
- uint32_t addr, cmd;
+ /* 2. set memory low address */
+ denali->host_write(denali, mode, lower_32_bits(dma_addr));
- addr = BANK(denali->flash_bank) | denali->page;
- cmd = MODE_10 | addr;
- index_addr(denali, cmd, MAIN_ACCESS);
+ /* 3. set memory high address */
+ denali->host_write(denali, mode, upper_32_bits(dma_addr));
}
-static void denali_mode_main_spare_access(struct denali_nand_info *denali)
+static void denali_setup_dma32(struct denali_nand_info *denali,
+ dma_addr_t dma_addr, int page, int write)
{
- uint32_t addr, cmd;
+ uint32_t mode;
+ const int page_count = 1;
- addr = BANK(denali->flash_bank) | denali->page;
- cmd = MODE_10 | addr;
- index_addr(denali, cmd, MAIN_SPARE_ACCESS);
-}
+ mode = DENALI_MAP10 | DENALI_BANK(denali);
-/* writes OOB data to the device */
-static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
-{
- struct denali_nand_info *denali = mtd_to_denali(mtd);
- uint32_t irq_status;
- uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP |
- INTR_STATUS__PROGRAM_FAIL;
- int status = 0;
+ /* DMA is a four step process */
- denali->page = page;
+ /* 1. setup transfer type and # of pages */
+ denali->host_write(denali, mode | page,
+ 0x2000 | (write << 8) | page_count);
- if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
- DENALI_WRITE) == 0) {
- write_data_to_flash_mem(denali, buf, mtd->oobsize);
+ /* 2. set memory high address bits 23:8 */
+ denali->host_write(denali, mode | ((dma_addr >> 16) << 8), 0x2200);
- /* wait for operation to complete */
- irq_status = wait_for_irq(denali, irq_mask);
+ /* 3. set memory low address bits 23:8 */
+ denali->host_write(denali, mode | ((dma_addr & 0xffff) << 8), 0x2300);
- if (irq_status == 0) {
- dev_err(denali->dev, "OOB write failed\n");
- status = -EIO;
- }
- } else {
- printf("unable to send pipeline command\n");
- status = -EIO;
- }
- return status;
+ /* 4. interrupt when complete, burst len = 64 bytes */
+ denali->host_write(denali, mode | 0x14000, 0x2400);
}
-/* reads OOB data from the device */
-static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
+static int denali_pio_read(struct denali_nand_info *denali, void *buf,
+ size_t size, int page, int raw)
{
- struct denali_nand_info *denali = mtd_to_denali(mtd);
- uint32_t irq_mask = INTR_STATUS__LOAD_COMP;
- uint32_t irq_status, addr, cmd;
+ u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
+ uint32_t *buf32 = (uint32_t *)buf;
+ uint32_t irq_status, ecc_err_mask;
+ int i;
- denali->page = page;
+ if (denali->caps & DENALI_CAP_HW_ECC_FIXUP)
+ ecc_err_mask = INTR__ECC_UNCOR_ERR;
+ else
+ ecc_err_mask = INTR__ECC_ERR;
- if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
- DENALI_READ) == 0) {
- read_data_from_flash_mem(denali, buf, mtd->oobsize);
+ denali_reset_irq(denali);
- /*
- * wait for command to be accepted
- * can always use status0 bit as the
- * mask is identical for each bank.
- */
- irq_status = wait_for_irq(denali, irq_mask);
+ for (i = 0; i < size / 4; i++)
+ *buf32++ = denali->host_read(denali, addr);
- if (irq_status == 0)
- printf("page on OOB timeout %d\n", denali->page);
+ irq_status = denali_wait_for_irq(denali, INTR__PAGE_XFER_INC);
+ if (!(irq_status & INTR__PAGE_XFER_INC))
+ return -EIO;
- /*
- * We set the device back to MAIN_ACCESS here as I observed
- * instability with the controller if you do a block erase
- * and the last transaction was a SPARE_ACCESS. Block erase
- * is reliable (according to the MTD test infrastructure)
- * if you are in MAIN_ACCESS.
- */
- addr = BANK(denali->flash_bank) | denali->page;
- cmd = MODE_10 | addr;
- index_addr(denali, cmd, MAIN_ACCESS);
- }
+ if (irq_status & INTR__ERASED_PAGE)
+ memset(buf, 0xff, size);
+
+ return irq_status & ecc_err_mask ? -EBADMSG : 0;
}
-/*
- * this function examines buffers to see if they contain data that
- * indicate that the buffer is part of an erased region of flash.
- */
-static bool is_erased(uint8_t *buf, int len)
+static int denali_pio_write(struct denali_nand_info *denali,
+ const void *buf, size_t size, int page, int raw)
{
+ u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
+ const uint32_t *buf32 = (uint32_t *)buf;
+ uint32_t irq_status;
int i;
- for (i = 0; i < len; i++)
- if (buf[i] != 0xFF)
- return false;
- return true;
+ denali_reset_irq(denali);
+
+ for (i = 0; i < size / 4; i++)
+ denali->host_write(denali, addr, *buf32++);
+
+ irq_status = denali_wait_for_irq(denali,
+ INTR__PROGRAM_COMP | INTR__PROGRAM_FAIL);
+ if (!(irq_status & INTR__PROGRAM_COMP))
+ return -EIO;
+
+ return 0;
}
-/* programs the controller to either enable/disable DMA transfers */
-static void denali_enable_dma(struct denali_nand_info *denali, bool en)
+static int denali_pio_xfer(struct denali_nand_info *denali, void *buf,
+ size_t size, int page, int raw, int write)
{
- writel(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE);
- readl(denali->flash_reg + DMA_ENABLE);
+ if (write)
+ return denali_pio_write(denali, buf, size, page, raw);
+ else
+ return denali_pio_read(denali, buf, size, page, raw);
}
-/* setups the HW to perform the data DMA */
-static void denali_setup_dma(struct denali_nand_info *denali, int op)
+static int denali_dma_xfer(struct denali_nand_info *denali, void *buf,
+ size_t size, int page, int raw, int write)
{
- uint32_t mode;
- const int page_count = 1;
- uint64_t addr = (unsigned long)denali->buf.dma_buf;
-
- flush_dcache_range(addr, addr + sizeof(denali->buf.dma_buf));
-
-/* For Denali controller that is 64 bit bus IP core */
-#ifdef CONFIG_SYS_NAND_DENALI_64BIT
- mode = MODE_10 | BANK(denali->flash_bank) | denali->page;
-
- /* DMA is a three step process */
+ dma_addr_t dma_addr;
+ uint32_t irq_mask, irq_status, ecc_err_mask;
+ enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
+ int ret = 0;
+
+ dma_addr = dma_map_single(denali->dev, buf, size, dir);
+ if (dma_mapping_error(denali->dev, dma_addr)) {
+ dev_dbg(denali->dev, "Failed to DMA-map buffer. Trying PIO.\n");
+ return denali_pio_xfer(denali, buf, size, page, raw, write);
+ }
- /* 1. setup transfer type, interrupt when complete,
- burst len = 64 bytes, the number of pages */
- index_addr(denali, mode, 0x01002000 | (64 << 16) | op | page_count);
+ if (write) {
+ /*
+ * INTR__PROGRAM_COMP is never asserted for the DMA transfer.
+ * We can use INTR__DMA_CMD_COMP instead. This flag is asserted
+ * when the page program is completed.
+ */
+ irq_mask = INTR__DMA_CMD_COMP | INTR__PROGRAM_FAIL;
+ ecc_err_mask = 0;
+ } else if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) {
+ irq_mask = INTR__DMA_CMD_COMP;
+ ecc_err_mask = INTR__ECC_UNCOR_ERR;
+ } else {
+ irq_mask = INTR__DMA_CMD_COMP;
+ ecc_err_mask = INTR__ECC_ERR;
+ }
- /* 2. set memory low address bits 31:0 */
- index_addr(denali, mode, addr);
+ iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE);
- /* 3. set memory high address bits 64:32 */
- index_addr(denali, mode, addr >> 32);
-#else
- mode = MODE_10 | BANK(denali->flash_bank);
+ denali_reset_irq(denali);
+ denali->setup_dma(denali, dma_addr, page, write);
- /* DMA is a four step process */
+ irq_status = denali_wait_for_irq(denali, irq_mask);
+ if (!(irq_status & INTR__DMA_CMD_COMP))
+ ret = -EIO;
+ else if (irq_status & ecc_err_mask)
+ ret = -EBADMSG;
- /* 1. setup transfer type and # of pages */
- index_addr(denali, mode | denali->page, 0x2000 | op | page_count);
+ iowrite32(0, denali->reg + DMA_ENABLE);
- /* 2. set memory high address bits 23:8 */
- index_addr(denali, mode | (((addr >> 16) & 0xffff) << 8), 0x2200);
+ dma_unmap_single(denali->dev, dma_addr, size, dir);
- /* 3. set memory low address bits 23:8 */
- index_addr(denali, mode | ((addr & 0xffff) << 8), 0x2300);
+ if (irq_status & INTR__ERASED_PAGE)
+ memset(buf, 0xff, size);
- /* 4. interrupt when complete, burst len = 64 bytes */
- index_addr(denali, mode | 0x14000, 0x2400);
-#endif
+ return ret;
}
-/* Common DMA function */
-static uint32_t denali_dma_configuration(struct denali_nand_info *denali,
- uint32_t ops, bool raw_xfer,
- uint32_t irq_mask, int oob_required)
+static int denali_data_xfer(struct denali_nand_info *denali, void *buf,
+ size_t size, int page, int raw, int write)
{
- uint32_t irq_status = 0;
- /* setup_ecc_for_xfer(bool ecc_en, bool transfer_spare) */
- setup_ecc_for_xfer(denali, !raw_xfer, oob_required);
-
- /* clear any previous interrupt flags */
- clear_interrupts(denali);
-
- /* enable the DMA */
- denali_enable_dma(denali, true);
-
- /* setup the DMA */
- denali_setup_dma(denali, ops);
-
- /* wait for operation to complete */
- irq_status = wait_for_irq(denali, irq_mask);
+ iowrite32(raw ? 0 : ECC_ENABLE__FLAG, denali->reg + ECC_ENABLE);
+ iowrite32(raw ? TRANSFER_SPARE_REG__FLAG : 0,
+ denali->reg + TRANSFER_SPARE_REG);
- /* if ECC fault happen, seems we need delay before turning off DMA.
- * If not, the controller will go into non responsive condition */
- if (irq_status & INTR_STATUS__ECC_UNCOR_ERR)
- udelay(100);
-
- /* disable the DMA */
- denali_enable_dma(denali, false);
-
- return irq_status;
+ if (denali->dma_avail)
+ return denali_dma_xfer(denali, buf, size, page, raw, write);
+ else
+ return denali_pio_xfer(denali, buf, size, page, raw, write);
}
-static int write_page(struct mtd_info *mtd, struct nand_chip *chip,
- const uint8_t *buf, bool raw_xfer, int oob_required)
+static void denali_oob_xfer(struct mtd_info *mtd, struct nand_chip *chip,
+ int page, int write)
{
struct denali_nand_info *denali = mtd_to_denali(mtd);
+ unsigned int start_cmd = write ? NAND_CMD_SEQIN : NAND_CMD_READ0;
+ unsigned int rnd_cmd = write ? NAND_CMD_RNDIN : NAND_CMD_RNDOUT;
+ int writesize = mtd->writesize;
+ int oobsize = mtd->oobsize;
+ uint8_t *bufpoi = chip->oob_poi;
+ int ecc_steps = chip->ecc.steps;
+ int ecc_size = chip->ecc.size;
+ int ecc_bytes = chip->ecc.bytes;
+ int oob_skip = denali->oob_skip_bytes;
+ size_t size = writesize + oobsize;
+ int i, pos, len;
+
+ /* BBM at the beginning of the OOB area */
+ chip->cmdfunc(mtd, start_cmd, writesize, page);
+ if (write)
+ chip->write_buf(mtd, bufpoi, oob_skip);
+ else
+ chip->read_buf(mtd, bufpoi, oob_skip);
+ bufpoi += oob_skip;
+
+ /* OOB ECC */
+ for (i = 0; i < ecc_steps; i++) {
+ pos = ecc_size + i * (ecc_size + ecc_bytes);
+ len = ecc_bytes;
+
+ if (pos >= writesize)
+ pos += oob_skip;
+ else if (pos + len > writesize)
+ len = writesize - pos;
+
+ chip->cmdfunc(mtd, rnd_cmd, pos, -1);
+ if (write)
+ chip->write_buf(mtd, bufpoi, len);
+ else
+ chip->read_buf(mtd, bufpoi, len);
+ bufpoi += len;
+ if (len < ecc_bytes) {
+ len = ecc_bytes - len;
+ chip->cmdfunc(mtd, rnd_cmd, writesize + oob_skip, -1);
+ if (write)
+ chip->write_buf(mtd, bufpoi, len);
+ else
+ chip->read_buf(mtd, bufpoi, len);
+ bufpoi += len;
+ }
+ }
- uint32_t irq_status = 0;
- uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP;
-
- denali->status = 0;
-
- /* copy buffer into DMA buffer */
- memcpy(denali->buf.dma_buf, buf, mtd->writesize);
+ /* OOB free */
+ len = oobsize - (bufpoi - chip->oob_poi);
+ chip->cmdfunc(mtd, rnd_cmd, size - len, -1);
+ if (write)
+ chip->write_buf(mtd, bufpoi, len);
+ else
+ chip->read_buf(mtd, bufpoi, len);
+}
- /* need extra memcpy for raw transfer */
- if (raw_xfer)
- memcpy(denali->buf.dma_buf + mtd->writesize,
- chip->oob_poi, mtd->oobsize);
+static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int oob_required, int page)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ int writesize = mtd->writesize;
+ int oobsize = mtd->oobsize;
+ int ecc_steps = chip->ecc.steps;
+ int ecc_size = chip->ecc.size;
+ int ecc_bytes = chip->ecc.bytes;
+ void *tmp_buf = denali->buf;
+ int oob_skip = denali->oob_skip_bytes;
+ size_t size = writesize + oobsize;
+ int ret, i, pos, len;
+
+ ret = denali_data_xfer(denali, tmp_buf, size, page, 1, 0);
+ if (ret)
+ return ret;
+
+ /* Arrange the buffer for syndrome payload/ecc layout */
+ if (buf) {
+ for (i = 0; i < ecc_steps; i++) {
+ pos = i * (ecc_size + ecc_bytes);
+ len = ecc_size;
+
+ if (pos >= writesize)
+ pos += oob_skip;
+ else if (pos + len > writesize)
+ len = writesize - pos;
+
+ memcpy(buf, tmp_buf + pos, len);
+ buf += len;
+ if (len < ecc_size) {
+ len = ecc_size - len;
+ memcpy(buf, tmp_buf + writesize + oob_skip,
+ len);
+ buf += len;
+ }
+ }
+ }
- /* setting up DMA */
- irq_status = denali_dma_configuration(denali, DENALI_WRITE, raw_xfer,
- irq_mask, oob_required);
+ if (oob_required) {
+ uint8_t *oob = chip->oob_poi;
+
+ /* BBM at the beginning of the OOB area */
+ memcpy(oob, tmp_buf + writesize, oob_skip);
+ oob += oob_skip;
+
+ /* OOB ECC */
+ for (i = 0; i < ecc_steps; i++) {
+ pos = ecc_size + i * (ecc_size + ecc_bytes);
+ len = ecc_bytes;
+
+ if (pos >= writesize)
+ pos += oob_skip;
+ else if (pos + len > writesize)
+ len = writesize - pos;
+
+ memcpy(oob, tmp_buf + pos, len);
+ oob += len;
+ if (len < ecc_bytes) {
+ len = ecc_bytes - len;
+ memcpy(oob, tmp_buf + writesize + oob_skip,
+ len);
+ oob += len;
+ }
+ }
- /* if timeout happen, error out */
- if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) {
- debug("DMA timeout for denali write_page\n");
- denali->status = NAND_STATUS_FAIL;
- return -EIO;
+ /* OOB free */
+ len = oobsize - (oob - chip->oob_poi);
+ memcpy(oob, tmp_buf + size - len, len);
}
- if (irq_status & INTR_STATUS__LOCKED_BLK) {
- debug("Failed as write to locked block\n");
- denali->status = NAND_STATUS_FAIL;
- return -EIO;
- }
return 0;
}
-/* NAND core entry points */
-
-/*
- * this is the callback that the NAND core calls to write a page. Since
- * writing a page with ECC or without is similar, all the work is done
- * by write_page above.
- */
-static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
- const uint8_t *buf, int oob_required, int page)
+static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
{
- struct denali_nand_info *denali = mtd_to_denali(mtd);
-
- /*
- * for regular page writes, we let HW handle all the ECC
- * data written to the device.
- */
- if (oob_required)
- /* switch to main + spare access */
- denali_mode_main_spare_access(denali);
- else
- /* switch to main access only */
- denali_mode_main_access(denali);
+ denali_oob_xfer(mtd, chip, page, 0);
- return write_page(mtd, chip, buf, false, oob_required);
+ return 0;
}
-/*
- * This is the callback that the NAND core calls to write a page without ECC.
- * raw access is similar to ECC page writes, so all the work is done in the
- * write_page() function above.
- */
-static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
- const uint8_t *buf, int oob_required,
- int page)
+static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
{
struct denali_nand_info *denali = mtd_to_denali(mtd);
+ int status;
- /*
- * for raw page writes, we want to disable ECC and simply write
- * whatever data is in the buffer.
- */
+ denali_reset_irq(denali);
- if (oob_required)
- /* switch to main + spare access */
- denali_mode_main_spare_access(denali);
- else
- /* switch to main access only */
- denali_mode_main_access(denali);
+ denali_oob_xfer(mtd, chip, page, 1);
- return write_page(mtd, chip, buf, true, oob_required);
-}
+ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+ status = chip->waitfunc(mtd, chip);
-static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
- int page)
-{
- return write_oob_data(mtd, chip->oob_poi, page);
+ return status & NAND_STATUS_FAIL ? -EIO : 0;
}
-/* raw include ECC value and all the spare area */
-static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
- uint8_t *buf, int oob_required, int page)
+static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int oob_required, int page)
{
struct denali_nand_info *denali = mtd_to_denali(mtd);
+ unsigned long uncor_ecc_flags = 0;
+ int stat = 0;
+ int ret;
- uint32_t irq_status, irq_mask = INTR_STATUS__DMA_CMD_COMP;
+ ret = denali_data_xfer(denali, buf, mtd->writesize, page, 0, 0);
+ if (ret && ret != -EBADMSG)
+ return ret;
- if (denali->page != page) {
- debug("Missing NAND_CMD_READ0 command\n");
- return -EIO;
- }
+ if (denali->caps & DENALI_CAP_HW_ECC_FIXUP)
+ stat = denali_hw_ecc_fixup(mtd, denali, &uncor_ecc_flags);
+ else if (ret == -EBADMSG)
+ stat = denali_sw_ecc_fixup(mtd, denali, &uncor_ecc_flags, buf);
- if (oob_required)
- /* switch to main + spare access */
- denali_mode_main_spare_access(denali);
- else
- /* switch to main access only */
- denali_mode_main_access(denali);
+ if (stat < 0)
+ return stat;
- /* setting up the DMA where ecc_enable is false */
- irq_status = denali_dma_configuration(denali, DENALI_READ, true,
- irq_mask, oob_required);
+ if (uncor_ecc_flags) {
+ ret = denali_read_oob(mtd, chip, page);
+ if (ret)
+ return ret;
- /* if timeout happen, error out */
- if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) {
- debug("DMA timeout for denali_read_page_raw\n");
- return -EIO;
+ stat = denali_check_erased_page(mtd, chip, buf,
+ uncor_ecc_flags, stat);
}
- /* splitting the content to destination buffer holder */
- memcpy(chip->oob_poi, (denali->buf.dma_buf + mtd->writesize),
- mtd->oobsize);
- memcpy(buf, denali->buf.dma_buf, mtd->writesize);
-
- return 0;
+ return stat;
}
-static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
- uint8_t *buf, int oob_required, int page)
+static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf, int oob_required, int page)
{
struct denali_nand_info *denali = mtd_to_denali(mtd);
- uint32_t irq_status, irq_mask = INTR_STATUS__DMA_CMD_COMP;
+ int writesize = mtd->writesize;
+ int oobsize = mtd->oobsize;
+ int ecc_steps = chip->ecc.steps;
+ int ecc_size = chip->ecc.size;
+ int ecc_bytes = chip->ecc.bytes;
+ void *tmp_buf = denali->buf;
+ int oob_skip = denali->oob_skip_bytes;
+ size_t size = writesize + oobsize;
+ int i, pos, len;
- if (denali->page != page) {
- debug("Missing NAND_CMD_READ0 command\n");
- return -EIO;
+ /*
+ * Fill the buffer with 0xff first except the full page transfer.
+ * This simplifies the logic.
+ */
+ if (!buf || !oob_required)
+ memset(tmp_buf, 0xff, size);
+
+ /* Arrange the buffer for syndrome payload/ecc layout */
+ if (buf) {
+ for (i = 0; i < ecc_steps; i++) {
+ pos = i * (ecc_size + ecc_bytes);
+ len = ecc_size;
+
+ if (pos >= writesize)
+ pos += oob_skip;
+ else if (pos + len > writesize)
+ len = writesize - pos;
+
+ memcpy(tmp_buf + pos, buf, len);
+ buf += len;
+ if (len < ecc_size) {
+ len = ecc_size - len;
+ memcpy(tmp_buf + writesize + oob_skip, buf,
+ len);
+ buf += len;
+ }
+ }
}
- if (oob_required)
- /* switch to main + spare access */
- denali_mode_main_spare_access(denali);
- else
- /* switch to main access only */
- denali_mode_main_access(denali);
-
- /* setting up the DMA where ecc_enable is true */
- irq_status = denali_dma_configuration(denali, DENALI_READ, false,
- irq_mask, oob_required);
-
- memcpy(buf, denali->buf.dma_buf, mtd->writesize);
-
- /* check whether any ECC error */
- if (irq_status & INTR_STATUS__ECC_UNCOR_ERR) {
- /* is the ECC cause by erase page, check using read_page_raw */
- debug(" Uncorrected ECC detected\n");
- denali_read_page_raw(mtd, chip, buf, oob_required,
- denali->page);
-
- if (is_erased(buf, mtd->writesize) == true &&
- is_erased(chip->oob_poi, mtd->oobsize) == true) {
- debug(" ECC error cause by erased block\n");
- /* false alarm, return the 0xFF */
- } else {
- return -EBADMSG;
+ if (oob_required) {
+ const uint8_t *oob = chip->oob_poi;
+
+ /* BBM at the beginning of the OOB area */
+ memcpy(tmp_buf + writesize, oob, oob_skip);
+ oob += oob_skip;
+
+ /* OOB ECC */
+ for (i = 0; i < ecc_steps; i++) {
+ pos = ecc_size + i * (ecc_size + ecc_bytes);
+ len = ecc_bytes;
+
+ if (pos >= writesize)
+ pos += oob_skip;
+ else if (pos + len > writesize)
+ len = writesize - pos;
+
+ memcpy(tmp_buf + pos, oob, len);
+ oob += len;
+ if (len < ecc_bytes) {
+ len = ecc_bytes - len;
+ memcpy(tmp_buf + writesize + oob_skip, oob,
+ len);
+ oob += len;
+ }
}
+
+ /* OOB free */
+ len = oobsize - (oob - chip->oob_poi);
+ memcpy(tmp_buf + size - len, oob, len);
}
- memcpy(buf, denali->buf.dma_buf, mtd->writesize);
- return 0;
+
+ return denali_data_xfer(denali, tmp_buf, size, page, 1, 1);
}
-static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
- int page)
+static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf, int oob_required, int page)
{
- read_oob_data(mtd, chip->oob_poi, page);
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
- return 0;
+ return denali_data_xfer(denali, (void *)buf, mtd->writesize,
+ page, 0, 1);
}
-static uint8_t denali_read_byte(struct mtd_info *mtd)
+static void denali_select_chip(struct mtd_info *mtd, int chip)
{
struct denali_nand_info *denali = mtd_to_denali(mtd);
- uint32_t addr, result;
- addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
- index_addr_read_data(denali, addr | 2, &result);
- return (uint8_t)result & 0xFF;
+ denali->active_bank = chip;
}
-static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
{
struct denali_nand_info *denali = mtd_to_denali(mtd);
- uint32_t i, addr, result;
-
- /* delay for tR (data transfer from Flash array to data register) */
- udelay(25);
+ uint32_t irq_status;
- /* ensure device completed else additional delay and polling */
- wait_for_irq(denali, INTR_STATUS__INT_ACT);
+ /* R/B# pin transitioned from low to high? */
+ irq_status = denali_wait_for_irq(denali, INTR__INT_ACT);
- addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
- for (i = 0; i < len; i++) {
- index_addr_read_data(denali, (uint32_t)addr | 2, &result);
- write_byte_to_buf(denali, result);
- }
- memcpy(buf, denali->buf.buf, len);
+ return irq_status & INTR__INT_ACT ? 0 : NAND_STATUS_FAIL;
}
-static void denali_select_chip(struct mtd_info *mtd, int chip)
+static int denali_erase(struct mtd_info *mtd, int page)
{
struct denali_nand_info *denali = mtd_to_denali(mtd);
+ uint32_t irq_status;
- denali->flash_bank = chip;
-}
+ denali_reset_irq(denali);
-static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
-{
- struct denali_nand_info *denali = mtd_to_denali(mtd);
- int status = denali->status;
+ denali->host_write(denali, DENALI_MAP10 | DENALI_BANK(denali) | page,
+ DENALI_ERASE);
- denali->status = 0;
+ /* wait for erase to complete or failure to occur */
+ irq_status = denali_wait_for_irq(denali,
+ INTR__ERASE_COMP | INTR__ERASE_FAIL);
- return status;
+ return irq_status & INTR__ERASE_COMP ? 0 : NAND_STATUS_FAIL;
}
-static int denali_erase(struct mtd_info *mtd, int page)
+static int __maybe_unused denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
+ const struct nand_data_interface *conf)
{
struct denali_nand_info *denali = mtd_to_denali(mtd);
+ const struct nand_sdr_timings *timings;
+ unsigned long t_clk;
+ int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data;
+ int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup;
+ int addr_2_data_mask;
+ uint32_t tmp;
- uint32_t cmd, irq_status;
+ timings = nand_get_sdr_timings(conf);
+ if (IS_ERR(timings))
+ return PTR_ERR(timings);
- clear_interrupts(denali);
+ /* clk_x period in picoseconds */
+ t_clk = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate);
+ if (!t_clk)
+ return -EINVAL;
- /* setup page read request for access type */
- cmd = MODE_10 | BANK(denali->flash_bank) | page;
- index_addr(denali, cmd, 0x1);
+ if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
+ return 0;
- /* wait for erase to complete or failure to occur */
- irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP |
- INTR_STATUS__ERASE_FAIL);
+ /* tREA -> ACC_CLKS */
+ acc_clks = DIV_ROUND_UP(timings->tREA_max, t_clk);
+ acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE);
+
+ tmp = ioread32(denali->reg + ACC_CLKS);
+ tmp &= ~ACC_CLKS__VALUE;
+ tmp |= FIELD_PREP(ACC_CLKS__VALUE, acc_clks);
+ iowrite32(tmp, denali->reg + ACC_CLKS);
+
+ /* tRWH -> RE_2_WE */
+ re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_clk);
+ re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE);
+
+ tmp = ioread32(denali->reg + RE_2_WE);
+ tmp &= ~RE_2_WE__VALUE;
+ tmp |= FIELD_PREP(RE_2_WE__VALUE, re_2_we);
+ iowrite32(tmp, denali->reg + RE_2_WE);
+
+ /* tRHZ -> RE_2_RE */
+ re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_clk);
+ re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE);
+
+ tmp = ioread32(denali->reg + RE_2_RE);
+ tmp &= ~RE_2_RE__VALUE;
+ tmp |= FIELD_PREP(RE_2_RE__VALUE, re_2_re);
+ iowrite32(tmp, denali->reg + RE_2_RE);
+
+ /*
+ * tCCS, tWHR -> WE_2_RE
+ *
+ * With WE_2_RE properly set, the Denali controller automatically takes
+ * care of the delay; the driver need not set NAND_WAIT_TCCS.
+ */
+ we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min),
+ t_clk);
+ we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE);
+
+ tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE);
+ tmp &= ~TWHR2_AND_WE_2_RE__WE_2_RE;
+ tmp |= FIELD_PREP(TWHR2_AND_WE_2_RE__WE_2_RE, we_2_re);
+ iowrite32(tmp, denali->reg + TWHR2_AND_WE_2_RE);
+
+ /* tADL -> ADDR_2_DATA */
- if (irq_status & INTR_STATUS__ERASE_FAIL ||
- irq_status & INTR_STATUS__LOCKED_BLK)
- return NAND_STATUS_FAIL;
+ /* for older versions, ADDR_2_DATA is only 6 bit wide */
+ addr_2_data_mask = TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA;
+ if (denali->revision < 0x0501)
+ addr_2_data_mask >>= 1;
+
+ addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_clk);
+ addr_2_data = min_t(int, addr_2_data, addr_2_data_mask);
+
+ tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA);
+ tmp &= ~TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA;
+ tmp |= FIELD_PREP(TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA, addr_2_data);
+ iowrite32(tmp, denali->reg + TCWAW_AND_ADDR_2_DATA);
+
+ /* tREH, tWH -> RDWR_EN_HI_CNT */
+ rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min),
+ t_clk);
+ rdwr_en_hi = min_t(int, rdwr_en_hi, RDWR_EN_HI_CNT__VALUE);
+
+ tmp = ioread32(denali->reg + RDWR_EN_HI_CNT);
+ tmp &= ~RDWR_EN_HI_CNT__VALUE;
+ tmp |= FIELD_PREP(RDWR_EN_HI_CNT__VALUE, rdwr_en_hi);
+ iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT);
+
+ /* tRP, tWP -> RDWR_EN_LO_CNT */
+ rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min),
+ t_clk);
+ rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min),
+ t_clk);
+ rdwr_en_lo_hi = max(rdwr_en_lo_hi, DENALI_CLK_X_MULT);
+ rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi);
+ rdwr_en_lo = min_t(int, rdwr_en_lo, RDWR_EN_LO_CNT__VALUE);
+
+ tmp = ioread32(denali->reg + RDWR_EN_LO_CNT);
+ tmp &= ~RDWR_EN_LO_CNT__VALUE;
+ tmp |= FIELD_PREP(RDWR_EN_LO_CNT__VALUE, rdwr_en_lo);
+ iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT);
+
+ /* tCS, tCEA -> CS_SETUP_CNT */
+ cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_clk) - rdwr_en_lo,
+ (int)DIV_ROUND_UP(timings->tCEA_max, t_clk) - acc_clks,
+ 0);
+ cs_setup = min_t(int, cs_setup, CS_SETUP_CNT__VALUE);
+
+ tmp = ioread32(denali->reg + CS_SETUP_CNT);
+ tmp &= ~CS_SETUP_CNT__VALUE;
+ tmp |= FIELD_PREP(CS_SETUP_CNT__VALUE, cs_setup);
+ iowrite32(tmp, denali->reg + CS_SETUP_CNT);
return 0;
}
-static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
- int page)
+static void denali_reset_banks(struct denali_nand_info *denali)
{
- struct denali_nand_info *denali = mtd_to_denali(mtd);
- uint32_t addr;
-
- switch (cmd) {
- case NAND_CMD_PAGEPROG:
- break;
- case NAND_CMD_STATUS:
- addr = MODE_11 | BANK(denali->flash_bank);
- index_addr(denali, addr | 0, cmd);
- break;
- case NAND_CMD_READID:
- case NAND_CMD_PARAM:
- reset_buf(denali);
- /*
- * sometimes ManufactureId read from register is not right
- * e.g. some of Micron MT29F32G08QAA MLC NAND chips
- * So here we send READID cmd to NAND insteand
- */
- addr = MODE_11 | BANK(denali->flash_bank);
- index_addr(denali, addr | 0, cmd);
- index_addr(denali, addr | 1, col & 0xFF);
- if (cmd == NAND_CMD_PARAM)
- udelay(50);
- break;
- case NAND_CMD_RNDOUT:
- addr = MODE_11 | BANK(denali->flash_bank);
- index_addr(denali, addr | 0, cmd);
- index_addr(denali, addr | 1, col & 0xFF);
- index_addr(denali, addr | 1, col >> 8);
- index_addr(denali, addr | 0, NAND_CMD_RNDOUTSTART);
- break;
- case NAND_CMD_READ0:
- case NAND_CMD_SEQIN:
- denali->page = page;
- break;
- case NAND_CMD_RESET:
- reset_bank(denali);
- break;
- case NAND_CMD_READOOB:
- /* TODO: Read OOB data */
- break;
- case NAND_CMD_ERASE1:
- /*
- * supporting block erase only, not multiblock erase as
- * it will cross plane and software need complex calculation
- * to identify the block count for the cross plane
- */
- denali_erase(mtd, page);
- break;
- case NAND_CMD_ERASE2:
- /* nothing to do here as it was done during NAND_CMD_ERASE1 */
- break;
- case NAND_CMD_UNLOCK1:
- addr = MODE_10 | BANK(denali->flash_bank) | page;
- index_addr(denali, addr | 0, DENALI_UNLOCK_START);
- break;
- case NAND_CMD_UNLOCK2:
- addr = MODE_10 | BANK(denali->flash_bank) | page;
- index_addr(denali, addr | 0, DENALI_UNLOCK_END);
- break;
- case NAND_CMD_LOCK:
- addr = MODE_10 | BANK(denali->flash_bank);
- index_addr(denali, addr | 0, DENALI_LOCK);
- break;
- default:
- printf(": unsupported command received 0x%x\n", cmd);
- break;
+ u32 irq_status;
+ int i;
+
+ for (i = 0; i < denali->max_banks; i++) {
+ denali->active_bank = i;
+
+ denali_reset_irq(denali);
+
+ iowrite32(DEVICE_RESET__BANK(i),
+ denali->reg + DEVICE_RESET);
+
+ irq_status = denali_wait_for_irq(denali,
+ INTR__RST_COMP | INTR__INT_ACT | INTR__TIME_OUT);
+ if (!(irq_status & INTR__INT_ACT))
+ break;
}
+
+ dev_dbg(denali->dev, "%d chips connected\n", i);
+ denali->max_banks = i;
}
-/* end NAND core entry points */
-/* Initialization code to bring the device up to a known good state */
static void denali_hw_init(struct denali_nand_info *denali)
{
/*
@@ -1154,125 +1086,284 @@ static void denali_hw_init(struct denali_nand_info *denali)
* override it.
*/
if (!denali->revision)
- denali->revision = swab16(ioread32(denali->flash_reg + REVISION));
+ denali->revision = swab16(ioread32(denali->reg + REVISION));
/*
* tell driver how many bit controller will skip before writing
* ECC code in OOB. This is normally used for bad block marker
*/
- writel(CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES,
- denali->flash_reg + SPARE_AREA_SKIP_BYTES);
- detect_max_banks(denali);
- denali_nand_reset(denali);
- writel(0x0F, denali->flash_reg + RB_PIN_ENABLED);
- writel(CHIP_EN_DONT_CARE__FLAG,
- denali->flash_reg + CHIP_ENABLE_DONT_CARE);
- writel(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
-
- /* Should set value for these registers when init */
- writel(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
- writel(1, denali->flash_reg + ECC_ENABLE);
- denali_nand_timing_set(denali);
- denali_irq_init(denali);
+ denali->oob_skip_bytes = CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES;
+ iowrite32(denali->oob_skip_bytes, denali->reg + SPARE_AREA_SKIP_BYTES);
+ denali_detect_max_banks(denali);
+ iowrite32(0x0F, denali->reg + RB_PIN_ENABLED);
+ iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE);
+
+ iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER);
}
-static struct nand_ecclayout nand_oob;
+int denali_calc_ecc_bytes(int step_size, int strength)
+{
+ /* BCH code. Denali requires ecc.bytes to be multiple of 2 */
+ return DIV_ROUND_UP(strength * fls(step_size * 8), 16) * 2;
+}
+EXPORT_SYMBOL(denali_calc_ecc_bytes);
-int denali_init(struct denali_nand_info *denali)
+static int denali_ecc_setup(struct mtd_info *mtd, struct nand_chip *chip,
+ struct denali_nand_info *denali)
{
- struct mtd_info *mtd = nand_to_mtd(&denali->nand);
+ int oobavail = mtd->oobsize - denali->oob_skip_bytes;
int ret;
- denali_hw_init(denali);
+ /*
+ * If .size and .strength are already set (usually by DT),
+ * check if they are supported by this controller.
+ */
+ if (chip->ecc.size && chip->ecc.strength)
+ return nand_check_ecc_caps(chip, denali->ecc_caps, oobavail);
+
+ /*
+ * We want .size and .strength closest to the chip's requirement
+ * unless NAND_ECC_MAXIMIZE is requested.
+ */
+ if (!(chip->ecc.options & NAND_ECC_MAXIMIZE)) {
+ ret = nand_match_ecc_req(chip, denali->ecc_caps, oobavail);
+ if (!ret)
+ return 0;
+ }
+
+ /* Max ECC strength is the last thing we can do */
+ return nand_maximize_ecc(chip, denali->ecc_caps, oobavail);
+}
+
+static struct nand_ecclayout nand_oob;
+
+static int denali_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ struct nand_chip *chip = mtd_to_nand(mtd);
+
+ if (section)
+ return -ERANGE;
+
+ oobregion->offset = denali->oob_skip_bytes;
+ oobregion->length = chip->ecc.total;
+
+ return 0;
+}
- mtd->name = "denali-nand";
- mtd->owner = THIS_MODULE;
+static int denali_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+ struct nand_chip *chip = mtd_to_nand(mtd);
+
+ if (section)
+ return -ERANGE;
+
+ oobregion->offset = chip->ecc.total + denali->oob_skip_bytes;
+ oobregion->length = mtd->oobsize - oobregion->offset;
+
+ return 0;
+}
- /* register the driver with the NAND core subsystem */
- denali->nand.select_chip = denali_select_chip;
- denali->nand.cmdfunc = denali_cmdfunc;
- denali->nand.read_byte = denali_read_byte;
- denali->nand.read_buf = denali_read_buf;
- denali->nand.waitfunc = denali_waitfunc;
+static const struct mtd_ooblayout_ops denali_ooblayout_ops = {
+ .ecc = denali_ooblayout_ecc,
+ .free = denali_ooblayout_free,
+};
+
+static int denali_multidev_fixup(struct denali_nand_info *denali)
+{
+ struct nand_chip *chip = &denali->nand;
+ struct mtd_info *mtd = nand_to_mtd(chip);
/*
- * scan for NAND devices attached to the controller
- * this is the first stage in a two step process to register
- * with the nand subsystem
+ * Support for multi device:
+ * When the IP configuration is x16 capable and two x8 chips are
+ * connected in parallel, DEVICES_CONNECTED should be set to 2.
+ * In this case, the core framework knows nothing about this fact,
+ * so we should tell it the _logical_ pagesize and anything necessary.
*/
- if (nand_scan_ident(mtd, denali->max_banks, NULL)) {
- ret = -ENXIO;
- goto fail;
- }
+ denali->devs_per_cs = ioread32(denali->reg + DEVICES_CONNECTED);
-#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
- /* check whether flash got BBT table (located at end of flash). As we
- * use NAND_BBT_NO_OOB, the BBT page will start with
- * bbt_pattern. We will have mirror pattern too */
- denali->nand.bbt_options |= NAND_BBT_USE_FLASH;
/*
- * We are using main + spare with ECC support. As BBT need ECC support,
- * we need to ensure BBT code don't write to OOB for the BBT pattern.
- * All BBT info will be stored into data area with ECC support.
+ * On some SoCs, DEVICES_CONNECTED is not auto-detected.
+ * For those, DEVICES_CONNECTED is left to 0. Set 1 if it is the case.
*/
- denali->nand.bbt_options |= NAND_BBT_NO_OOB;
-#endif
+ if (denali->devs_per_cs == 0) {
+ denali->devs_per_cs = 1;
+ iowrite32(1, denali->reg + DEVICES_CONNECTED);
+ }
+
+ if (denali->devs_per_cs == 1)
+ return 0;
+
+ if (denali->devs_per_cs != 2) {
+ dev_err(denali->dev, "unsupported number of devices %d\n",
+ denali->devs_per_cs);
+ return -EINVAL;
+ }
+
+ /* 2 chips in parallel */
+ mtd->size <<= 1;
+ mtd->erasesize <<= 1;
+ mtd->writesize <<= 1;
+ mtd->oobsize <<= 1;
+ chip->chipsize <<= 1;
+ chip->page_shift += 1;
+ chip->phys_erase_shift += 1;
+ chip->bbt_erase_shift += 1;
+ chip->chip_shift += 1;
+ chip->pagemask <<= 1;
+ chip->ecc.size <<= 1;
+ chip->ecc.bytes <<= 1;
+ chip->ecc.strength <<= 1;
+ denali->oob_skip_bytes <<= 1;
+
+ return 0;
+}
+
+int denali_init(struct denali_nand_info *denali)
+{
+ struct nand_chip *chip = &denali->nand;
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ u32 features = ioread32(denali->reg + FEATURES);
+ int ret;
+
+ denali_hw_init(denali);
+
+ denali_clear_irq_all(denali);
- denali->nand.ecc.mode = NAND_ECC_HW;
- denali->nand.ecc.size = CONFIG_NAND_DENALI_ECC_SIZE;
+ denali_reset_banks(denali);
+
+ denali->active_bank = DENALI_INVALID_BANK;
+
+ chip->flash_node = dev_of_offset(denali->dev);
+ /* Fallback to the default name if DT did not give "label" property */
+ if (!mtd->name)
+ mtd->name = "denali-nand";
+
+ chip->select_chip = denali_select_chip;
+ chip->read_byte = denali_read_byte;
+ chip->write_byte = denali_write_byte;
+ chip->read_word = denali_read_word;
+ chip->cmd_ctrl = denali_cmd_ctrl;
+ chip->dev_ready = denali_dev_ready;
+ chip->waitfunc = denali_waitfunc;
+
+ if (features & FEATURES__INDEX_ADDR) {
+ denali->host_read = denali_indexed_read;
+ denali->host_write = denali_indexed_write;
+ } else {
+ denali->host_read = denali_direct_read;
+ denali->host_write = denali_direct_write;
+ }
+
+ /* clk rate info is needed for setup_data_interface */
+ if (denali->clk_x_rate)
+ chip->setup_data_interface = denali_setup_data_interface;
+
+ ret = nand_scan_ident(mtd, denali->max_banks, NULL);
+ if (ret)
+ return ret;
+
+ if (ioread32(denali->reg + FEATURES) & FEATURES__DMA)
+ denali->dma_avail = 1;
+
+ if (denali->dma_avail) {
+ chip->buf_align = 16;
+ if (denali->caps & DENALI_CAP_DMA_64BIT)
+ denali->setup_dma = denali_setup_dma64;
+ else
+ denali->setup_dma = denali_setup_dma32;
+ } else {
+ chip->buf_align = 4;
+ }
+
+ chip->options |= NAND_USE_BOUNCE_BUFFER;
+ chip->bbt_options |= NAND_BBT_USE_FLASH;
+ chip->bbt_options |= NAND_BBT_NO_OOB;
+ denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
/* no subpage writes on denali */
- denali->nand.options |= NAND_NO_SUBPAGE_WRITE;
+ chip->options |= NAND_NO_SUBPAGE_WRITE;
- /*
- * Tell driver the ecc strength. This register may be already set
- * correctly. So we read this value out.
- */
- denali->nand.ecc.strength = readl(denali->flash_reg + ECC_CORRECTION);
- switch (denali->nand.ecc.size) {
- case 512:
- denali->nand.ecc.bytes =
- (denali->nand.ecc.strength * 13 + 15) / 16 * 2;
- break;
- case 1024:
- denali->nand.ecc.bytes =
- (denali->nand.ecc.strength * 14 + 15) / 16 * 2;
- break;
- default:
- pr_err("Unsupported ECC size\n");
- ret = -EINVAL;
- goto fail;
+ ret = denali_ecc_setup(mtd, chip, denali);
+ if (ret) {
+ dev_err(denali->dev, "Failed to setup ECC settings.\n");
+ return ret;
}
+
+ dev_dbg(denali->dev,
+ "chosen ECC settings: step=%d, strength=%d, bytes=%d\n",
+ chip->ecc.size, chip->ecc.strength, chip->ecc.bytes);
+
+ iowrite32(FIELD_PREP(ECC_CORRECTION__ERASE_THRESHOLD, 1) |
+ FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength),
+ denali->reg + ECC_CORRECTION);
+ iowrite32(mtd->erasesize / mtd->writesize,
+ denali->reg + PAGES_PER_BLOCK);
+ iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0,
+ denali->reg + DEVICE_WIDTH);
+ iowrite32(chip->options & NAND_ROW_ADDR_3 ? 0 : TWO_ROW_ADDR_CYCLES__FLAG,
+ denali->reg + TWO_ROW_ADDR_CYCLES);
+ iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE);
+ iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE);
+
+ iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE);
+ iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE);
+ /* chip->ecc.steps is set by nand_scan_tail(); not available here */
+ iowrite32(mtd->writesize / chip->ecc.size,
+ denali->reg + CFG_NUM_DATA_BLOCKS);
+
+ mtd_set_ooblayout(mtd, &denali_ooblayout_ops);
+
nand_oob.eccbytes = denali->nand.ecc.bytes;
denali->nand.ecc.layout = &nand_oob;
- writel(mtd->erasesize / mtd->writesize,
- denali->flash_reg + PAGES_PER_BLOCK);
- writel(denali->nand.options & NAND_BUSWIDTH_16 ? 1 : 0,
- denali->flash_reg + DEVICE_WIDTH);
- writel(mtd->writesize,
- denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
- writel(mtd->oobsize,
- denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
- if (readl(denali->flash_reg + DEVICES_CONNECTED) == 0)
- writel(1, denali->flash_reg + DEVICES_CONNECTED);
-
- /* override the default operations */
- denali->nand.ecc.read_page = denali_read_page;
- denali->nand.ecc.read_page_raw = denali_read_page_raw;
- denali->nand.ecc.write_page = denali_write_page;
- denali->nand.ecc.write_page_raw = denali_write_page_raw;
- denali->nand.ecc.read_oob = denali_read_oob;
- denali->nand.ecc.write_oob = denali_write_oob;
-
- if (nand_scan_tail(mtd)) {
- ret = -ENXIO;
- goto fail;
+ if (chip->options & NAND_BUSWIDTH_16) {
+ chip->read_buf = denali_read_buf16;
+ chip->write_buf = denali_write_buf16;
+ } else {
+ chip->read_buf = denali_read_buf;
+ chip->write_buf = denali_write_buf;
}
+ chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS;
+ chip->ecc.read_page = denali_read_page;
+ chip->ecc.read_page_raw = denali_read_page_raw;
+ chip->ecc.write_page = denali_write_page;
+ chip->ecc.write_page_raw = denali_write_page_raw;
+ chip->ecc.read_oob = denali_read_oob;
+ chip->ecc.write_oob = denali_write_oob;
+ chip->erase = denali_erase;
+
+ ret = denali_multidev_fixup(denali);
+ if (ret)
+ return ret;
+
+ /*
+ * This buffer is DMA-mapped by denali_{read,write}_page_raw. Do not
+ * use devm_kmalloc() because the memory allocated by devm_ does not
+ * guarantee DMA-safe alignment.
+ */
+ denali->buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
+ if (!denali->buf)
+ return -ENOMEM;
+
+ ret = nand_scan_tail(mtd);
+ if (ret)
+ goto free_buf;
ret = nand_register(0, mtd);
+ if (ret) {
+ dev_err(denali->dev, "Failed to register MTD: %d\n", ret);
+ goto free_buf;
+ }
+ return 0;
+
+free_buf:
+ kfree(denali->buf);
-fail:
return ret;
}
@@ -1289,8 +1380,8 @@ static int __board_nand_init(void)
* In the future, these base addresses should be taken from
* Device Tree or platform data.
*/
- denali->flash_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
- denali->flash_mem = (void __iomem *)CONFIG_SYS_NAND_DATA_BASE;
+ denali->reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
+ denali->host = (void __iomem *)CONFIG_SYS_NAND_DATA_BASE;
return denali_init(denali);
}
diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h
index f796f0dad1..04b4ae2683 100644
--- a/drivers/mtd/nand/denali.h
+++ b/drivers/mtd/nand/denali.h
@@ -8,466 +8,319 @@
#ifndef __DENALI_H__
#define __DENALI_H__
+#include <linux/bitops.h>
#include <linux/mtd/nand.h>
+#include <linux/types.h>
#define DEVICE_RESET 0x0
-#define DEVICE_RESET__BANK0 0x0001
-#define DEVICE_RESET__BANK1 0x0002
-#define DEVICE_RESET__BANK2 0x0004
-#define DEVICE_RESET__BANK3 0x0008
+#define DEVICE_RESET__BANK(bank) BIT(bank)
#define TRANSFER_SPARE_REG 0x10
-#define TRANSFER_SPARE_REG__FLAG 0x0001
+#define TRANSFER_SPARE_REG__FLAG BIT(0)
#define LOAD_WAIT_CNT 0x20
-#define LOAD_WAIT_CNT__VALUE 0xffff
+#define LOAD_WAIT_CNT__VALUE GENMASK(15, 0)
#define PROGRAM_WAIT_CNT 0x30
-#define PROGRAM_WAIT_CNT__VALUE 0xffff
+#define PROGRAM_WAIT_CNT__VALUE GENMASK(15, 0)
#define ERASE_WAIT_CNT 0x40
-#define ERASE_WAIT_CNT__VALUE 0xffff
+#define ERASE_WAIT_CNT__VALUE GENMASK(15, 0)
#define INT_MON_CYCCNT 0x50
-#define INT_MON_CYCCNT__VALUE 0xffff
+#define INT_MON_CYCCNT__VALUE GENMASK(15, 0)
#define RB_PIN_ENABLED 0x60
-#define RB_PIN_ENABLED__BANK0 0x0001
-#define RB_PIN_ENABLED__BANK1 0x0002
-#define RB_PIN_ENABLED__BANK2 0x0004
-#define RB_PIN_ENABLED__BANK3 0x0008
+#define RB_PIN_ENABLED__BANK(bank) BIT(bank)
#define MULTIPLANE_OPERATION 0x70
-#define MULTIPLANE_OPERATION__FLAG 0x0001
+#define MULTIPLANE_OPERATION__FLAG BIT(0)
#define MULTIPLANE_READ_ENABLE 0x80
-#define MULTIPLANE_READ_ENABLE__FLAG 0x0001
+#define MULTIPLANE_READ_ENABLE__FLAG BIT(0)
#define COPYBACK_DISABLE 0x90
-#define COPYBACK_DISABLE__FLAG 0x0001
+#define COPYBACK_DISABLE__FLAG BIT(0)
#define CACHE_WRITE_ENABLE 0xa0
-#define CACHE_WRITE_ENABLE__FLAG 0x0001
+#define CACHE_WRITE_ENABLE__FLAG BIT(0)
#define CACHE_READ_ENABLE 0xb0
-#define CACHE_READ_ENABLE__FLAG 0x0001
+#define CACHE_READ_ENABLE__FLAG BIT(0)
#define PREFETCH_MODE 0xc0
-#define PREFETCH_MODE__PREFETCH_EN 0x0001
-#define PREFETCH_MODE__PREFETCH_BURST_LENGTH 0xfff0
+#define PREFETCH_MODE__PREFETCH_EN BIT(0)
+#define PREFETCH_MODE__PREFETCH_BURST_LENGTH GENMASK(15, 4)
#define CHIP_ENABLE_DONT_CARE 0xd0
-#define CHIP_EN_DONT_CARE__FLAG 0x01
+#define CHIP_EN_DONT_CARE__FLAG BIT(0)
#define ECC_ENABLE 0xe0
-#define ECC_ENABLE__FLAG 0x0001
+#define ECC_ENABLE__FLAG BIT(0)
#define GLOBAL_INT_ENABLE 0xf0
-#define GLOBAL_INT_EN_FLAG 0x01
+#define GLOBAL_INT_EN_FLAG BIT(0)
-#define WE_2_RE 0x100
-#define WE_2_RE__VALUE 0x003f
+#define TWHR2_AND_WE_2_RE 0x100
+#define TWHR2_AND_WE_2_RE__WE_2_RE GENMASK(5, 0)
+#define TWHR2_AND_WE_2_RE__TWHR2 GENMASK(13, 8)
-#define ADDR_2_DATA 0x110
-#define ADDR_2_DATA__VALUE 0x003f
+#define TCWAW_AND_ADDR_2_DATA 0x110
+/* The width of ADDR_2_DATA is 6 bit for old IP, 7 bit for new IP */
+#define TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA GENMASK(6, 0)
+#define TCWAW_AND_ADDR_2_DATA__TCWAW GENMASK(13, 8)
#define RE_2_WE 0x120
-#define RE_2_WE__VALUE 0x003f
+#define RE_2_WE__VALUE GENMASK(5, 0)
#define ACC_CLKS 0x130
-#define ACC_CLKS__VALUE 0x000f
+#define ACC_CLKS__VALUE GENMASK(3, 0)
#define NUMBER_OF_PLANES 0x140
-#define NUMBER_OF_PLANES__VALUE 0x0007
+#define NUMBER_OF_PLANES__VALUE GENMASK(2, 0)
#define PAGES_PER_BLOCK 0x150
-#define PAGES_PER_BLOCK__VALUE 0xffff
+#define PAGES_PER_BLOCK__VALUE GENMASK(15, 0)
#define DEVICE_WIDTH 0x160
-#define DEVICE_WIDTH__VALUE 0x0003
+#define DEVICE_WIDTH__VALUE GENMASK(1, 0)
#define DEVICE_MAIN_AREA_SIZE 0x170
-#define DEVICE_MAIN_AREA_SIZE__VALUE 0xffff
+#define DEVICE_MAIN_AREA_SIZE__VALUE GENMASK(15, 0)
#define DEVICE_SPARE_AREA_SIZE 0x180
-#define DEVICE_SPARE_AREA_SIZE__VALUE 0xffff
+#define DEVICE_SPARE_AREA_SIZE__VALUE GENMASK(15, 0)
#define TWO_ROW_ADDR_CYCLES 0x190
-#define TWO_ROW_ADDR_CYCLES__FLAG 0x0001
+#define TWO_ROW_ADDR_CYCLES__FLAG BIT(0)
#define MULTIPLANE_ADDR_RESTRICT 0x1a0
-#define MULTIPLANE_ADDR_RESTRICT__FLAG 0x0001
+#define MULTIPLANE_ADDR_RESTRICT__FLAG BIT(0)
#define ECC_CORRECTION 0x1b0
-#define ECC_CORRECTION__VALUE 0x001f
+#define ECC_CORRECTION__VALUE GENMASK(4, 0)
+#define ECC_CORRECTION__ERASE_THRESHOLD GENMASK(31, 16)
#define READ_MODE 0x1c0
-#define READ_MODE__VALUE 0x000f
+#define READ_MODE__VALUE GENMASK(3, 0)
#define WRITE_MODE 0x1d0
-#define WRITE_MODE__VALUE 0x000f
+#define WRITE_MODE__VALUE GENMASK(3, 0)
#define COPYBACK_MODE 0x1e0
-#define COPYBACK_MODE__VALUE 0x000f
+#define COPYBACK_MODE__VALUE GENMASK(3, 0)
#define RDWR_EN_LO_CNT 0x1f0
-#define RDWR_EN_LO_CNT__VALUE 0x001f
+#define RDWR_EN_LO_CNT__VALUE GENMASK(4, 0)
#define RDWR_EN_HI_CNT 0x200
-#define RDWR_EN_HI_CNT__VALUE 0x001f
+#define RDWR_EN_HI_CNT__VALUE GENMASK(4, 0)
#define MAX_RD_DELAY 0x210
-#define MAX_RD_DELAY__VALUE 0x000f
+#define MAX_RD_DELAY__VALUE GENMASK(3, 0)
#define CS_SETUP_CNT 0x220
-#define CS_SETUP_CNT__VALUE 0x001f
+#define CS_SETUP_CNT__VALUE GENMASK(4, 0)
+#define CS_SETUP_CNT__TWB GENMASK(17, 12)
#define SPARE_AREA_SKIP_BYTES 0x230
-#define SPARE_AREA_SKIP_BYTES__VALUE 0x003f
+#define SPARE_AREA_SKIP_BYTES__VALUE GENMASK(5, 0)
#define SPARE_AREA_MARKER 0x240
-#define SPARE_AREA_MARKER__VALUE 0xffff
+#define SPARE_AREA_MARKER__VALUE GENMASK(15, 0)
#define DEVICES_CONNECTED 0x250
-#define DEVICES_CONNECTED__VALUE 0x0007
+#define DEVICES_CONNECTED__VALUE GENMASK(2, 0)
#define DIE_MASK 0x260
-#define DIE_MASK__VALUE 0x00ff
+#define DIE_MASK__VALUE GENMASK(7, 0)
#define FIRST_BLOCK_OF_NEXT_PLANE 0x270
-#define FIRST_BLOCK_OF_NEXT_PLANE__VALUE 0xffff
+#define FIRST_BLOCK_OF_NEXT_PLANE__VALUE GENMASK(15, 0)
#define WRITE_PROTECT 0x280
-#define WRITE_PROTECT__FLAG 0x0001
+#define WRITE_PROTECT__FLAG BIT(0)
#define RE_2_RE 0x290
-#define RE_2_RE__VALUE 0x003f
+#define RE_2_RE__VALUE GENMASK(5, 0)
#define MANUFACTURER_ID 0x300
-#define MANUFACTURER_ID__VALUE 0x00ff
+#define MANUFACTURER_ID__VALUE GENMASK(7, 0)
#define DEVICE_ID 0x310
-#define DEVICE_ID__VALUE 0x00ff
+#define DEVICE_ID__VALUE GENMASK(7, 0)
#define DEVICE_PARAM_0 0x320
-#define DEVICE_PARAM_0__VALUE 0x00ff
+#define DEVICE_PARAM_0__VALUE GENMASK(7, 0)
#define DEVICE_PARAM_1 0x330
-#define DEVICE_PARAM_1__VALUE 0x00ff
+#define DEVICE_PARAM_1__VALUE GENMASK(7, 0)
#define DEVICE_PARAM_2 0x340
-#define DEVICE_PARAM_2__VALUE 0x00ff
+#define DEVICE_PARAM_2__VALUE GENMASK(7, 0)
#define LOGICAL_PAGE_DATA_SIZE 0x350
-#define LOGICAL_PAGE_DATA_SIZE__VALUE 0xffff
+#define LOGICAL_PAGE_DATA_SIZE__VALUE GENMASK(15, 0)
#define LOGICAL_PAGE_SPARE_SIZE 0x360
-#define LOGICAL_PAGE_SPARE_SIZE__VALUE 0xffff
+#define LOGICAL_PAGE_SPARE_SIZE__VALUE GENMASK(15, 0)
#define REVISION 0x370
-#define REVISION__VALUE 0xffff
+#define REVISION__VALUE GENMASK(15, 0)
#define ONFI_DEVICE_FEATURES 0x380
-#define ONFI_DEVICE_FEATURES__VALUE 0x003f
+#define ONFI_DEVICE_FEATURES__VALUE GENMASK(5, 0)
#define ONFI_OPTIONAL_COMMANDS 0x390
-#define ONFI_OPTIONAL_COMMANDS__VALUE 0x003f
+#define ONFI_OPTIONAL_COMMANDS__VALUE GENMASK(5, 0)
#define ONFI_TIMING_MODE 0x3a0
-#define ONFI_TIMING_MODE__VALUE 0x003f
+#define ONFI_TIMING_MODE__VALUE GENMASK(5, 0)
#define ONFI_PGM_CACHE_TIMING_MODE 0x3b0
-#define ONFI_PGM_CACHE_TIMING_MODE__VALUE 0x003f
+#define ONFI_PGM_CACHE_TIMING_MODE__VALUE GENMASK(5, 0)
#define ONFI_DEVICE_NO_OF_LUNS 0x3c0
-#define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS 0x00ff
-#define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE 0x0100
+#define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS GENMASK(7, 0)
+#define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE BIT(8)
#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L 0x3d0
-#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE 0xffff
+#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE GENMASK(15, 0)
#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U 0x3e0
-#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE 0xffff
-
-#define FEATURES 0x3f0
-#define FEATURES__N_BANKS 0x0003
-#define FEATURES__ECC_MAX_ERR 0x003c
-#define FEATURES__DMA 0x0040
-#define FEATURES__CMD_DMA 0x0080
-#define FEATURES__PARTITION 0x0100
-#define FEATURES__XDMA_SIDEBAND 0x0200
-#define FEATURES__GPREG 0x0400
-#define FEATURES__INDEX_ADDR 0x0800
+#define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE GENMASK(15, 0)
+
+#define FEATURES 0x3f0
+#define FEATURES__N_BANKS GENMASK(1, 0)
+#define FEATURES__ECC_MAX_ERR GENMASK(5, 2)
+#define FEATURES__DMA BIT(6)
+#define FEATURES__CMD_DMA BIT(7)
+#define FEATURES__PARTITION BIT(8)
+#define FEATURES__XDMA_SIDEBAND BIT(9)
+#define FEATURES__GPREG BIT(10)
+#define FEATURES__INDEX_ADDR BIT(11)
#define TRANSFER_MODE 0x400
-#define TRANSFER_MODE__VALUE 0x0003
-
-#define INTR_STATUS(__bank) (0x410 + ((__bank) * 0x50))
-#define INTR_EN(__bank) (0x420 + ((__bank) * 0x50))
-
-/*
- * Some versions of the IP have the ECC fixup handled in hardware. In this
- * configuration we only get interrupted when the error is uncorrectable.
- * Unfortunately this bit replaces INTR_STATUS__ECC_TRANSACTION_DONE from the
- * old IP.
- */
-#define INTR_STATUS__ECC_UNCOR_ERR 0x0001
-#define INTR_STATUS__ECC_TRANSACTION_DONE 0x0001
-#define INTR_STATUS__ECC_ERR 0x0002
-#define INTR_STATUS__DMA_CMD_COMP 0x0004
-#define INTR_STATUS__TIME_OUT 0x0008
-#define INTR_STATUS__PROGRAM_FAIL 0x0010
-#define INTR_STATUS__ERASE_FAIL 0x0020
-#define INTR_STATUS__LOAD_COMP 0x0040
-#define INTR_STATUS__PROGRAM_COMP 0x0080
-#define INTR_STATUS__ERASE_COMP 0x0100
-#define INTR_STATUS__PIPE_CPYBCK_CMD_COMP 0x0200
-#define INTR_STATUS__LOCKED_BLK 0x0400
-#define INTR_STATUS__UNSUP_CMD 0x0800
-#define INTR_STATUS__INT_ACT 0x1000
-#define INTR_STATUS__RST_COMP 0x2000
-#define INTR_STATUS__PIPE_CMD_ERR 0x4000
-#define INTR_STATUS__PAGE_XFER_INC 0x8000
-
-#define INTR_EN__ECC_TRANSACTION_DONE 0x0001
-#define INTR_EN__ECC_ERR 0x0002
-#define INTR_EN__DMA_CMD_COMP 0x0004
-#define INTR_EN__TIME_OUT 0x0008
-#define INTR_EN__PROGRAM_FAIL 0x0010
-#define INTR_EN__ERASE_FAIL 0x0020
-#define INTR_EN__LOAD_COMP 0x0040
-#define INTR_EN__PROGRAM_COMP 0x0080
-#define INTR_EN__ERASE_COMP 0x0100
-#define INTR_EN__PIPE_CPYBCK_CMD_COMP 0x0200
-#define INTR_EN__LOCKED_BLK 0x0400
-#define INTR_EN__UNSUP_CMD 0x0800
-#define INTR_EN__INT_ACT 0x1000
-#define INTR_EN__RST_COMP 0x2000
-#define INTR_EN__PIPE_CMD_ERR 0x4000
-#define INTR_EN__PAGE_XFER_INC 0x8000
-
-#define PAGE_CNT(__bank) (0x430 + ((__bank) * 0x50))
-#define ERR_PAGE_ADDR(__bank) (0x440 + ((__bank) * 0x50))
-#define ERR_BLOCK_ADDR(__bank) (0x450 + ((__bank) * 0x50))
-
-#define DATA_INTR 0x550
-#define DATA_INTR__WRITE_SPACE_AV 0x0001
-#define DATA_INTR__READ_DATA_AV 0x0002
-
-#define DATA_INTR_EN 0x560
-#define DATA_INTR_EN__WRITE_SPACE_AV 0x0001
-#define DATA_INTR_EN__READ_DATA_AV 0x0002
-
-#define GPREG_0 0x570
-#define GPREG_0__VALUE 0xffff
-
-#define GPREG_1 0x580
-#define GPREG_1__VALUE 0xffff
-
-#define GPREG_2 0x590
-#define GPREG_2__VALUE 0xffff
-
-#define GPREG_3 0x5a0
-#define GPREG_3__VALUE 0xffff
+#define TRANSFER_MODE__VALUE GENMASK(1, 0)
+
+#define INTR_STATUS(bank) (0x410 + (bank) * 0x50)
+#define INTR_EN(bank) (0x420 + (bank) * 0x50)
+/* bit[1:0] is used differently depending on IP version */
+#define INTR__ECC_UNCOR_ERR BIT(0) /* new IP */
+#define INTR__ECC_TRANSACTION_DONE BIT(0) /* old IP */
+#define INTR__ECC_ERR BIT(1) /* old IP */
+#define INTR__DMA_CMD_COMP BIT(2)
+#define INTR__TIME_OUT BIT(3)
+#define INTR__PROGRAM_FAIL BIT(4)
+#define INTR__ERASE_FAIL BIT(5)
+#define INTR__LOAD_COMP BIT(6)
+#define INTR__PROGRAM_COMP BIT(7)
+#define INTR__ERASE_COMP BIT(8)
+#define INTR__PIPE_CPYBCK_CMD_COMP BIT(9)
+#define INTR__LOCKED_BLK BIT(10)
+#define INTR__UNSUP_CMD BIT(11)
+#define INTR__INT_ACT BIT(12)
+#define INTR__RST_COMP BIT(13)
+#define INTR__PIPE_CMD_ERR BIT(14)
+#define INTR__PAGE_XFER_INC BIT(15)
+#define INTR__ERASED_PAGE BIT(16)
+
+#define PAGE_CNT(bank) (0x430 + (bank) * 0x50)
+#define ERR_PAGE_ADDR(bank) (0x440 + (bank) * 0x50)
+#define ERR_BLOCK_ADDR(bank) (0x450 + (bank) * 0x50)
#define ECC_THRESHOLD 0x600
-#define ECC_THRESHOLD__VALUE 0x03ff
+#define ECC_THRESHOLD__VALUE GENMASK(9, 0)
#define ECC_ERROR_BLOCK_ADDRESS 0x610
-#define ECC_ERROR_BLOCK_ADDRESS__VALUE 0xffff
+#define ECC_ERROR_BLOCK_ADDRESS__VALUE GENMASK(15, 0)
#define ECC_ERROR_PAGE_ADDRESS 0x620
-#define ECC_ERROR_PAGE_ADDRESS__VALUE 0x0fff
-#define ECC_ERROR_PAGE_ADDRESS__BANK 0xf000
+#define ECC_ERROR_PAGE_ADDRESS__VALUE GENMASK(11, 0)
+#define ECC_ERROR_PAGE_ADDRESS__BANK GENMASK(15, 12)
#define ECC_ERROR_ADDRESS 0x630
-#define ECC_ERROR_ADDRESS__OFFSET 0x0fff
-#define ECC_ERROR_ADDRESS__SECTOR_NR 0xf000
+#define ECC_ERROR_ADDRESS__OFFSET GENMASK(11, 0)
+#define ECC_ERROR_ADDRESS__SECTOR GENMASK(15, 12)
#define ERR_CORRECTION_INFO 0x640
-#define ERR_CORRECTION_INFO__BYTEMASK 0x00ff
-#define ERR_CORRECTION_INFO__DEVICE_NR 0x0f00
-#define ERR_CORRECTION_INFO__ERROR_TYPE 0x4000
-#define ERR_CORRECTION_INFO__LAST_ERR_INFO 0x8000
+#define ERR_CORRECTION_INFO__BYTE GENMASK(7, 0)
+#define ERR_CORRECTION_INFO__DEVICE GENMASK(11, 8)
+#define ERR_CORRECTION_INFO__UNCOR BIT(14)
+#define ERR_CORRECTION_INFO__LAST_ERR BIT(15)
+
+#define ECC_COR_INFO(bank) (0x650 + (bank) / 2 * 0x10)
+#define ECC_COR_INFO__SHIFT(bank) ((bank) % 2 * 8)
+#define ECC_COR_INFO__MAX_ERRORS GENMASK(6, 0)
+#define ECC_COR_INFO__UNCOR_ERR BIT(7)
+
+#define CFG_DATA_BLOCK_SIZE 0x6b0
+
+#define CFG_LAST_DATA_BLOCK_SIZE 0x6c0
+
+#define CFG_NUM_DATA_BLOCKS 0x6d0
+
+#define CFG_META_DATA_SIZE 0x6e0
#define DMA_ENABLE 0x700
-#define DMA_ENABLE__FLAG 0x0001
+#define DMA_ENABLE__FLAG BIT(0)
#define IGNORE_ECC_DONE 0x710
-#define IGNORE_ECC_DONE__FLAG 0x0001
+#define IGNORE_ECC_DONE__FLAG BIT(0)
#define DMA_INTR 0x720
-#define DMA_INTR__TARGET_ERROR 0x0001
-#define DMA_INTR__DESC_COMP_CHANNEL0 0x0002
-#define DMA_INTR__DESC_COMP_CHANNEL1 0x0004
-#define DMA_INTR__DESC_COMP_CHANNEL2 0x0008
-#define DMA_INTR__DESC_COMP_CHANNEL3 0x0010
-#define DMA_INTR__MEMCOPY_DESC_COMP 0x0020
-
#define DMA_INTR_EN 0x730
-#define DMA_INTR_EN__TARGET_ERROR 0x0001
-#define DMA_INTR_EN__DESC_COMP_CHANNEL0 0x0002
-#define DMA_INTR_EN__DESC_COMP_CHANNEL1 0x0004
-#define DMA_INTR_EN__DESC_COMP_CHANNEL2 0x0008
-#define DMA_INTR_EN__DESC_COMP_CHANNEL3 0x0010
-#define DMA_INTR_EN__MEMCOPY_DESC_COMP 0x0020
+#define DMA_INTR__TARGET_ERROR BIT(0)
+#define DMA_INTR__DESC_COMP_CHANNEL0 BIT(1)
+#define DMA_INTR__DESC_COMP_CHANNEL1 BIT(2)
+#define DMA_INTR__DESC_COMP_CHANNEL2 BIT(3)
+#define DMA_INTR__DESC_COMP_CHANNEL3 BIT(4)
+#define DMA_INTR__MEMCOPY_DESC_COMP BIT(5)
#define TARGET_ERR_ADDR_LO 0x740
-#define TARGET_ERR_ADDR_LO__VALUE 0xffff
+#define TARGET_ERR_ADDR_LO__VALUE GENMASK(15, 0)
#define TARGET_ERR_ADDR_HI 0x750
-#define TARGET_ERR_ADDR_HI__VALUE 0xffff
+#define TARGET_ERR_ADDR_HI__VALUE GENMASK(15, 0)
#define CHNL_ACTIVE 0x760
-#define CHNL_ACTIVE__CHANNEL0 0x0001
-#define CHNL_ACTIVE__CHANNEL1 0x0002
-#define CHNL_ACTIVE__CHANNEL2 0x0004
-#define CHNL_ACTIVE__CHANNEL3 0x0008
-
-#define ACTIVE_SRC_ID 0x800
-#define ACTIVE_SRC_ID__VALUE 0x00ff
-
-#define PTN_INTR 0x810
-#define PTN_INTR__CONFIG_ERROR 0x0001
-#define PTN_INTR__ACCESS_ERROR_BANK0 0x0002
-#define PTN_INTR__ACCESS_ERROR_BANK1 0x0004
-#define PTN_INTR__ACCESS_ERROR_BANK2 0x0008
-#define PTN_INTR__ACCESS_ERROR_BANK3 0x0010
-#define PTN_INTR__REG_ACCESS_ERROR 0x0020
-
-#define PTN_INTR_EN 0x820
-#define PTN_INTR_EN__CONFIG_ERROR 0x0001
-#define PTN_INTR_EN__ACCESS_ERROR_BANK0 0x0002
-#define PTN_INTR_EN__ACCESS_ERROR_BANK1 0x0004
-#define PTN_INTR_EN__ACCESS_ERROR_BANK2 0x0008
-#define PTN_INTR_EN__ACCESS_ERROR_BANK3 0x0010
-#define PTN_INTR_EN__REG_ACCESS_ERROR 0x0020
-
-#define PERM_SRC_ID(__bank) (0x830 + ((__bank) * 0x40))
-#define PERM_SRC_ID__SRCID 0x00ff
-#define PERM_SRC_ID__DIRECT_ACCESS_ACTIVE 0x0800
-#define PERM_SRC_ID__WRITE_ACTIVE 0x2000
-#define PERM_SRC_ID__READ_ACTIVE 0x4000
-#define PERM_SRC_ID__PARTITION_VALID 0x8000
-
-#define MIN_BLK_ADDR(__bank) (0x840 + ((__bank) * 0x40))
-#define MIN_BLK_ADDR__VALUE 0xffff
-
-#define MAX_BLK_ADDR(__bank) (0x850 + ((__bank) * 0x40))
-#define MAX_BLK_ADDR__VALUE 0xffff
-
-#define MIN_MAX_BANK(__bank) (0x860 + ((__bank) * 0x40))
-#define MIN_MAX_BANK__MIN_VALUE 0x0003
-#define MIN_MAX_BANK__MAX_VALUE 0x000c
-
-/* lld.h */
-#define GOOD_BLOCK 0
-#define DEFECTIVE_BLOCK 1
-#define READ_ERROR 2
-
-#define CLK_X 5
-#define CLK_MULTI 4
-
-/* spectraswconfig.h */
-#define CMD_DMA 0
-
-#define SPECTRA_PARTITION_ID 0
-/**** Block Table and Reserved Block Parameters *****/
-#define SPECTRA_START_BLOCK 3
-#define NUM_FREE_BLOCKS_GATE 30
-
-/* KBV - Updated to LNW scratch register address */
-#define SCRATCH_REG_ADDR CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR
-#define SCRATCH_REG_SIZE 64
-
-#define GLOB_HWCTL_DEFAULT_BLKS 2048
-
-#define CUSTOM_CONF_PARAMS 0
-
-#define INDEX_CTRL_REG 0x0
-#define INDEX_DATA_REG 0x10
-
-#define MODE_00 0x00000000
-#define MODE_01 0x04000000
-#define MODE_10 0x08000000
-#define MODE_11 0x0C000000
-
-
-#define DATA_TRANSFER_MODE 0
-#define PROTECTION_PER_BLOCK 1
-#define LOAD_WAIT_COUNT 2
-#define PROGRAM_WAIT_COUNT 3
-#define ERASE_WAIT_COUNT 4
-#define INT_MONITOR_CYCLE_COUNT 5
-#define READ_BUSY_PIN_ENABLED 6
-#define MULTIPLANE_OPERATION_SUPPORT 7
-#define PRE_FETCH_MODE 8
-#define CE_DONT_CARE_SUPPORT 9
-#define COPYBACK_SUPPORT 10
-#define CACHE_WRITE_SUPPORT 11
-#define CACHE_READ_SUPPORT 12
-#define NUM_PAGES_IN_BLOCK 13
-#define ECC_ENABLE_SELECT 14
-#define WRITE_ENABLE_2_READ_ENABLE 15
-#define ADDRESS_2_DATA 16
-#define READ_ENABLE_2_WRITE_ENABLE 17
-#define TWO_ROW_ADDRESS_CYCLES 18
-#define MULTIPLANE_ADDRESS_RESTRICT 19
-#define ACC_CLOCKS 20
-#define READ_WRITE_ENABLE_LOW_COUNT 21
-#define READ_WRITE_ENABLE_HIGH_COUNT 22
-
-#define ECC_SECTOR_SIZE 512
-
-#define DENALI_BUF_SIZE (NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE)
-
-struct nand_buf {
- int head;
- int tail;
- /* seprating dma_buf as buf can be used for status read purpose */
- uint8_t dma_buf[DENALI_BUF_SIZE] __aligned(64);
- uint8_t buf[DENALI_BUF_SIZE];
-};
+#define CHNL_ACTIVE__CHANNEL0 BIT(0)
+#define CHNL_ACTIVE__CHANNEL1 BIT(1)
+#define CHNL_ACTIVE__CHANNEL2 BIT(2)
+#define CHNL_ACTIVE__CHANNEL3 BIT(3)
-#define INTEL_CE4100 1
-#define INTEL_MRST 2
-#define DT 3
+struct udevice;
struct denali_nand_info {
struct nand_chip nand;
unsigned long clk_x_rate; /* bus interface clock rate */
- int flash_bank; /* currently selected chip */
- int status;
- int platform;
- struct nand_buf buf;
- struct device *dev;
- int total_used_banks;
- uint32_t block; /* stored for future use */
+ int active_bank; /* currently selected bank */
+ struct udevice *dev;
uint32_t page;
- void __iomem *flash_reg; /* Mapped io reg base address */
- void __iomem *flash_mem; /* Mapped io reg base address */
-
- /* elements used by ISR */
- /*struct completion complete;*/
-
- uint32_t irq_status;
- int irq_debug_array[32];
- int idx;
+ void __iomem *reg; /* Register Interface */
+ void __iomem *host; /* Host Data/Command Interface */
+ u32 irq_mask; /* interrupts we are waiting for */
+ u32 irq_status; /* interrupts that have happened */
int irq;
-
- uint32_t devnum; /* represent how many nands connected */
- uint32_t fwblks; /* represent how many blocks FW used */
- uint32_t totalblks;
- uint32_t blksperchip;
- uint32_t bbtskipbytes;
- uint32_t max_banks;
- unsigned int revision;
- unsigned int caps;
+ void *buf; /* for syndrome layout conversion */
+ dma_addr_t dma_addr;
+ int dma_avail; /* can support DMA? */
+ int devs_per_cs; /* devices connected in parallel */
+ int oob_skip_bytes; /* number of bytes reserved for BBM */
+ int max_banks;
+ unsigned int revision; /* IP revision */
+ unsigned int caps; /* IP capability (or quirk) */
+ const struct nand_ecc_caps *ecc_caps;
+ u32 (*host_read)(struct denali_nand_info *denali, u32 addr);
+ void (*host_write)(struct denali_nand_info *denali, u32 addr, u32 data);
+ void (*setup_dma)(struct denali_nand_info *denali, dma_addr_t dma_addr,
+ int page, int write);
};
#define DENALI_CAP_HW_ECC_FIXUP BIT(0)
#define DENALI_CAP_DMA_64BIT BIT(1)
+int denali_calc_ecc_bytes(int step_size, int strength);
int denali_init(struct denali_nand_info *denali);
#endif /* __DENALI_H__ */
diff --git a/drivers/mtd/nand/denali_dt.c b/drivers/mtd/nand/denali_dt.c
index 805c066b40..9d6cb09b42 100644
--- a/drivers/mtd/nand/denali_dt.c
+++ b/drivers/mtd/nand/denali_dt.c
@@ -16,21 +16,31 @@
struct denali_dt_data {
unsigned int revision;
unsigned int caps;
+ const struct nand_ecc_caps *ecc_caps;
};
+NAND_ECC_CAPS_SINGLE(denali_socfpga_ecc_caps, denali_calc_ecc_bytes,
+ 512, 8, 15);
static const struct denali_dt_data denali_socfpga_data = {
.caps = DENALI_CAP_HW_ECC_FIXUP,
+ .ecc_caps = &denali_socfpga_ecc_caps,
};
+NAND_ECC_CAPS_SINGLE(denali_uniphier_v5a_ecc_caps, denali_calc_ecc_bytes,
+ 1024, 8, 16, 24);
static const struct denali_dt_data denali_uniphier_v5a_data = {
.caps = DENALI_CAP_HW_ECC_FIXUP |
DENALI_CAP_DMA_64BIT,
+ .ecc_caps = &denali_uniphier_v5a_ecc_caps,
};
+NAND_ECC_CAPS_SINGLE(denali_uniphier_v5b_ecc_caps, denali_calc_ecc_bytes,
+ 1024, 8, 16);
static const struct denali_dt_data denali_uniphier_v5b_data = {
.revision = 0x0501,
.caps = DENALI_CAP_HW_ECC_FIXUP |
DENALI_CAP_DMA_64BIT,
+ .ecc_caps = &denali_uniphier_v5b_ecc_caps,
};
static const struct udevice_id denali_nand_dt_ids[] = {
@@ -61,19 +71,22 @@ static int denali_dt_probe(struct udevice *dev)
if (data) {
denali->revision = data->revision;
denali->caps = data->caps;
+ denali->ecc_caps = data->ecc_caps;
}
+ denali->dev = dev;
+
ret = dev_read_resource_byname(dev, "denali_reg", &res);
if (ret)
return ret;
- denali->flash_reg = devm_ioremap(dev, res.start, resource_size(&res));
+ denali->reg = devm_ioremap(dev, res.start, resource_size(&res));
ret = dev_read_resource_byname(dev, "nand_data", &res);
if (ret)
return ret;
- denali->flash_mem = devm_ioremap(dev, res.start, resource_size(&res));
+ denali->host = devm_ioremap(dev, res.start, resource_size(&res));
ret = clk_get_by_index(dev, 0, &clk);
if (ret)
diff --git a/drivers/mtd/nand/denali_spl.c b/drivers/mtd/nand/denali_spl.c
index c693032530..3cb9849735 100644
--- a/drivers/mtd/nand/denali_spl.c
+++ b/drivers/mtd/nand/denali_spl.c
@@ -11,6 +11,12 @@
#include <linux/mtd/nand.h>
#include "denali.h"
+#define DENALI_MAP01 (1 << 26) /* read/write pages in PIO */
+#define DENALI_MAP10 (2 << 26) /* high-level control plane */
+
+#define INDEX_CTRL_REG 0x0
+#define INDEX_DATA_REG 0x10
+
#define SPARE_ACCESS 0x41
#define MAIN_ACCESS 0x42
#define PIPELINE_ACCESS 0x2000
@@ -39,7 +45,7 @@ static int wait_for_irq(uint32_t irq_mask)
do {
intr_status = readl(denali_flash_reg + INTR_STATUS(flash_bank));
- if (intr_status & INTR_STATUS__ECC_UNCOR_ERR) {
+ if (intr_status & INTR__ECC_UNCOR_ERR) {
debug("Uncorrected ECC detected\n");
return -EBADMSG;
}
@@ -106,16 +112,16 @@ int denali_send_pipeline_cmd(int page, int ecc_en, int access_type)
addr = BANK(flash_bank) | page;
/* setup the acccess type */
- cmd = MODE_10 | addr;
+ cmd = DENALI_MAP10 | addr;
index_addr(cmd, access_type);
/* setup the pipeline command */
index_addr(cmd, PIPELINE_ACCESS | page_count);
- cmd = MODE_01 | addr;
+ cmd = DENALI_MAP01 | addr;
writel(cmd, denali_flash_mem + INDEX_CTRL_REG);
- return wait_for_irq(INTR_STATUS__LOAD_COMP);
+ return wait_for_irq(INTR__LOAD_COMP);
}
static int nand_read_oob(void *buf, int page)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 5bb4ea859b..aca32318d5 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -634,8 +634,7 @@ static void nand_command(struct mtd_info *mtd, unsigned int command,
chip->cmd_ctrl(mtd, page_addr, ctrl);
ctrl &= ~NAND_CTRL_CHANGE;
chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
- /* One more address cycle for devices > 32MiB */
- if (chip->chipsize > (32 << 20))
+ if (chip->options & NAND_ROW_ADDR_3)
chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
}
chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
@@ -729,8 +728,7 @@ static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
chip->cmd_ctrl(mtd, page_addr, ctrl);
chip->cmd_ctrl(mtd, page_addr >> 8,
NAND_NCE | NAND_ALE);
- /* One more address cycle for devices > 128MiB */
- if (chip->chipsize > (128 << 20))
+ if (chip->options & NAND_ROW_ADDR_3)
chip->cmd_ctrl(mtd, page_addr >> 16,
NAND_NCE | NAND_ALE);
}
@@ -901,7 +899,184 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
return status;
}
-#define BITS_PER_BYTE 8
+/**
+ * nand_reset_data_interface - Reset data interface and timings
+ * @chip: The NAND chip
+ * @chipnr: Internal die id
+ *
+ * Reset the Data interface and timings to ONFI mode 0.
+ *
+ * Returns 0 for success or negative error code otherwise.
+ */
+static int nand_reset_data_interface(struct nand_chip *chip, int chipnr)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ const struct nand_data_interface *conf;
+ int ret;
+
+ if (!chip->setup_data_interface)
+ return 0;
+
+ /*
+ * The ONFI specification says:
+ * "
+ * To transition from NV-DDR or NV-DDR2 to the SDR data
+ * interface, the host shall use the Reset (FFh) command
+ * using SDR timing mode 0. A device in any timing mode is
+ * required to recognize Reset (FFh) command issued in SDR
+ * timing mode 0.
+ * "
+ *
+ * Configure the data interface in SDR mode and set the
+ * timings to timing mode 0.
+ */
+
+ conf = nand_get_default_data_interface();
+ ret = chip->setup_data_interface(mtd, chipnr, conf);
+ if (ret)
+ pr_err("Failed to configure data interface to SDR timing mode 0\n");
+
+ return ret;
+}
+
+/**
+ * nand_setup_data_interface - Setup the best data interface and timings
+ * @chip: The NAND chip
+ * @chipnr: Internal die id
+ *
+ * Find and configure the best data interface and NAND timings supported by
+ * the chip and the driver.
+ * First tries to retrieve supported timing modes from ONFI information,
+ * and if the NAND chip does not support ONFI, relies on the
+ * ->onfi_timing_mode_default specified in the nand_ids table.
+ *
+ * Returns 0 for success or negative error code otherwise.
+ */
+static int nand_setup_data_interface(struct nand_chip *chip, int chipnr)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ int ret;
+
+ if (!chip->setup_data_interface || !chip->data_interface)
+ return 0;
+
+ /*
+ * Ensure the timing mode has been changed on the chip side
+ * before changing timings on the controller side.
+ */
+ if (chip->onfi_version) {
+ u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = {
+ chip->onfi_timing_mode_default,
+ };
+
+ ret = chip->onfi_set_features(mtd, chip,
+ ONFI_FEATURE_ADDR_TIMING_MODE,
+ tmode_param);
+ if (ret)
+ goto err;
+ }
+
+ ret = chip->setup_data_interface(mtd, chipnr, chip->data_interface);
+err:
+ return ret;
+}
+
+/**
+ * nand_init_data_interface - find the best data interface and timings
+ * @chip: The NAND chip
+ *
+ * Find the best data interface and NAND timings supported by the chip
+ * and the driver.
+ * First tries to retrieve supported timing modes from ONFI information,
+ * and if the NAND chip does not support ONFI, relies on the
+ * ->onfi_timing_mode_default specified in the nand_ids table. After this
+ * function nand_chip->data_interface is initialized with the best timing mode
+ * available.
+ *
+ * Returns 0 for success or negative error code otherwise.
+ */
+static int nand_init_data_interface(struct nand_chip *chip)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ int modes, mode, ret;
+
+ if (!chip->setup_data_interface)
+ return 0;
+
+ /*
+ * First try to identify the best timings from ONFI parameters and
+ * if the NAND does not support ONFI, fallback to the default ONFI
+ * timing mode.
+ */
+ modes = onfi_get_async_timing_mode(chip);
+ if (modes == ONFI_TIMING_MODE_UNKNOWN) {
+ if (!chip->onfi_timing_mode_default)
+ return 0;
+
+ modes = GENMASK(chip->onfi_timing_mode_default, 0);
+ }
+
+ chip->data_interface = kzalloc(sizeof(*chip->data_interface),
+ GFP_KERNEL);
+ if (!chip->data_interface)
+ return -ENOMEM;
+
+ for (mode = fls(modes) - 1; mode >= 0; mode--) {
+ ret = onfi_init_data_interface(chip, chip->data_interface,
+ NAND_SDR_IFACE, mode);
+ if (ret)
+ continue;
+
+ /* Pass -1 to only */
+ ret = chip->setup_data_interface(mtd,
+ NAND_DATA_IFACE_CHECK_ONLY,
+ chip->data_interface);
+ if (!ret) {
+ chip->onfi_timing_mode_default = mode;
+ break;
+ }
+ }
+
+ return 0;
+}
+
+static void __maybe_unused nand_release_data_interface(struct nand_chip *chip)
+{
+ kfree(chip->data_interface);
+}
+
+/**
+ * nand_reset - Reset and initialize a NAND device
+ * @chip: The NAND chip
+ * @chipnr: Internal die id
+ *
+ * Returns 0 for success or negative error code otherwise
+ */
+int nand_reset(struct nand_chip *chip, int chipnr)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ int ret;
+
+ ret = nand_reset_data_interface(chip, chipnr);
+ if (ret)
+ return ret;
+
+ /*
+ * The CS line has to be released before we can apply the new NAND
+ * interface settings, hence this weird ->select_chip() dance.
+ */
+ chip->select_chip(mtd, chipnr);
+ chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+ chip->select_chip(mtd, -1);
+
+ chip->select_chip(mtd, chipnr);
+ ret = nand_setup_data_interface(chip, chipnr);
+ chip->select_chip(mtd, -1);
+ if (ret)
+ return ret;
+
+ return 0;
+}
/**
* nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
@@ -1547,6 +1722,9 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
if (!aligned)
use_bufpoi = 1;
+ else if (chip->options & NAND_USE_BOUNCE_BUFFER)
+ use_bufpoi = !IS_ALIGNED((unsigned long)buf,
+ chip->buf_align);
else
use_bufpoi = 0;
@@ -1559,7 +1737,8 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
__func__, buf);
read_retry:
- chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
+ if (nand_standard_page_accessors(&chip->ecc))
+ chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
/*
* Now read the page into the buffer. Absent an error,
@@ -2235,12 +2414,11 @@ static int nand_write_page_syndrome(struct mtd_info *mtd,
* @buf: the data to write
* @oob_required: must write chip->oob_poi to OOB
* @page: page number to write
- * @cached: cached programming
* @raw: use _raw version of write_page
*/
static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
uint32_t offset, int data_len, const uint8_t *buf,
- int oob_required, int page, int cached, int raw)
+ int oob_required, int page, int raw)
{
int status, subpage;
@@ -2250,7 +2428,8 @@ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
else
subpage = 0;
- chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
+ if (nand_standard_page_accessors(&chip->ecc))
+ chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
if (unlikely(raw))
status = chip->ecc.write_page_raw(mtd, chip, buf,
@@ -2265,29 +2444,12 @@ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
if (status < 0)
return status;
- /*
- * Cached progamming disabled for now. Not sure if it's worth the
- * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
- */
- cached = 0;
-
- if (!cached || !NAND_HAS_CACHEPROG(chip)) {
-
+ if (nand_standard_page_accessors(&chip->ecc)) {
chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
- status = chip->waitfunc(mtd, chip);
- /*
- * See if operation failed and additional status checks are
- * available.
- */
- if ((status & NAND_STATUS_FAIL) && (chip->errstat))
- status = chip->errstat(mtd, chip, FL_WRITING, status,
- page);
+ status = chip->waitfunc(mtd, chip);
if (status & NAND_STATUS_FAIL)
return -EIO;
- } else {
- chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
- status = chip->waitfunc(mtd, chip);
}
return 0;
@@ -2362,7 +2524,7 @@ static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
struct mtd_oob_ops *ops)
{
- int chipnr, realpage, page, blockmask, column;
+ int chipnr, realpage, page, column;
struct nand_chip *chip = mtd_to_nand(mtd);
uint32_t writelen = ops->len;
@@ -2398,7 +2560,6 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
realpage = (int)(to >> chip->page_shift);
page = realpage & chip->pagemask;
- blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
/* Invalidate the page cache, when we write to the cached page */
if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
@@ -2413,13 +2574,15 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
while (1) {
int bytes = mtd->writesize;
- int cached = writelen > bytes && page != blockmask;
uint8_t *wbuf = buf;
int use_bufpoi;
int part_pagewr = (column || writelen < mtd->writesize);
if (part_pagewr)
use_bufpoi = 1;
+ else if (chip->options & NAND_USE_BOUNCE_BUFFER)
+ use_bufpoi = !IS_ALIGNED((unsigned long)buf,
+ chip->buf_align);
else
use_bufpoi = 0;
@@ -2428,7 +2591,6 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
if (use_bufpoi) {
pr_debug("%s: using write bounce buffer for buf@%p\n",
__func__, buf);
- cached = 0;
if (part_pagewr)
bytes = min_t(int, bytes - column, writelen);
chip->pagebuf = -1;
@@ -2446,7 +2608,7 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
memset(chip->oob_poi, 0xff, mtd->oobsize);
}
ret = chip->write_page(mtd, chip, column, bytes, wbuf,
- oob_required, page, cached,
+ oob_required, page,
(ops->mode == MTD_OPS_RAW));
if (ret)
break;
@@ -2582,10 +2744,6 @@ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
}
chipnr = (int)(to >> chip->chip_shift);
- chip->select_chip(mtd, chipnr);
-
- /* Shift to get page */
- page = (int)(to >> chip->page_shift);
/*
* Reset the chip. Some chips (like the Toshiba TC5832DC found in one
@@ -2593,7 +2751,12 @@ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
* if we don't do this. I have no clue why, but I seem to have 'fixed'
* it in the doc2000 driver in August 1999. dwmw2.
*/
- chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+ nand_reset(chip, chipnr);
+
+ chip->select_chip(mtd, chipnr);
+
+ /* Shift to get page */
+ page = (int)(to >> chip->page_shift);
/* Check, if it is write protected */
if (nand_check_wp(mtd)) {
@@ -2763,14 +2926,6 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
status = chip->erase(mtd, page & chip->pagemask);
- /*
- * See if operation failed and additional status checks are
- * available
- */
- if ((status & NAND_STATUS_FAIL) && (chip->errstat))
- status = chip->errstat(mtd, chip, FL_ERASING,
- status, page);
-
/* See if block erase succeeded */
if (status & NAND_STATUS_FAIL) {
pr_debug("%s: failed erase, page 0x%08x\n",
@@ -2972,6 +3127,8 @@ static void nand_set_defaults(struct nand_chip *chip, int busw)
init_waitqueue_head(&chip->controller->wq);
}
+ if (!chip->buf_align)
+ chip->buf_align = 1;
}
/* Sanitize ONFI strings so we can safely print them */
@@ -3607,14 +3764,14 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
int i, maf_idx;
u8 id_data[8];
- /* Select the device */
- chip->select_chip(mtd, 0);
-
/*
* Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
* after power-up.
*/
- chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+ nand_reset(chip, 0);
+
+ /* Select the device */
+ chip->select_chip(mtd, 0);
/* Send the command for reading device ID */
chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
@@ -3730,6 +3887,9 @@ ident_done:
chip->chip_shift += 32 - 1;
}
+ if (chip->chip_shift - chip->page_shift > 16)
+ chip->options |= NAND_ROW_ADDR_3;
+
chip->badblockbits = 8;
chip->erase = single_erase;
@@ -3819,6 +3979,9 @@ static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node)
if (ecc_step > 0)
chip->ecc.size = ecc_step;
+ if (fdt_getprop(blob, node, "nand-ecc-maximize", NULL))
+ chip->ecc.options |= NAND_ECC_MAXIMIZE;
+
return 0;
}
#else
@@ -3866,13 +4029,31 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips,
return PTR_ERR(type);
}
+ /* Initialize the ->data_interface field. */
+ ret = nand_init_data_interface(chip);
+ if (ret)
+ return ret;
+
+ /*
+ * Setup the data interface correctly on the chip and controller side.
+ * This explicit call to nand_setup_data_interface() is only required
+ * for the first die, because nand_reset() has been called before
+ * ->data_interface and ->default_onfi_timing_mode were set.
+ * For the other dies, nand_reset() will automatically switch to the
+ * best mode for us.
+ */
+ ret = nand_setup_data_interface(chip, 0);
+ if (ret)
+ return ret;
+
chip->select_chip(mtd, -1);
/* Check for a chip array */
for (i = 1; i < maxchips; i++) {
- chip->select_chip(mtd, i);
/* See comment in nand_get_flash_type for reset */
- chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+ nand_reset(chip, i);
+
+ chip->select_chip(mtd, i);
/* Send the command for reading device ID */
chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
/* Read manufacturer and device IDs */
@@ -3897,6 +4078,226 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips,
}
EXPORT_SYMBOL(nand_scan_ident);
+/**
+ * nand_check_ecc_caps - check the sanity of preset ECC settings
+ * @chip: nand chip info structure
+ * @caps: ECC caps info structure
+ * @oobavail: OOB size that the ECC engine can use
+ *
+ * When ECC step size and strength are already set, check if they are supported
+ * by the controller and the calculated ECC bytes fit within the chip's OOB.
+ * On success, the calculated ECC bytes is set.
+ */
+int nand_check_ecc_caps(struct nand_chip *chip,
+ const struct nand_ecc_caps *caps, int oobavail)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ const struct nand_ecc_step_info *stepinfo;
+ int preset_step = chip->ecc.size;
+ int preset_strength = chip->ecc.strength;
+ int nsteps, ecc_bytes;
+ int i, j;
+
+ if (WARN_ON(oobavail < 0))
+ return -EINVAL;
+
+ if (!preset_step || !preset_strength)
+ return -ENODATA;
+
+ nsteps = mtd->writesize / preset_step;
+
+ for (i = 0; i < caps->nstepinfos; i++) {
+ stepinfo = &caps->stepinfos[i];
+
+ if (stepinfo->stepsize != preset_step)
+ continue;
+
+ for (j = 0; j < stepinfo->nstrengths; j++) {
+ if (stepinfo->strengths[j] != preset_strength)
+ continue;
+
+ ecc_bytes = caps->calc_ecc_bytes(preset_step,
+ preset_strength);
+ if (WARN_ON_ONCE(ecc_bytes < 0))
+ return ecc_bytes;
+
+ if (ecc_bytes * nsteps > oobavail) {
+ pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB",
+ preset_step, preset_strength);
+ return -ENOSPC;
+ }
+
+ chip->ecc.bytes = ecc_bytes;
+
+ return 0;
+ }
+ }
+
+ pr_err("ECC (step, strength) = (%d, %d) not supported on this controller",
+ preset_step, preset_strength);
+
+ return -ENOTSUPP;
+}
+EXPORT_SYMBOL_GPL(nand_check_ecc_caps);
+
+/**
+ * nand_match_ecc_req - meet the chip's requirement with least ECC bytes
+ * @chip: nand chip info structure
+ * @caps: ECC engine caps info structure
+ * @oobavail: OOB size that the ECC engine can use
+ *
+ * If a chip's ECC requirement is provided, try to meet it with the least
+ * number of ECC bytes (i.e. with the largest number of OOB-free bytes).
+ * On success, the chosen ECC settings are set.
+ */
+int nand_match_ecc_req(struct nand_chip *chip,
+ const struct nand_ecc_caps *caps, int oobavail)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ const struct nand_ecc_step_info *stepinfo;
+ int req_step = chip->ecc_step_ds;
+ int req_strength = chip->ecc_strength_ds;
+ int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total;
+ int best_step, best_strength, best_ecc_bytes;
+ int best_ecc_bytes_total = INT_MAX;
+ int i, j;
+
+ if (WARN_ON(oobavail < 0))
+ return -EINVAL;
+
+ /* No information provided by the NAND chip */
+ if (!req_step || !req_strength)
+ return -ENOTSUPP;
+
+ /* number of correctable bits the chip requires in a page */
+ req_corr = mtd->writesize / req_step * req_strength;
+
+ for (i = 0; i < caps->nstepinfos; i++) {
+ stepinfo = &caps->stepinfos[i];
+ step_size = stepinfo->stepsize;
+
+ for (j = 0; j < stepinfo->nstrengths; j++) {
+ strength = stepinfo->strengths[j];
+
+ /*
+ * If both step size and strength are smaller than the
+ * chip's requirement, it is not easy to compare the
+ * resulted reliability.
+ */
+ if (step_size < req_step && strength < req_strength)
+ continue;
+
+ if (mtd->writesize % step_size)
+ continue;
+
+ nsteps = mtd->writesize / step_size;
+
+ ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
+ if (WARN_ON_ONCE(ecc_bytes < 0))
+ continue;
+ ecc_bytes_total = ecc_bytes * nsteps;
+
+ if (ecc_bytes_total > oobavail ||
+ strength * nsteps < req_corr)
+ continue;
+
+ /*
+ * We assume the best is to meet the chip's requrement
+ * with the least number of ECC bytes.
+ */
+ if (ecc_bytes_total < best_ecc_bytes_total) {
+ best_ecc_bytes_total = ecc_bytes_total;
+ best_step = step_size;
+ best_strength = strength;
+ best_ecc_bytes = ecc_bytes;
+ }
+ }
+ }
+
+ if (best_ecc_bytes_total == INT_MAX)
+ return -ENOTSUPP;
+
+ chip->ecc.size = best_step;
+ chip->ecc.strength = best_strength;
+ chip->ecc.bytes = best_ecc_bytes;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(nand_match_ecc_req);
+
+/**
+ * nand_maximize_ecc - choose the max ECC strength available
+ * @chip: nand chip info structure
+ * @caps: ECC engine caps info structure
+ * @oobavail: OOB size that the ECC engine can use
+ *
+ * Choose the max ECC strength that is supported on the controller, and can fit
+ * within the chip's OOB. On success, the chosen ECC settings are set.
+ */
+int nand_maximize_ecc(struct nand_chip *chip,
+ const struct nand_ecc_caps *caps, int oobavail)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ const struct nand_ecc_step_info *stepinfo;
+ int step_size, strength, nsteps, ecc_bytes, corr;
+ int best_corr = 0;
+ int best_step = 0;
+ int best_strength, best_ecc_bytes;
+ int i, j;
+
+ if (WARN_ON(oobavail < 0))
+ return -EINVAL;
+
+ for (i = 0; i < caps->nstepinfos; i++) {
+ stepinfo = &caps->stepinfos[i];
+ step_size = stepinfo->stepsize;
+
+ /* If chip->ecc.size is already set, respect it */
+ if (chip->ecc.size && step_size != chip->ecc.size)
+ continue;
+
+ for (j = 0; j < stepinfo->nstrengths; j++) {
+ strength = stepinfo->strengths[j];
+
+ if (mtd->writesize % step_size)
+ continue;
+
+ nsteps = mtd->writesize / step_size;
+
+ ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
+ if (WARN_ON_ONCE(ecc_bytes < 0))
+ continue;
+
+ if (ecc_bytes * nsteps > oobavail)
+ continue;
+
+ corr = strength * nsteps;
+
+ /*
+ * If the number of correctable bits is the same,
+ * bigger step_size has more reliability.
+ */
+ if (corr > best_corr ||
+ (corr == best_corr && step_size > best_step)) {
+ best_corr = corr;
+ best_step = step_size;
+ best_strength = strength;
+ best_ecc_bytes = ecc_bytes;
+ }
+ }
+ }
+
+ if (!best_corr)
+ return -ENOTSUPP;
+
+ chip->ecc.size = best_step;
+ chip->ecc.strength = best_strength;
+ chip->ecc.bytes = best_ecc_bytes;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(nand_maximize_ecc);
+
/*
* Check if the chip configuration meet the datasheet requirements.
@@ -3931,6 +4332,26 @@ static bool nand_ecc_strength_good(struct mtd_info *mtd)
return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
}
+static bool invalid_ecc_page_accessors(struct nand_chip *chip)
+{
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+
+ if (nand_standard_page_accessors(ecc))
+ return false;
+
+ /*
+ * NAND_ECC_CUSTOM_PAGE_ACCESS flag is set, make sure the NAND
+ * controller driver implements all the page accessors because
+ * default helpers are not suitable when the core does not
+ * send the READ0/PAGEPROG commands.
+ */
+ return (!ecc->read_page || !ecc->write_page ||
+ !ecc->read_page_raw || !ecc->write_page_raw ||
+ (NAND_HAS_SUBPAGE_READ(chip) && !ecc->read_subpage) ||
+ (NAND_HAS_SUBPAGE_WRITE(chip) && !ecc->write_subpage &&
+ ecc->hwctl && ecc->calculate));
+}
+
/**
* nand_scan_tail - [NAND Interface] Scan for the NAND device
* @mtd: MTD device structure
@@ -3950,6 +4371,11 @@ int nand_scan_tail(struct mtd_info *mtd)
BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
!(chip->bbt_options & NAND_BBT_USE_FLASH));
+ if (invalid_ecc_page_accessors(chip)) {
+ pr_err("Invalid ECC page accessors setup\n");
+ return -EINVAL;
+ }
+
if (!(chip->options & NAND_OWN_BUFFERS)) {
nbuf = kzalloc(sizeof(struct nand_buffers), GFP_KERNEL);
chip->buffers = nbuf;
diff --git a/drivers/mtd/nand/nand_timings.c b/drivers/mtd/nand/nand_timings.c
index 53dcbd323d..9935557291 100644
--- a/drivers/mtd/nand/nand_timings.c
+++ b/drivers/mtd/nand/nand_timings.c
@@ -12,228 +12,258 @@
#include <linux/kernel.h>
#include <linux/mtd/nand.h>
-static const struct nand_sdr_timings onfi_sdr_timings[] = {
+static const struct nand_data_interface onfi_sdr_timings[] = {
/* Mode 0 */
{
- .tADL_min = 200000,
- .tALH_min = 20000,
- .tALS_min = 50000,
- .tAR_min = 25000,
- .tCEA_max = 100000,
- .tCEH_min = 20000,
- .tCH_min = 20000,
- .tCHZ_max = 100000,
- .tCLH_min = 20000,
- .tCLR_min = 20000,
- .tCLS_min = 50000,
- .tCOH_min = 0,
- .tCS_min = 70000,
- .tDH_min = 20000,
- .tDS_min = 40000,
- .tFEAT_max = 1000000,
- .tIR_min = 10000,
- .tITC_max = 1000000,
- .tRC_min = 100000,
- .tREA_max = 40000,
- .tREH_min = 30000,
- .tRHOH_min = 0,
- .tRHW_min = 200000,
- .tRHZ_max = 200000,
- .tRLOH_min = 0,
- .tRP_min = 50000,
- .tRST_max = 250000000000ULL,
- .tWB_max = 200000,
- .tRR_min = 40000,
- .tWC_min = 100000,
- .tWH_min = 30000,
- .tWHR_min = 120000,
- .tWP_min = 50000,
- .tWW_min = 100000,
+ .type = NAND_SDR_IFACE,
+ .timings.sdr = {
+ .tCCS_min = 500000,
+ .tR_max = 200000000,
+ .tADL_min = 400000,
+ .tALH_min = 20000,
+ .tALS_min = 50000,
+ .tAR_min = 25000,
+ .tCEA_max = 100000,
+ .tCEH_min = 20000,
+ .tCH_min = 20000,
+ .tCHZ_max = 100000,
+ .tCLH_min = 20000,
+ .tCLR_min = 20000,
+ .tCLS_min = 50000,
+ .tCOH_min = 0,
+ .tCS_min = 70000,
+ .tDH_min = 20000,
+ .tDS_min = 40000,
+ .tFEAT_max = 1000000,
+ .tIR_min = 10000,
+ .tITC_max = 1000000,
+ .tRC_min = 100000,
+ .tREA_max = 40000,
+ .tREH_min = 30000,
+ .tRHOH_min = 0,
+ .tRHW_min = 200000,
+ .tRHZ_max = 200000,
+ .tRLOH_min = 0,
+ .tRP_min = 50000,
+ .tRR_min = 40000,
+ .tRST_max = 250000000000ULL,
+ .tWB_max = 200000,
+ .tWC_min = 100000,
+ .tWH_min = 30000,
+ .tWHR_min = 120000,
+ .tWP_min = 50000,
+ .tWW_min = 100000,
+ },
},
/* Mode 1 */
{
- .tADL_min = 100000,
- .tALH_min = 10000,
- .tALS_min = 25000,
- .tAR_min = 10000,
- .tCEA_max = 45000,
- .tCEH_min = 20000,
- .tCH_min = 10000,
- .tCHZ_max = 50000,
- .tCLH_min = 10000,
- .tCLR_min = 10000,
- .tCLS_min = 25000,
- .tCOH_min = 15000,
- .tCS_min = 35000,
- .tDH_min = 10000,
- .tDS_min = 20000,
- .tFEAT_max = 1000000,
- .tIR_min = 0,
- .tITC_max = 1000000,
- .tRC_min = 50000,
- .tREA_max = 30000,
- .tREH_min = 15000,
- .tRHOH_min = 15000,
- .tRHW_min = 100000,
- .tRHZ_max = 100000,
- .tRLOH_min = 0,
- .tRP_min = 25000,
- .tRR_min = 20000,
- .tRST_max = 500000000,
- .tWB_max = 100000,
- .tWC_min = 45000,
- .tWH_min = 15000,
- .tWHR_min = 80000,
- .tWP_min = 25000,
- .tWW_min = 100000,
+ .type = NAND_SDR_IFACE,
+ .timings.sdr = {
+ .tCCS_min = 500000,
+ .tR_max = 200000000,
+ .tADL_min = 400000,
+ .tALH_min = 10000,
+ .tALS_min = 25000,
+ .tAR_min = 10000,
+ .tCEA_max = 45000,
+ .tCEH_min = 20000,
+ .tCH_min = 10000,
+ .tCHZ_max = 50000,
+ .tCLH_min = 10000,
+ .tCLR_min = 10000,
+ .tCLS_min = 25000,
+ .tCOH_min = 15000,
+ .tCS_min = 35000,
+ .tDH_min = 10000,
+ .tDS_min = 20000,
+ .tFEAT_max = 1000000,
+ .tIR_min = 0,
+ .tITC_max = 1000000,
+ .tRC_min = 50000,
+ .tREA_max = 30000,
+ .tREH_min = 15000,
+ .tRHOH_min = 15000,
+ .tRHW_min = 100000,
+ .tRHZ_max = 100000,
+ .tRLOH_min = 0,
+ .tRP_min = 25000,
+ .tRR_min = 20000,
+ .tRST_max = 500000000,
+ .tWB_max = 100000,
+ .tWC_min = 45000,
+ .tWH_min = 15000,
+ .tWHR_min = 80000,
+ .tWP_min = 25000,
+ .tWW_min = 100000,
+ },
},
/* Mode 2 */
{
- .tADL_min = 100000,
- .tALH_min = 10000,
- .tALS_min = 15000,
- .tAR_min = 10000,
- .tCEA_max = 30000,
- .tCEH_min = 20000,
- .tCH_min = 10000,
- .tCHZ_max = 50000,
- .tCLH_min = 10000,
- .tCLR_min = 10000,
- .tCLS_min = 15000,
- .tCOH_min = 15000,
- .tCS_min = 25000,
- .tDH_min = 5000,
- .tDS_min = 15000,
- .tFEAT_max = 1000000,
- .tIR_min = 0,
- .tITC_max = 1000000,
- .tRC_min = 35000,
- .tREA_max = 25000,
- .tREH_min = 15000,
- .tRHOH_min = 15000,
- .tRHW_min = 100000,
- .tRHZ_max = 100000,
- .tRLOH_min = 0,
- .tRR_min = 20000,
- .tRST_max = 500000000,
- .tWB_max = 100000,
- .tRP_min = 17000,
- .tWC_min = 35000,
- .tWH_min = 15000,
- .tWHR_min = 80000,
- .tWP_min = 17000,
- .tWW_min = 100000,
+ .type = NAND_SDR_IFACE,
+ .timings.sdr = {
+ .tCCS_min = 500000,
+ .tR_max = 200000000,
+ .tADL_min = 400000,
+ .tALH_min = 10000,
+ .tALS_min = 15000,
+ .tAR_min = 10000,
+ .tCEA_max = 30000,
+ .tCEH_min = 20000,
+ .tCH_min = 10000,
+ .tCHZ_max = 50000,
+ .tCLH_min = 10000,
+ .tCLR_min = 10000,
+ .tCLS_min = 15000,
+ .tCOH_min = 15000,
+ .tCS_min = 25000,
+ .tDH_min = 5000,
+ .tDS_min = 15000,
+ .tFEAT_max = 1000000,
+ .tIR_min = 0,
+ .tITC_max = 1000000,
+ .tRC_min = 35000,
+ .tREA_max = 25000,
+ .tREH_min = 15000,
+ .tRHOH_min = 15000,
+ .tRHW_min = 100000,
+ .tRHZ_max = 100000,
+ .tRLOH_min = 0,
+ .tRR_min = 20000,
+ .tRST_max = 500000000,
+ .tWB_max = 100000,
+ .tRP_min = 17000,
+ .tWC_min = 35000,
+ .tWH_min = 15000,
+ .tWHR_min = 80000,
+ .tWP_min = 17000,
+ .tWW_min = 100000,
+ },
},
/* Mode 3 */
{
- .tADL_min = 100000,
- .tALH_min = 5000,
- .tALS_min = 10000,
- .tAR_min = 10000,
- .tCEA_max = 25000,
- .tCEH_min = 20000,
- .tCH_min = 5000,
- .tCHZ_max = 50000,
- .tCLH_min = 5000,
- .tCLR_min = 10000,
- .tCLS_min = 10000,
- .tCOH_min = 15000,
- .tCS_min = 25000,
- .tDH_min = 5000,
- .tDS_min = 10000,
- .tFEAT_max = 1000000,
- .tIR_min = 0,
- .tITC_max = 1000000,
- .tRC_min = 30000,
- .tREA_max = 20000,
- .tREH_min = 10000,
- .tRHOH_min = 15000,
- .tRHW_min = 100000,
- .tRHZ_max = 100000,
- .tRLOH_min = 0,
- .tRP_min = 15000,
- .tRR_min = 20000,
- .tRST_max = 500000000,
- .tWB_max = 100000,
- .tWC_min = 30000,
- .tWH_min = 10000,
- .tWHR_min = 80000,
- .tWP_min = 15000,
- .tWW_min = 100000,
+ .type = NAND_SDR_IFACE,
+ .timings.sdr = {
+ .tCCS_min = 500000,
+ .tR_max = 200000000,
+ .tADL_min = 400000,
+ .tALH_min = 5000,
+ .tALS_min = 10000,
+ .tAR_min = 10000,
+ .tCEA_max = 25000,
+ .tCEH_min = 20000,
+ .tCH_min = 5000,
+ .tCHZ_max = 50000,
+ .tCLH_min = 5000,
+ .tCLR_min = 10000,
+ .tCLS_min = 10000,
+ .tCOH_min = 15000,
+ .tCS_min = 25000,
+ .tDH_min = 5000,
+ .tDS_min = 10000,
+ .tFEAT_max = 1000000,
+ .tIR_min = 0,
+ .tITC_max = 1000000,
+ .tRC_min = 30000,
+ .tREA_max = 20000,
+ .tREH_min = 10000,
+ .tRHOH_min = 15000,
+ .tRHW_min = 100000,
+ .tRHZ_max = 100000,
+ .tRLOH_min = 0,
+ .tRP_min = 15000,
+ .tRR_min = 20000,
+ .tRST_max = 500000000,
+ .tWB_max = 100000,
+ .tWC_min = 30000,
+ .tWH_min = 10000,
+ .tWHR_min = 80000,
+ .tWP_min = 15000,
+ .tWW_min = 100000,
+ },
},
/* Mode 4 */
{
- .tADL_min = 70000,
- .tALH_min = 5000,
- .tALS_min = 10000,
- .tAR_min = 10000,
- .tCEA_max = 25000,
- .tCEH_min = 20000,
- .tCH_min = 5000,
- .tCHZ_max = 30000,
- .tCLH_min = 5000,
- .tCLR_min = 10000,
- .tCLS_min = 10000,
- .tCOH_min = 15000,
- .tCS_min = 20000,
- .tDH_min = 5000,
- .tDS_min = 10000,
- .tFEAT_max = 1000000,
- .tIR_min = 0,
- .tITC_max = 1000000,
- .tRC_min = 25000,
- .tREA_max = 20000,
- .tREH_min = 10000,
- .tRHOH_min = 15000,
- .tRHW_min = 100000,
- .tRHZ_max = 100000,
- .tRLOH_min = 5000,
- .tRP_min = 12000,
- .tRR_min = 20000,
- .tRST_max = 500000000,
- .tWB_max = 100000,
- .tWC_min = 25000,
- .tWH_min = 10000,
- .tWHR_min = 80000,
- .tWP_min = 12000,
- .tWW_min = 100000,
+ .type = NAND_SDR_IFACE,
+ .timings.sdr = {
+ .tCCS_min = 500000,
+ .tR_max = 200000000,
+ .tADL_min = 400000,
+ .tALH_min = 5000,
+ .tALS_min = 10000,
+ .tAR_min = 10000,
+ .tCEA_max = 25000,
+ .tCEH_min = 20000,
+ .tCH_min = 5000,
+ .tCHZ_max = 30000,
+ .tCLH_min = 5000,
+ .tCLR_min = 10000,
+ .tCLS_min = 10000,
+ .tCOH_min = 15000,
+ .tCS_min = 20000,
+ .tDH_min = 5000,
+ .tDS_min = 10000,
+ .tFEAT_max = 1000000,
+ .tIR_min = 0,
+ .tITC_max = 1000000,
+ .tRC_min = 25000,
+ .tREA_max = 20000,
+ .tREH_min = 10000,
+ .tRHOH_min = 15000,
+ .tRHW_min = 100000,
+ .tRHZ_max = 100000,
+ .tRLOH_min = 5000,
+ .tRP_min = 12000,
+ .tRR_min = 20000,
+ .tRST_max = 500000000,
+ .tWB_max = 100000,
+ .tWC_min = 25000,
+ .tWH_min = 10000,
+ .tWHR_min = 80000,
+ .tWP_min = 12000,
+ .tWW_min = 100000,
+ },
},
/* Mode 5 */
{
- .tADL_min = 70000,
- .tALH_min = 5000,
- .tALS_min = 10000,
- .tAR_min = 10000,
- .tCEA_max = 25000,
- .tCEH_min = 20000,
- .tCH_min = 5000,
- .tCHZ_max = 30000,
- .tCLH_min = 5000,
- .tCLR_min = 10000,
- .tCLS_min = 10000,
- .tCOH_min = 15000,
- .tCS_min = 15000,
- .tDH_min = 5000,
- .tDS_min = 7000,
- .tFEAT_max = 1000000,
- .tIR_min = 0,
- .tITC_max = 1000000,
- .tRC_min = 20000,
- .tREA_max = 16000,
- .tREH_min = 7000,
- .tRHOH_min = 15000,
- .tRHW_min = 100000,
- .tRHZ_max = 100000,
- .tRLOH_min = 5000,
- .tRP_min = 10000,
- .tRR_min = 20000,
- .tRST_max = 500000000,
- .tWB_max = 100000,
- .tWC_min = 20000,
- .tWH_min = 7000,
- .tWHR_min = 80000,
- .tWP_min = 10000,
- .tWW_min = 100000,
+ .type = NAND_SDR_IFACE,
+ .timings.sdr = {
+ .tCCS_min = 500000,
+ .tR_max = 200000000,
+ .tADL_min = 400000,
+ .tALH_min = 5000,
+ .tALS_min = 10000,
+ .tAR_min = 10000,
+ .tCEA_max = 25000,
+ .tCEH_min = 20000,
+ .tCH_min = 5000,
+ .tCHZ_max = 30000,
+ .tCLH_min = 5000,
+ .tCLR_min = 10000,
+ .tCLS_min = 10000,
+ .tCOH_min = 15000,
+ .tCS_min = 15000,
+ .tDH_min = 5000,
+ .tDS_min = 7000,
+ .tFEAT_max = 1000000,
+ .tIR_min = 0,
+ .tITC_max = 1000000,
+ .tRC_min = 20000,
+ .tREA_max = 16000,
+ .tREH_min = 7000,
+ .tRHOH_min = 15000,
+ .tRHW_min = 100000,
+ .tRHZ_max = 100000,
+ .tRLOH_min = 5000,
+ .tRP_min = 10000,
+ .tRR_min = 20000,
+ .tRST_max = 500000000,
+ .tWB_max = 100000,
+ .tWC_min = 20000,
+ .tWH_min = 7000,
+ .tWHR_min = 80000,
+ .tWP_min = 10000,
+ .tWW_min = 100000,
+ },
},
};
@@ -247,6 +277,58 @@ const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode)
if (mode < 0 || mode >= ARRAY_SIZE(onfi_sdr_timings))
return ERR_PTR(-EINVAL);
- return &onfi_sdr_timings[mode];
+ return &onfi_sdr_timings[mode].timings.sdr;
}
EXPORT_SYMBOL(onfi_async_timing_mode_to_sdr_timings);
+
+/**
+ * onfi_init_data_interface - [NAND Interface] Initialize a data interface from
+ * given ONFI mode
+ * @iface: The data interface to be initialized
+ * @mode: The ONFI timing mode
+ */
+int onfi_init_data_interface(struct nand_chip *chip,
+ struct nand_data_interface *iface,
+ enum nand_data_interface_type type,
+ int timing_mode)
+{
+ if (type != NAND_SDR_IFACE)
+ return -EINVAL;
+
+ if (timing_mode < 0 || timing_mode >= ARRAY_SIZE(onfi_sdr_timings))
+ return -EINVAL;
+
+ *iface = onfi_sdr_timings[timing_mode];
+
+ /*
+ * Initialize timings that cannot be deduced from timing mode:
+ * tR, tPROG, tCCS, ...
+ * These information are part of the ONFI parameter page.
+ */
+ if (chip->onfi_version) {
+ struct nand_onfi_params *params = &chip->onfi_params;
+ struct nand_sdr_timings *timings = &iface->timings.sdr;
+
+ /* microseconds -> picoseconds */
+ timings->tPROG_max = 1000000ULL * le16_to_cpu(params->t_prog);
+ timings->tBERS_max = 1000000ULL * le16_to_cpu(params->t_bers);
+ timings->tR_max = 1000000ULL * le16_to_cpu(params->t_r);
+
+ /* nanoseconds -> picoseconds */
+ timings->tCCS_min = 1000UL * le16_to_cpu(params->t_ccs);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(onfi_init_data_interface);
+
+/**
+ * nand_get_default_data_interface - [NAND Interface] Retrieve NAND
+ * data interface for mode 0. This is used as default timing after
+ * reset.
+ */
+const struct nand_data_interface *nand_get_default_data_interface(void)
+{
+ return &onfi_sdr_timings[0];
+}
+EXPORT_SYMBOL(nand_get_default_data_interface);
diff --git a/drivers/pci/pci_msc01.c b/drivers/pci/pci_msc01.c
index 284ffa09b6..a1b9116e4d 100644
--- a/drivers/pci/pci_msc01.c
+++ b/drivers/pci/pci_msc01.c
@@ -1,6 +1,6 @@
/*
* Copyright (C) 2013 Imagination Technologies
- * Author: Paul Burton <paul.burton@imgtec.com>
+ * Author: Paul Burton <paul.burton@mips.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c
index fd3da922a6..dd7b9cddb1 100644
--- a/drivers/usb/gadget/f_sdp.c
+++ b/drivers/usb/gadget/f_sdp.c
@@ -32,6 +32,7 @@
#include <spl.h>
#include <image.h>
#include <imximage.h>
+#include <watchdog.h>
#define HID_REPORT_ID_MASK 0x000000ff
@@ -602,6 +603,8 @@ int sdp_init(int controller_index)
puts("\rCTRL+C - Operation aborted.\n");
return 1;
}
+
+ WATCHDOG_RESET();
usb_gadget_handle_interrupts(controller_index);
}
@@ -712,6 +715,7 @@ void sdp_handle(int controller_index)
return;
}
+ WATCHDOG_RESET();
usb_gadget_handle_interrupts(controller_index);
sdp_handle_in_ep();
diff --git a/drivers/usb/gadget/storage_common.c b/drivers/usb/gadget/storage_common.c
index b6df130a14..4d5a9a8c42 100644
--- a/drivers/usb/gadget/storage_common.c
+++ b/drivers/usb/gadget/storage_common.c
@@ -309,7 +309,7 @@ static struct fsg_lun *fsg_lun_from_dev(struct device *dev)
#define FSG_NUM_BUFFERS 2
/* Default size of buffer length. */
-#define FSG_BUFLEN ((u32)16384)
+#define FSG_BUFLEN ((u32)131072)
/* Maximal number of LUNs supported in mass storage function */
#define FSG_MAX_LUNS 8
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 5264475fa5..c79f866cf1 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -47,6 +47,14 @@ config USB_XHCI_ROCKCHIP
help
Enables support for the on-chip xHCI controller on Rockchip SoCs.
+config USB_XHCI_RCAR
+ bool "Renesas RCar USB 3.0 support"
+ default y
+ depends on ARCH_RMOBILE
+ help
+ Choose this option to add support for USB 3.0 driver on Renesas
+ RCar Gen3 SoCs.
+
config USB_XHCI_STI
bool "Support for STMicroelectronics STiH407 family on-chip xHCI USB controller"
depends on ARCH_STI
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 83903fcf99..79df888fce 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
obj-$(CONFIG_USB_XHCI_MVEBU) += xhci-mvebu.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
+obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o
obj-$(CONFIG_USB_XHCI_STI) += dwc3-sti-glue.o
# designware
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index be3e842dcc..2582bf36eb 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -210,9 +210,6 @@ static int ehci_shutdown(struct ehci_ctrl *ctrl)
uint32_t cmd, reg;
int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams));
- if (!ctrl || !ctrl->hcor)
- return -EINVAL;
-
cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
/* If not run, directly return */
if (!(cmd & CMD_RUN))
@@ -595,8 +592,9 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
* dangerous operation, it's responsibility of the calling
* code to make sure enough space is reserved.
*/
- invalidate_dcache_range((unsigned long)buffer,
- ALIGN((unsigned long)buffer + length, ARCH_DMA_MINALIGN));
+ if (buffer != NULL && length > 0)
+ invalidate_dcache_range((unsigned long)buffer,
+ ALIGN((unsigned long)buffer + length, ARCH_DMA_MINALIGN));
/* Check that the TD processing happened */
if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
@@ -1112,6 +1110,8 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
if (rc)
return rc;
+ if (!ctrl->hccr || !ctrl->hcor)
+ return -1;
if (init == USB_INIT_DEVICE)
goto done;
@@ -1613,11 +1613,14 @@ int ehci_register(struct udevice *dev, struct ehci_hccr *hccr,
{
struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
struct ehci_ctrl *ctrl = dev_get_priv(dev);
- int ret;
+ int ret = -1;
debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p, init=%d\n", __func__,
dev->name, ctrl, hccr, hcor, init);
+ if (!ctrl || !hccr || !hcor)
+ goto err;
+
priv->desc_before_addr = true;
ehci_setup_ops(ctrl, ops);
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
index 7c39becd24..18692b732e 100644
--- a/drivers/usb/host/ehci.h
+++ b/drivers/usb/host/ehci.h
@@ -101,11 +101,11 @@ struct usb_linux_config_descriptor {
} __attribute__ ((packed));
#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
-#define ehci_readl(x) cpu_to_be32(readl(x))
-#define ehci_writel(a, b) writel(cpu_to_be32(b), a)
+#define ehci_readl(x) be32_to_cpu(__raw_readl(x))
+#define ehci_writel(a, b) __raw_writel(cpu_to_be32(b), a)
#else
-#define ehci_readl(x) cpu_to_le32(readl(x))
-#define ehci_writel(a, b) writel(cpu_to_le32(b), a)
+#define ehci_readl(x) readl(x)
+#define ehci_writel(a, b) writel(b, a)
#endif
#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c
index 6ef51906c2..28d2bc8454 100644
--- a/drivers/usb/host/r8a66597-hcd.c
+++ b/drivers/usb/host/r8a66597-hcd.c
@@ -82,6 +82,7 @@ static int r8a66597_clock_enable(struct r8a66597 *r8a66597)
}
} while ((tmp & USBE) != USBE);
r8a66597_bclr(r8a66597, USBE, SYSCFG0);
+#if !defined(CONFIG_RZA_USB)
r8a66597_mdfy(r8a66597, CONFIG_R8A66597_XTAL, XTAL, SYSCFG0);
i = 0;
@@ -94,6 +95,20 @@ static int r8a66597_clock_enable(struct r8a66597 *r8a66597)
return -1;
}
} while ((tmp & SCKE) != SCKE);
+#else
+ /*
+ * RZ/A Only:
+ * Bits XTAL(UCKSEL) and UPLLE in SYSCFG0 for USB0 controls both USB0
+ * and USB1, so we must always set the USB0 register
+ */
+#if (CONFIG_R8A66597_XTAL == 1)
+ setbits(le16, R8A66597_BASE0, XTAL);
+#endif
+ mdelay(1);
+ setbits(le16, R8A66597_BASE0, UPLLE);
+ mdelay(1);
+ r8a66597_bset(r8a66597, SUSPM, SUSPMODE0);
+#endif /* CONFIG_RZA_USB */
#endif /* #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) */
return 0;
@@ -101,6 +116,7 @@ static int r8a66597_clock_enable(struct r8a66597 *r8a66597)
static void r8a66597_clock_disable(struct r8a66597 *r8a66597)
{
+#if !defined(CONFIG_RZA_USB)
r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
udelay(1);
#if !defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
@@ -108,6 +124,15 @@ static void r8a66597_clock_disable(struct r8a66597 *r8a66597)
r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
r8a66597_bclr(r8a66597, USBE, SYSCFG0);
#endif
+#else
+ r8a66597_bclr(r8a66597, SUSPM, SUSPMODE0);
+
+ clrbits(le16, R8A66597_BASE0, UPLLE);
+ mdelay(1);
+ r8a66597_bclr(r8a66597, USBE, SYSCFG0);
+ mdelay(1);
+
+#endif
}
static void r8a66597_enable_port(struct r8a66597 *r8a66597, int port)
@@ -118,7 +143,9 @@ static void r8a66597_enable_port(struct r8a66597 *r8a66597, int port)
r8a66597_bset(r8a66597, val, get_syscfg_reg(port));
r8a66597_bset(r8a66597, HSE, get_syscfg_reg(port));
+#if !defined(CONFIG_RZA_USB)
r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR, get_dmacfg_reg(port));
+#endif
}
static void r8a66597_disable_port(struct r8a66597 *r8a66597, int port)
@@ -148,7 +175,9 @@ static int enable_controller(struct r8a66597 *r8a66597)
if (ret < 0)
return ret;
+#if !defined(CONFIG_RZA_USB)
r8a66597_bset(r8a66597, CONFIG_R8A66597_LDRV & LDRV, PINCFG);
+#endif
r8a66597_bset(r8a66597, USBE, SYSCFG0);
r8a66597_bset(r8a66597, INTL, SOFCFG);
@@ -266,12 +295,30 @@ static int send_setup_packet(struct r8a66597 *r8a66597, struct usb_device *dev,
unsigned long setup_addr = USBREQ;
u16 intsts1;
int timeout = 3000;
+#if defined(CONFIG_RZA_USB)
+ u16 dcpctr;
+ int timeout2 = 10000;
+#endif
u16 devsel = setup->request == USB_REQ_SET_ADDRESS ? 0 : dev->devnum;
r8a66597_write(r8a66597, make_devsel(devsel) |
(8 << dev->maxpacketsize), DCPMAXP);
r8a66597_write(r8a66597, ~(SIGN | SACK), INTSTS1);
+#if defined(CONFIG_RZA_USB)
+ dcpctr = r8a66597_read(r8a66597, DCPCTR);
+ if ((dcpctr & PID) == PID_BUF) {
+ timeout2 = 10000;
+ while (!(dcpctr & BSTS)) {
+ dcpctr = r8a66597_read(r8a66597, DCPCTR);
+ if (timeout2-- < 0) {
+ printf("DCPCTR clear timeout!\n");
+ break;
+ }
+ }
+ }
+#endif
+
for (i = 0; i < 4; i++) {
r8a66597_write(r8a66597, le16_to_cpu(p[i]), setup_addr);
setup_addr += 2;
diff --git a/drivers/usb/host/r8a66597.h b/drivers/usb/host/r8a66597.h
index 67dc3c4588..baa16605d8 100644
--- a/drivers/usb/host/r8a66597.h
+++ b/drivers/usb/host/r8a66597.h
@@ -87,8 +87,10 @@
#define DEVADD8 0xE0
#define DEVADD9 0xE2
#define DEVADDA 0xE4
+#define SUSPMODE0 0x102 /* RZ/A only */
/* System Configuration Control Register */
+#if !defined(CONFIG_RZA_USB)
#define XTAL 0xC000 /* b15-14: Crystal selection */
#define XTAL48 0x8000 /* 48MHz */
#define XTAL24 0x4000 /* 24MHz */
@@ -98,10 +100,17 @@
#define SCKE 0x0400 /* b10: USB clock enable */
#define PCSDIS 0x0200 /* b9: not CS wakeup */
#define LPSME 0x0100 /* b8: Low power sleep mode */
+#endif
#define HSE 0x0080 /* b7: Hi-speed enable */
#define DCFM 0x0040 /* b6: Controller function select */
#define DRPD 0x0020 /* b5: D+/- pull down control */
#define DPRPU 0x0010 /* b4: D+ pull up control */
+#if defined(CONFIG_RZA_USB)
+#define XTAL 0x0004 /* b2: Crystal selection */
+#define XTAL12 0x0004 /* 12MHz */
+#define XTAL48 0x0000 /* 48MHz */
+#define UPLLE 0x0002 /* b1: internal PLL control */
+#endif
#define USBE 0x0001 /* b0: USB module operation enable */
/* System Configuration Status Register */
@@ -173,10 +182,15 @@
#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
#define MBW 0x0800
#else
+#if !defined(CONFIG_RZA_USB)
#define MBW 0x0400 /* b10: Maximum bit width for FIFO access */
+#else
+#define MBW 0x0800 /* b10: Maximum bit width for FIFO access */
+#endif
#endif
#define MBW_8 0x0000 /* 8bit */
#define MBW_16 0x0400 /* 16bit */
+#define MBW_32 0x0800 /* 32bit */
#define BIGEND 0x0100 /* b8: Big endian mode */
#define BYTE_LITTLE 0x0000 /* little dendian */
#define BYTE_BIG 0x0100 /* big endifan */
@@ -379,6 +393,9 @@
#define USBSPD 0x00C0
#define RTPORT 0x0001
+/* Suspend Mode Register */
+#define SUSPM 0x4000 /* b14: Suspend */
+
#define R8A66597_MAX_NUM_PIPE 10
#define R8A66597_BUF_BSIZE 8
#define R8A66597_MAX_DEVICE 10
@@ -419,7 +436,7 @@ static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
int len)
{
int i;
-#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
+#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) || defined(CONFIG_RZA_USB)
unsigned long fifoaddr = r8a66597->reg + offset;
unsigned long count;
unsigned long *p = buf;
@@ -453,7 +470,7 @@ static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
{
int i;
unsigned long fifoaddr = r8a66597->reg + offset;
-#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
+#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) || defined(CONFIG_RZA_USB)
unsigned long count;
unsigned char *pb;
unsigned long *p = buf;
diff --git a/drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h b/drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h
new file mode 100644
index 0000000000..f0f48a3354
--- /dev/null
+++ b/drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h
@@ -0,0 +1,643 @@
+/*
+ * Renesas RCar xHCI controller firmware version 3
+ *
+ * Copyright (c) 2014, Renesas Electronics Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in binary form, without modification, are permitted
+ * provided that the following conditions are met:
+ *
+ * 1. Redistribution in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 2. The name of Renesas Electronics Corporation may not be used to endorse or
+ * promote products derived from this software without specific prior written
+ * permission.
+ * 3. Reverse engineering, decompilation, or disassembly of this software is
+ * not permitted.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS ELECTRONICS CORPORATION DISCLAIMS
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NONINFRINGEMENT OF THIRD PARTY RIGHTS. IN NO EVENT SHALL RENESAS ELECTRONICS
+ * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file is generated from the firmware blob r8a779x_usb3_v3.dlmem
+ * with associated license file LICENCE.r8a779x_usb3, both taken from
+ * linux-firmware.git [1] as of:
+ *
+ * commit 7c3dfc0bb21bf717dc19a6b677a866aef8b70c35
+ * Author: Yoshihiro Shimoda
+ * Date: Wed Aug 10 19:56:39 2016 +0900
+ *
+ * usb: host: xhci-rcar: update firmware for R-Car H3 and M3-W
+ *
+ * To generate the content of the array below, use ie. the following command:
+ * $ hexdump -v -e '/4 "0x%08x, "' r8a779x_usb3_v3.dlmem | \
+ * sed "s@\(.\{47\}\) @\1\n@g"
+ *
+ * [1] git://git.kernel.org/pub/scm/linux/kernel/git/dwmw2/linux-firmware.git
+ */
+
+#ifndef __FIRMWARE_R8A779X_USB3_V3__
+#define __FIRMWARE_R8A779X_USB3_V3__
+
+static const u32 firmware_r8a779x_usb3_v3[] = {
+ 0xf4c455aa, 0x00d20014, 0x00000000, 0x23dc00e8,
+ 0x00000000, 0x1a5c2007, 0x0001ff63, 0x001eff80,
+ 0x0001ff23, 0x007f1a44, 0xff631a5c, 0xff800001,
+ 0xff2301e2, 0x1a440001, 0x0780007f, 0x06250061,
+ 0x00021e74, 0x40002e05, 0x40002e05, 0x8000f625,
+ 0xdc90062a, 0x556f0000, 0xdd14062a, 0x17040000,
+ 0x5573d612, 0x15ea062a, 0x57650000, 0x16c285d5,
+ 0x060200f0, 0x1deaffe0, 0xe4251724, 0x05d9128d,
+ 0x10001620, 0xe4251764, 0xd6151724, 0x1db1129f,
+ 0x8625ef25, 0x0088063f, 0x32010002, 0x3200007d,
+ 0x0392ffbe, 0x05e251e0, 0xffbe3200, 0x51e003e4,
+ 0x520005ba, 0xef2515f5, 0x063f8625, 0x000200ae,
+ 0x007d3200, 0xd6151724, 0x05b9129d, 0x0d8cffbe,
+ 0xd61417c4, 0xd6179e24, 0x000037d3, 0x4ad0ffbe,
+ 0x06405201, 0x26e6007f, 0x0f9a0631, 0x063f0000,
+ 0x00000e64, 0x0782007f, 0x8f250061, 0xee248019,
+ 0x30030000, 0x00f4063f, 0x00710002, 0x80158725,
+ 0x00d00626, 0x3a010002, 0x0108063f, 0x00700002,
+ 0x0505f01d, 0x7e3d0501, 0x7d030008, 0x80001640,
+ 0x150d1511, 0xf6241509, 0x0509fd00, 0x1503121f,
+ 0x801d7725, 0x00013723, 0x1764121e, 0x063f5c11,
+ 0x0002013e, 0x0642006e, 0x0780007f, 0xe8060061,
+ 0x0d0cffbe, 0x0001577d, 0x007f0640, 0x0d0a07be,
+ 0x17201624, 0x9c00062a, 0x118a03ff, 0x17210764,
+ 0xffec0602, 0xf6240d89, 0x35011720, 0x12820503,
+ 0x1505125d, 0x1724007f, 0x11461721, 0xf6241db2,
+ 0x55021720, 0x12c2100a, 0x3f6211c4, 0x160a172d,
+ 0x15030001, 0x17295724, 0x05bb51e2, 0x17250764,
+ 0x17251724, 0xeeee062a, 0x12c2eeee, 0x576211c4,
+ 0x007f172d, 0x00610780, 0xe8060086, 0x17e0ffbe,
+ 0x5c591724, 0x1281580a, 0xe9e00db1, 0x17240d92,
+ 0x129dd605, 0x172405d9, 0x129dd605, 0x500bfdd1,
+ 0x007f0640, 0x3bd60631, 0x063f0000, 0x00000e64,
+ 0x0780007f, 0x06250061, 0x00021e74, 0x40002e05,
+ 0x40002e05, 0x0dd00744, 0x17441201, 0xef840dd1,
+ 0xea610dd1, 0x0dc205e1, 0x0dd1ea63, 0x15b50df2,
+ 0x0046ff80, 0x1de251e0, 0x14b6ff80, 0xff800df5,
+ 0x0dc50116, 0x023aff80, 0xff8005b5, 0xff800360,
+ 0x05c514be, 0xffbe3201, 0x3f841702, 0x39fd0dd1,
+ 0x0622ddf2, 0xaaaa1100, 0x32013902, 0x16d8ffbe,
+ 0x0640d5f5, 0x0780007f, 0xffbe0061, 0x51e00398,
+ 0x320105ca, 0x00eeffbe, 0x1c3affbe, 0x0386ffbe,
+ 0x05ca51e0, 0xffbe3201, 0xff8000dc, 0xff800438,
+ 0x321f04a2, 0xfebcffbf, 0x036affbe, 0x05ca51e0,
+ 0xffbe3201, 0x172400c0, 0x1282d60d, 0xffbe15e9,
+ 0xf62442ce, 0x1500d600, 0xf1ff5620, 0x1501114a,
+ 0xd6051724, 0x05d9128d, 0xd6019e24, 0x000087d3,
+ 0xd6b91724, 0x08f01764, 0x032affbe, 0x05ca51e0,
+ 0xffbe3201, 0xef250080, 0x063f8625, 0x000202fc,
+ 0x007d3201, 0x030effbe, 0x05ca51e0, 0xffbe3201,
+ 0xff800064, 0x062604d6, 0x000224ac, 0x1de8ffbe,
+ 0x15f251e0, 0x02eeffbe, 0x05ca51e0, 0xffbe3201,
+ 0xef250044, 0x063f8625, 0x00020338, 0x007d3200,
+ 0x016087e0, 0xffbe3201, 0x52011578, 0x0dd05744,
+ 0x007f0640, 0x30e10780, 0xd6051724, 0x128dd200,
+ 0x172415a9, 0x1282d60d, 0x172405d1, 0x1285d605,
+ 0x9e240da1, 0x17d3d600, 0xffbe0000, 0xff80440a,
+ 0x6dd500e2, 0x481affbe, 0xd7e91724, 0x15d11284,
+ 0xd60d1724, 0x15911282, 0x1e26ffbe, 0xd6011724,
+ 0x05b91298, 0xd602bfc4, 0xd6051724, 0x05d9129b,
+ 0x04001640, 0xd6051764, 0xd7e91724, 0x05a91284,
+ 0x1724d201, 0x128dd605, 0x17240d91, 0x1282d60d,
+ 0xd1e005d9, 0xffbe05ba, 0xef251eda, 0x063f82b1,
+ 0x000203de, 0x1724007d, 0x1282d60d, 0xd1e035a9,
+ 0x172435ea, 0x1281d6b9, 0x178425f9, 0x11e008f3,
+ 0xea0125ba, 0x80001625, 0x00c4de02, 0x301d15d5,
+ 0xffbe0086, 0x51e0d8a6, 0x372a0de2, 0xe73b0001,
+ 0x063f0001, 0x00020422, 0x51e0007c, 0x87c405ca,
+ 0x0da5d6b8, 0x1724ea41, 0x52025c59, 0x05a91281,
+ 0xe9ea5201, 0x1201e5d7, 0x08f91744, 0xd60c8fc4,
+ 0x05dad1e0, 0x205affbe, 0x03caff80, 0x30ff0640,
+ 0x00610780, 0x8625ef25, 0x046a063f, 0x32010002,
+ 0xffbe007d, 0xffbe1572, 0x064015de, 0x0780007f,
+ 0x17a40061, 0x12610dd1, 0x178415ba, 0x11e0e459,
+ 0xffbe0df2, 0xef2542f2, 0x063f806d, 0x0002049a,
+ 0x9e24007d, 0x1fd3d60f, 0x07440000, 0x17240dd1,
+ 0x1285d605, 0x27c405e9, 0xff80d6b2, 0x45d50092,
+ 0x82b9ef25, 0x04c4063f, 0x007d0002, 0x05c251e0,
+ 0x181effbe, 0x17243da5, 0x1282e421, 0x32000dd9,
+ 0x13deffbe, 0x82c1ef25, 0x04e8063f, 0x007d0002,
+ 0x0dd00744, 0x17242da5, 0x1288e421, 0xffbe05b9,
+ 0x17242250, 0x1289e425, 0xffbe05b9, 0x1724224c,
+ 0x128ae425, 0xffbe05b9, 0xffbe24d6, 0x51e000f8,
+ 0x320105ca, 0xfe4effbd, 0xe4211724, 0x0dd91281,
+ 0x0dd117a4, 0x05da1261, 0xd60f9e24, 0x00001fd3,
+ 0xd60c9fc4, 0x0026ff80, 0x007f0640, 0x00610780,
+ 0x8625ef25, 0x0556063f, 0x32000002, 0xffbe007d,
+ 0xffbe1562, 0x0640166e, 0x0782007f, 0xef250061,
+ 0x063f8019, 0x00020574, 0x007d3003, 0x8625ef25,
+ 0x0582063f, 0x32000002, 0xffbe007d, 0xffbe168c,
+ 0x372316b4, 0xef250001, 0x063f801d, 0x0002059a,
+ 0xffbe007d, 0x06421724, 0x0780007f, 0x172400e1,
+ 0x1281e421, 0x17240d81, 0x1284e439, 0xff8005c1,
+ 0x45c50090, 0x82b9ef25, 0x05c8063f, 0x007d0002,
+ 0x05c251e0, 0x188affbe, 0xef253d95, 0x063f82d5,
+ 0x000205e0, 0x007d3200, 0x8311ef25, 0x05ec063f,
+ 0x007d0002, 0x08f717a4, 0x05ba11e0, 0x0450ff80,
+ 0x02bcff80, 0x08f71784, 0x25821262, 0x08f717a4,
+ 0x1dca11e0, 0x456cffbe, 0xffbee00a, 0xef25313e,
+ 0x063f82e1, 0x00020622, 0xef25007d, 0x063f82f1,
+ 0x0002062e, 0xffbe007d, 0xe1e0327a, 0xffbe05f2,
+ 0x51e04542, 0xffbe05ba, 0x06402cf4, 0x078200ff,
+ 0xef250061, 0x063f8019, 0x00020658, 0x007d3003,
+ 0x8625ef25, 0x0666063f, 0x32010002, 0x1724007d,
+ 0x1281ea01, 0x07c405b1, 0xffbeea00, 0xf62416da,
+ 0x1558d600, 0x00105640, 0x1559110a, 0x171affbe,
+ 0x00013723, 0x801def25, 0x0698063f, 0x007d0002,
+ 0x85adef25, 0x06a4063f, 0x007d0002, 0x8019ef25,
+ 0x06b2063f, 0x30030002, 0xffbe007d, 0x3723174e,
+ 0xef250001, 0x063f801d, 0x000206c6, 0x0642007d,
+ 0x0780007f, 0x121f0061, 0x5c00f624, 0x15091507,
+ 0x150d150b, 0xfd00f624, 0x15031505, 0xe900f624,
+ 0x15071505, 0xd600f624, 0x15061505, 0x0d911282,
+ 0x1764121f, 0x0000d605, 0x00000000, 0x00000000,
+ 0x8001ef25, 0x0714063f, 0x007d0002, 0x8015ef25,
+ 0x01ec0626, 0x3a020002, 0x0728063f, 0x007d0002,
+ 0x8021ef25, 0x0734063f, 0x007d0002, 0x007f0640,
+ 0x00210780, 0xfbccffbd, 0x07d01620, 0x0fb8f624,
+ 0x56801480, 0x5481ffff, 0x14835482, 0x001c1620,
+ 0x0818f624, 0x520413b0, 0x120353b1, 0x13b313b2,
+ 0x5bb45a01, 0x5c8153b5, 0x00c85620, 0x5e205482,
+ 0x5c830190, 0x00645e20, 0x54855c84, 0x04870486,
+ 0x00fa5620, 0x5e205488, 0x5c89012c, 0x5e20548a,
+ 0x5c8b0014, 0x03c05620, 0x5205548c, 0x539b539a,
+ 0x639c6206, 0x6b9d6a09, 0x539f5b9e, 0x63a153a0,
+ 0x5ba25a0a, 0x00105e20, 0x5a025ba3, 0x5ba55ba4,
+ 0x13a713a6, 0x5ba913a8, 0x13ab5baa, 0x13ad13ac,
+ 0x5baf53ae, 0x003f0640, 0x00610780, 0xe000f624,
+ 0x96201544, 0x9e24f0ff, 0x1152fb75, 0x03001682,
+ 0xafd31545, 0xffbe0000, 0x27c41806, 0xef25d6b2,
+ 0x063f834d, 0x00020812, 0xffbe007d, 0x064018a0,
+ 0x0782007f, 0xef250061, 0x063f8019, 0x0002082c,
+ 0x007d3003, 0x08f317a4, 0x1d8a1261, 0xd6051724,
+ 0x15c9129c, 0x08001640, 0xd6051764, 0x00001200,
+ 0x00000000, 0x00000000, 0x12671241, 0x1724fd96,
+ 0x129cd605, 0x074405b1, 0xffbe08f3, 0x51e02500,
+ 0xffbe1dc2, 0x37232554, 0xef250001, 0x063f801d,
+ 0x0002087e, 0x1724007d, 0x5640d605, 0x114a0300,
+ 0xffbe15c2, 0x17241a1e, 0x1282fd05, 0x17240de1,
+ 0x1285d605, 0x0d95fd91, 0x00013723, 0x801def25,
+ 0x08b0063f, 0x007d0002, 0x007f0642, 0x00610782,
+ 0x8019ef25, 0x08c6063f, 0x30030002, 0xffbe007d,
+ 0x51e02650, 0xffbe05da, 0xffbe26d6, 0x37232710,
+ 0xef250001, 0x063f801d, 0x000208e6, 0x0642007d,
+ 0x0780007f, 0xffbe0021, 0x51e02906, 0xffbe05b2,
+ 0x06402acc, 0x0780003f, 0xef250061, 0x063f8631,
+ 0x0002090e, 0x51e0007d, 0xffbe05ba, 0x0640325c,
+ 0x0780007f, 0xd20070e1, 0x17441201, 0x16250855,
+ 0xce028000, 0xde020330, 0x17240334, 0xe802eab5,
+ 0xea9aeaca, 0x003f16c2, 0x35c2e9e2, 0x001f16dd,
+ 0x000c36e2, 0x170631c4, 0x362694b4, 0x12d894b0,
+ 0x1261129c, 0x05d21df1, 0x0da11263, 0x1da515c2,
+ 0x0001e739, 0x0974063f, 0x007c0002, 0xe73b15d5,
+ 0x063f0001, 0x00020982, 0x06aa007c, 0x0dc2ffff,
+ 0x0da5d201, 0x0009e73b, 0x0998063f, 0x007c0002,
+ 0xff8005b5, 0xea41003e, 0x003f56dd, 0xeab65744,
+ 0x1640c5d5, 0xf6240001, 0x1503ea00, 0xe802155a,
+ 0xea9aeaca, 0x003f16c2, 0xbd8ae9e2, 0x05fad261,
+ 0x8339ef25, 0x09d4063f, 0x007d0002, 0x70ff0640,
+ 0x00610780, 0x5864f006, 0x5ad81303, 0x12d85a9c,
+ 0x0dba1299, 0x80011724, 0x30005640, 0x25d2114a,
+ 0x80011724, 0x129a12ca, 0x52c25002, 0x572a51c4,
+ 0x66408001, 0x514c8000, 0x060b1d82, 0x15d1fff0,
+ 0x57eb5201, 0x5f2400c0, 0x514be435, 0x38020de2,
+ 0x000c16e2, 0x854def25, 0x47e211c4, 0x32440fc9,
+ 0x0a40063f, 0x007d0002, 0x007f0640, 0x00e10780,
+ 0x2200063c, 0xf624aaaa, 0xe86000a4, 0xea610384,
+ 0x0d8205e1, 0x0d91ea63, 0x0dd50db2, 0x4292ffbe,
+ 0xff800dd5, 0x0da50034, 0x0076ff80, 0xffbe05f5,
+ 0x05c542de, 0xffbe3202, 0x3f840ed2, 0x39fd00a5,
+ 0x391c05d2, 0xffbe3202, 0x17840eae, 0x11e000a9,
+ 0x0640ddba, 0x078000ff, 0xefa40061, 0xea6100a5,
+ 0x159205e1, 0x05e1ea63, 0x0da50d82, 0x430effbe,
+ 0xffbe0da5, 0x05f543bc, 0x4406ffbe, 0x320305c5,
+ 0x0e88ffbe, 0x00a53fa4, 0x0d8239fd, 0x33000622,
+ 0x3902aaaa, 0xffbe3204, 0x06400e5e, 0x0780007f,
+ 0xef8400e1, 0xe7a400a7, 0x101d00a7, 0xffed0602,
+ 0x00424de1, 0x00160013, 0x001c0019, 0x0022001f,
+ 0x00280025, 0x002e002b, 0x00340031, 0x003a0037,
+ 0x0040003d, 0x00490043, 0xffbe0046, 0x3da543ea,
+ 0x4488ffbe, 0xffbe35f5, 0x35c5448a, 0x0098ff80,
+ 0xff803595, 0x2de500d4, 0x0114ff80, 0xff802db5,
+ 0x2d8501a8, 0x01e0ff80, 0xff8025d5, 0x25a502fe,
+ 0x05b0ff80, 0xff801df5, 0x1dc505d4, 0x694effbe,
+ 0xffbe1d95, 0x15e56a22, 0x0604ff80, 0xff8015b5,
+ 0x1585061e, 0x6c9effbe, 0xffbe0dd5, 0x0da56cea,
+ 0x6d96ffbe, 0xffbe05f5, 0x05c56e5e, 0xffbe3204,
+ 0x3f840dba, 0x39fd00a7, 0x06220d82, 0xaaaa4400,
+ 0x32083902, 0x0d90ffbe, 0x00a73fa4, 0x0d9239fc,
+ 0x55000622, 0x3902aaaa, 0x00103620, 0x0d78ffbe,
+ 0x00ff0640, 0x00a717a4, 0x1dab1269, 0x000a0042,
+ 0x001b000c, 0x0010000e, 0x0012001b, 0x001b0014,
+ 0x07be0016, 0x07be4470, 0x07be4522, 0x07be458e,
+ 0x07be45ae, 0x07be461a, 0x07be463a, 0x32054696,
+ 0x0d4807be, 0x17a4007f, 0x126900a7, 0x00421dcb,
+ 0x001d000a, 0x0010000c, 0x0016000e, 0x00140012,
+ 0x0018001d, 0x46fc07be, 0x47d607be, 0x494407be,
+ 0x487207be, 0x4a3607be, 0x4a8a07be, 0x497a07be,
+ 0x4b7407be, 0x07be3206, 0x007f0d02, 0x00a717a4,
+ 0xffe70602, 0x004245d1, 0x00460019, 0x001d001b,
+ 0x0021001f, 0x00250023, 0x00290027, 0x002d002b,
+ 0x0031002f, 0x00350033, 0x00370046, 0x003b0039,
+ 0x0046003d, 0x0046003f, 0x07be0041, 0x07be4b80,
+ 0x07be4c5e, 0x07be4d0c, 0x07be4d72, 0x07be4dd2,
+ 0x07be4e8c, 0x07be4f12, 0x07be504c, 0x07be50f6,
+ 0x07be512c, 0x07be51c6, 0x07be5212, 0x07be5320,
+ 0x07be5462, 0x07be54d0, 0x07be55fa, 0x07be562e,
+ 0x07be5698, 0x07be56d0, 0x07be582c, 0x3207599c,
+ 0x0c6807be, 0x17a4007f, 0x126900a7, 0x00421d8b,
+ 0x0019000a, 0x000e000c, 0x00100019, 0x00120019,
+ 0x00140019, 0x5a3e07be, 0x5abc07be, 0x5b5407be,
+ 0x5bba07be, 0x5c2207be, 0x5d3c07be, 0x07be3208,
+ 0x007f0c2a, 0x00a717a4, 0x0d811261, 0x12631582,
+ 0x0dd205f1, 0x05e21264, 0x07be05f5, 0x07805d24,
+ 0x07be0010, 0x32095f2c, 0x0c0007be, 0x0786007f,
+ 0x378470e1, 0x16240811, 0xe8068284, 0xe9c2eac5,
+ 0xe4391724, 0xd200e200, 0x07a4de24, 0x05e91283,
+ 0x07b337a4, 0x6cb6ffbe, 0xffbe65e5, 0x171da9f6,
+ 0x12d90001, 0x1264129d, 0xf7dd0d9a, 0x05e20006,
+ 0x0007e79d, 0xe2d8d201, 0x17bbe29f, 0x3784000d,
+ 0xcf250811, 0x063f83cd, 0x00020dbc, 0x129f12de,
+ 0x00793802, 0xf6241201, 0x139c00ac, 0xd1e0039d,
+ 0xe1e02582, 0x171d0dda, 0xf6240015, 0x12ddeb54,
+ 0x12c3129e, 0x121ff1c2, 0x15031501, 0x120115a5,
+ 0x00acf624, 0x571d139c, 0x56ca000b, 0x5241001f,
+ 0x00c017ea, 0x139d125f, 0x07b4f624, 0x05030501,
+ 0x0e5497c4, 0x0e540fc4, 0x000d3f3b, 0x0e5407c4,
+ 0x17441203, 0x300700a7, 0x3acb3298, 0x3ac63a9b,
+ 0x08e0ffbe, 0x00ac3624, 0x00401620, 0x1501f003,
+ 0x17250503, 0x3e24839d, 0x400a0e54, 0x1505480b,
+ 0x05ccffbe, 0x70ff0646, 0x00210780, 0x00a717a4,
+ 0x0d911261, 0x126415f2, 0x15f22591, 0x1d811266,
+ 0x1d950de2, 0x003aff80, 0xfd191724, 0x129512c5,
+ 0x16c21242, 0x17440003, 0x15851714, 0x0132ff80,
+ 0xffbe0dd5, 0x0da55f18, 0x01a6ff80, 0xffbe05f5,
+ 0x05c560f8, 0xffbe320a, 0x06400ab2, 0x0780003f,
+ 0x5f2400e1, 0xee2407b1, 0x662407a4, 0x100b8000,
+ 0x50021298, 0x51cc52c2, 0x0da211e0, 0xffdf0602,
+ 0x172a05f1, 0x56400001, 0x51428000, 0x320b05ba,
+ 0x56405dc5, 0x51423000, 0x36c255e2, 0x100b00ff,
+ 0xe72512cb, 0x129b841d, 0x063f3802, 0x00020efa,
+ 0x5744007c, 0x008a0810, 0x060d680a, 0x05baff01,
+ 0x45b53205, 0x100d6ac5, 0x172211c4, 0x16c28299,
+ 0x12610007, 0x12633df2, 0x100a35ea, 0x66c21285,
+ 0x16ca0003, 0x5a01001f, 0x00c05fe2, 0x17196764,
+ 0x100c62c2, 0x172211c4, 0x5f64ea49, 0x114b171d,
+ 0x17241dea, 0x12c5fd19, 0x12421295, 0x000376c2,
+ 0xfd191724, 0x129512c5, 0x000316c2, 0xfd9a11ee,
+ 0x172d69c4, 0x16c28299, 0x12610007, 0x126315b2,
+ 0x61c40daa, 0xea49172c, 0x05d25942, 0x17441206,
+ 0x15c500a7, 0x00133620, 0x000f3fbd, 0x6b0effbe,
+ 0xef250dd5, 0x063f8625, 0x00020fa8, 0x007d3201,
+ 0xf6241201, 0x138400a4, 0x06401383, 0x172400ff,
+ 0x5e24e421, 0x128107a4, 0x172405d9, 0x1283e439,
+ 0x37ab05d9, 0x07be000f, 0x17846a64, 0x12c50811,
+ 0x172211c4, 0x16c28299, 0x12630007, 0xf62405f2,
+ 0x038300a4, 0x13841201, 0x172425a5, 0x57241719,
+ 0x12c2171d, 0x172211c4, 0x5142ea49, 0xfd191724,
+ 0x129512c5, 0x05f251e0, 0x16c21242, 0x17440003,
+ 0x0dd51714, 0x17155784, 0x000316c2, 0x05fa11ea,
+ 0x000f3fab, 0x00133620, 0x6a7207be, 0x0788007f,
+ 0x67240021, 0x62d2eab1, 0x160c629a, 0x1261ffff,
+ 0x126315b3, 0x12691592, 0x126b0df2, 0x126d0dd2,
+ 0x06020db2, 0x0d82ffef, 0xffed1602, 0x05c31261,
+ 0x12611259, 0x57844d9b, 0x5e240811, 0x100a8284,
+ 0x11cb12c5, 0x05b26261, 0x0dba6262, 0x51c452c2,
+ 0x8085572a, 0x05d9528e, 0x07635200, 0x05f50001,
+ 0xeb6d5724, 0x00015763, 0xeb715724, 0x5503f003,
+ 0x1b005640, 0x05075505, 0x56ca530d, 0x568a0003,
+ 0x538d0080, 0x57225b0e, 0x5ecb0001, 0x6eca00e0,
+ 0x590d001f, 0x52d45b8e, 0x538f5299, 0xffff560c,
+ 0x05e35261, 0x05c25269, 0xffef060a, 0x3f8205ea,
+ 0x3ec7000d, 0x05d5000f, 0xeab13f24, 0x3a9c3acc,
+ 0xffbe3003, 0x12050436, 0x00a71744, 0x003f0648,
+ 0x00a717a4, 0x0d811261, 0x12631582, 0x0dd205f1,
+ 0x05e21264, 0x07be05f5, 0x07be5eac, 0x07be5fc4,
+ 0x320b6022, 0x082407be, 0x17a4007f, 0x126900a7,
+ 0x00421dab, 0x000c000a, 0x000e001b, 0x001b0010,
+ 0x00140012, 0x0016001b, 0x603607be, 0x613a07be,
+ 0x61a607be, 0x61c607be, 0x623207be, 0x625207be,
+ 0x62d007be, 0x07be320c, 0x007f07e2, 0x00a717a4,
+ 0x05d11261, 0x12620db2, 0x05d505c2, 0x643807be,
+ 0x655407be, 0x07be320d, 0x007f07c2, 0x00a717a4,
+ 0x05d11261, 0x126205e2, 0x05f505e2, 0x654007be,
+ 0x65fe07be, 0x666607be, 0x07be320e, 0x0780079e,
+ 0x008610e1, 0xeac5e806, 0x077de9c4, 0x077d8289,
+ 0x077d828d, 0x077d8291, 0x077d8295, 0x077d8299,
+ 0x077d829d, 0xe00682a1, 0xd8070087, 0x6b06ffbe,
+ 0x8285171d, 0x301c381b, 0x129d12d9, 0x05ca1264,
+ 0x6c54ffbe, 0xffbe05b5, 0x06406c86, 0x078010ff,
+ 0xd80770e1, 0xd008009b, 0xc809009a, 0x009ce006,
+ 0xeac5e81c, 0x82841624, 0x301de9c2, 0x46203a00,
+ 0xffbe0020, 0x301c062a, 0x401a381b, 0xffbe4819,
+ 0x301c6cba, 0x0001171d, 0x401a381b, 0x12d94819,
+ 0x1264129d, 0xffbe158a, 0xf7dd6e9e, 0x48190006,
+ 0x381b401a, 0x05ca301c, 0x6f1affbe, 0xffbe05e5,
+ 0x05b56f4e, 0x6f54ffbe, 0x70ff0640, 0x10e10780,
+ 0xe8060086, 0xe9c4eac5, 0x0087e006, 0xffbed807,
+ 0x171d7016, 0xee3d8285, 0x301c8284, 0x12d9381b,
+ 0x1264129d, 0xffbe0dea, 0xf7dd7012, 0x381b0006,
+ 0x05ca301c, 0x7064ffbe, 0xffbe05e5, 0x05b570c6,
+ 0x70f8ffbe, 0x10ff0640, 0x00610780, 0xe8060086,
+ 0x1624eac4, 0xe9c205a4, 0x00051728, 0x008b5807,
+ 0x30025002, 0x529852d0, 0x00013e0a, 0x32900087,
+ 0x2da25a61, 0x1dc25a63, 0x35aa5a64, 0x129d12da,
+ 0x05e21261, 0x0d821263, 0x0da21265, 0x30080dd5,
+ 0x8512ffbe, 0x300825f5, 0x85f4ffbe, 0x300825b5,
+ 0x86d6ffbe, 0x30081df5, 0x879cffbe, 0x12da1db5,
+ 0x1261129d, 0x126505b2, 0xffbe05ca, 0x15a58858,
+ 0x8862ffbe, 0x12da0df5, 0x1261129d, 0x126505b2,
+ 0xffbe05ca, 0x05e58860, 0x8886ffbe, 0xffbe05b5,
+ 0x577d88ac, 0x06400001, 0x0780007f, 0x00860061,
+ 0xeac4e806, 0x05a41624, 0xefc7e9c2, 0x30070004,
+ 0xffbe05ca, 0x05b588c4, 0x8976ffbe, 0x0005577d,
+ 0x007f0640, 0xffe1078a, 0x00bc3620, 0x8cbcffbe,
+ 0xffbea00a, 0x57638cbe, 0xffbe0002, 0x57638cb6,
+ 0xffbe0004, 0x57638cb4, 0x36200006, 0xffbe00bc,
+ 0x57638cae, 0x36200008, 0xffbe00bc, 0x57638caa,
+ 0xffbe000a, 0x57638cdc, 0xffbe000c, 0x57638cd4,
+ 0xffbe000e, 0x57638cd2, 0x36200010, 0xffbe00bc,
+ 0x57638ccc, 0xaa000012, 0xb200ba00, 0xe815ca00,
+ 0x1624eac3, 0xe9c204a4, 0xd860f01d, 0xe063c067,
+ 0x0220dff4, 0xffbe3018, 0xf01d8c42, 0xe7ea1061,
+ 0x57e30220, 0x5fe30003, 0x17ea0005, 0x50650220,
+ 0x57ebe1db, 0x11dc0220, 0x5fe351c2, 0x10640007,
+ 0x022017eb, 0x11cad862, 0x000957e3, 0xdfeae066,
+ 0x30180220, 0xffbed9c2, 0xe7ea8c16, 0xf01d0220,
+ 0xd060e1db, 0x000b17e3, 0xd8633018, 0x0220d7e2,
+ 0x8c04ffbe, 0x1061f01d, 0x0220dfea, 0x000d57e3,
+ 0x000f5fe3, 0x022017ea, 0xd9da5065, 0x022057eb,
+ 0x51c211db, 0x00115fe3, 0x17eb1064, 0xd0620220,
+ 0x57e311ca, 0xd8660013, 0x0220d7ea, 0xd1c23018,
+ 0x8c0affbe, 0x0220dfea, 0xb9fcd9da, 0xb81c05a9,
+ 0x05a9b1fb, 0xee1db01b, 0xca410040, 0xca640099,
+ 0x10159dc1, 0x500212c2, 0xbf6a51c4, 0x11c403bd,
+ 0x03ddb762, 0x0095aa41, 0x85f1aa68, 0xffff064a,
+ 0x00210780, 0x00041706, 0x12da0087, 0x16c2129d,
+ 0x3a610003, 0x2dc255b1, 0x3dd13a63, 0x3a6415e2,
+ 0x12614dda, 0x0de205e1, 0x05e11263, 0x45e50d82,
+ 0xa402ffbe, 0xffbe45c5, 0x4595a464, 0xa546ffbe,
+ 0xffbe3de5, 0x3db5a602, 0x05e11261, 0x12630de2,
+ 0x0d8205e1, 0xffbe35b5, 0x3595a3b8, 0xa41affbe,
+ 0xffbe2de5, 0x2db5a4d2, 0xa58effbe, 0x12612d85,
+ 0x0de205e1, 0x05e11263, 0x25850d82, 0xa35cffbe,
+ 0xffbe1de5, 0x1db5a3d0, 0xa47cffbe, 0xffbe1d85,
+ 0x15d5a538, 0x05e11261, 0x12630de2, 0x0d8205e1,
+ 0xffbe0dd5, 0x0db5a31c, 0xa3a6ffbe, 0xffbe0d85,
+ 0x05d5a428, 0xa50effbe, 0x520105a5, 0x003f0640,
+ 0x00210780, 0x0fc11784, 0x05f211e0, 0x0fb8f624,
+ 0x03883069, 0xabf4ffbe, 0xfd111724, 0x05b11284,
+ 0xfd081fc4, 0x003f0640, 0xf0e10780, 0x8625ef25,
+ 0x3201d200, 0x15e4063f, 0x007d0002, 0x5c591724,
+ 0x1281c00a, 0x0000e7e9, 0x80001625, 0x00c0ce02,
+ 0x301c1db5, 0xffbe0086, 0xe80ac6b2, 0x15b2e9e0,
+ 0xff80301d, 0x373d00a0, 0xdf390001, 0x063f0001,
+ 0x0002161e, 0x5261007b, 0xcfdd05c2, 0x05b20003,
+ 0x0d95d201, 0x1724e241, 0x12815c59, 0x000017e9,
+ 0xe587e1e2, 0x8625ef25, 0x164a063f, 0x30180002,
+ 0x501a007d, 0xf0ff0640, 0x10e10780, 0x5c591724,
+ 0x1281ea02, 0xea0105a9, 0x80001625, 0x00c0de02,
+ 0x301d15e5, 0xffbe0086, 0xe00ac642, 0x0de2e1e0,
+ 0xff80301c, 0x373c0030, 0xe73b0001, 0x063f0001,
+ 0x0002168e, 0x5261007c, 0xea410db2, 0x5c591724,
+ 0x12815202, 0x520105a9, 0xe5c7e9ea, 0x06405200,
+ 0x1a5c10ff, 0x00011726, 0x0001062a, 0x17630012,
+ 0x12cb0001, 0x114a128b, 0x00125640, 0x0dea11ea,
+ 0x17461202, 0x00000002, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x1a440000, 0xf624007f,
+ 0x03800d24, 0x00dc1620, 0x12021381, 0x03831382,
+ 0x0d290764, 0x12011388, 0x007f1389, 0x00e10780,
+ 0x09e1ef84, 0x09e1e7a4, 0x1267101d, 0x0042259b,
+ 0x000b0008, 0x0011000e, 0x00170014, 0x001d001a,
+ 0x006eff80, 0xff8015d5, 0x15a501c2, 0xd03cffbe,
+ 0xffbe0df5, 0x0dc5d088, 0xd0f8ffbe, 0xff800d95,
+ 0x05e501f8, 0xd1f6ffbe, 0xffbe05b5, 0x3f84d2f4,
+ 0x39fd09e1, 0x06220d92, 0xaaaa6600, 0x36203902,
+ 0xffbe0020, 0x3fa401d2, 0x39fc09e1, 0x06220d92,
+ 0xaaaa7700, 0x36203902, 0xffbe0040, 0x178401ba,
+ 0x11e009e1, 0xff8005b2, 0x0640066c, 0x078000ff,
+ 0x17a40021, 0x126109e1, 0x05f205d1, 0x0d821263,
+ 0xff800d95, 0x05e5002c, 0x0056ff80, 0xffbe05b5,
+ 0xffbecdd4, 0x5784d2a8, 0x17a409e1, 0x51e209e3,
+ 0xf62405d2, 0x13a409bc, 0x064003a5, 0x0780003f,
+ 0xffbe0061, 0x1724cc88, 0x12815c59, 0xef250df1,
+ 0x063f8625, 0x000217f4, 0x007d3201, 0x8625ef25,
+ 0x1802063f, 0x300a0002, 0x0640007d, 0x0788007f,
+ 0x17240061, 0x12815c59, 0x17246de1, 0x5640c0a1,
+ 0x114a8000, 0x17240d9a, 0x129cd621, 0x962405d1,
+ 0x1fd2d623, 0x17240000, 0x5640c0a1, 0x114a8000,
+ 0x12035da2, 0xc000f624, 0x15501531, 0x55b2114a,
+ 0x8625ef25, 0x1856063f, 0x32010002, 0x1724007d,
+ 0x128efb75, 0x178415c9, 0x06025c61, 0xfdc2ffdf,
+ 0x5c611784, 0xffde0602, 0x172405ea, 0x06c2fb9d,
+ 0xf5fa000c, 0xfb759624, 0x0000afd2, 0xc0648fc4,
+ 0xd6239624, 0x00009fd2, 0x0dd11784, 0x05fa1262,
+ 0x3a013200, 0x4a024200, 0x3224ffbe, 0x17441202,
+ 0x172409e1, 0x1282c061, 0x074405c9, 0x1db509e1,
+ 0xc000f624, 0x35583d5a, 0xffbd4210, 0x1624fdf4,
+ 0xf00308fc, 0x16201501, 0x150300c0, 0x20001620,
+ 0x17251505, 0x362481ad, 0x400a09bc, 0x1507480b,
+ 0xfad6ffbd, 0x007f0648, 0x00210780, 0x09e117a4,
+ 0x05e211e0, 0x05f21264, 0x0d821265, 0xffbe0d95,
+ 0x05e5ccac, 0xccf2ffbe, 0xffbe05b5, 0xffbecd76,
+ 0x5784d14c, 0x17a409e1, 0x51e209e3, 0x12640db2,
+ 0x9e2405da, 0x07d3c049, 0xf6240000, 0x13a409bc,
+ 0x064003a5, 0x0780003f, 0xffbe0061, 0x1784cf60,
+ 0x126609e1, 0xef250dda, 0x063f824d, 0x0002195a,
+ 0xef25007d, 0x063f8251, 0x00021966, 0x0640007d,
+ 0x0780007f, 0xffbe0021, 0x1784d2a0, 0x12610a15,
+ 0x05d20de1, 0x05e11263, 0x0d950d82, 0xd30cffbe,
+ 0xffbe05e5, 0x05b5d3da, 0xd4b4ffbe, 0x003f0640,
+ 0x00210780, 0x0a0d1724, 0x00ff062b, 0x5200ffff,
+ 0x1262114b, 0x96400da2, 0x11f20030, 0x96400d92,
+ 0x11f20031, 0x0d950d82, 0xd518ffbe, 0xffbe05e5,
+ 0x05b5d5f8, 0xd60effbe, 0x003f0640, 0x00210780,
+ 0x0a0d1724, 0x5ec25200, 0x060b00ff, 0x15eaff80,
+ 0x12611298, 0x05f215b1, 0x0d811263, 0x126f0da2,
+ 0x0dc50db2, 0xd63cffbe, 0xffbe0d95, 0x05e5d64c,
+ 0xd65cffbe, 0xffbe05b5, 0x0640d662, 0x17a4003f,
+ 0x12610a0f, 0x05f21581, 0x05f11263, 0x126f0d82,
+ 0x0d950d82, 0xd65a07be, 0xd68007be, 0xd6a607be,
+ 0xd6c007be, 0x0780007f, 0x17840021, 0x52000a0d,
+ 0xff800602, 0x05e20df9, 0xff7e0602, 0x0d8205e9,
+ 0xffbe0d95, 0x05e5d6f6, 0xd706ffbe, 0xffbe05b5,
+ 0x0640d720, 0x1784003f, 0x06020a0d, 0x05baff80,
+ 0xd74607be, 0xff7f0602, 0x07be05ba, 0x07bed768,
+ 0x0780d76e, 0x17240021, 0x062b0a0d, 0xffff00ff,
+ 0x114b5200, 0x0da21262, 0x00309640, 0x0d9211f2,
+ 0x00319640, 0x0d8211f2, 0xffbe0d95, 0x05e5d822,
+ 0xd8d4ffbe, 0xffbe05b5, 0x0640d8ec, 0x1784003f,
+ 0x520109e1, 0x05ba1266, 0xd91a07be, 0x1784007f,
+ 0x520109e1, 0x05ba1266, 0xd98007be, 0x0780007f,
+ 0xee240061, 0x301dc500, 0xd9d6ffbe, 0x0009361d,
+ 0xd9e8ffbe, 0x0012361d, 0xffbe3a00, 0x361dda00,
+ 0x3a000019, 0xda2cffbe, 0x001f361d, 0xffbe3a01,
+ 0x361dd9ec, 0x3a010026, 0xda18ffbe, 0x007f0640,
+ 0x00610780, 0xc500ee24, 0xffbe301d, 0x361dda12,
+ 0xffbe0005, 0x0640da1a, 0x0780007f, 0x170400e1,
+ 0x16c2097c, 0x12610007, 0x126305b2, 0xffbe05ba,
+ 0x1724db90, 0x1285c0a1, 0x063c2dd1, 0xaaaa8800,
+ 0x0b71efa4, 0x0b700744, 0x0d91ea61, 0xea630db2,
+ 0xea650dc2, 0xea660dd2, 0x0df50de2, 0xdce8ffbe,
+ 0xffbe0dc5, 0x0d95dd3a, 0xdddcffbe, 0xffbe05e5,
+ 0x05b5de32, 0x00a6ff80, 0x0b713fa4, 0x05e239fd,
+ 0x3620391c, 0xffbd0080, 0x1784fd8e, 0x11e00b71,
+ 0x0640dd8a, 0x078000ff, 0x170400e1, 0x16c2093c,
+ 0x12610007, 0x126305b2, 0xffbe05ba, 0xffbedbb8,
+ 0x51e0eba0, 0x17243592, 0x1285c0a1, 0x063c2dd1,
+ 0xaaaacc00, 0x0c57efa4, 0x0c560744, 0x0d91ea61,
+ 0xea630db2, 0xea650dc2, 0xea660dd2, 0x0df50de2,
+ 0xe2dcffbe, 0xffbe0dc5, 0x0d95e32e, 0xe3e8ffbe,
+ 0xffbe05e5, 0x05b5e47c, 0x00feff80, 0x0c573fa4,
+ 0x05e239fd, 0x3620391c, 0xffbd0400, 0x1784fd0a,
+ 0x11e00c57, 0x0640dd8a, 0x078000ff, 0xef840061,
+ 0x101d0b73, 0x359b126b, 0x000c0042, 0x0012000f,
+ 0x00180015, 0x001e001b, 0x00240021, 0x002a0027,
+ 0xffbe002d, 0x2595dd88, 0x005cff80, 0xffbe1de5,
+ 0x1db5de12, 0xde3effbe, 0xffbe1d85, 0x15d5de94,
+ 0xde9cffbe, 0xffbe15a5, 0x0df5dea4, 0xdf38ffbe,
+ 0xffbe0dc5, 0x0d95dfaa, 0xdfe0ffbe, 0xffbe05e5,
+ 0x05b5dff6, 0xe054ffbe, 0x0b733f84, 0x0d9239fd,
+ 0x99000622, 0x3902aaaa, 0x01003620, 0xfc78ffbd,
+ 0x007f0640, 0x00610780, 0x0b73efa4, 0x0d81ea61,
+ 0xea630da2, 0x0dd20db1, 0x0de2ea65, 0xffbe0df5,
+ 0x0dc5e036, 0xe05cffbe, 0xffbe0d95, 0x05e5e098,
+ 0xe0e8ffbe, 0xffbe05b5, 0x3fa4e198, 0x39fd0b73,
+ 0x06220d92, 0xaaaabb00, 0x36203902, 0xffbd0200,
+ 0x0640fc26, 0x0780007f, 0xef840061, 0x101d0c59,
+ 0x359b126b, 0x000c0042, 0x0012000f, 0x00180015,
+ 0x001e001b, 0x00240021, 0x002a0027, 0xffbe002d,
+ 0x2595e3c8, 0x005cff80, 0xffbe1de5, 0x1db5e41c,
+ 0xe47affbe, 0xffbe1d85, 0x15d5e4e0, 0xe508ffbe,
+ 0xffbe15a5, 0x0df5e530, 0xe544ffbe, 0xffbe0dc5,
+ 0x0d95e61e, 0xe680ffbe, 0xffbe05e5, 0x05b5e696,
+ 0xe728ffbe, 0x0c593f84, 0x0d9239fd, 0xdd000622,
+ 0x3902aaaa, 0x08003620, 0xfb9cffbd, 0x007f0640,
+ 0x00610780, 0x0c59efa4, 0x0d81ea61, 0xea630dd2,
+ 0x05f20de1, 0x0de2ea65, 0xffbe0df5, 0x0dc5e70a,
+ 0xe734ffbe, 0xffbe0d95, 0x05e5e840, 0xe890ffbe,
+ 0xffbe05b5, 0x3fa4e8c4, 0x39fd0c59, 0x06220d92,
+ 0xaaaaee00, 0x36203902, 0xffbd1000, 0x0640fb4a,
+ 0x0780007f, 0x17240061, 0x1286c061, 0x16200d99,
+ 0x17640020, 0x3202c061, 0xffbe3a00, 0xefa4ef1c,
+ 0x07440cd5, 0xea610cd9, 0x0db20d91, 0x15c1ea63,
+ 0xea650db2, 0x0de20dc1, 0xffbe0df5, 0x0dc5eb38,
+ 0xeb5effbe, 0xffbe0d95, 0x05e5ebe6, 0xec4affbe,
+ 0xffbe05b5, 0x3fa4ecc8, 0x39fd0cd5, 0x06220d92,
+ 0xaaaaff00, 0x36203902, 0xffbd2000, 0x17a4fada,
+ 0x11e00cd9, 0x0640d5da, 0x0000007f, 0x000200de,
+ 0x0000102c, 0x00001064, 0x0000109e, 0x0000111c,
+ 0x0000115a, 0x00020142, 0x00020154, 0x000011a6,
+ 0x000011ee, 0x000012a6, 0x00001250, 0x000012f4,
+ 0x00001376, 0x0000ccc8, 0x0000ccfc, 0x0000cd72,
+ 0x0000cda8, 0x0000ce0a, 0x0000cecc, 0x000215d0,
+ 0x0000cfc4, 0x0000d018, 0x0000d062, 0x00021650,
+ 0x0000d12e, 0x0000d1a8, 0x0000d204, 0x0000d274,
+ 0x0000d2d0, 0x0000d334, 0x0000d3fe, 0x0000d462,
+ 0x0000d4e8, 0x0000d54a, 0x0000d5d0, 0x0000d632,
+ 0x0000d67a, 0x0000d6e2, 0x0000d73a, 0x0000d7b4,
+ 0x0000d84c, 0x0000d8c4, 0x0000d916, 0x0000d968,
+ 0x0000d9e4, 0x0000da36, 0x0000dab2, 0x0000db04,
+ 0x0000db5a, 0x0000db84, 0x0000dba4, 0x0000dbd8,
+ 0x0000dc22, 0x0000dc50, 0x0000dc90, 0x0000dcc6,
+ 0x0000dd14, 0x0000dd62, 0x0000dd86, 0x0000dda2,
+ 0x0000ddba, 0x0000ddce, 0x0000dde2, 0x0000ddf8,
+ 0x0000de12, 0x0000de28, 0x0000de3e, 0x0000de84,
+ 0x0000defe, 0x0000dfb2, 0x0000dfe6, 0x0000e01a,
+ 0x0000e050, 0x0000e086, 0x0000e0bc, 0x0000e0f2,
+ 0x0000e150, 0x0000e19c, 0x0000e1d0, 0x0000e212,
+ 0x0000e304, 0x0000e27a, 0x0000e318, 0x0000e3a4,
+ 0x0000e42a, 0x0000c608, 0x0000c6d8, 0x0000c74e,
+ 0x0000c76a, 0x0000c786, 0x0000c7d6, 0x0000c866,
+ 0x0000c930, 0x0000c960, 0x0000c98e, 0x0000c9c8,
+ 0x0000c9de, 0x0000c9fc, 0x0000ca28, 0x0000ca6c,
+ 0x0000ca90, 0x0000caa2, 0x0000cae4, 0x0000cb88,
+ 0x0000cc30, 0x0000cc52, 0x0000e578, 0x0000ea76,
+ 0x0000eae6, 0x0000eb6a, 0x0002196a, 0x00021998,
+ 0x0000eff6, 0x0000f018, 0x000219d4, 0x00021a16,
+ 0x0000f11e, 0x0000f146, 0x00021a3e, 0x00021a6e,
+ 0x0000f23e, 0x0000f268, 0x0000f29e, 0x00021a8a,
+ 0x0000f3c8, 0x0000f3e8, 0x00021ac6, 0x00021ad6,
+ 0x0000f48a, 0x00021ae6, 0x00021b28, 0x0000f57e,
+ 0x0000f60c, 0x0000f660, 0x0000f68a, 0x0000f6a2,
+ 0x0000f6b2, 0x0000f6dc, 0x00021b42, 0x00021bbe,
+ 0x0000f940, 0x0000f9b6, 0x0000fe5e, 0x0000ffbc,
+ 0x00010084, 0x000105e0, 0x000106ee, 0x00010722,
+ 0x00010762, 0x0001078a, 0x000107f8, 0x0001085c,
+ 0x0001089e, 0x000109e8, 0x00010be0, 0x00010c84,
+ 0x00010cf4, 0x00010d82, 0x00010da0, 0x00010e0e,
+ 0x00010e60, 0x00010eb4, 0x00010f18, 0x00010f66,
+ 0x00010f6e, 0x00010f76, 0x00010fb6, 0x00010fd4,
+ 0x00001ed6, 0x00002164, 0x000022bc, 0x000023ec,
+ 0x00002328, 0x00002530, 0x00000000, 0x000025d4,
+ 0x0000274c, 0x000208ea, 0x000034b4, 0x000035ca,
+ 0x000036ae, 0x0000372e, 0x0000382e, 0x0000385e,
+ 0x00003910, 0x00003960, 0x0000398e, 0x000039fc,
+ 0x00003a68, 0x00003a98, 0x00003ace, 0x00003b0e,
+ 0x00003b2e, 0x00003b60, 0x00003b6a, 0x000208fe,
+ 0x00003bb4, 0x00003cba, 0x00003d48, 0x00003dd4,
+ 0x00003e80, 0x00003f26, 0x0002091a, 0x00004030,
+ 0x0000408a, 0x00004116, 0x00004144, 0x000041e4,
+ 0x00004328, 0x00004416, 0x0000450a, 0x00004572,
+ 0x000045a8, 0x000045fc, 0x00004650, 0x0000468c,
+ 0x000046de, 0x00004790, 0x0000488c, 0x00004a8c,
+ 0x000048ac, 0x00004ab0, 0x00000000, 0x00000000,
+ 0x00000000, 0x00004c18, 0x00004ae0, 0x000022f2,
+ 0x00004e64, 0x00006e08, 0x00006c0e, 0x00007a08,
+ 0x00007a48, 0x00007aba, 0x00007ada, 0x00007af8,
+ 0x00007b82, 0x00007bd2, 0x00007c40, 0x00007cae,
+ 0x000211b6, 0x00021206, 0x00021274, 0x00008484,
+ 0x0000851c, 0x0000857a, 0x000085ca, 0x0000865e,
+ 0x00008758, 0x000087ec, 0x000088a2, 0x00008948,
+ 0x00008a54, 0x00008ac8, 0x00008b58, 0x00008bdc,
+ 0x00008bf2, 0x00008c4c, 0x00008cb4, 0x00008d5e,
+ 0x00008de6, 0x00008e6c, 0x00008f34, 0x00008f5e,
+ 0x00008ff4, 0x00009046, 0x000090da, 0x0000911c,
+ 0x00009146, 0x0000918e, 0x000091ae, 0x000091fa,
+ 0x000092e4, 0x000093a0, 0x000093e2, 0x00009424,
+ 0x00009458, 0x00009488, 0x000094ca, 0x0000950c,
+ 0x00009540, 0x00009586, 0x000096ac, 0x000097f6,
+ 0x000212c0, 0x00009bb2, 0x00009bde, 0x00009c12,
+ 0x00021362, 0x00009daa, 0x00009e20, 0x00009e7a,
+ 0x00009eb4, 0x00009f1a, 0x00009f7e, 0x00009fd6,
+ 0x0000a00a, 0x0002138c, 0x0000a0cc, 0x0000a110,
+ 0x0000a156, 0x0000a192, 0x0000a1e2, 0x0000a28e,
+ 0x0000a3ec, 0x0000a4ac, 0x0000a4d6, 0x0000a52a,
+ 0x0000a62c, 0x0000a662, 0x0000a77c, 0x0000a7be,
+ 0x0000a7e4, 0x0000a820, 0x0000a87a, 0x0000a914,
+ 0x0000a972, 0x0000aa32, 0x0000aaa2, 0x0000abf8,
+ 0x0000ad28, 0x0000ad48, 0x0000adb0, 0x0000ae52,
+ 0x0000ae8c, 0x0000af88, 0x0000b002, 0x0000b0ae,
+ 0x0000b1aa, 0x0000b2f0, 0x0000b3b0, 0x0000b442,
+ 0x0000b470, 0x0000b51a, 0x0000b550, 0x0000b578,
+ 0x0000b59a, 0x0000b5cc, 0x0000b5f6, 0x0000b648,
+ 0x0000b78e, 0x0000b7e6, 0x0000b894, 0x000214e8,
+ 0x0000bb76, 0x0000bce2, 0x0000bd04, 0x0000bd94,
+ 0x0000be98, 0x0000bfb0, 0x0000bfb2, 0x0000bff2,
+ 0x0000c060, 0x0000c0d8, 0x0000c158, 0x0000c1c6,
+ 0x0000c30e, 0x000215a8, 0x0000c388, 0x0000c4d0,
+ 0x0000c50e, 0x0000c548, 0x0000c588, 0x0000c5c8,
+ 0x000013e4, 0x00001436, 0x0000147e, 0x000014a6,
+ 0x000014de, 0x000014f2, 0x00001546, 0x000015c4,
+ 0x000015ea, 0x0000164c, 0x00001660, 0x0000168e,
+ 0x000016ca, 0x000016f0, 0x0000171e, 0x0000175e,
+ 0x00001798, 0x000017be, 0x000017e4, 0x0000183a,
+ 0x0000186a, 0x000018cc, 0x0000193a, 0x0002017e,
+ 0x00001966, 0x0000198e, 0x0000a1ca, 0x0000c2b4,
+ 0x000201bc, 0x0000cc74, 0x00011014, 0x00011076,
+ 0x000032dc, 0x000079cf
+};
+
+#endif /* __FIRMWARE_R8A779X_USB3_V3__ */
diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c
new file mode 100644
index 0000000000..d47c99644d
--- /dev/null
+++ b/drivers/usb/host/xhci-rcar.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Renesas RCar USB HOST xHCI Controller
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <usb.h>
+#include <wait_bit.h>
+
+#include "xhci.h"
+#include "xhci-rcar-r8a779x_usb3_v3.h"
+
+/* Register Offset */
+#define RCAR_USB3_DL_CTRL 0x250 /* FW Download Control & Status */
+#define RCAR_USB3_FW_DATA0 0x258 /* FW Data0 */
+
+/* Register Settings */
+/* FW Download Control & Status */
+#define RCAR_USB3_DL_CTRL_ENABLE BIT(0)
+#define RCAR_USB3_DL_CTRL_FW_SUCCESS BIT(4)
+#define RCAR_USB3_DL_CTRL_FW_SET_DATA0 BIT(8)
+
+struct rcar_xhci_platdata {
+ fdt_addr_t hcd_base;
+ struct clk clk;
+};
+
+/**
+ * Contains pointers to register base addresses
+ * for the usb controller.
+ */
+struct rcar_xhci {
+ struct xhci_ctrl ctrl; /* Needs to come first in this struct! */
+ struct usb_platdata usb_plat;
+ struct xhci_hccr *hcd;
+};
+
+static int xhci_rcar_download_fw(struct rcar_xhci *ctx, const u32 *fw_data,
+ const size_t fw_array_size)
+{
+ void __iomem *regs = (void __iomem *)ctx->hcd;
+ int i, ret;
+
+ /* Download R-Car USB3.0 firmware */
+ setbits_le32(regs + RCAR_USB3_DL_CTRL, RCAR_USB3_DL_CTRL_ENABLE);
+
+ for (i = 0; i < fw_array_size; i++) {
+ writel(fw_data[i], regs + RCAR_USB3_FW_DATA0);
+ setbits_le32(regs + RCAR_USB3_DL_CTRL,
+ RCAR_USB3_DL_CTRL_FW_SET_DATA0);
+
+ ret = wait_for_bit("xhci-rcar", regs + RCAR_USB3_DL_CTRL,
+ RCAR_USB3_DL_CTRL_FW_SET_DATA0, false,
+ 10, false);
+ if (ret)
+ break;
+ }
+
+ clrbits_le32(regs + RCAR_USB3_DL_CTRL, RCAR_USB3_DL_CTRL_ENABLE);
+
+ ret = wait_for_bit("xhci-rcar", regs + RCAR_USB3_DL_CTRL,
+ RCAR_USB3_DL_CTRL_FW_SUCCESS, true,
+ 10, false);
+
+ return ret;
+}
+
+static int xhci_rcar_probe(struct udevice *dev)
+{
+ struct rcar_xhci_platdata *plat = dev_get_platdata(dev);
+ struct rcar_xhci *ctx = dev_get_priv(dev);
+ struct xhci_hcor *hcor;
+ int len, ret;
+
+ ret = clk_get_by_index(dev, 0, &plat->clk);
+ if (ret < 0) {
+ dev_err(dev, "Failed to get USB3 clock\n");
+ return ret;
+ }
+
+ ret = clk_enable(&plat->clk);
+ if (ret) {
+ dev_err(dev, "Failed to enable USB3 clock\n");
+ goto err_clk;
+ }
+
+ ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
+ len = HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase));
+ hcor = (struct xhci_hcor *)((uintptr_t)ctx->hcd + len);
+
+ ret = xhci_rcar_download_fw(ctx, firmware_r8a779x_usb3_v3,
+ ARRAY_SIZE(firmware_r8a779x_usb3_v3));
+ if (ret) {
+ dev_err(dev, "Failed to download firmware\n");
+ goto err_fw;
+ }
+
+ ret = xhci_register(dev, ctx->hcd, hcor);
+ if (ret) {
+ dev_err(dev, "Failed to register xHCI\n");
+ goto err_fw;
+ }
+
+ return 0;
+
+err_fw:
+ clk_disable(&plat->clk);
+err_clk:
+ clk_free(&plat->clk);
+ return ret;
+}
+
+static int xhci_rcar_deregister(struct udevice *dev)
+{
+ struct rcar_xhci_platdata *plat = dev_get_platdata(dev);
+
+ clk_disable(&plat->clk);
+ clk_free(&plat->clk);
+
+ return xhci_deregister(dev);
+}
+
+static int xhci_rcar_ofdata_to_platdata(struct udevice *dev)
+{
+ struct rcar_xhci_platdata *plat = dev_get_platdata(dev);
+
+ plat->hcd_base = devfdt_get_addr(dev);
+ if (plat->hcd_base == FDT_ADDR_T_NONE) {
+ debug("Can't get the XHCI register base address\n");
+ return -ENXIO;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id xhci_rcar_ids[] = {
+ { .compatible = "renesas,xhci-r8a7795" },
+ { .compatible = "renesas,xhci-r8a7796" },
+ { }
+};
+
+U_BOOT_DRIVER(usb_xhci) = {
+ .name = "xhci_rcar",
+ .id = UCLASS_USB,
+ .probe = xhci_rcar_probe,
+ .remove = xhci_rcar_deregister,
+ .ops = &xhci_usb_ops,
+ .of_match = xhci_rcar_ids,
+ .ofdata_to_platdata = xhci_rcar_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct rcar_xhci_platdata),
+ .priv_auto_alloc_size = sizeof(struct rcar_xhci),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
generated by cgit (git 2.34.1) at 2024-12-29 15:44:31 +0000