diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 34 | ||||
| -rw-r--r-- | drivers/mmc/renesas-sdhi.c | 305 | ||||
| -rw-r--r-- | drivers/mmc/sdhci.c | 2 | ||||
| -rw-r--r-- | drivers/mmc/tmio-common.h | 4 | ||||
| -rw-r--r-- | drivers/pinctrl/broadcom/pinctrl-bcm283x.c | 3 | ||||
| -rw-r--r-- | drivers/serial/serial_bcm283x_mu.c | 2 | ||||
| -rw-r--r-- | drivers/serial/serial_bcm283x_pl011.c | 2 | ||||
| -rw-r--r-- | drivers/usb/Kconfig | 6 | ||||
| -rw-r--r-- | drivers/usb/emul/sandbox_keyb.c | 27 | ||||
| -rw-r--r-- | drivers/video/mxsfb.c | 6 |
10 files changed, 295 insertions, 96 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 8ff84aa3a8..09cb773fe9 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -12,7 +12,6 @@ #include <config.h> #include <common.h> #include <command.h> -#include <clk.h> #include <errno.h> #include <hwconfig.h> #include <mmc.h> @@ -81,7 +80,6 @@ struct fsl_esdhc_plat { struct fsl_esdhc_priv { struct fsl_esdhc *esdhc_regs; unsigned int sdhc_clk; - struct clk per_clk; unsigned int clock; #if !CONFIG_IS_ENABLED(DM_MMC) struct mmc *mmc; @@ -831,9 +829,6 @@ int fsl_esdhc_mmc_init(bd_t *bis) return fsl_esdhc_initialize(bis, cfg); } #else /* DM_MMC */ -#ifndef CONFIG_PPC -#include <asm/arch/clock.h> -#endif static int fsl_esdhc_probe(struct udevice *dev) { struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); @@ -841,7 +836,6 @@ static int fsl_esdhc_probe(struct udevice *dev) struct fsl_esdhc_priv *priv = dev_get_priv(dev); fdt_addr_t addr; struct mmc *mmc; - int ret; addr = dev_read_addr(dev); if (addr == FDT_ADDR_T_NONE) @@ -853,30 +847,10 @@ static int fsl_esdhc_probe(struct udevice *dev) #endif priv->dev = dev; - if (IS_ENABLED(CONFIG_CLK)) { - /* Assigned clock already set clock */ - ret = clk_get_by_name(dev, "per", &priv->per_clk); - if (ret) { - printf("Failed to get per_clk\n"); - return ret; - } - ret = clk_enable(&priv->per_clk); - if (ret) { - printf("Failed to enable per_clk\n"); - return ret; - } - - priv->sdhc_clk = clk_get_rate(&priv->per_clk); - } else { -#ifndef CONFIG_PPC - priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq); -#else - priv->sdhc_clk = gd->arch.sdhc_clk; -#endif - if (priv->sdhc_clk <= 0) { - dev_err(dev, "Unable to get clk for %s\n", dev->name); - return -EINVAL; - } + priv->sdhc_clk = gd->arch.sdhc_clk; + if (priv->sdhc_clk <= 0) { + dev_err(dev, "Unable to get clk for %s\n", dev->name); + return -EINVAL; } fsl_esdhc_get_cfg_common(priv, &plat->cfg); diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index 0cb65b480d..e01ac310e9 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -34,7 +34,12 @@ #define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0) #define RENESAS_SDHI_SCC_RVSREQ 0x814 #define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2) +#define RENESAS_SDHI_SCC_RVSREQ_REQTAPUP BIT(1) +#define RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0) #define RENESAS_SDHI_SCC_SMPCMP 0x818 +#define RENESAS_SDHI_SCC_SMPCMP_CMD_ERR (BIT(24) | BIT(8)) +#define RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24) +#define RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8) #define RENESAS_SDHI_SCC_TMPPORT2 0x81c #define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31) #define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) @@ -58,6 +63,49 @@ #define RENESAS_SDHI_MAX_TAP 3 +#define CALIB_TABLE_MAX (RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK + 1) + +static const u8 r8a7795_calib_table[2][CALIB_TABLE_MAX] = { + { 0, 0, 0, 0, 0, 1, 1, 2, 3, 4, 5, 5, 6, 6, 7, 11, + 15, 16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 21 }, + { 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 12, 15, + 16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 22 } +}; + +static const u8 r8a7796_rev1_calib_table[2][CALIB_TABLE_MAX] = { + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 3, 4, 9, + 15, 15, 15, 16, 16, 16, 16, 16, 17, 18, 19, 20, 21, 21, 22, 22 }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, + 2, 9, 16, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 23, 24} +}; + +static const u8 r8a7796_rev3_calib_table[2][CALIB_TABLE_MAX] = { + { 0, 0, 0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 9, 10, + 11, 12, 13, 15, 16, 17, 17, 18, 19, 19, 20, 21, 21, 22, 23, 23 }, + { 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, + 13, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22, 22, 23, 24, 24 } +}; + +static const u8 r8a77965_calib_table[2][CALIB_TABLE_MAX] = { + { 0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, + 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 29 }, + { 0, 1, 2, 2, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 15, + 16, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 31 } +}; + +static const u8 r8a77990_calib_table[2][CALIB_TABLE_MAX] = { + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 1, 2, 3, 4, 4, 4, 4, 5, 5, 6, 7, 8, 10, 11, + 12, 13, 14, 16, 17, 18, 18, 18, 19, 19, 20, 24, 26, 26, 26, 26 } +}; + +static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv) +{ + /* On R-Car Gen3, MMC0 is at 0xee140000 */ + return (uintptr_t)(priv->regbase) == 0xee140000; +} + static u32 sd_scc_tmpport_read32(struct tmio_sd_priv *priv, u32 addr) { /* read mode */ @@ -87,6 +135,102 @@ static void sd_scc_tmpport_write32(struct tmio_sd_priv *priv, u32 addr, u32 val) tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4); } +static bool renesas_sdhi_check_scc_error(struct udevice *dev) +{ + struct tmio_sd_priv *priv = dev_get_priv(dev); + struct mmc *mmc = mmc_get_mmc_dev(dev); + unsigned long new_tap = priv->tap_set; + unsigned long error_tap = priv->tap_set; + u32 reg, smpcmp; + + if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) && + (mmc->selected_mode != UHS_SDR104) && + (mmc->selected_mode != MMC_HS_200) && + (mmc->selected_mode != MMC_HS_400) && + (priv->nrtaps != 4)) + return false; + + reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL); + /* Handle automatic tuning correction */ + if (reg & RENESAS_SDHI_SCC_RVSCNTL_RVSEN) { + reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ); + if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR) { + tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ); + return true; + } + + return false; + } + + /* Handle manual tuning correction */ + reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ); + if (!reg) /* No error */ + return false; + + tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ); + + if (mmc->selected_mode == MMC_HS_400) { + /* + * Correction Error Status contains CMD and DAT signal status. + * In HS400, DAT signal based on DS signal, not CLK. + * Therefore, use only CMD status. + */ + smpcmp = tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP) & + RENESAS_SDHI_SCC_SMPCMP_CMD_ERR; + + switch (smpcmp) { + case 0: + return false; /* No error in CMD signal */ + case RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP: + new_tap = (priv->tap_set + + priv->tap_num + 1) % priv->tap_num; + error_tap = (priv->tap_set + + priv->tap_num - 1) % priv->tap_num; + break; + case RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN: + new_tap = (priv->tap_set + + priv->tap_num - 1) % priv->tap_num; + error_tap = (priv->tap_set + + priv->tap_num + 1) % priv->tap_num; + break; + default: + return true; /* Need re-tune */ + } + + if (priv->hs400_bad_tap & BIT(new_tap)) { + /* + * New tap is bad tap (cannot change). + * Compare with HS200 tuning result. + * In HS200 tuning, when smpcmp[error_tap] + * is OK, retune is executed. + */ + if (priv->smpcmp & BIT(error_tap)) + return true; /* Need retune */ + + return false; /* cannot change */ + } + + priv->tap_set = new_tap; + } else { + if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR) + return true; /* Need re-tune */ + else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPUP) + priv->tap_set = (priv->tap_set + + priv->tap_num + 1) % priv->tap_num; + else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN) + priv->tap_set = (priv->tap_set + + priv->tap_num - 1) % priv->tap_num; + else + return false; + } + + /* Set TAP position */ + tmio_sd_writel(priv, priv->tap_set >> ((priv->nrtaps == 4) ? 1 : 0), + RENESAS_SDHI_SCC_TAPSET); + + return false; +} + static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_sd_priv *priv) { u32 calib_code; @@ -97,28 +241,30 @@ static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_sd_priv *priv) if (!priv->needs_adjust_hs400) return; + if (!priv->adjust_hs400_calib_table) + return; + /* * Enabled Manual adjust HS400 mode * * 1) Disabled Write Protect * W(addr=0x00, WP_DISABLE_CODE) - * 2) Read Calibration code and adjust - * R(addr=0x26) - adjust value - * 3) Enabled Manual Calibration + * + * 2) Read Calibration code + * read_value = R(addr=0x26) + * 3) Refer to calibration table + * Calibration code = table[read_value] + * 4) Enabled Manual Calibration * W(addr=0x22, manual mode | Calibration code) - * 4) Set Offset value to TMPPORT3 Reg + * 5) Set Offset value to TMPPORT3 Reg */ sd_scc_tmpport_write32(priv, 0x00, RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); calib_code = sd_scc_tmpport_read32(priv, 0x26); calib_code &= RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK; - if (calib_code > priv->adjust_hs400_calibrate) - calib_code -= priv->adjust_hs400_calibrate; - else - calib_code = 0; sd_scc_tmpport_write32(priv, 0x22, RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE | - calib_code); + priv->adjust_hs400_calib_table[calib_code]); tmio_sd_writel(priv, priv->adjust_hs400_offset, RENESAS_SDHI_SCC_TMPPORT3); @@ -220,6 +366,7 @@ static int renesas_sdhi_hs400(struct udevice *dev) struct mmc *mmc = mmc_get_mmc_dev(dev); bool hs400 = (mmc->selected_mode == MMC_HS_400); int ret, taps = hs400 ? priv->nrtaps : 8; + unsigned long new_tap; u32 reg; if (taps == 4) /* HS400 on 4tap SoC needs different clock */ @@ -229,7 +376,9 @@ static int renesas_sdhi_hs400(struct udevice *dev) if (ret < 0) return ret; - tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ); + reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL); + reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN; + tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL); reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2); if (hs400) { @@ -250,24 +399,38 @@ static int renesas_sdhi_hs400(struct udevice *dev) RENESAS_SDHI_SCC_DTCNTL_TAPEN, RENESAS_SDHI_SCC_DTCNTL); + /* Avoid bad TAP */ + if (priv->hs400_bad_tap & BIT(priv->tap_set)) { + new_tap = (priv->tap_set + + priv->tap_num + 1) % priv->tap_num; + + if (priv->hs400_bad_tap & BIT(new_tap)) + new_tap = (priv->tap_set + + priv->tap_num - 1) % priv->tap_num; + + if (priv->hs400_bad_tap & BIT(new_tap)) { + new_tap = priv->tap_set; + debug("Three consecutive bad tap is prohibited\n"); + } + + priv->tap_set = new_tap; + tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET); + } + if (taps == 4) { tmio_sd_writel(priv, priv->tap_set >> 1, RENESAS_SDHI_SCC_TAPSET); + tmio_sd_writel(priv, hs400 ? 0x100 : 0x300, + RENESAS_SDHI_SCC_DT2FF); } else { tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET); + tmio_sd_writel(priv, 0x300, RENESAS_SDHI_SCC_DT2FF); } - tmio_sd_writel(priv, hs400 ? 0x704 : 0x300, - RENESAS_SDHI_SCC_DT2FF); - reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL); reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL; tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL); - reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL); - reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN; - tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL); - /* Execute adjust hs400 offset after setting to HS400 mode */ if (hs400) priv->needs_adjust_hs400 = true; @@ -289,8 +452,7 @@ static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv) } static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv, - unsigned int tap_num, unsigned int taps, - unsigned int smpcmp) + unsigned int taps) { unsigned long tap_cnt; /* counter of tuning success */ unsigned long tap_start;/* start position of tuning success */ @@ -307,14 +469,14 @@ static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv, tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ); /* Merge the results */ - for (i = 0; i < tap_num * 2; i++) { + for (i = 0; i < priv->tap_num * 2; i++) { if (!(taps & BIT(i))) { - taps &= ~BIT(i % tap_num); - taps &= ~BIT((i % tap_num) + tap_num); + taps &= ~BIT(i % priv->tap_num); + taps &= ~BIT((i % priv->tap_num) + priv->tap_num); } - if (!(smpcmp & BIT(i))) { - smpcmp &= ~BIT(i % tap_num); - smpcmp &= ~BIT((i % tap_num) + tap_num); + if (!(priv->smpcmp & BIT(i))) { + priv->smpcmp &= ~BIT(i % priv->tap_num); + priv->smpcmp &= ~BIT((i % priv->tap_num) + priv->tap_num); } } @@ -327,7 +489,7 @@ static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv, ntap = 0; tap_start = 0; tap_end = 0; - for (i = 0; i < tap_num * 2; i++) { + for (i = 0; i < priv->tap_num * 2; i++) { if (taps & BIT(i)) ntap++; else { @@ -350,13 +512,13 @@ static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv, * If all of the TAP is OK, the sampling clock position is selected by * identifying the change point of data. */ - if (tap_cnt == tap_num * 2) { + if (tap_cnt == priv->tap_num * 2) { match_cnt = 0; ntap = 0; tap_start = 0; tap_end = 0; - for (i = 0; i < tap_num * 2; i++) { - if (smpcmp & BIT(i)) + for (i = 0; i < priv->tap_num * 2; i++) { + if (priv->smpcmp & BIT(i)) ntap++; else { if (ntap > match_cnt) { @@ -378,7 +540,7 @@ static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv, select = true; if (select) - priv->tap_set = ((tap_start + tap_end) / 2) % tap_num; + priv->tap_set = ((tap_start + tap_end) / 2) % priv->tap_num; else return -EIO; @@ -399,7 +561,7 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode) struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct mmc *mmc = upriv->mmc; unsigned int tap_num; - unsigned int taps = 0, smpcmp = 0; + unsigned int taps = 0; int i, ret = 0; u32 caps; @@ -419,15 +581,19 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode) /* Tuning is not supported */ goto out; - if (tap_num * 2 >= sizeof(taps) * 8) { + priv->tap_num = tap_num; + + if (priv->tap_num * 2 >= sizeof(taps) * 8) { dev_err(dev, "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n"); goto out; } + priv->smpcmp = 0; + /* Issue CMD19 twice for each tap */ - for (i = 0; i < 2 * tap_num; i++) { - renesas_sdhi_prepare_tuning(priv, i % tap_num); + for (i = 0; i < 2 * priv->tap_num; i++) { + renesas_sdhi_prepare_tuning(priv, i % priv->tap_num); /* Force PIO for the tuning */ caps = priv->caps; @@ -442,12 +608,12 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode) ret = renesas_sdhi_compare_scc_data(priv); if (ret == 0) - smpcmp |= BIT(i); + priv->smpcmp |= BIT(i); mdelay(1); } - ret = renesas_sdhi_select_tuning(priv, tap_num, taps, smpcmp); + ret = renesas_sdhi_select_tuning(priv, taps); out: if (ret < 0) { @@ -535,6 +701,8 @@ static int renesas_sdhi_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) struct tmio_sd_priv *priv = dev_get_priv(dev); + renesas_sdhi_check_scc_error(dev); + if (cmd->cmdidx == MMC_CMD_SEND_STATUS) renesas_sdhi_adjust_hs400_mode_enable(priv); #endif @@ -582,50 +750,89 @@ static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv) static void renesas_sdhi_filter_caps(struct udevice *dev) { - struct tmio_sd_plat *plat = dev_get_platdata(dev); struct tmio_sd_priv *priv = dev_get_priv(dev); if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3)) return; - /* HS400 is not supported on H3 ES1.x and M3W ES1.0,ES1.1,ES1.2 */ +#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) + struct tmio_sd_plat *plat = dev_get_platdata(dev); + + /* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */ if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && (rmobile_get_cpu_rev_integer() <= 1)) || ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) && (rmobile_get_cpu_rev_integer() == 1) && - (rmobile_get_cpu_rev_fraction() <= 2))) + (rmobile_get_cpu_rev_fraction() < 2))) plat->cfg.host_caps &= ~MMC_MODE_HS400; - /* M3W ES1.x for x>2 can use HS400 with manual adjustment */ + /* H3 ES2.0, ES3.0 and M3W ES1.2 and M3N bad taps */ + if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && + (rmobile_get_cpu_rev_integer() >= 2)) || + ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) && + (rmobile_get_cpu_rev_integer() == 1) && + (rmobile_get_cpu_rev_fraction() == 2)) || + (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965)) + priv->hs400_bad_tap = BIT(2) | BIT(3) | BIT(6) | BIT(7); + + /* H3 ES3.0 can use HS400 with manual adjustment */ + if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && + (rmobile_get_cpu_rev_integer() >= 3)) { + priv->adjust_hs400_enable = true; + priv->adjust_hs400_offset = 0; + priv->adjust_hs400_calib_table = + r8a7795_calib_table[!rmobile_is_gen3_mmc0(priv)]; + } + + /* M3W ES1.2 can use HS400 with manual adjustment */ + if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) && + (rmobile_get_cpu_rev_integer() == 1) && + (rmobile_get_cpu_rev_fraction() == 2)) { + priv->adjust_hs400_enable = true; + priv->adjust_hs400_offset = 3; + priv->adjust_hs400_calib_table = + r8a7796_rev1_calib_table[!rmobile_is_gen3_mmc0(priv)]; + } + + /* M3W ES1.x for x>2 can use HS400 with manual adjustment and taps */ if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) && (rmobile_get_cpu_rev_integer() == 1) && (rmobile_get_cpu_rev_fraction() > 2)) { priv->adjust_hs400_enable = true; priv->adjust_hs400_offset = 0; - priv->adjust_hs400_calibrate = 0x9; + priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7); + priv->adjust_hs400_calib_table = + r8a7796_rev3_calib_table[!rmobile_is_gen3_mmc0(priv)]; } /* M3N can use HS400 with manual adjustment */ if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) { priv->adjust_hs400_enable = true; - priv->adjust_hs400_offset = 0; - priv->adjust_hs400_calibrate = 0x0; + priv->adjust_hs400_offset = 3; + priv->adjust_hs400_calib_table = + r8a77965_calib_table[!rmobile_is_gen3_mmc0(priv)]; } /* E3 can use HS400 with manual adjustment */ if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) { priv->adjust_hs400_enable = true; - priv->adjust_hs400_offset = 0; - priv->adjust_hs400_calibrate = 0x2; + priv->adjust_hs400_offset = 3; + priv->adjust_hs400_calib_table = + r8a77990_calib_table[!rmobile_is_gen3_mmc0(priv)]; } - /* H3 ES2.0 uses 4 tuning taps */ - if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && - (rmobile_get_cpu_rev_integer() == 2)) + /* H3 ES1.x, ES2.0 and M3W ES1.0, ES1.1, ES1.2 uses 4 tuning taps */ + if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && + (rmobile_get_cpu_rev_integer() <= 2)) || + ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) && + (rmobile_get_cpu_rev_integer() == 1) && + (rmobile_get_cpu_rev_fraction() <= 2))) priv->nrtaps = 4; else priv->nrtaps = 8; - +#endif /* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */ if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && (rmobile_get_cpu_rev_integer() <= 1)) || diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index fbc576fd72..32e83db8e0 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -660,7 +660,7 @@ int sdhci_probe(struct udevice *dev) return sdhci_init(mmc); } -int sdhci_get_cd(struct udevice *dev) +static int sdhci_get_cd(struct udevice *dev) { struct mmc *mmc = mmc_get_mmc_dev(dev); struct sdhci_host *host = mmc->priv; diff --git a/drivers/mmc/tmio-common.h b/drivers/mmc/tmio-common.h index 51607de142..047458849b 100644 --- a/drivers/mmc/tmio-common.h +++ b/drivers/mmc/tmio-common.h @@ -137,12 +137,16 @@ struct tmio_sd_priv { struct clk clk; #endif #if CONFIG_IS_ENABLED(RENESAS_SDHI) + unsigned int smpcmp; u8 tap_set; + u8 tap_num; u8 nrtaps; bool needs_adjust_hs400; bool adjust_hs400_enable; u8 adjust_hs400_offset; u8 adjust_hs400_calibrate; + u8 hs400_bad_tap; + const u8 *adjust_hs400_calib_table; #endif ulong (*clk_get_rate)(struct tmio_sd_priv *); }; diff --git a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c index 3be080d29e..eb720f09f8 100644 --- a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c +++ b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c @@ -99,6 +99,7 @@ static int bcm283x_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, static const struct udevice_id bcm2835_pinctrl_id[] = { {.compatible = "brcm,bcm2835-gpio"}, + {.compatible = "brcm,bcm2711-gpio"}, {} }; @@ -148,7 +149,7 @@ U_BOOT_DRIVER(pinctrl_bcm283x) = { .priv_auto_alloc_size = sizeof(struct bcm283x_pinctrl_priv), .ops = &bcm283x_pinctrl_ops, .probe = bcm283x_pinctl_probe, -#if !CONFIG_IS_ENABLED(OF_CONTROL) +#if !CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_BOARD) .flags = DM_FLAG_PRE_RELOC, #endif }; diff --git a/drivers/serial/serial_bcm283x_mu.c b/drivers/serial/serial_bcm283x_mu.c index bd1d89ec83..a6ffc84b96 100644 --- a/drivers/serial/serial_bcm283x_mu.c +++ b/drivers/serial/serial_bcm283x_mu.c @@ -199,7 +199,7 @@ U_BOOT_DRIVER(serial_bcm283x_mu) = { .platdata_auto_alloc_size = sizeof(struct bcm283x_mu_serial_platdata), .probe = bcm283x_mu_serial_probe, .ops = &bcm283x_mu_serial_ops, -#if !CONFIG_IS_ENABLED(OF_CONTROL) +#if !CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_BOARD) .flags = DM_FLAG_PRE_RELOC, #endif .priv_auto_alloc_size = sizeof(struct bcm283x_mu_priv), diff --git a/drivers/serial/serial_bcm283x_pl011.c b/drivers/serial/serial_bcm283x_pl011.c index 2527bb8b1c..7d8ab7b716 100644 --- a/drivers/serial/serial_bcm283x_pl011.c +++ b/drivers/serial/serial_bcm283x_pl011.c @@ -90,7 +90,7 @@ U_BOOT_DRIVER(bcm283x_pl011_uart) = { .platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata), .probe = pl01x_serial_probe, .ops = &bcm283x_pl011_serial_ops, -#if !CONFIG_IS_ENABLED(OF_CONTROL) +#if !CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_BOARD) .flags = DM_FLAG_PRE_RELOC, #endif .priv_auto_alloc_size = sizeof(struct pl01x_priv), diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 9af78e8822..bea4a92b61 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -100,6 +100,12 @@ config USB_KEYBOARD if USB_KEYBOARD +config USB_KEYBOARD_FN_KEYS + bool "USB keyboard function key support" + help + Say Y here if you want support for keys F1 - F12, INS, HOME, DELETE, + END, PAGE UP, and PAGE DOWN. + choice prompt "USB keyboard polling" default SYS_USB_EVENT_POLL diff --git a/drivers/usb/emul/sandbox_keyb.c b/drivers/usb/emul/sandbox_keyb.c index dc43880d27..32bc9a1698 100644 --- a/drivers/usb/emul/sandbox_keyb.c +++ b/drivers/usb/emul/sandbox_keyb.c @@ -155,14 +155,20 @@ static void *keyb_desc_list[] = { NULL, }; -int sandbox_usb_keyb_add_string(struct udevice *dev, const char *str) +/** + * sandbox_usb_keyb_add_string() - provide a USB scancode buffer + * + * @dev: the keyboard emulation device + * @scancode: scancode buffer with USB_KBD_BOOT_REPORT_SIZE bytes + */ +int sandbox_usb_keyb_add_string(struct udevice *dev, + const char scancode[USB_KBD_BOOT_REPORT_SIZE]) { struct sandbox_keyb_priv *priv = dev_get_priv(dev); - int len, ret; + int ret; - len = strlen(str); - ret = membuff_put(&priv->in, str, len); - if (ret != len) + ret = membuff_put(&priv->in, scancode, USB_KBD_BOOT_REPORT_SIZE); + if (ret != USB_KBD_BOOT_REPORT_SIZE) return -ENOSPC; return 0; @@ -183,12 +189,12 @@ static int sandbox_keyb_interrupt(struct udevice *dev, struct usb_device *udev, { struct sandbox_keyb_priv *priv = dev_get_priv(dev); uint8_t *data = buffer; - int ch; memset(data, '\0', length); - ch = membuff_getbyte(&priv->in); - if (ch != -1) - data[2] = 4 + ch - 'a'; + if (length < USB_KBD_BOOT_REPORT_SIZE) + return 0; + + membuff_get(&priv->in, buffer, USB_KBD_BOOT_REPORT_SIZE); return 0; } @@ -213,7 +219,8 @@ static int sandbox_keyb_probe(struct udevice *dev) { struct sandbox_keyb_priv *priv = dev_get_priv(dev); - return membuff_new(&priv->in, 256); + /* Provide an 80 character keyboard buffer */ + return membuff_new(&priv->in, 80 * USB_KBD_BOOT_REPORT_SIZE); } static const struct dm_usb_ops sandbox_usb_keyb_ops = { diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index d73a8bac99..c52981053e 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -57,6 +57,9 @@ static void mxs_lcd_init(u32 fb_addr, struct ctfb_res_modes *mode, int bpp) uint32_t word_len = 0, bus_width = 0; uint8_t valid_data = 0; + /* Kick in the LCDIF clock */ + mxs_set_lcdclk(MXS_LCDIF_BASE, PS2KHZ(mode->pixclock)); + /* Restart the LCDIF block */ mxs_reset_block(®s->hw_lcdif_ctrl_reg); @@ -127,9 +130,6 @@ static void mxs_lcd_init(u32 fb_addr, struct ctfb_res_modes *mode, int bpp) /* FIFO cleared */ writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_clr); - /* Kick in the LCDIF clock */ - mxs_set_lcdclk(MXS_LCDIF_BASE, PS2KHZ(mode->pixclock)); - /* RUN! */ writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set); } |