diff options
Diffstat (limited to 'drivers')
28 files changed, 630 insertions, 55 deletions
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index e69de29bb2..1b92c7789d 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -0,0 +1,22 @@ +menu "DMA Support" + +config DMA + bool "Enable Driver Model for DMA drivers" + depends on DM + help + Enable driver model for DMA. DMA engines can do + asynchronous data transfers without involving the host + CPU. Currently, this framework can be used to offload + memory copies to and from devices like qspi, ethernet + etc Drivers provide methods to access the DMA devices + buses that is used to transfer data to and from memory. + The uclass interface is defined in include/dma.h. + +config TI_EDMA3 + bool "TI EDMA3 driver" + help + Enable the TI EDMA3 driver for DRA7xx and AM43xx evms. + This driver support data transfer between memory + regions. + +endmenu # menu "DMA Support" diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index f95fe70a99..39b78b2a3d 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -5,6 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-$(CONFIG_DMA) += dma-uclass.o + obj-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o obj-$(CONFIG_APBH_DMA) += apbh_dma.o obj-$(CONFIG_FSL_DMA) += fsl_dma.o diff --git a/drivers/dma/dma-uclass.c b/drivers/dma/dma-uclass.c new file mode 100644 index 0000000000..ea21fd9c6f --- /dev/null +++ b/drivers/dma/dma-uclass.c @@ -0,0 +1,72 @@ +/* + * Direct Memory Access U-Class driver + * + * (C) Copyright 2015 + * Texas Instruments Incorporated, <www.ti.com> + * + * Author: Mugunthan V N <mugunthanvnm@ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dma.h> +#include <dm.h> +#include <dm/uclass-internal.h> +#include <dm/device-internal.h> +#include <errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dma_get_device(u32 transfer_type, struct udevice **devp) +{ + struct udevice *dev; + int ret; + + for (ret = uclass_first_device(UCLASS_DMA, &dev); dev && !ret; + ret = uclass_next_device(&dev)) { + struct dma_dev_priv *uc_priv; + + uc_priv = dev_get_uclass_priv(dev); + if (uc_priv->supported & transfer_type) + break; + } + + if (!dev) { + error("No DMA device found that supports %x type\n", + transfer_type); + return -EPROTONOSUPPORT; + } + + *devp = dev; + + return ret; +} + +int dma_memcpy(void *dst, void *src, size_t len) +{ + struct udevice *dev; + const struct dma_ops *ops; + int ret; + + ret = dma_get_device(DMA_SUPPORTS_MEM_TO_MEM, &dev); + if (ret < 0) + return ret; + + ops = device_get_ops(dev); + if (!ops->transfer) + return -ENOSYS; + + /* Invalidate the area, so no writeback into the RAM races with DMA */ + invalidate_dcache_range((unsigned long)dst, (unsigned long)dst + + roundup(len, ARCH_DMA_MINALIGN)); + + return ops->transfer(dev, DMA_MEM_TO_MEM, dst, src, len); +} + +UCLASS_DRIVER(dma) = { + .id = UCLASS_DMA, + .name = "dma", + .flags = DM_UC_FLAG_SEQ_ALIAS, + .per_device_auto_alloc_size = sizeof(struct dma_dev_priv), +}; diff --git a/drivers/dma/ti-edma3.c b/drivers/dma/ti-edma3.c index d6a427f2e2..247843891e 100644 --- a/drivers/dma/ti-edma3.c +++ b/drivers/dma/ti-edma3.c @@ -11,6 +11,9 @@ #include <asm/io.h> #include <common.h> +#include <dma.h> +#include <dm/device.h> +#include <asm/omap_common.h> #include <asm/ti-common/ti-edma3.h> #define EDMA3_SL_BASE(slot) (0x4000 + ((slot) << 5)) @@ -31,6 +34,10 @@ #define EDMA3_QEESR 0x108c #define EDMA3_QSECR 0x1094 +struct ti_edma3_priv { + u32 base; +}; + /** * qedma3_start - start qdma on a channel * @base: base address of edma @@ -383,8 +390,8 @@ void qedma3_stop(u32 base, struct edma3_channel_config *cfg) __raw_writel(0, base + EDMA3_QCHMAP(cfg->chnum)); } -void edma3_transfer(unsigned long edma3_base_addr, unsigned int - edma_slot_num, void *dst, void *src, size_t len) +void __edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, + void *dst, void *src, size_t len) { struct edma3_slot_config slot; struct edma3_channel_config edma_channel; @@ -460,3 +467,74 @@ void edma3_transfer(unsigned long edma3_base_addr, unsigned int qedma3_stop(edma3_base_addr, &edma_channel); } } + +#ifndef CONFIG_DMA + +void edma3_transfer(unsigned long edma3_base_addr, unsigned int edma_slot_num, + void *dst, void *src, size_t len) +{ + __edma3_transfer(edma3_base_addr, edma_slot_num, dst, src, len); +} + +#else + +static int ti_edma3_transfer(struct udevice *dev, int direction, void *dst, + void *src, size_t len) +{ + struct ti_edma3_priv *priv = dev_get_priv(dev); + + /* enable edma3 clocks */ + enable_edma3_clocks(); + + switch (direction) { + case DMA_MEM_TO_MEM: + __edma3_transfer(priv->base, 1, dst, src, len); + break; + default: + error("Transfer type not implemented in DMA driver\n"); + break; + } + + /* disable edma3 clocks */ + disable_edma3_clocks(); + + return 0; +} + +static int ti_edma3_ofdata_to_platdata(struct udevice *dev) +{ + struct ti_edma3_priv *priv = dev_get_priv(dev); + + priv->base = dev_get_addr(dev); + + return 0; +} + +static int ti_edma3_probe(struct udevice *dev) +{ + struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + uc_priv->supported = DMA_SUPPORTS_MEM_TO_MEM; + + return 0; +} + +static const struct dma_ops ti_edma3_ops = { + .transfer = ti_edma3_transfer, +}; + +static const struct udevice_id ti_edma3_ids[] = { + { .compatible = "ti,edma3" }, + { } +}; + +U_BOOT_DRIVER(ti_edma3) = { + .name = "ti_edma3", + .id = UCLASS_DMA, + .of_match = ti_edma3_ids, + .ops = &ti_edma3_ops, + .ofdata_to_platdata = ti_edma3_ofdata_to_platdata, + .probe = ti_edma3_probe, + .priv_auto_alloc_size = sizeof(struct ti_edma3_priv), +}; +#endif /* CONFIG_DMA */ diff --git a/drivers/gpio/stm32_gpio.c b/drivers/gpio/stm32_gpio.c index 75a84e111f..50f86d3dd6 100644 --- a/drivers/gpio/stm32_gpio.c +++ b/drivers/gpio/stm32_gpio.c @@ -19,17 +19,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_STM32F4) -#define STM32_GPIOA_BASE (STM32_AHB1PERIPH_BASE + 0x0000) -#define STM32_GPIOB_BASE (STM32_AHB1PERIPH_BASE + 0x0400) -#define STM32_GPIOC_BASE (STM32_AHB1PERIPH_BASE + 0x0800) -#define STM32_GPIOD_BASE (STM32_AHB1PERIPH_BASE + 0x0C00) -#define STM32_GPIOE_BASE (STM32_AHB1PERIPH_BASE + 0x1000) -#define STM32_GPIOF_BASE (STM32_AHB1PERIPH_BASE + 0x1400) -#define STM32_GPIOG_BASE (STM32_AHB1PERIPH_BASE + 0x1800) -#define STM32_GPIOH_BASE (STM32_AHB1PERIPH_BASE + 0x1C00) -#define STM32_GPIOI_BASE (STM32_AHB1PERIPH_BASE + 0x2000) - +#if defined(CONFIG_STM32F4) || defined(CONFIG_STM32F7) static const unsigned long io_base[] = { STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE, STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE, @@ -70,8 +60,6 @@ int stm32_gpio_config(const struct stm32_gpio_dsc *dsc, gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port]; - setbits_le32(&STM32_RCC->ahb1enr, 1 << dsc->port); - i = (dsc->pin & 0x07) * 4; clrsetbits_le32(&gpio_regs->afr[dsc->pin >> 3], 0xF << i, ctl->af << i); @@ -87,14 +75,6 @@ out: return rv; } #elif defined(CONFIG_STM32F1) -#define STM32_GPIOA_BASE (STM32_APB2PERIPH_BASE + 0x0800) -#define STM32_GPIOB_BASE (STM32_APB2PERIPH_BASE + 0x0C00) -#define STM32_GPIOC_BASE (STM32_APB2PERIPH_BASE + 0x1000) -#define STM32_GPIOD_BASE (STM32_APB2PERIPH_BASE + 0x1400) -#define STM32_GPIOE_BASE (STM32_APB2PERIPH_BASE + 0x1800) -#define STM32_GPIOF_BASE (STM32_APB2PERIPH_BASE + 0x1C00) -#define STM32_GPIOG_BASE (STM32_APB2PERIPH_BASE + 0x2000) - static const unsigned long io_base[] = { STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE, STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE, @@ -141,9 +121,6 @@ int stm32_gpio_config(const struct stm32_gpio_dsc *dsc, gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port]; - /* Enable clock for GPIO port */ - setbits_le32(&STM32_RCC->apb2enr, 0x04 << dsc->port); - if (p < 8) { cr = &gpio_regs->crl; crp = p; @@ -230,7 +207,7 @@ int gpio_direction_input(unsigned gpio) dsc.port = stm32_gpio_to_port(gpio); dsc.pin = stm32_gpio_to_pin(gpio); -#if defined(CONFIG_STM32F4) +#if defined(CONFIG_STM32F4) || defined(CONFIG_STM32F7) ctl.af = STM32_GPIO_AF0; ctl.mode = STM32_GPIO_MODE_IN; ctl.otype = STM32_GPIO_OTYPE_PP; @@ -256,7 +233,7 @@ int gpio_direction_output(unsigned gpio, int value) dsc.port = stm32_gpio_to_port(gpio); dsc.pin = stm32_gpio_to_pin(gpio); -#if defined(CONFIG_STM32F4) +#if defined(CONFIG_STM32F4) || defined(CONFIG_STM32F7) ctl.af = STM32_GPIO_AF0; ctl.mode = STM32_GPIO_MODE_OUT; ctl.pupd = STM32_GPIO_PUPD_NO; diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 9f4b766f7a..9d3f7e908f 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -37,4 +37,10 @@ config PIC32_SDHCI help Support for Microchip PIC32 SDHCI controller. +config ZYNQ_SDHCI + bool "Arasan SDHCI controller support" + depends on DM_MMC && OF_CONTROL + help + Support for Arasan SDHCI host controller on Zynq/ZynqMP ARM SoCs platform + endmenu diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 8a60c72926..3c365d5e9a 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -16,6 +16,7 @@ #include <spi.h> #include <spi_flash.h> #include <linux/log2.h> +#include <dma.h> #include "sf_internal.h" @@ -454,8 +455,16 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, return ret; } +/* + * TODO: remove the weak after all the other spi_flash_copy_mmap + * implementations removed from drivers + */ void __weak spi_flash_copy_mmap(void *data, void *offset, size_t len) { +#ifdef CONFIG_DMA + if (!dma_memcpy(data, offset, len)) + return; +#endif memcpy(data, offset, len); } diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index bba48da409..259a87fcc5 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -203,6 +203,14 @@ static int rtl8211x_startup(struct phy_device *phydev) return 0; } +static int rtl8211e_startup(struct phy_device *phydev) +{ + genphy_update_link(phydev); + genphy_parse_link(phydev); + + return 0; +} + static int rtl8211f_startup(struct phy_device *phydev) { /* Read the Status (2x to make sure link is right) */ @@ -230,7 +238,7 @@ static struct phy_driver RTL8211E_driver = { .mask = 0xffffff, .features = PHY_GBIT_FEATURES, .config = &rtl8211x_config, - .startup = &rtl8211x_startup, + .startup = &rtl8211e_startup, .shutdown = &genphy_shutdown, }; diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index d5bf6f4c47..9eb605be74 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -266,7 +266,7 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void), int exec_method) { struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); - struct pci_rom_header *rom, *ram = NULL; + struct pci_rom_header *rom = NULL, *ram = NULL; int vesa_mode = -1; bool emulate, alloced; int ret; diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 10683a21d9..adc64552e7 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -48,6 +48,13 @@ config AXP818_POWER Say y here to enable support for the axp818 pmic found on A83T dev board. +config SY8106A_POWER + boolean "SY8106A pmic support" + depends on MACH_SUN8I_H3 + ---help--- + Select this to enable support for the SY8106A pmic found on some + H3 boards. + endchoice config AXP_DCDC1_VOLT @@ -232,4 +239,13 @@ config AXP_ELDO3_VOLT 1.2V for the SSD2828 chip (converter of parallel LCD interface into MIPI DSI). +config SY8106A_VOUT1_VOLT + int "SY8106A pmic VOUT1 voltage" + depends on SY8106A_POWER + default 1200 + ---help--- + Set the voltage (mV) to program the SY8106A pmic VOUT1. This + is typically used to power the VDD-CPU and should be 1200mV. + Values can range from 680mV till 1950mV. + endmenu diff --git a/drivers/power/Makefile b/drivers/power/Makefile index 0fdbca3c35..690faa0f5e 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_AXP221_POWER) += axp221.o obj-$(CONFIG_AXP818_POWER) += axp818.o obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o obj-$(CONFIG_FTPMU010_POWER) += ftpmu010.o +obj-$(CONFIG_SY8106A_POWER) += sy8106a.o obj-$(CONFIG_TPS6586X_POWER) += tps6586x.o obj-$(CONFIG_TWL4030_POWER) += twl4030.o obj-$(CONFIG_TWL6030_POWER) += twl6030.o diff --git a/drivers/power/pmic/pmic_tps65218.c b/drivers/power/pmic/pmic_tps65218.c index dbc7a73a72..0fd0ad478a 100644 --- a/drivers/power/pmic/pmic_tps65218.c +++ b/drivers/power/pmic/pmic_tps65218.c @@ -11,6 +11,20 @@ #include <power/pmic.h> #include <power/tps65218.h> +int tps65218_reg_read(uchar dest_reg, uchar *dest_val) +{ + uchar read_val; + int ret; + + ret = i2c_read(TPS65218_CHIP_PM, dest_reg, 1, &read_val, 1); + if (ret) + return ret; + + *dest_val = read_val; + + return 0; +} + /** * tps65218_reg_write() - Generic function that can write a TPS65218 PMIC * register or bit field regardless of protection @@ -98,6 +112,48 @@ int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel) return 0; } +/** + * tps65218_toggle_fseal() - Perform the sequence that toggles the FSEAL bit. + * + * @return: 0 on success, -EBADE if the sequence was broken + */ +int tps65218_toggle_fseal(void) +{ + if (tps65218_reg_write(TPS65218_PROT_LEVEL_NONE, TPS65218_PASSWORD, + 0xb1, TPS65218_MASK_ALL_BITS)) + return -EBADE; + + if (tps65218_reg_write(TPS65218_PROT_LEVEL_NONE, TPS65218_PASSWORD, + 0xfe, TPS65218_MASK_ALL_BITS)) + return -EBADE; + + if (tps65218_reg_write(TPS65218_PROT_LEVEL_NONE, TPS65218_PASSWORD, + 0xa3, TPS65218_MASK_ALL_BITS)) + return -EBADE; + + return 0; +} + +/** + * tps65218_lock_fseal() - Perform the sequence that locks the FSEAL bit to 1. + * + * The FSEAL bit prevents the PMIC from turning off DCDC5 and DCDC6. It can be + * toggled at most 3 times: 0->1, 1->0, and finally 0->1. After the third switch + * its value is locked and can only be reset by powering off the PMIC entirely. + * + * @return: 0 on success, -EBADE if the sequence was broken + */ +int tps65218_lock_fseal(void) +{ + int i; + + for (i = 0; i < 3; i++) + if (tps65218_toggle_fseal()) + return -EBADE; + + return 0; +} + int power_tps65218_init(unsigned char bus) { static const char name[] = "TPS65218_PMIC"; diff --git a/drivers/power/sy8106a.c b/drivers/power/sy8106a.c new file mode 100644 index 0000000000..bbf116f655 --- /dev/null +++ b/drivers/power/sy8106a.c @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2016 + * Jelle van der Waa <jelle@vdwaa.nl> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <i2c.h> +#include <sy8106a.h> + +#define SY8106A_I2C_ADDR 0x65 +#define SY8106A_VOUT1_SEL 1 +#define SY8106A_VOUT1_SEL_ENABLE (1 << 7) + +static u8 sy8106a_mvolt_to_cfg(int mvolt, int min, int max, int div) +{ + if (mvolt < min) + mvolt = min; + else if (mvolt > max) + mvolt = max; + + return (mvolt - min) / div; +} + +int sy8106a_set_vout1(unsigned int mvolt) +{ + u8 data = sy8106a_mvolt_to_cfg(mvolt, 680, 1950, 10) | SY8106A_VOUT1_SEL_ENABLE; + return i2c_write(SY8106A_I2C_ADDR, SY8106A_VOUT1_SEL, 1, &data, 1); +} diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index c63999ac41..05bdf56c6f 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_ARC_SERIAL) += serial_arc.o obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o +obj-$(CONFIG_STM32X7_SERIAL) += serial_stm32x7.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 93dad338b3..28da9ddfd8 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -105,7 +105,7 @@ static void ns16550_writeb(NS16550_t port, int offset, int value) * As far as we know it doesn't make sense to support selection of * these options at run-time, so use the existing CONFIG options. */ - serial_out_shift(addr, plat->reg_shift, value); + serial_out_shift(addr + plat->reg_offset, plat->reg_shift, value); } static int ns16550_readb(NS16550_t port, int offset) @@ -116,7 +116,7 @@ static int ns16550_readb(NS16550_t port, int offset) offset *= 1 << plat->reg_shift; addr = map_physmem(plat->base, 0, MAP_NOCACHE) + offset; - return serial_in_shift(addr, plat->reg_shift); + return serial_in_shift(addr + plat->reg_offset, plat->reg_shift); } /* We can clean these up once everything is moved to driver model */ @@ -401,6 +401,8 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev) return -EINVAL; plat->base = addr; + plat->reg_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "reg-offset", 0); plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg-shift", 0); plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c new file mode 100644 index 0000000000..cfbfab7e41 --- /dev/null +++ b/drivers/serial/serial_stm32x7.c @@ -0,0 +1,83 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, <vikas.manocha@st.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <serial.h> +#include <dm/platform_data/serial_stm32x7.h> +#include "serial_stm32x7.h" + +DECLARE_GLOBAL_DATA_PTR; + +static int stm32_serial_setbrg(struct udevice *dev, int baudrate) +{ + struct stm32x7_serial_platdata *plat = dev->platdata; + struct stm32_usart *const usart = plat->base; + writel(plat->clock/baudrate, &usart->brr); + + return 0; +} + +static int stm32_serial_getc(struct udevice *dev) +{ + struct stm32x7_serial_platdata *plat = dev->platdata; + struct stm32_usart *const usart = plat->base; + + if ((readl(&usart->sr) & USART_SR_FLAG_RXNE) == 0) + return -EAGAIN; + + return readl(&usart->rd_dr); +} + +static int stm32_serial_putc(struct udevice *dev, const char c) +{ + struct stm32x7_serial_platdata *plat = dev->platdata; + struct stm32_usart *const usart = plat->base; + + if ((readl(&usart->sr) & USART_SR_FLAG_TXE) == 0) + return -EAGAIN; + + writel(c, &usart->tx_dr); + + return 0; +} + +static int stm32_serial_pending(struct udevice *dev, bool input) +{ + struct stm32x7_serial_platdata *plat = dev->platdata; + struct stm32_usart *const usart = plat->base; + + if (input) + return readl(&usart->sr) & USART_SR_FLAG_RXNE ? 1 : 0; + else + return readl(&usart->sr) & USART_SR_FLAG_TXE ? 0 : 1; +} + +static int stm32_serial_probe(struct udevice *dev) +{ + struct stm32x7_serial_platdata *plat = dev->platdata; + struct stm32_usart *const usart = plat->base; + setbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE); + + return 0; +} + +static const struct dm_serial_ops stm32_serial_ops = { + .putc = stm32_serial_putc, + .pending = stm32_serial_pending, + .getc = stm32_serial_getc, + .setbrg = stm32_serial_setbrg, +}; + +U_BOOT_DRIVER(serial_stm32) = { + .name = "serial_stm32x7", + .id = UCLASS_SERIAL, + .ops = &stm32_serial_ops, + .probe = stm32_serial_probe, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32x7.h new file mode 100644 index 0000000000..6190d67406 --- /dev/null +++ b/drivers/serial/serial_stm32x7.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, <vikas.manocha@st.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SERIAL_STM32_X7_ +#define _SERIAL_STM32_X7_ + +struct stm32_usart { + u32 cr1; + u32 cr2; + u32 cr3; + u32 brr; + u32 gtpr; + u32 rtor; + u32 rqr; + u32 sr; + u32 icr; + u32 rd_dr; + u32 tx_dr; +}; + + +#define USART_CR1_RE (1 << 2) +#define USART_CR1_TE (1 << 3) +#define USART_CR1_UE (1 << 0) + +#define USART_SR_FLAG_RXNE (1 << 5) +#define USART_SR_FLAG_TXE (1 << 7) + +#define USART_BRR_F_MASK 0xFF +#define USART_BRR_M_SHIFT 4 +#define USART_BRR_M_MASK 0xFFF0 + +#endif diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index e79d997cba..66d54e32ab 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR; -#define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ +#define ZYNQ_UART_SR_TXEMPTY (1 << 3) /* TX FIFO empty */ #define ZYNQ_UART_SR_TXACTIVE (1 << 11) /* TX active */ #define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ @@ -97,7 +97,7 @@ static void _uart_zynq_serial_init(struct uart_zynq *regs) static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c) { - if (readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) + if (!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXEMPTY)) return -EAGAIN; writel(c, ®s->tx_rx_fifo); diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index 85f9e85fd4..95cdfa36ef 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -336,7 +336,6 @@ int omap3_spi_txrx(struct spi_slave *slave, unsigned int len, struct omap3_spi_slave *ds = to_omap3_spi(slave); ulong start; int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf); - int irqstatus = readl(&ds->regs->irqstatus); int i=0; /*Enable SPI channel*/ @@ -351,7 +350,6 @@ int omap3_spi_txrx(struct spi_slave *slave, unsigned int len, /*Shift in and out 1 byte at time*/ for (i=0; i < len; i++){ /* Write: wait for TX empty (TXS == 1)*/ - irqstatus |= (1<< (4*(ds->slave.bus))); start = get_timer(0); while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) & OMAP3_MCSPI_CHSTAT_TXS)) { diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 677c020b11..5561f36762 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -158,6 +158,7 @@ static int spi_child_pre_probe(struct udevice *dev) slave->max_hz = plat->max_hz; slave->mode = plat->mode; slave->mode_rx = plat->mode_rx; + slave->wordlen = SPI_DEFAULT_WORDLEN; return 0; } diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index b5c974ce38..409a5c41ab 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -277,7 +277,7 @@ static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen, } /* TODO: control from sf layer to here through dm-spi */ -#ifdef CONFIG_TI_EDMA3 +#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA) void spi_flash_copy_mmap(void *data, void *offset, size_t len) { unsigned int addr = (unsigned int) (data); diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c index d494ca10bb..cf3dcc4327 100644 --- a/drivers/usb/host/ehci-sunxi.c +++ b/drivers/usb/host/ehci-sunxi.c @@ -35,13 +35,12 @@ static int ehci_usb_probe(struct udevice *dev) * This should go away once we've moved to the driver model for * clocks resp. phys. */ - if (hccr == (void *)SUNXI_USB1_BASE) { - priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0; - priv->phy_index = 1; - } else { - priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI1; - priv->phy_index = 2; - } + priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0; +#ifdef CONFIG_MACH_SUN8I_H3 + priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_OHCI0; +#endif + priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / 0x1000 + 1; + priv->ahb_gate_mask <<= priv->phy_index - 1; setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask); #ifdef CONFIG_SUNXI_GEN_SUN6I @@ -83,6 +82,7 @@ static const struct udevice_id ehci_usb_ids[] = { { .compatible = "allwinner,sun6i-a31-ehci", }, { .compatible = "allwinner,sun7i-a20-ehci", }, { .compatible = "allwinner,sun8i-a23-ehci", }, + { .compatible = "allwinner,sun8i-h3-ehci", }, { .compatible = "allwinner,sun9i-a80-ehci", }, { } }; diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c index 60792726ee..1b1f651697 100644 --- a/drivers/usb/host/ohci-sunxi.c +++ b/drivers/usb/host/ohci-sunxi.c @@ -37,15 +37,14 @@ static int ohci_usb_probe(struct udevice *dev) * This should go away once we've moved to the driver model for * clocks resp. phys. */ - if (regs == (void *)(SUNXI_USB1_BASE + 0x400)) { - priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0; - priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK; - priv->phy_index = 1; - } else { - priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI1; - priv->usb_gate_mask = CCM_USB_CTRL_OHCI1_CLK; - priv->phy_index = 2; - } + priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0; +#ifdef CONFIG_MACH_SUN8I_H3 + priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_EHCI0; +#endif + priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK; + priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / 0x1000 + 1; + priv->ahb_gate_mask <<= priv->phy_index - 1; + priv->usb_gate_mask <<= priv->phy_index - 1; setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask); setbits_le32(&ccm->usb_clk_cfg, priv->usb_gate_mask); @@ -86,6 +85,7 @@ static const struct udevice_id ohci_usb_ids[] = { { .compatible = "allwinner,sun6i-a31-ohci", }, { .compatible = "allwinner,sun7i-a20-ohci", }, { .compatible = "allwinner,sun8i-a23-ohci", }, + { .compatible = "allwinner,sun8i-h3-ohci", }, { .compatible = "allwinner,sun9i-a80-ohci", }, { } }; diff --git a/drivers/video/Makefile b/drivers/video/Makefile index d19a1d9042..9b635fc403 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o obj-$(CONFIG_VIDEO_MVEBU) += mvebu_lcd.o obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o +obj-$(CONFIG_VIDEO_S3C) += s3c-fb.o videomodes.o obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o obj-$(CONFIG_VIDEO_SED13806) += sed13806.o obj-$(CONFIG_VIDEO_SM501) += sm501.o diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index f15c964546..ef4984becb 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -117,7 +117,7 @@ #define VIDEO_HW_BITBLT #endif -#ifdef CONFIG_VIDEO_MXS +#if defined(CONFIG_VIDEO_MXS) || defined(CONFIG_VIDEO_S3C) #define VIDEO_FB_16BPP_WORD_SWAP #endif diff --git a/drivers/video/console_truetype.c b/drivers/video/console_truetype.c index c249f047f5..e16f95a02c 100644 --- a/drivers/video/console_truetype.c +++ b/drivers/video/console_truetype.c @@ -289,6 +289,7 @@ static int console_truetype_putc_xy(struct udevice *dev, uint x, uint y, } #endif default: + free(data); return -ENOSYS; } diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c new file mode 100644 index 0000000000..521eb75a82 --- /dev/null +++ b/drivers/video/s3c-fb.c @@ -0,0 +1,172 @@ +/* + * S3C24x0 LCD driver + * + * NOTE: Only 16/24 bpp operation with TFT LCD is supported. + * + * Copyright (C) 2014 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <malloc.h> +#include <video_fb.h> + +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/s3c24x0_cpu.h> + +#include "videomodes.h" + +static GraphicDevice panel; + +/* S3C requires the FB to be 4MiB aligned. */ +#define S3CFB_ALIGN (4 << 20) + +#define S3CFB_LCDCON1_CLKVAL(x) ((x) << 8) +#define S3CFB_LCDCON1_PNRMODE_TFT (0x3 << 5) +#define S3CFB_LCDCON1_BPPMODE_TFT_16BPP (0xc << 1) +#define S3CFB_LCDCON1_BPPMODE_TFT_24BPP (0xd << 1) + +#define S3CFB_LCDCON2_VBPD(x) ((x) << 24) +#define S3CFB_LCDCON2_LINEVAL(x) ((x) << 14) +#define S3CFB_LCDCON2_VFPD(x) ((x) << 6) +#define S3CFB_LCDCON2_VSPW(x) ((x) << 0) + +#define S3CFB_LCDCON3_HBPD(x) ((x) << 19) +#define S3CFB_LCDCON3_HOZVAL(x) ((x) << 8) +#define S3CFB_LCDCON3_HFPD(x) ((x) << 0) + +#define S3CFB_LCDCON4_HSPW(x) ((x) << 0) + +#define S3CFB_LCDCON5_BPP24BL (1 << 12) +#define S3CFB_LCDCON5_FRM565 (1 << 11) +#define S3CFB_LCDCON5_HWSWP (1 << 0) + +#define PS2KHZ(ps) (1000000000UL / (ps)) + +/* + * Example: + * setenv videomode video=ctfb:x:800,y:480,depth:16,mode:0,\ + * pclk:30066,le:41,ri:89,up:45,lo:12, + * hs:1,vs:1,sync:100663296,vmode:0 + */ +static void s3c_lcd_init(GraphicDevice *panel, + struct ctfb_res_modes *mode, int bpp) +{ + uint32_t clk_divider; + struct s3c24x0_lcd *regs = s3c24x0_get_base_lcd(); + + /* Stop the controller. */ + clrbits_le32(®s->lcdcon1, 1); + + /* Calculate clock divider. */ + clk_divider = (get_HCLK() / PS2KHZ(mode->pixclock)) / 1000; + clk_divider = DIV_ROUND_UP(clk_divider, 2); + if (clk_divider) + clk_divider -= 1; + + /* Program LCD configuration. */ + switch (bpp) { + case 16: + writel(S3CFB_LCDCON1_BPPMODE_TFT_16BPP | + S3CFB_LCDCON1_PNRMODE_TFT | + S3CFB_LCDCON1_CLKVAL(clk_divider), + ®s->lcdcon1); + writel(S3CFB_LCDCON5_HWSWP | S3CFB_LCDCON5_FRM565, + ®s->lcdcon5); + break; + case 24: + writel(S3CFB_LCDCON1_BPPMODE_TFT_24BPP | + S3CFB_LCDCON1_PNRMODE_TFT | + S3CFB_LCDCON1_CLKVAL(clk_divider), + ®s->lcdcon1); + writel(S3CFB_LCDCON5_BPP24BL, ®s->lcdcon5); + break; + } + + writel(S3CFB_LCDCON2_LINEVAL(mode->yres - 1) | + S3CFB_LCDCON2_VBPD(mode->upper_margin - 1) | + S3CFB_LCDCON2_VFPD(mode->lower_margin - 1) | + S3CFB_LCDCON2_VSPW(mode->vsync_len - 1), + ®s->lcdcon2); + + writel(S3CFB_LCDCON3_HBPD(mode->right_margin - 1) | + S3CFB_LCDCON3_HFPD(mode->left_margin - 1) | + S3CFB_LCDCON3_HOZVAL(mode->xres - 1), + ®s->lcdcon3); + + writel(S3CFB_LCDCON4_HSPW(mode->hsync_len - 1), + ®s->lcdcon4); + + /* Write FB address. */ + writel(panel->frameAdrs >> 1, ®s->lcdsaddr1); + writel((panel->frameAdrs + + (mode->xres * mode->yres * panel->gdfBytesPP)) >> 1, + ®s->lcdsaddr2); + writel(mode->xres * bpp / 16, ®s->lcdsaddr3); + + /* Start the controller. */ + setbits_le32(®s->lcdcon1, 1); +} + +void *video_hw_init(void) +{ + int bpp = -1; + char *penv; + void *fb; + struct ctfb_res_modes mode; + + puts("Video: "); + + /* Suck display configuration from "videomode" variable */ + penv = getenv("videomode"); + if (!penv) { + puts("S3CFB: 'videomode' variable not set!\n"); + return NULL; + } + + bpp = video_get_params(&mode, penv); + + /* fill in Graphic device struct */ + sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp); + + panel.winSizeX = mode.xres; + panel.winSizeY = mode.yres; + panel.plnSizeX = mode.xres; + panel.plnSizeY = mode.yres; + + switch (bpp) { + case 24: + panel.gdfBytesPP = 4; + panel.gdfIndex = GDF_32BIT_X888RGB; + break; + case 16: + panel.gdfBytesPP = 2; + panel.gdfIndex = GDF_16BIT_565RGB; + break; + default: + printf("S3CFB: Invalid BPP specified! (bpp = %i)\n", bpp); + return NULL; + } + + panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP; + + /* Allocate framebuffer */ + fb = memalign(S3CFB_ALIGN, roundup(panel.memSize, S3CFB_ALIGN)); + if (!fb) { + printf("S3CFB: Error allocating framebuffer!\n"); + return NULL; + } + + /* Wipe framebuffer */ + memset(fb, 0, panel.memSize); + + panel.frameAdrs = (u32)fb; + + printf("%s\n", panel.modeIdent); + + /* Start framebuffer */ + s3c_lcd_init(&panel, &mode, bpp); + + return (void *)&panel; +} diff --git a/drivers/video/stb_truetype.h b/drivers/video/stb_truetype.h index 91d8e6f905..26e483cf56 100644 --- a/drivers/video/stb_truetype.h +++ b/drivers/video/stb_truetype.h @@ -2426,7 +2426,10 @@ STBTT_DEF unsigned char *stbtt_GetGlyphBitmapSubpixel(const stbtt_fontinfo *info if (scale_x == 0) scale_x = scale_y; if (scale_y == 0) { - if (scale_x == 0) return NULL; + if (scale_x == 0) { + STBTT_free(vertices, info->userdata); + return NULL; + } scale_y = scale_x; } |