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-rw-r--r--drivers/clk/clk_versal.c8
-rw-r--r--drivers/firmware/firmware-zynqmp.c19
-rw-r--r--drivers/firmware/psci.c4
-rw-r--r--drivers/fpga/versalpl.c2
-rw-r--r--drivers/fpga/zynqmppl.c2
-rw-r--r--drivers/fpga/zynqpl.c39
-rw-r--r--drivers/gpio/mxc_gpio.c5
-rw-r--r--drivers/mmc/zynq_sdhci.c2
-rw-r--r--drivers/net/fec_mxc.c7
-rw-r--r--drivers/net/fec_mxc.h1
-rw-r--r--drivers/net/phy/atheros.c7
-rw-r--r--drivers/net/xilinx_axi_emac.c3
-rw-r--r--drivers/net/zynq_gem.c4
-rw-r--r--drivers/spi/xilinx_spi.c6
-rw-r--r--drivers/spi/zynq_qspi.c6
-rw-r--r--drivers/spi/zynq_spi.c6
16 files changed, 76 insertions, 45 deletions
diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
index 2fb3171d71..6f82b60f04 100644
--- a/drivers/clk/clk_versal.c
+++ b/drivers/clk/clk_versal.c
@@ -117,7 +117,6 @@ struct versal_clk_priv {
struct versal_clock *clk;
};
-static ulong alt_ref_clk;
static ulong pl_alt_ref_clk;
static ulong ref_clk;
@@ -548,8 +547,7 @@ int soc_clk_dump(void)
printf("\n ****** VERSAL CLOCKS *****\n");
- printf("alt_ref_clk:%ld pl_alt_ref_clk:%ld ref_clk:%ld\n",
- alt_ref_clk, pl_alt_ref_clk, ref_clk);
+ printf("pl_alt_ref_clk:%ld ref_clk:%ld\n", pl_alt_ref_clk, ref_clk);
for (i = 0; i < clock_max_idx; i++) {
debug("%s\n", clock[i].clk_name);
ret = versal_get_clock_type(i, &type);
@@ -667,10 +665,6 @@ static int versal_clk_probe(struct udevice *dev)
debug("%s\n", __func__);
- ret = versal_clock_get_freq_by_name("alt_ref_clk", dev, &alt_ref_clk);
- if (ret < 0)
- return -EINVAL;
-
ret = versal_clock_get_freq_by_name("pl_alt_ref_clk",
dev, &pl_alt_ref_clk);
if (ret < 0)
diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c
index 2bdf7771f6..66edc16930 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -18,6 +18,8 @@
#define PMUFW_PAYLOAD_ARG_CNT 8
+#define XST_PM_NO_ACCESS 2002L
+
struct zynqmp_power {
struct mbox_chan tx_chan;
struct mbox_chan rx_chan;
@@ -99,16 +101,25 @@ void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
PM_SET_CONFIGURATION,
(u32)((u64)cfg_obj)
};
- u32 response;
+ u32 response = 0;
int err;
printf("Loading new PMUFW cfg obj (%ld bytes)\n", size);
err = send_req(request, ARRAY_SIZE(request), &response, 1);
+ if (err == XST_PM_NO_ACCESS) {
+ printf("PMUFW no permission to change config object\n");
+ return;
+ }
+
if (err)
- panic("Cannot load PMUFW configuration object (%d)\n", err);
- if (response != 0)
- panic("PMUFW returned 0x%08x status!\n", response);
+ printf("Cannot load PMUFW configuration object (%d)\n", err);
+
+ if (response)
+ printf("PMUFW returned 0x%08x status!\n", response);
+
+ if ((err || response) && IS_ENABLED(CONFIG_SPL_BUILD))
+ panic("PMUFW config object loading failed in EL3\n");
}
static int zynqmp_power_probe(struct udevice *dev)
diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c
index e0d66d74f5..23cf807591 100644
--- a/drivers/firmware/psci.c
+++ b/drivers/firmware/psci.c
@@ -67,11 +67,9 @@ static int psci_bind(struct udevice *dev)
static int psci_probe(struct udevice *dev)
{
- DECLARE_GLOBAL_DATA_PTR;
const char *method;
- method = fdt_stringlist_get(gd->fdt_blob, dev_of_offset(dev), "method",
- 0, NULL);
+ method = ofnode_read_string(dev_ofnode(dev), "method");
if (!method) {
pr_warn("missing \"method\" property\n");
return -ENXIO;
diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c
index b96519e1a4..8e2ef4f0da 100644
--- a/drivers/fpga/versalpl.c
+++ b/drivers/fpga/versalpl.c
@@ -45,7 +45,7 @@ static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize,
ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
buf_hi, 0, ret_payload);
if (ret)
- puts("PL FPGA LOAD fail\n");
+ printf("PL FPGA LOAD failed with err: 0x%08x\n", ret);
return ret;
}
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index 2ac4e38952..5b103cfeaf 100644
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@@ -239,7 +239,7 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
buf_hi, (u32)bsize, 0, ret_payload);
if (ret)
- puts("PL FPGA LOAD fail\n");
+ printf("PL FPGA LOAD failed with err: 0x%08x\n", ret);
return ret;
}
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index dcfe513eeb..a11e485525 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -22,6 +22,7 @@
#define DEVCFG_CTRL_PCFG_PROG_B 0x40000000
#define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK 0x00001000
#define DEVCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000
+#define DEVCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00
#define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040
#define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840
#define DEVCFG_ISR_RX_FIFO_OV 0x00040000
@@ -204,7 +205,7 @@ static int zynq_dma_xfer_init(bitstream_type bstype)
/* Clear loopback bit */
clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
- if (bstype != BIT_PARTIAL) {
+ if (bstype != BIT_PARTIAL && bstype != BIT_NONE) {
zynq_slcr_devcfg_disable();
/* Setting PCFG_PROG_B signal to high */
@@ -511,15 +512,25 @@ struct xilinx_fpga_op zynq_op = {
* Load the encrypted image from src addr and decrypt the image and
* place it back the decrypted image into dstaddr.
*/
-int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen)
+int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
+ u8 bstype)
{
+ u32 isr_status, ts;
+
if (srcaddr < SZ_1M || dstaddr < SZ_1M) {
printf("%s: src and dst addr should be > 1M\n",
__func__);
return FPGA_FAIL;
}
- if (zynq_dma_xfer_init(BIT_NONE)) {
+ /* Check AES engine is enabled */
+ if (!(readl(&devcfg_base->ctrl) &
+ DEVCFG_CTRL_PCFG_AES_EN_MASK)) {
+ printf("%s: AES engine is not enabled\n", __func__);
+ return FPGA_FAIL;
+ }
+
+ if (zynq_dma_xfer_init(bstype)) {
printf("%s: zynq_dma_xfer_init FAIL\n", __func__);
return FPGA_FAIL;
}
@@ -537,14 +548,28 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen)
* Flush destination address range only if image is not
* bitstream.
*/
- flush_dcache_range((u32)dstaddr, (u32)dstaddr +
- roundup(dstlen << 2, ARCH_DMA_MINALIGN));
+ if (bstype == BIT_NONE && dstaddr != 0xFFFFFFFF)
+ flush_dcache_range((u32)dstaddr, (u32)dstaddr +
+ roundup(dstlen << 2, ARCH_DMA_MINALIGN));
if (zynq_dma_transfer(srcaddr | 1, srclen, dstaddr | 1, dstlen))
return FPGA_FAIL;
- writel((readl(&devcfg_base->ctrl) & ~DEVCFG_CTRL_PCAP_RATE_EN_MASK),
- &devcfg_base->ctrl);
+ if (bstype == BIT_FULL) {
+ isr_status = readl(&devcfg_base->int_sts);
+ /* Check FPGA configuration completion */
+ ts = get_timer(0);
+ while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
+ if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
+ printf("%s: Timeout wait for FPGA to config\n",
+ __func__);
+ return FPGA_FAIL;
+ }
+ isr_status = readl(&devcfg_base->int_sts);
+ }
+ printf("%s: FPGA config done\n", __func__);
+ zynq_slcr_devcfg_enable();
+ }
return FPGA_SUCCESS;
}
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index c924e52f07..316dcc757b 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -281,7 +281,10 @@ static int mxc_gpio_probe(struct udevice *dev)
char name[18], *str;
banknum = plat->bank_index;
- sprintf(name, "GPIO%d_", banknum + 1);
+ if (IS_ENABLED(CONFIG_ARCH_IMX8))
+ sprintf(name, "GPIO%d_", banknum);
+ else
+ sprintf(name, "GPIO%d_", banknum + 1);
str = strdup(name);
if (!str)
return -ENOMEM;
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index de404aa956..43b9f21522 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -19,8 +19,6 @@
#include <sdhci.h>
#include <zynqmp_tap_delay.h>
-DECLARE_GLOBAL_DATA_PTR;
-
struct arasan_sdhci_plat {
struct mmc_config cfg;
struct mmc mmc;
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 9ae2db033e..992180df86 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1294,7 +1294,7 @@ static const struct eth_ops fecmxc_ops = {
.read_rom_hwaddr = fecmxc_read_rom_hwaddr,
};
-static int device_get_phy_addr(struct udevice *dev)
+static int device_get_phy_addr(struct fec_priv *priv, struct udevice *dev)
{
struct ofnode_phandle_args phandle_args;
int reg;
@@ -1305,6 +1305,8 @@ static int device_get_phy_addr(struct udevice *dev)
return -ENODEV;
}
+ priv->phy_of_node = phandle_args.node;
+
reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
return reg;
@@ -1315,7 +1317,7 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
struct phy_device *phydev;
int addr;
- addr = device_get_phy_addr(dev);
+ addr = device_get_phy_addr(priv, dev);
#ifdef CONFIG_FEC_MXC_PHYADDR
addr = CONFIG_FEC_MXC_PHYADDR;
#endif
@@ -1325,6 +1327,7 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
return -ENODEV;
priv->phydev = phydev;
+ priv->phydev->node = priv->phy_of_node;
phy_config(phydev);
return 0;
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 0e8f08a51a..659d62646f 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -250,6 +250,7 @@ struct fec_priv {
struct mii_dev *bus;
#ifdef CONFIG_PHYLIB
struct phy_device *phydev;
+ ofnode phy_of_node;
#else
int phy_id;
int (*mii_postcall)(int);
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 13f7275d17..f922fecd6b 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -275,11 +275,10 @@ static int ar803x_of_init(struct phy_device *phydev)
* Fixup for the AR8035 which only has two bits. The two
* remaining bits map to the same frequencies.
*/
- if (phydev->drv->uid == AR8035_PHY_ID) {
- u16 clear = AR803x_CLK_25M_MASK & AR8035_CLK_25M_MASK;
- priv->clk_25m_mask &= ~clear;
- priv->clk_25m_reg &= ~clear;
+ if (phydev->drv->uid == AR8035_PHY_ID) {
+ priv->clk_25m_reg &= AR8035_CLK_25M_MASK;
+ priv->clk_25m_mask &= AR8035_CLK_25M_MASK;
}
}
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index d0683db80d..2cd5596768 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -244,7 +244,8 @@ static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
static int axiemac_phy_init(struct udevice *dev)
{
u16 phyreg;
- u32 i, ret;
+ int i;
+ u32 ret;
struct axidma_priv *priv = dev_get_priv(dev);
struct axi_regs *regs = priv->iobase;
struct phy_device *phydev;
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 412daf7d58..da4b6fba9f 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -451,8 +451,12 @@ static int zynq_gem_init(struct udevice *dev)
nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
ZYNQ_GEM_NWCFG_PCS_SEL;
#ifdef CONFIG_ARM64
+ if (priv->phydev->phy_id != PHY_FIXED_ID)
writel(readl(&regs->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
&regs->pcscntrl);
+ else
+ writel(readl(&regs->pcscntrl) & ~ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
+ &regs->pcscntrl);
#endif
}
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 05768eef72..348630faf3 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -76,9 +76,7 @@
SPICR_SPE)
#define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)
-#ifndef CONFIG_XILINX_SPI_IDLE_VAL
-#define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0)
-#endif
+#define XILINX_SPI_IDLE_VAL GENMASK(7, 0)
#define XILINX_SPISR_TIMEOUT 10000 /* in milliseconds */
@@ -176,7 +174,7 @@ static u32 xilinx_spi_fill_txfifo(struct udevice *bus, const u8 *txp,
while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) &&
i < priv->fifo_depth) {
- d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
+ d = txp ? *txp++ : XILINX_SPI_IDLE_VAL;
debug("spi_xfer: tx:%x ", d);
/* write out and wait for processing (receive data) */
writel(d & SPIDTR_8BIT_MASK, &regs->spidtr);
diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index db473da6ea..3f39ef05f2 100644
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -47,9 +47,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define ZYNQ_QSPI_CR_SS_SHIFT 10 /* Slave select shift */
#define ZYNQ_QSPI_FIFO_DEPTH 63
-#ifndef CONFIG_SYS_ZYNQ_QSPI_WAIT
-#define CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
-#endif
+#define ZYNQ_QSPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */
/* zynq qspi register set */
struct zynq_qspi_regs {
@@ -350,7 +348,7 @@ static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv)
do {
status = readl(&regs->isr);
} while ((status == 0) &&
- (get_timer(timeout) < CONFIG_SYS_ZYNQ_QSPI_WAIT));
+ (get_timer(timeout) < ZYNQ_QSPI_WAIT));
if (status == 0) {
printf("zynq_qspi_irq_poll: Timeout!\n");
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index 3e66b34ebb..78ffd3e2fe 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -36,9 +36,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */
#define ZYNQ_SPI_FIFO_DEPTH 128
-#ifndef CONFIG_SYS_ZYNQ_SPI_WAIT
-#define CONFIG_SYS_ZYNQ_SPI_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
-#endif
+#define ZYNQ_SPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */
/* zynq spi register set */
struct zynq_spi_regs {
@@ -251,7 +249,7 @@ static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
ts = get_timer(0);
status = readl(&regs->isr);
while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
- if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) {
+ if (get_timer(ts) > ZYNQ_SPI_WAIT) {
printf("spi_xfer: Timeout! TX FIFO not full\n");
return -1;
}
generated by cgit (git 2.34.1) at 2025-01-05 19:50:56 +0000