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-rw-r--r--drivers/Makefile1
-rw-r--r--drivers/block/dwc_ahsata.c2
-rw-r--r--drivers/crypto/rsa_mod_exp/mod_exp_sw.c1
-rw-r--r--drivers/gpio/at91_gpio.c11
-rw-r--r--drivers/gpio/intel_broadwell_gpio.c7
-rw-r--r--drivers/gpio/intel_ich6_gpio.c5
-rw-r--r--drivers/i2c/i2c_core.c5
-rw-r--r--drivers/i2c/mxc_i2c.c27
-rw-r--r--drivers/misc/mxc_ocotp.c4
-rw-r--r--drivers/mtd/nand/atmel_nand.c5
-rw-r--r--drivers/mtd/nand/mxs_nand.c2
-rw-r--r--drivers/net/fec_mxc.c2
-rw-r--r--drivers/net/macb.c320
-rw-r--r--drivers/serial/atmel_usart.c19
-rw-r--r--drivers/spi/Kconfig8
-rw-r--r--drivers/spi/Makefile1
-rw-r--r--drivers/spi/pic32_spi.c448
-rw-r--r--drivers/usb/musb-new/sunxi.c7
-rw-r--r--drivers/video/atmel_lcdfb.c197
19 files changed, 938 insertions, 134 deletions
diff --git a/drivers/Makefile b/drivers/Makefile
index f6295d285e..db5317c9c7 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_$(SPL_)RAM) += ram/
ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
obj-$(CONFIG_SPL_I2C_SUPPORT) += i2c/
obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/
obj-$(CONFIG_SPL_MMC_SUPPORT) += mmc/
diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c
index 6ec52a9114..6056fe5dfd 100644
--- a/drivers/block/dwc_ahsata.c
+++ b/drivers/block/dwc_ahsata.c
@@ -563,7 +563,7 @@ int init_sata(int dev)
struct ahci_probe_ent *probe_ent = NULL;
#if defined(CONFIG_MX6)
- if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+ if (!is_mx6dq() && !is_mx6dqp())
return 1;
#endif
if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
diff --git a/drivers/crypto/rsa_mod_exp/mod_exp_sw.c b/drivers/crypto/rsa_mod_exp/mod_exp_sw.c
index dc6c064b4e..3817fb3e47 100644
--- a/drivers/crypto/rsa_mod_exp/mod_exp_sw.c
+++ b/drivers/crypto/rsa_mod_exp/mod_exp_sw.c
@@ -32,6 +32,7 @@ U_BOOT_DRIVER(mod_exp_sw) = {
.name = "mod_exp_sw",
.id = UCLASS_MOD_EXP,
.ops = &mod_exp_ops_sw,
+ .flags = DM_FLAG_PRE_RELOC,
};
U_BOOT_DEVICE(mod_exp_sw) = {
diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c
index 75a32ee815..8e52e3dad0 100644
--- a/drivers/gpio/at91_gpio.c
+++ b/drivers/gpio/at91_gpio.c
@@ -59,6 +59,11 @@ int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
{
struct at91_port *at91_port = at91_pio_get_port(port);
+#if defined(CPU_HAS_PIO3)
+ if (use_pullup)
+ at91_set_pio_pulldown(port, pin, 0);
+#endif
+
if (at91_port && (pin < GPIO_PER_BANK))
at91_set_port_pullup(at91_port, pin, use_pullup);
@@ -305,10 +310,10 @@ int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on)
if (at91_port && (pin < GPIO_PER_BANK)) {
mask = 1 << pin;
- writel(mask, &at91_port->pudr);
- if (is_on)
+ if (is_on) {
+ at91_set_pio_pullup(port, pin, 0);
writel(mask, &at91_port->ppder);
- else
+ } else
writel(mask, &at91_port->ppddr);
}
diff --git a/drivers/gpio/intel_broadwell_gpio.c b/drivers/gpio/intel_broadwell_gpio.c
index 81ce446e1a..8b50900f9f 100644
--- a/drivers/gpio/intel_broadwell_gpio.c
+++ b/drivers/gpio/intel_broadwell_gpio.c
@@ -9,7 +9,6 @@
#include <fdtdec.h>
#include <pch.h>
#include <pci.h>
-#include <syscon.h>
#include <asm/cpu.h>
#include <asm/gpio.h>
#include <asm/io.h>
@@ -119,12 +118,6 @@ static int broadwell_gpio_probe(struct udevice *dev)
struct broadwell_bank_platdata *plat = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct broadwell_bank_priv *priv = dev_get_priv(dev);
- struct udevice *pinctrl;
- int ret;
-
- /* Set up pin control if available */
- ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl);
- debug("%s, pinctrl=%p, ret=%d\n", __func__, pinctrl, ret);
uc_priv->gpio_count = GPIO_PER_BANK;
uc_priv->bank_name = plat->bank_name;
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index b7e379ab97..fd6181fa5a 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -32,7 +32,6 @@
#include <fdtdec.h>
#include <pch.h>
#include <pci.h>
-#include <syscon.h>
#include <asm/cpu.h>
#include <asm/gpio.h>
#include <asm/io.h>
@@ -113,10 +112,6 @@ static int ich6_gpio_probe(struct udevice *dev)
struct ich6_bank_platdata *plat = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct ich6_bank_priv *bank = dev_get_priv(dev);
- struct udevice *pinctrl;
-
- /* Set up pin control if available */
- syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl);
uc_priv->gpio_count = GPIO_PER_BANK;
uc_priv->bank_name = plat->bank_name;
diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c
index 41cc3b8fa4..16b1aba32a 100644
--- a/drivers/i2c/i2c_core.c
+++ b/drivers/i2c/i2c_core.c
@@ -233,6 +233,11 @@ __weak void i2c_init_board(void)
{
}
+/* implement possible for i2c specific early i2c init */
+__weak void i2c_early_init_f(void)
+{
+}
+
/*
* i2c_init_all():
*
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 445fa21082..f3402089a8 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -32,6 +32,14 @@ DECLARE_GLOBAL_DATA_PTR;
#define IMX_I2C_REGSHIFT 2
#define VF610_I2C_REGSHIFT 0
+
+#define I2C_EARLY_INIT_INDEX 0
+#ifdef CONFIG_SYS_I2C_IFDR_DIV
+#define I2C_IFDR_DIV_CONSERVATIVE CONFIG_SYS_I2C_IFDR_DIV
+#else
+#define I2C_IFDR_DIV_CONSERVATIVE 0x7e
+#endif
+
/* Register index */
#define IADR 0
#define IFDR 1
@@ -660,6 +668,25 @@ void bus_i2c_init(int index, int speed, int unused,
}
/*
+ * Early init I2C for prepare read the clk through I2C.
+ */
+void i2c_early_init_f(void)
+{
+ ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
+ bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
+ & I2C_QUIRK_FLAG ? true : false;
+ int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
+
+ /* Set I2C divider value */
+ writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
+ /* Reset module */
+ writeb(I2CR_IDIS, base + (I2CR << reg_shift));
+ writeb(0, base + (I2SR << reg_shift));
+ /* Enable I2C */
+ writeb(I2CR_IEN, base + (I2CR << reg_shift));
+}
+
+/*
* Init I2C Bus
*/
static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
index 65ff8158e5..38344e8090 100644
--- a/drivers/misc/mxc_ocotp.c
+++ b/drivers/misc/mxc_ocotp.c
@@ -95,9 +95,9 @@ u32 fuse_bank_physical(int index)
{
u32 phy_index;
- if (is_cpu_type(MXC_CPU_MX6SL)) {
+ if (is_mx6sl()) {
phy_index = index;
- } else if (is_cpu_type(MXC_CPU_MX6UL)) {
+ } else if (is_mx6ul()) {
if (index >= 6)
phy_index = fuse_bank_physical(5) + (index - 6) + 3;
else
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 75e830724c..ad5ded3a56 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -24,9 +24,9 @@
/* Register access macros */
#define ecc_readl(add, reg) \
- readl(AT91_BASE_SYS + add + ATMEL_ECC_##reg)
+ readl(add + ATMEL_ECC_##reg)
#define ecc_writel(add, reg, value) \
- writel((value), AT91_BASE_SYS + add + ATMEL_ECC_##reg)
+ writel((value), add + ATMEL_ECC_##reg)
#include "atmel_nand_ecc.h" /* Hardware ECC registers */
@@ -1156,6 +1156,7 @@ int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
nand->ecc.hwctl = atmel_nand_hwctl;
nand->ecc.read_page = atmel_nand_read_page;
nand->ecc.bytes = 4;
+ nand->ecc.strength = 4;
if (nand->ecc.mode == NAND_ECC_HW) {
/* ECC is calculated for the whole page (1 step) */
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index 7be1f86bc2..c90a3a7bd2 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -152,7 +152,7 @@ static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
int max_ecc_strength_supported;
/* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
- if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7))
+ if (is_mx6sx() || is_mx7())
max_ecc_strength_supported = 62;
else
max_ecc_strength_supported = 40;
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 3340dd256f..360f8e44d1 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -566,7 +566,7 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
/* Do not access reserved register for i.MX6UL */
- if (!is_cpu_type(MXC_CPU_MX6UL)) {
+ if (!is_mx6ul()) {
/* clear MIB RAM */
for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
writel(0, i);
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 4bf8fa45d7..0835fdc306 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -4,6 +4,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <dm.h>
/*
* The u-boot networking stack is a little weird. It seems like the
@@ -28,7 +29,9 @@
*/
#include <net.h>
+#ifndef CONFIG_DM_ETH
#include <netdev.h>
+#endif
#include <malloc.h>
#include <miiphy.h>
@@ -84,6 +87,8 @@ struct macb_device {
unsigned int rx_tail;
unsigned int tx_head;
unsigned int tx_tail;
+ unsigned int next_rx_tail;
+ bool wrapped;
void *rx_buffer;
void *tx_buffer;
@@ -98,11 +103,15 @@ struct macb_device {
unsigned long dummy_desc_dma;
const struct device *dev;
+#ifndef CONFIG_DM_ETH
struct eth_device netdev;
+#endif
unsigned short phy_addr;
struct mii_dev *bus;
};
+#ifndef CONFIG_DM_ETH
#define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
+#endif
static int macb_is_gem(struct macb_device *macb)
{
@@ -192,8 +201,13 @@ void __weak arch_get_mdio_control(const char *name)
int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
{
+#ifdef CONFIG_DM_ETH
+ struct udevice *dev = eth_get_dev_by_name(devname);
+ struct macb_device *macb = dev_get_priv(dev);
+#else
struct eth_device *dev = eth_get_dev_by_name(devname);
struct macb_device *macb = to_macb(dev);
+#endif
if (macb->phy_addr != phy_adr)
return -1;
@@ -206,8 +220,13 @@ int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
int macb_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value)
{
+#ifdef CONFIG_DM_ETH
+ struct udevice *dev = eth_get_dev_by_name(devname);
+ struct macb_device *macb = dev_get_priv(dev);
+#else
struct eth_device *dev = eth_get_dev_by_name(devname);
struct macb_device *macb = to_macb(dev);
+#endif
if (macb->phy_addr != phy_adr)
return -1;
@@ -255,9 +274,9 @@ static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
#if defined(CONFIG_CMD_NET)
-static int macb_send(struct eth_device *netdev, void *packet, int length)
+static int _macb_send(struct macb_device *macb, const char *name, void *packet,
+ int length)
{
- struct macb_device *macb = to_macb(netdev);
unsigned long paddr, ctrl;
unsigned int tx_head = macb->tx_head;
int i;
@@ -278,7 +297,7 @@ static int macb_send(struct eth_device *netdev, void *packet, int length)
barrier();
macb_flush_ring_desc(macb, TX);
/* Do we need check paddr and length is dcache line aligned? */
- flush_dcache_range(paddr, paddr + length);
+ flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN));
macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
/*
@@ -298,12 +317,11 @@ static int macb_send(struct eth_device *netdev, void *packet, int length)
if (i <= MACB_TX_TIMEOUT) {
if (ctrl & TXBUF_UNDERRUN)
- printf("%s: TX underrun\n", netdev->name);
+ printf("%s: TX underrun\n", name);
if (ctrl & TXBUF_EXHAUSTED)
- printf("%s: TX buffers exhausted in mid frame\n",
- netdev->name);
+ printf("%s: TX buffers exhausted in mid frame\n", name);
} else {
- printf("%s: TX timeout\n", netdev->name);
+ printf("%s: TX timeout\n", name);
}
/* No one cares anyway */
@@ -335,26 +353,25 @@ static void reclaim_rx_buffers(struct macb_device *macb,
macb->rx_tail = new_tail;
}
-static int macb_recv(struct eth_device *netdev)
+static int _macb_recv(struct macb_device *macb, uchar **packetp)
{
- struct macb_device *macb = to_macb(netdev);
- unsigned int rx_tail = macb->rx_tail;
+ unsigned int next_rx_tail = macb->next_rx_tail;
void *buffer;
int length;
- int wrapped = 0;
u32 status;
+ macb->wrapped = false;
for (;;) {
macb_invalidate_ring_desc(macb, RX);
- if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED))
- return -1;
+ if (!(macb->rx_ring[next_rx_tail].addr & RXADDR_USED))
+ return -EAGAIN;
- status = macb->rx_ring[rx_tail].ctrl;
+ status = macb->rx_ring[next_rx_tail].ctrl;
if (status & RXBUF_FRAME_START) {
- if (rx_tail != macb->rx_tail)
- reclaim_rx_buffers(macb, rx_tail);
- wrapped = 0;
+ if (next_rx_tail != macb->rx_tail)
+ reclaim_rx_buffers(macb, next_rx_tail);
+ macb->wrapped = false;
}
if (status & RXBUF_FRAME_END) {
@@ -362,7 +379,7 @@ static int macb_recv(struct eth_device *netdev)
length = status & RXBUF_FRMLEN_MASK;
macb_invalidate_rx_buffer(macb);
- if (wrapped) {
+ if (macb->wrapped) {
unsigned int headlen, taillen;
headlen = 128 * (MACB_RX_RING_SIZE
@@ -372,34 +389,33 @@ static int macb_recv(struct eth_device *netdev)
buffer, headlen);
memcpy((void *)net_rx_packets[0] + headlen,
macb->rx_buffer, taillen);
- buffer = (void *)net_rx_packets[0];
+ *packetp = (void *)net_rx_packets[0];
+ } else {
+ *packetp = buffer;
}
- net_process_received_packet(buffer, length);
- if (++rx_tail >= MACB_RX_RING_SIZE)
- rx_tail = 0;
- reclaim_rx_buffers(macb, rx_tail);
+ if (++next_rx_tail >= MACB_RX_RING_SIZE)
+ next_rx_tail = 0;
+ macb->next_rx_tail = next_rx_tail;
+ return length;
} else {
- if (++rx_tail >= MACB_RX_RING_SIZE) {
- wrapped = 1;
- rx_tail = 0;
+ if (++next_rx_tail >= MACB_RX_RING_SIZE) {
+ macb->wrapped = true;
+ next_rx_tail = 0;
}
}
barrier();
}
-
- return 0;
}
-static void macb_phy_reset(struct macb_device *macb)
+static void macb_phy_reset(struct macb_device *macb, const char *name)
{
- struct eth_device *netdev = &macb->netdev;
int i;
u16 status, adv;
adv = ADVERTISE_CSMA | ADVERTISE_ALL;
macb_mdio_write(macb, MII_ADVERTISE, adv);
- printf("%s: Starting autonegotiation...\n", netdev->name);
+ printf("%s: Starting autonegotiation...\n", name);
macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
| BMCR_ANRESTART));
@@ -411,10 +427,10 @@ static void macb_phy_reset(struct macb_device *macb)
}
if (status & BMSR_ANEGCOMPLETE)
- printf("%s: Autonegotiation complete\n", netdev->name);
+ printf("%s: Autonegotiation complete\n", name);
else
printf("%s: Autonegotiation timed out (status=0x%04x)\n",
- netdev->name, status);
+ name, status);
}
#ifdef CONFIG_MACB_SEARCH_PHY
@@ -441,9 +457,8 @@ static int macb_phy_find(struct macb_device *macb)
#endif /* CONFIG_MACB_SEARCH_PHY */
-static int macb_phy_init(struct macb_device *macb)
+static int macb_phy_init(struct macb_device *macb, const char *name)
{
- struct eth_device *netdev = &macb->netdev;
#ifdef CONFIG_PHYLIB
struct phy_device *phydev;
#endif
@@ -452,7 +467,7 @@ static int macb_phy_init(struct macb_device *macb)
int media, speed, duplex;
int i;
- arch_get_mdio_control(netdev->name);
+ arch_get_mdio_control(name);
#ifdef CONFIG_MACB_SEARCH_PHY
/* Auto-detect phy_addr */
if (!macb_phy_find(macb))
@@ -462,13 +477,13 @@ static int macb_phy_init(struct macb_device *macb)
/* Check if the PHY is up to snuff... */
phy_id = macb_mdio_read(macb, MII_PHYSID1);
if (phy_id == 0xffff) {
- printf("%s: No PHY present\n", netdev->name);
+ printf("%s: No PHY present\n", name);
return 0;
}
#ifdef CONFIG_PHYLIB
/* need to consider other phy interface mode */
- phydev = phy_connect(macb->bus, macb->phy_addr, netdev,
+ phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
printf("phy_connect failed\n");
@@ -481,7 +496,7 @@ static int macb_phy_init(struct macb_device *macb)
status = macb_mdio_read(macb, MII_BMSR);
if (!(status & BMSR_LSTATUS)) {
/* Try to re-negotiate if we don't have link already. */
- macb_phy_reset(macb);
+ macb_phy_reset(macb, name);
for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
status = macb_mdio_read(macb, MII_BMSR);
@@ -493,7 +508,7 @@ static int macb_phy_init(struct macb_device *macb)
if (!(status & BMSR_LSTATUS)) {
printf("%s: link down (status: 0x%04x)\n",
- netdev->name, status);
+ name, status);
return 0;
}
@@ -505,7 +520,7 @@ static int macb_phy_init(struct macb_device *macb)
duplex = ((lpa & LPA_1000FULL) ? 1 : 0);
printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n",
- netdev->name,
+ name,
duplex ? "full" : "half",
lpa);
@@ -530,7 +545,7 @@ static int macb_phy_init(struct macb_device *macb)
? 1 : 0);
duplex = (media & ADVERTISE_FULL) ? 1 : 0;
printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
- netdev->name,
+ name,
speed ? "100" : "10",
duplex ? "full" : "half",
lpa);
@@ -570,9 +585,8 @@ static int gmac_init_multi_queues(struct macb_device *macb)
return 0;
}
-static int macb_init(struct eth_device *netdev, bd_t *bd)
+static int _macb_init(struct macb_device *macb, const char *name)
{
- struct macb_device *macb = to_macb(netdev);
unsigned long paddr;
int i;
@@ -605,6 +619,7 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
macb->rx_tail = 0;
macb->tx_head = 0;
macb->tx_tail = 0;
+ macb->next_rx_tail = 0;
macb_writel(macb, RBQP, macb->rx_ring_dma);
macb_writel(macb, TBQP, macb->tx_ring_dma);
@@ -641,7 +656,7 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
#endif /* CONFIG_RMII */
}
- if (!macb_phy_init(macb))
+ if (!macb_phy_init(macb, name))
return -1;
/* Enable TX and RX */
@@ -650,9 +665,8 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
return 0;
}
-static void macb_halt(struct eth_device *netdev)
+static void _macb_halt(struct macb_device *macb)
{
- struct macb_device *macb = to_macb(netdev);
u32 ncr, tsr;
/* Halt the controller and wait for any ongoing transmission to end. */
@@ -668,17 +682,16 @@ static void macb_halt(struct eth_device *netdev)
macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
}
-static int macb_write_hwaddr(struct eth_device *dev)
+static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr)
{
- struct macb_device *macb = to_macb(dev);
u32 hwaddr_bottom;
u16 hwaddr_top;
/* set hardware address */
- hwaddr_bottom = dev->enetaddr[0] | dev->enetaddr[1] << 8 |
- dev->enetaddr[2] << 16 | dev->enetaddr[3] << 24;
+ hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 |
+ enetaddr[2] << 16 | enetaddr[3] << 24;
macb_writel(macb, SA1B, hwaddr_bottom);
- hwaddr_top = dev->enetaddr[4] | dev->enetaddr[5] << 8;
+ hwaddr_top = enetaddr[4] | enetaddr[5] << 8;
macb_writel(macb, SA1T, hwaddr_top);
return 0;
}
@@ -739,11 +752,87 @@ static u32 macb_dbw(struct macb_device *macb)
}
}
+static void _macb_eth_initialize(struct macb_device *macb)
+{
+ int id = 0; /* This is not used by functions we call */
+ u32 ncfgr;
+
+ /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
+ macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE,
+ &macb->rx_buffer_dma);
+ macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
+ &macb->rx_ring_dma);
+ macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
+ &macb->tx_ring_dma);
+ macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
+ &macb->dummy_desc_dma);
+
+ /*
+ * Do some basic initialization so that we at least can talk
+ * to the PHY
+ */
+ if (macb_is_gem(macb)) {
+ ncfgr = gem_mdc_clk_div(id, macb);
+ ncfgr |= macb_dbw(macb);
+ } else {
+ ncfgr = macb_mdc_clk_div(id, macb);
+ }
+
+ macb_writel(macb, NCFGR, ncfgr);
+}
+
+#ifndef CONFIG_DM_ETH
+static int macb_send(struct eth_device *netdev, void *packet, int length)
+{
+ struct macb_device *macb = to_macb(netdev);
+
+ return _macb_send(macb, netdev->name, packet, length);
+}
+
+static int macb_recv(struct eth_device *netdev)
+{
+ struct macb_device *macb = to_macb(netdev);
+ uchar *packet;
+ int length;
+
+ macb->wrapped = false;
+ for (;;) {
+ macb->next_rx_tail = macb->rx_tail;
+ length = _macb_recv(macb, &packet);
+ if (length >= 0) {
+ net_process_received_packet(packet, length);
+ reclaim_rx_buffers(macb, macb->next_rx_tail);
+ } else if (length < 0) {
+ return length;
+ }
+ }
+}
+
+static int macb_init(struct eth_device *netdev, bd_t *bd)
+{
+ struct macb_device *macb = to_macb(netdev);
+
+ return _macb_init(macb, netdev->name);
+}
+
+static void macb_halt(struct eth_device *netdev)
+{
+ struct macb_device *macb = to_macb(netdev);
+
+ return _macb_halt(macb);
+}
+
+static int macb_write_hwaddr(struct eth_device *netdev)
+{
+ struct macb_device *macb = to_macb(netdev);
+
+ return _macb_write_hwaddr(macb, netdev->enetaddr);
+}
+
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
{
struct macb_device *macb;
struct eth_device *netdev;
- u32 ncfgr;
macb = malloc(sizeof(struct macb_device));
if (!macb) {
@@ -754,17 +843,6 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
netdev = &macb->netdev;
- macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE,
- &macb->rx_buffer_dma);
- macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
- &macb->rx_ring_dma);
- macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
- &macb->tx_ring_dma);
- macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
- &macb->dummy_desc_dma);
-
- /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
-
macb->regs = regs;
macb->phy_addr = phy_addr;
@@ -779,18 +857,7 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
netdev->recv = macb_recv;
netdev->write_hwaddr = macb_write_hwaddr;
- /*
- * Do some basic initialization so that we at least can talk
- * to the PHY
- */
- if (macb_is_gem(macb)) {
- ncfgr = gem_mdc_clk_div(id, macb);
- ncfgr |= macb_dbw(macb);
- } else {
- ncfgr = macb_mdc_clk_div(id, macb);
- }
-
- macb_writel(macb, NCFGR, ncfgr);
+ _macb_eth_initialize(macb);
eth_register(netdev);
@@ -800,5 +867,106 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
#endif
return 0;
}
+#endif /* !CONFIG_DM_ETH */
+
+#ifdef CONFIG_DM_ETH
+
+static int macb_start(struct udevice *dev)
+{
+ struct macb_device *macb = dev_get_priv(dev);
+
+ return _macb_init(macb, dev->name);
+}
+
+static int macb_send(struct udevice *dev, void *packet, int length)
+{
+ struct macb_device *macb = dev_get_priv(dev);
+
+ return _macb_send(macb, dev->name, packet, length);
+}
+
+static int macb_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct macb_device *macb = dev_get_priv(dev);
+
+ macb->next_rx_tail = macb->rx_tail;
+ macb->wrapped = false;
+
+ return _macb_recv(macb, packetp);
+}
+
+static int macb_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct macb_device *macb = dev_get_priv(dev);
+
+ reclaim_rx_buffers(macb, macb->next_rx_tail);
+
+ return 0;
+}
+
+static void macb_stop(struct udevice *dev)
+{
+ struct macb_device *macb = dev_get_priv(dev);
+
+ _macb_halt(macb);
+}
+
+static int macb_write_hwaddr(struct udevice *dev)
+{
+ struct eth_pdata *plat = dev_get_platdata(dev);
+ struct macb_device *macb = dev_get_priv(dev);
+
+ return _macb_write_hwaddr(macb, plat->enetaddr);
+}
+
+static const struct eth_ops macb_eth_ops = {
+ .start = macb_start,
+ .send = macb_send,
+ .recv = macb_recv,
+ .stop = macb_stop,
+ .free_pkt = macb_free_pkt,
+ .write_hwaddr = macb_write_hwaddr,
+};
+
+static int macb_eth_probe(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct macb_device *macb = dev_get_priv(dev);
+
+ macb->regs = (void *)pdata->iobase;
+
+ _macb_eth_initialize(macb);
+#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
+ miiphy_register(dev->name, macb_miiphy_read, macb_miiphy_write);
+ macb->bus = miiphy_get_dev_by_name(dev->name);
+#endif
+
+ return 0;
+}
+
+static int macb_eth_ofdata_to_platdata(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+
+ pdata->iobase = dev_get_addr(dev);
+ return 0;
+}
+
+static const struct udevice_id macb_eth_ids[] = {
+ { .compatible = "cdns,macb" },
+ { }
+};
+
+U_BOOT_DRIVER(eth_macb) = {
+ .name = "eth_macb",
+ .id = UCLASS_ETH,
+ .of_match = macb_eth_ids,
+ .ofdata_to_platdata = macb_eth_ofdata_to_platdata,
+ .probe = macb_eth_probe,
+ .ops = &macb_eth_ops,
+ .priv_auto_alloc_size = sizeof(struct macb_device),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
+#endif
#endif
diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c
index 4fe992bf2b..e450135c75 100644
--- a/drivers/serial/atmel_usart.c
+++ b/drivers/serial/atmel_usart.c
@@ -191,16 +191,35 @@ static int atmel_serial_probe(struct udevice *dev)
{
struct atmel_serial_platdata *plat = dev->platdata;
struct atmel_serial_priv *priv = dev_get_priv(dev);
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ fdt_addr_t addr_base;
+ addr_base = dev_get_addr(dev);
+ if (addr_base == FDT_ADDR_T_NONE)
+ return -ENODEV;
+
+ plat->base_addr = (uint32_t)addr_base;
+#endif
priv->usart = (atmel_usart3_t *)plat->base_addr;
atmel_serial_init_internal(priv->usart);
return 0;
}
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+static const struct udevice_id atmel_serial_ids[] = {
+ { .compatible = "atmel,at91sam9260-usart" },
+ { }
+};
+#endif
+
U_BOOT_DRIVER(serial_atmel) = {
.name = "serial_atmel",
.id = UCLASS_SERIAL,
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+ .of_match = atmel_serial_ids,
+ .platdata_auto_alloc_size = sizeof(struct atmel_serial_platdata),
+#endif
.probe = atmel_serial_probe,
.ops = &atmel_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index b7fd8e53a2..aca385d5e5 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -75,6 +75,14 @@ config ICH_SPI
access the SPI NOR flash on platforms embedding this Intel
ICH IP core.
+config PIC32_SPI
+ bool "Microchip PIC32 SPI driver"
+ depends on MACH_PIC32
+ help
+ Enable the Microchip PIC32 SPI driver. This driver can be used
+ to access the SPI NOR flash, MMC-over-SPI on platforms based on
+ Microchip PIC32 family devices.
+
config ROCKCHIP_SPI
bool "Rockchip SPI driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 7fb2926e78..b1d9e2075e 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
obj-$(CONFIG_MXC_SPI) += mxc_spi.o
obj-$(CONFIG_MXS_SPI) += mxs_spi.o
obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
+obj-$(CONFIG_PIC32_SPI) += pic32_spi.o
obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
obj-$(CONFIG_SH_SPI) += sh_spi.o
diff --git a/drivers/spi/pic32_spi.c b/drivers/spi/pic32_spi.c
new file mode 100644
index 0000000000..25ca1f3e1b
--- /dev/null
+++ b/drivers/spi/pic32_spi.c
@@ -0,0 +1,448 @@
+/*
+ * Microchip PIC32 SPI controller driver.
+ *
+ * Copyright (c) 2015, Microchip Technology Inc.
+ * Purna Chandra Mandal <purna.mandal@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <linux/compat.h>
+#include <malloc.h>
+#include <spi.h>
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <dt-bindings/clock/microchip,clock.h>
+#include <mach/pic32.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* PIC32 SPI controller registers */
+struct pic32_reg_spi {
+ struct pic32_reg_atomic ctrl;
+ struct pic32_reg_atomic status;
+ struct pic32_reg_atomic buf;
+ struct pic32_reg_atomic baud;
+ struct pic32_reg_atomic ctrl2;
+};
+
+/* Bit fields in SPI Control Register */
+#define PIC32_SPI_CTRL_MSTEN BIT(5) /* Enable SPI Master */
+#define PIC32_SPI_CTRL_CKP BIT(6) /* active low */
+#define PIC32_SPI_CTRL_CKE BIT(8) /* Tx on falling edge */
+#define PIC32_SPI_CTRL_SMP BIT(9) /* Rx at middle or end of tx */
+#define PIC32_SPI_CTRL_BPW_MASK 0x03 /* Bits per word */
+#define PIC32_SPI_CTRL_BPW_8 0x0
+#define PIC32_SPI_CTRL_BPW_16 0x1
+#define PIC32_SPI_CTRL_BPW_32 0x2
+#define PIC32_SPI_CTRL_BPW_SHIFT 10
+#define PIC32_SPI_CTRL_ON BIT(15) /* Macro enable */
+#define PIC32_SPI_CTRL_ENHBUF BIT(16) /* Enable enhanced buffering */
+#define PIC32_SPI_CTRL_MCLKSEL BIT(23) /* Select SPI Clock src */
+#define PIC32_SPI_CTRL_MSSEN BIT(28) /* SPI macro will drive SS */
+#define PIC32_SPI_CTRL_FRMEN BIT(31) /* Enable framing mode */
+
+/* Bit fields in SPI Status Register */
+#define PIC32_SPI_STAT_RX_OV BIT(6) /* err, s/w needs to clear */
+#define PIC32_SPI_STAT_TF_LVL_MASK 0x1f
+#define PIC32_SPI_STAT_TF_LVL_SHIFT 16
+#define PIC32_SPI_STAT_RF_LVL_MASK 0x1f
+#define PIC32_SPI_STAT_RF_LVL_SHIFT 24
+
+/* Bit fields in SPI Baud Register */
+#define PIC32_SPI_BAUD_MASK 0x1ff
+
+struct pic32_spi_priv {
+ struct pic32_reg_spi *regs;
+ u32 fifo_depth; /* FIFO depth in bytes */
+ u32 fifo_n_word; /* FIFO depth in words */
+ struct gpio_desc cs_gpio;
+
+ /* Current SPI slave specific */
+ ulong clk_rate;
+ u32 speed_hz; /* spi-clk rate */
+ int mode;
+
+ /* Current message/transfer state */
+ const void *tx;
+ const void *tx_end;
+ const void *rx;
+ const void *rx_end;
+ u32 len;
+
+ /* SPI FiFo accessor */
+ void (*rx_fifo)(struct pic32_spi_priv *);
+ void (*tx_fifo)(struct pic32_spi_priv *);
+};
+
+static inline void pic32_spi_enable(struct pic32_spi_priv *priv)
+{
+ writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.set);
+}
+
+static inline void pic32_spi_disable(struct pic32_spi_priv *priv)
+{
+ writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.clr);
+}
+
+static inline u32 pic32_spi_rx_fifo_level(struct pic32_spi_priv *priv)
+{
+ u32 sr = readl(&priv->regs->status.raw);
+
+ return (sr >> PIC32_SPI_STAT_RF_LVL_SHIFT) & PIC32_SPI_STAT_RF_LVL_MASK;
+}
+
+static inline u32 pic32_spi_tx_fifo_level(struct pic32_spi_priv *priv)
+{
+ u32 sr = readl(&priv->regs->status.raw);
+
+ return (sr >> PIC32_SPI_STAT_TF_LVL_SHIFT) & PIC32_SPI_STAT_TF_LVL_MASK;
+}
+
+/* Return the max entries we can fill into tx fifo */
+static u32 pic32_tx_max(struct pic32_spi_priv *priv, int n_bytes)
+{
+ u32 tx_left, tx_room, rxtx_gap;
+
+ tx_left = (priv->tx_end - priv->tx) / n_bytes;
+ tx_room = priv->fifo_n_word - pic32_spi_tx_fifo_level(priv);
+
+ rxtx_gap = (priv->rx_end - priv->rx) - (priv->tx_end - priv->tx);
+ rxtx_gap /= n_bytes;
+ return min3(tx_left, tx_room, (u32)(priv->fifo_n_word - rxtx_gap));
+}
+
+/* Return the max entries we should read out of rx fifo */
+static u32 pic32_rx_max(struct pic32_spi_priv *priv, int n_bytes)
+{
+ u32 rx_left = (priv->rx_end - priv->rx) / n_bytes;
+
+ return min_t(u32, rx_left, pic32_spi_rx_fifo_level(priv));
+}
+
+#define BUILD_SPI_FIFO_RW(__name, __type, __bwl) \
+static void pic32_spi_rx_##__name(struct pic32_spi_priv *priv) \
+{ \
+ __type val; \
+ u32 mx = pic32_rx_max(priv, sizeof(__type)); \
+ \
+ for (; mx; mx--) { \
+ val = read##__bwl(&priv->regs->buf.raw); \
+ if (priv->rx_end - priv->len) \
+ *(__type *)(priv->rx) = val; \
+ priv->rx += sizeof(__type); \
+ } \
+} \
+ \
+static void pic32_spi_tx_##__name(struct pic32_spi_priv *priv) \
+{ \
+ __type val; \
+ u32 mx = pic32_tx_max(priv, sizeof(__type)); \
+ \
+ for (; mx ; mx--) { \
+ val = (__type) ~0U; \
+ if (priv->tx_end - priv->len) \
+ val = *(__type *)(priv->tx); \
+ write##__bwl(val, &priv->regs->buf.raw); \
+ priv->tx += sizeof(__type); \
+ } \
+}
+BUILD_SPI_FIFO_RW(byte, u8, b);
+BUILD_SPI_FIFO_RW(word, u16, w);
+BUILD_SPI_FIFO_RW(dword, u32, l);
+
+static int pic32_spi_set_word_size(struct pic32_spi_priv *priv,
+ unsigned int wordlen)
+{
+ u32 bits_per_word;
+ u32 val;
+
+ switch (wordlen) {
+ case 8:
+ priv->rx_fifo = pic32_spi_rx_byte;
+ priv->tx_fifo = pic32_spi_tx_byte;
+ bits_per_word = PIC32_SPI_CTRL_BPW_8;
+ break;
+ case 16:
+ priv->rx_fifo = pic32_spi_rx_word;
+ priv->tx_fifo = pic32_spi_tx_word;
+ bits_per_word = PIC32_SPI_CTRL_BPW_16;
+ break;
+ case 32:
+ priv->rx_fifo = pic32_spi_rx_dword;
+ priv->tx_fifo = pic32_spi_tx_dword;
+ bits_per_word = PIC32_SPI_CTRL_BPW_32;
+ break;
+ default:
+ printf("pic32-spi: unsupported wordlen\n");
+ return -EINVAL;
+ }
+
+ /* set bits-per-word */
+ val = readl(&priv->regs->ctrl.raw);
+ val &= ~(PIC32_SPI_CTRL_BPW_MASK << PIC32_SPI_CTRL_BPW_SHIFT);
+ val |= bits_per_word << PIC32_SPI_CTRL_BPW_SHIFT;
+ writel(val, &priv->regs->ctrl.raw);
+
+ /* calculate maximum number of words fifo can hold */
+ priv->fifo_n_word = DIV_ROUND_UP(priv->fifo_depth, wordlen / 8);
+
+ return 0;
+}
+
+static int pic32_spi_claim_bus(struct udevice *slave)
+{
+ struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
+
+ /* enable chip */
+ pic32_spi_enable(priv);
+
+ return 0;
+}
+
+static int pic32_spi_release_bus(struct udevice *slave)
+{
+ struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
+
+ /* disable chip */
+ pic32_spi_disable(priv);
+
+ return 0;
+}
+
+static void spi_cs_activate(struct pic32_spi_priv *priv)
+{
+ if (!dm_gpio_is_valid(&priv->cs_gpio))
+ return;
+
+ dm_gpio_set_value(&priv->cs_gpio, 1);
+}
+
+static void spi_cs_deactivate(struct pic32_spi_priv *priv)
+{
+ if (!dm_gpio_is_valid(&priv->cs_gpio))
+ return;
+
+ dm_gpio_set_value(&priv->cs_gpio, 0);
+}
+
+static int pic32_spi_xfer(struct udevice *slave, unsigned int bitlen,
+ const void *tx_buf, void *rx_buf,
+ unsigned long flags)
+{
+ struct dm_spi_slave_platdata *slave_plat;
+ struct udevice *bus = slave->parent;
+ struct pic32_spi_priv *priv;
+ int len = bitlen / 8;
+ int ret = 0;
+ ulong tbase;
+
+ priv = dev_get_priv(bus);
+ slave_plat = dev_get_parent_platdata(slave);
+
+ debug("spi_xfer: bus:%i cs:%i flags:%lx\n",
+ bus->seq, slave_plat->cs, flags);
+ debug("msg tx %p, rx %p submitted of %d byte(s)\n",
+ tx_buf, rx_buf, len);
+
+ /* assert cs */
+ if (flags & SPI_XFER_BEGIN)
+ spi_cs_activate(priv);
+
+ /* set current transfer information */
+ priv->tx = tx_buf;
+ priv->rx = rx_buf;
+ priv->tx_end = priv->tx + len;
+ priv->rx_end = priv->rx + len;
+ priv->len = len;
+
+ /* transact by polling */
+ tbase = get_timer(0);
+ for (;;) {
+ priv->tx_fifo(priv);
+ priv->rx_fifo(priv);
+
+ /* received sufficient data */
+ if (priv->rx >= priv->rx_end) {
+ ret = 0;
+ break;
+ }
+
+ if (get_timer(tbase) > 5 * CONFIG_SYS_HZ) {
+ printf("pic32_spi: error, xfer timedout.\n");
+ flags |= SPI_XFER_END;
+ ret = -ETIMEDOUT;
+ break;
+ }
+ }
+
+ /* deassert cs */
+ if (flags & SPI_XFER_END)
+ spi_cs_deactivate(priv);
+
+ return ret;
+}
+
+static int pic32_spi_set_speed(struct udevice *bus, uint speed)
+{
+ struct pic32_spi_priv *priv = dev_get_priv(bus);
+ u32 div;
+
+ debug("%s: %s, speed %u\n", __func__, bus->name, speed);
+
+ /* div = [clk_in / (2 * spi_clk)] - 1 */
+ div = (priv->clk_rate / 2 / speed) - 1;
+ div &= PIC32_SPI_BAUD_MASK;
+ writel(div, &priv->regs->baud.raw);
+
+ priv->speed_hz = speed;
+
+ return 0;
+}
+
+static int pic32_spi_set_mode(struct udevice *bus, uint mode)
+{
+ struct pic32_spi_priv *priv = dev_get_priv(bus);
+ u32 val;
+
+ debug("%s: %s, mode %d\n", __func__, bus->name, mode);
+
+ /* set spi-clk mode */
+ val = readl(&priv->regs->ctrl.raw);
+ /* HIGH when idle */
+ if (mode & SPI_CPOL)
+ val |= PIC32_SPI_CTRL_CKP;
+ else
+ val &= ~PIC32_SPI_CTRL_CKP;
+
+ /* TX at idle-to-active clk transition */
+ if (mode & SPI_CPHA)
+ val &= ~PIC32_SPI_CTRL_CKE;
+ else
+ val |= PIC32_SPI_CTRL_CKE;
+
+ /* RX at end of tx */
+ val |= PIC32_SPI_CTRL_SMP;
+ writel(val, &priv->regs->ctrl.raw);
+
+ priv->mode = mode;
+
+ return 0;
+}
+
+static int pic32_spi_set_wordlen(struct udevice *slave, unsigned int wordlen)
+{
+ struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
+
+ return pic32_spi_set_word_size(priv, wordlen);
+}
+
+static void pic32_spi_hw_init(struct pic32_spi_priv *priv)
+{
+ u32 val;
+
+ /* disable module */
+ pic32_spi_disable(priv);
+
+ val = readl(&priv->regs->ctrl);
+
+ /* enable enhanced fifo of 128bit deep */
+ val |= PIC32_SPI_CTRL_ENHBUF;
+ priv->fifo_depth = 16;
+
+ /* disable framing mode */
+ val &= ~PIC32_SPI_CTRL_FRMEN;
+
+ /* enable master mode */
+ val |= PIC32_SPI_CTRL_MSTEN;
+
+ /* select clk source */
+ val &= ~PIC32_SPI_CTRL_MCLKSEL;
+
+ /* set manual /CS mode */
+ val &= ~PIC32_SPI_CTRL_MSSEN;
+
+ writel(val, &priv->regs->ctrl);
+
+ /* clear rx overflow indicator */
+ writel(PIC32_SPI_STAT_RX_OV, &priv->regs->status.clr);
+}
+
+static int pic32_spi_probe(struct udevice *bus)
+{
+ struct pic32_spi_priv *priv = dev_get_priv(bus);
+ struct dm_spi_bus *dm_spi = dev_get_uclass_priv(bus);
+ struct udevice *clkdev;
+ fdt_addr_t addr;
+ fdt_size_t size;
+ int ret;
+
+ debug("%s: %d, bus: %i\n", __func__, __LINE__, bus->seq);
+ addr = fdtdec_get_addr_size(gd->fdt_blob, bus->of_offset, "reg", &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->regs = ioremap(addr, size);
+ if (!priv->regs)
+ return -EINVAL;
+
+ dm_spi->max_hz = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+ "spi-max-frequency", 250000000);
+ /* get clock rate */
+ ret = clk_get_by_index(bus, 0, &clkdev);
+ if (ret < 0) {
+ printf("pic32-spi: error, clk not found\n");
+ return ret;
+ }
+ priv->clk_rate = clk_get_periph_rate(clkdev, ret);
+
+ /* initialize HW */
+ pic32_spi_hw_init(priv);
+
+ /* set word len */
+ pic32_spi_set_word_size(priv, SPI_DEFAULT_WORDLEN);
+
+ /* PIC32 SPI controller can automatically drive /CS during transfer
+ * depending on fifo fill-level. /CS will stay asserted as long as
+ * TX fifo is non-empty, else will be deasserted confirming completion
+ * of the ongoing transfer. To avoid this sort of error we will drive
+ * /CS manually by toggling cs-gpio pins.
+ */
+ ret = gpio_request_by_name_nodev(gd->fdt_blob, bus->of_offset,
+ "cs-gpios", 0,
+ &priv->cs_gpio, GPIOD_IS_OUT);
+ if (ret) {
+ printf("pic32-spi: error, cs-gpios not found\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct dm_spi_ops pic32_spi_ops = {
+ .claim_bus = pic32_spi_claim_bus,
+ .release_bus = pic32_spi_release_bus,
+ .xfer = pic32_spi_xfer,
+ .set_speed = pic32_spi_set_speed,
+ .set_mode = pic32_spi_set_mode,
+ .set_wordlen = pic32_spi_set_wordlen,
+};
+
+static const struct udevice_id pic32_spi_ids[] = {
+ { .compatible = "microchip,pic32mzda-spi" },
+ { }
+};
+
+U_BOOT_DRIVER(pic32_spi) = {
+ .name = "pic32_spi",
+ .id = UCLASS_SPI,
+ .of_match = pic32_spi_ids,
+ .ops = &pic32_spi_ops,
+ .priv_auto_alloc_size = sizeof(struct pic32_spi_priv),
+ .probe = pic32_spi_probe,
+};
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index 3081afca0e..c016a0bb54 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -340,9 +340,16 @@ int musb_usb_probe(struct udevice *dev)
int musb_usb_remove(struct udevice *dev)
{
struct musb_host_data *host = dev_get_priv(dev);
+ struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
musb_stop(host->host);
+ sunxi_usb_phy_exit(0);
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+ clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
+#endif
+ clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
+
return 0;
}
diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
index d43d8a59d3..39cd7caff1 100644
--- a/drivers/video/atmel_lcdfb.c
+++ b/drivers/video/atmel_lcdfb.c
@@ -7,6 +7,10 @@
*/
#include <common.h>
+#include <atmel_lcd.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <video.h>
#include <asm/io.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
@@ -14,6 +18,21 @@
#include <bmp_layout.h>
#include <atmel_lcdc.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_DM_VIDEO
+enum {
+ /* Maximum LCD size we support */
+ LCD_MAX_WIDTH = 1366,
+ LCD_MAX_HEIGHT = 768,
+ LCD_MAX_LOG2_BPP = VIDEO_BPP16,
+};
+#endif
+
+struct atmel_fb_priv {
+ struct display_timing timing;
+};
+
/* configurable parameters */
#define ATMEL_LCDC_CVAL_DEFAULT 0xc8
#define ATMEL_LCDC_DMA_BURST_LEN 8
@@ -30,6 +49,7 @@
#define lcdc_readl(mmio, reg) __raw_readl((mmio)+(reg))
#define lcdc_writel(mmio, reg, val) __raw_writel((val), (mmio)+(reg))
+#ifndef CONFIG_DM_VIDEO
ushort *configuration_get_cmap(void)
{
return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
@@ -90,40 +110,43 @@ void lcd_set_cmap(struct bmp_image *bmp, unsigned colors)
lcd_setcolreg(i, cte.red, cte.green, cte.blue);
}
}
+#endif
-void lcd_ctrl_init(void *lcdbase)
+static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,
+ bool tft, bool cont_pol_low, ulong lcdbase)
{
unsigned long value;
+ void *reg = (void *)addr;
/* Turn off the LCD controller and the DMA controller */
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON,
+ lcdc_writel(reg, ATMEL_LCDC_PWRCON,
ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET);
/* Wait for the LCDC core to become idle */
- while (lcdc_readl(panel_info.mmio, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
+ while (lcdc_readl(reg, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
udelay(10);
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, 0);
+ lcdc_writel(reg, ATMEL_LCDC_DMACON, 0);
/* Reset LCDC DMA */
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
+ lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
/* ...set frame size and burst length = 8 words (?) */
- value = (panel_info.vl_col * panel_info.vl_row *
- NBITS(panel_info.vl_bpix)) / 32;
+ value = (timing->hactive.typ * timing->vactive.typ *
+ (1 << bpix)) / 32;
value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMAFRMCFG, value);
+ lcdc_writel(reg, ATMEL_LCDC_DMAFRMCFG, value);
/* Set pixel clock */
- value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
- if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
+ value = get_lcdc_clk_rate(0) / timing->pixelclock.typ;
+ if (get_lcdc_clk_rate(0) % timing->pixelclock.typ)
value++;
value = (value / 2) - 1;
if (!value) {
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
+ lcdc_writel(reg, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
} else
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1,
+ lcdc_writel(reg, ATMEL_LCDC_LCDCON1,
value << ATMEL_LCDC_CLKVAL_OFFSET);
/* Initialize control register 2 */
@@ -132,58 +155,160 @@ void lcd_ctrl_init(void *lcdbase)
#else
value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
#endif
- if (panel_info.vl_tft)
+ if (tft)
value |= ATMEL_LCDC_DISTYPE_TFT;
- value |= panel_info.vl_sync;
- value |= (panel_info.vl_bpix << 5);
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON2, value);
+ if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
+ value |= ATMEL_LCDC_INVLINE_INVERTED;
+ if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
+ value |= ATMEL_LCDC_INVFRAME_INVERTED;
+ value |= bpix << 5;
+ lcdc_writel(reg, ATMEL_LCDC_LCDCON2, value);
/* Vertical timing */
- value = (panel_info.vl_vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
- value |= panel_info.vl_upper_margin << ATMEL_LCDC_VBP_OFFSET;
- value |= panel_info.vl_lower_margin;
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM1, value);
+ value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET;
+ value |= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET;
+ value |= timing->vfront_porch.typ;
+ /* Magic! (Datasheet says "Bit 31 must be written to 1") */
+ value |= 1U << 31;
+ lcdc_writel(reg, ATMEL_LCDC_TIM1, value);
/* Horizontal timing */
- value = (panel_info.vl_right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
- value |= (panel_info.vl_hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
- value |= (panel_info.vl_left_margin - 1);
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM2, value);
+ value = (timing->hfront_porch.typ - 1) << ATMEL_LCDC_HFP_OFFSET;
+ value |= (timing->hsync_len.typ - 1) << ATMEL_LCDC_HPW_OFFSET;
+ value |= (timing->hback_porch.typ - 1);
+ lcdc_writel(reg, ATMEL_LCDC_TIM2, value);
/* Display size */
- value = (panel_info.vl_col - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
- value |= panel_info.vl_row - 1;
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDFRMCFG, value);
+ value = (timing->hactive.typ - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
+ value |= timing->vactive.typ - 1;
+ lcdc_writel(reg, ATMEL_LCDC_LCDFRMCFG, value);
/* FIFO Threshold: Use formula from data sheet */
value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_FIFO, value);
+ lcdc_writel(reg, ATMEL_LCDC_FIFO, value);
/* Toggle LCD_MODE every frame */
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_MVAL, 0);
+ lcdc_writel(reg, ATMEL_LCDC_MVAL, 0);
/* Disable all interrupts */
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_IDR, ~0UL);
+ lcdc_writel(reg, ATMEL_LCDC_IDR, ~0UL);
/* Set contrast */
value = ATMEL_LCDC_PS_DIV8 |
ATMEL_LCDC_ENA_PWMENABLE;
- if (!panel_info.vl_cont_pol_low)
+ if (!cont_pol_low)
value |= ATMEL_LCDC_POL_POSITIVE;
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_CTR, value);
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
+ lcdc_writel(reg, ATMEL_LCDC_CONTRAST_CTR, value);
+ lcdc_writel(reg, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
/* Set framebuffer DMA base address and pixel offset */
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMABADDR1, (u_long)lcdbase);
+ lcdc_writel(reg, ATMEL_LCDC_DMABADDR1, lcdbase);
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
- lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON,
+ lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
+ lcdc_writel(reg, ATMEL_LCDC_PWRCON,
(ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
}
+#ifndef CONFIG_DM_VIDEO
+void lcd_ctrl_init(void *lcdbase)
+{
+ struct display_timing timing;
+
+ timing.flags = 0;
+ if (!(panel_info.vl_sync & ATMEL_LCDC_INVLINE_INVERTED))
+ timing.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
+ if (!(panel_info.vl_sync & ATMEL_LCDC_INVFRAME_INVERTED))
+ timing.flags |= DISPLAY_FLAGS_VSYNC_LOW;
+ timing.pixelclock.typ = panel_info.vl_clk;
+
+ timing.hactive.typ = panel_info.vl_col;
+ timing.hfront_porch.typ = panel_info.vl_right_margin;
+ timing.hback_porch.typ = panel_info.vl_left_margin;
+ timing.hsync_len.typ = panel_info.vl_hsync_len;
+
+ timing.vactive.typ = panel_info.vl_row;
+ timing.vfront_porch.typ = panel_info.vl_clk;
+ timing.vback_porch.typ = panel_info.vl_clk;
+ timing.vsync_len.typ = panel_info.vl_clk;
+
+ atmel_fb_init(panel_info.mmio, &timing, panel_info.vl_bpix,
+ panel_info.vl_tft, panel_info.vl_cont_pol_low,
+ (ulong)lcdbase);
+}
+
ulong calc_fbsize(void)
{
return ((panel_info.vl_col * panel_info.vl_row *
NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
}
+#endif
+
+#ifdef CONFIG_DM_VIDEO
+static int atmel_fb_lcd_probe(struct udevice *dev)
+{
+ struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+ struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct atmel_fb_priv *priv = dev_get_priv(dev);
+ struct display_timing *timing = &priv->timing;
+
+ /*
+ * For now some values are hard-coded. We could use the device tree
+ * bindings in simple-framebuffer.txt to specify the format/bpp and
+ * some Atmel-specific binding for tft and cont_pol_low.
+ */
+ atmel_fb_init(ATMEL_BASE_LCDC, timing, VIDEO_BPP16, true, false,
+ uc_plat->base);
+ uc_priv->xsize = timing->hactive.typ;
+ uc_priv->ysize = timing->vactive.typ;
+ uc_priv->bpix = VIDEO_BPP16;
+ video_set_flush_dcache(dev, true);
+ debug("LCD frame buffer at %lx, size %x, %dx%d pixels\n", uc_plat->base,
+ uc_plat->size, uc_priv->xsize, uc_priv->ysize);
+
+ return 0;
+}
+
+static int atmel_fb_ofdata_to_platdata(struct udevice *dev)
+{
+ struct atmel_lcd_platdata *plat = dev_get_platdata(dev);
+ struct atmel_fb_priv *priv = dev_get_priv(dev);
+ struct display_timing *timing = &priv->timing;
+ const void *blob = gd->fdt_blob;
+
+ if (fdtdec_decode_display_timing(blob, dev->of_offset,
+ plat->timing_index, timing)) {
+ debug("%s: Failed to decode display timing\n", __func__);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int atmel_fb_lcd_bind(struct udevice *dev)
+{
+ struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
+
+ uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
+ (1 << VIDEO_BPP16) / 8;
+ debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
+
+ return 0;
+}
+
+static const struct udevice_id atmel_fb_lcd_ids[] = {
+ { .compatible = "atmel,at91sam9g45-lcdc" },
+ { }
+};
+
+U_BOOT_DRIVER(atmel_fb) = {
+ .name = "atmel_fb",
+ .id = UCLASS_VIDEO,
+ .of_match = atmel_fb_lcd_ids,
+ .bind = atmel_fb_lcd_bind,
+ .ofdata_to_platdata = atmel_fb_ofdata_to_platdata,
+ .probe = atmel_fb_lcd_probe,
+ .platdata_auto_alloc_size = sizeof(struct atmel_lcd_platdata),
+ .priv_auto_alloc_size = sizeof(struct atmel_fb_priv),
+};
+#endif
generated by cgit (git 2.34.1) at 2025-02-08 13:18:19 +0000