diff options
Diffstat (limited to 'include/asm-ppc')
| -rw-r--r-- | include/asm-ppc/gpio.h | 24 | ||||
| -rw-r--r-- | include/asm-ppc/ppc4xx_config.h | 42 | ||||
| -rw-r--r-- | include/asm-ppc/processor.h | 46 |
3 files changed, 112 insertions, 0 deletions
diff --git a/include/asm-ppc/gpio.h b/include/asm-ppc/gpio.h index fc05dc0df7..23e29b195e 100644 --- a/include/asm-ppc/gpio.h +++ b/include/asm-ppc/gpio.h @@ -24,6 +24,8 @@ #ifndef __ASM_PPC_GPIO_H #define __ASM_PPC_GPIO_H +#include <asm/types.h> + /* 4xx PPC's have 2 GPIO controllers */ #if defined(CONFIG_405EZ) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ @@ -34,6 +36,28 @@ #define GPIO_GROUP_MAX 1 #endif +/* GPIO controller */ +struct ppc4xx_gpio { + u32 or; /* Output Control */ + u32 tcr; /* Tri-State Control */ + u32 osl; /* Output Select 16..31 */ + u32 osh; /* Output Select 0..15 */ + u32 tsl; /* Tri-State Select 16..31 */ + u32 tsh; /* Tri-State Select 0..15 */ + u32 odr; /* Open Drain */ + u32 ir; /* Input */ + u32 rr1; /* Receive Register 1 */ + u32 rr2; /* Receive Register 2 */ + u32 rr3; /* Receive Register 3 */ + u32 reserved; + u32 is1l; /* Input Select 1 16..31 */ + u32 is1h; /* Input Select 1 0..15 */ + u32 is2l; /* Input Select 2 16..31 */ + u32 is2h; /* Input Select 2 0..15 */ + u32 is3l; /* Input Select 3 16..31 */ + u32 is3h; /* Input Select 3 0..15 */ +}; + /* Offsets */ #define GPIOx_OR 0x00 /* GPIO Output Register */ #define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */ diff --git a/include/asm-ppc/ppc4xx_config.h b/include/asm-ppc/ppc4xx_config.h new file mode 100644 index 0000000000..49acb60aed --- /dev/null +++ b/include/asm-ppc/ppc4xx_config.h @@ -0,0 +1,42 @@ +/* + * (C) Copyright 2008-2009 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2009 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __PPC4xx_CONFIG_H +#define __PPC4xx_CONFIG_H + +#include <common.h> + +struct ppc4xx_config { + char label[16]; + char description[64]; + u8 val[CONFIG_4xx_CONFIG_BLOCKSIZE]; +}; + +extern struct ppc4xx_config ppc4xx_config_val[]; +extern int ppc4xx_config_count; + +#endif /* __PPC4xx_CONFIG_H */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 65546adbca..2c0c0cee40 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -96,6 +96,10 @@ #define CONFIG_BOOKE #endif +#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ +#ifdef CONFIG_BOOKE +#define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */ +#endif #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ #define SPRN_CTR 0x009 /* Count Register */ #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ @@ -166,6 +170,9 @@ #define SPRN_DBSR 0x3F0 /* Debug Status Register */ #else #define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */ +#ifdef CONFIG_BOOKE +#define SPRN_DBDR 0x3f3 /* Debug Data Register */ +#endif #define SPRN_DBSR 0x130 /* Book E Debug Status Register */ #define DBSR_IC 0x08000000 /* Book E Instruction Completion */ #define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */ @@ -173,6 +180,10 @@ #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ #define DCCR_NOCACHE 0 /* Noncacheable */ #define DCCR_CACHE 1 /* Cacheable */ +#ifndef CONFIG_BOOKE +#define SPRN_DCDBTRL 0x39c /* Data Cache Debug Tag Register Low */ +#define SPRN_DCDBTRH 0x39d /* Data Cache Debug Tag Register High */ +#endif #define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ #define DCWR_COPY 0 /* Copy-back */ @@ -184,7 +195,20 @@ #endif /* CONFIG_BOOKE */ #define SPRN_DEC 0x016 /* Decrement Register */ #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ +#ifdef CONFIG_BOOKE +#define SPRN_DNV0 0x390 /* Data Cache Normal Victim 0 */ +#define SPRN_DNV1 0x391 /* Data Cache Normal Victim 1 */ +#define SPRN_DNV2 0x392 /* Data Cache Normal Victim 2 */ +#define SPRN_DNV3 0x393 /* Data Cache Normal Victim 3 */ +#endif #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ +#ifdef CONFIG_BOOKE +#define SPRN_DTV0 0x394 /* Data Cache Transient Victim 0 */ +#define SPRN_DTV1 0x395 /* Data Cache Transient Victim 1 */ +#define SPRN_DTV2 0x396 /* Data Cache Transient Victim 2 */ +#define SPRN_DTV3 0x397 /* Data Cache Transient Victim 3 */ +#define SPRN_DVLIM 0x398 /* Data Cache Victim Limit */ +#endif #define SPRN_EAR 0x11A /* External Address Register */ #ifndef CONFIG_BOOKE #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ @@ -269,16 +293,34 @@ #define ICCR_NOCACHE 0 /* Noncacheable */ #define ICCR_CACHE 1 /* Cacheable */ #define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ +#ifdef CONFIG_BOOKE +#define SPRN_ICDBTRL 0x39e /* instruction cache debug tag register low */ +#define SPRN_ICDBTRH 0x39f /* instruction cache debug tag register high */ +#endif #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ #define SPRN_IMMR 0x27E /* Internal Memory Map Register */ +#ifdef CONFIG_BOOKE +#define SPRN_INV0 0x370 /* Instruction Cache Normal Victim 0 */ +#define SPRN_INV1 0x371 /* Instruction Cache Normal Victim 1 */ +#define SPRN_INV2 0x372 /* Instruction Cache Normal Victim 2 */ +#define SPRN_INV3 0x373 /* Instruction Cache Normal Victim 3 */ +#define SPRN_ITV0 0x374 /* Instruction Cache Transient Victim 0 */ +#define SPRN_ITV1 0x375 /* Instruction Cache Transient Victim 1 */ +#define SPRN_ITV2 0x376 /* Instruction Cache Transient Victim 2 */ +#define SPRN_ITV3 0x377 /* Instruction Cache Transient Victim 3 */ +#define SPRN_IVLIM 0x399 /* Instruction Cache Victim Limit */ +#endif #define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ #define SPRN_LR 0x008 /* Link Register */ #define SPRN_MBAR 0x137 /* System memory base address */ #define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */ #define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */ +#ifdef CONFIG_BOOKE +#define SPRN_MMUCR 0x3b2 /* MMU Control Register */ +#endif #define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ #define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ #define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ @@ -297,6 +339,9 @@ #define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */ #define SPRN_PVR 0x11F /* Processor Version Register */ #define SPRN_RPA 0x3D6 /* Required Physical Address Register */ +#ifdef CONFIG_BOOKE +#define SPRN_RSTCFG 0x39b /* Reset Configuration */ +#endif #define SPRN_SDA 0x3BF /* Sampled Data Address Register */ #define SPRN_SDR1 0x019 /* MMU Hash Base Register */ #define SPRN_SGR 0x3B9 /* Storage Guarded Register */ @@ -315,6 +360,7 @@ #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ #define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ + #ifdef CONFIG_BOOKE #define SPRN_SVR 0x3FF /* System Version Register */ #else |