diff options
Diffstat (limited to 'include/asm-ppc')
| -rw-r--r-- | include/asm-ppc/4xx_pci.h | 52 | ||||
| -rw-r--r-- | include/asm-ppc/4xx_pcie.h | 336 | ||||
| -rw-r--r-- | include/asm-ppc/cache.h | 21 | ||||
| -rw-r--r-- | include/asm-ppc/global_data.h | 3 | ||||
| -rw-r--r-- | include/asm-ppc/gpio.h | 35 | ||||
| -rw-r--r-- | include/asm-ppc/mmu.h | 1 | ||||
| -rw-r--r-- | include/asm-ppc/processor.h | 9 | ||||
| -rw-r--r-- | include/asm-ppc/u-boot.h | 1 |
8 files changed, 453 insertions, 5 deletions
diff --git a/include/asm-ppc/4xx_pci.h b/include/asm-ppc/4xx_pci.h new file mode 100644 index 0000000000..3c1adec19c --- /dev/null +++ b/include/asm-ppc/4xx_pci.h @@ -0,0 +1,52 @@ +#ifndef _405GP_PCI_H +#define _405GP_PCI_H + +/*----------------------------------------------------------------------------+ +| 405GP PCI core memory map defines. ++----------------------------------------------------------------------------*/ +#define MIN_PCI_MEMADDR1 0x80000000 +#define MIN_PCI_MEMADDR2 0x00000000 +#define MIN_PLB_PCI_IOADDR 0xE8000000 /* PLB side of PCI I/O address space */ +#define MIN_PCI_PCI_IOADDR 0x00000000 /* PCI side of PCI I/O address space */ +#define MAX_PCI_DEVICES 32 + +/*----------------------------------------------------------------------------+ +| Defines for the 405GP PCI Config address and data registers followed by +| defines for the standard PCI device configuration header. ++----------------------------------------------------------------------------*/ +#define PCICFGADR 0xEEC00000 +#define PCICFGDATA 0xEEC00004 + +#define PCIBUSNUM 0x40 /* 405GP specific parameters */ +#define PCISUBBUSNUM 0x41 +#define PCIDISCOUNT 0x42 +#define PCIBRDGOPT1 0x4A +#define PCIBRDGOPT2 0x60 + +/*----------------------------------------------------------------------------+ +| Defines for 405GP PCI Master local configuration regs. ++----------------------------------------------------------------------------*/ +#define PMM0LA 0xEF400000 +#define PMM0MA 0xEF400004 +#define PMM0PCILA 0xEF400008 +#define PMM0PCIHA 0xEF40000C +#define PMM1LA 0xEF400010 +#define PMM1MA 0xEF400014 +#define PMM1PCILA 0xEF400018 +#define PMM1PCIHA 0xEF40001C +#define PMM2LA 0xEF400020 +#define PMM2MA 0xEF400024 +#define PMM2PCILA 0xEF400028 +#define PMM2PCIHA 0xEF40002C + +/*----------------------------------------------------------------------------+ +| Defines for 405GP PCI Target local configuration regs. ++----------------------------------------------------------------------------*/ +#define PTM1MS 0xEF400030 +#define PTM1LA 0xEF400034 +#define PTM2MS 0xEF400038 +#define PTM2LA 0xEF40003C + +#define PCIDEVID_405GP 0x0 + +#endif diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h new file mode 100644 index 0000000000..4c03b050fe --- /dev/null +++ b/include/asm-ppc/4xx_pcie.h @@ -0,0 +1,336 @@ +/* + * Copyright (c) 2005 Cisco Systems. All rights reserved. + * Roland Dreier <rolandd@cisco.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <ppc4xx.h> +#ifndef __4XX_PCIE_H +#define __4XX_PCIE_H + +#define DCRN_SDR0_CFGADDR 0x00e +#define DCRN_SDR0_CFGDATA 0x00f + +#if defined(CONFIG_440SPE) +#define CFG_PCIE_NR_PORTS 3 + +#define CFG_PCIE_ADDR_HIGH 0x0000000d + +#define DCRN_PCIE0_BASE 0x100 +#define DCRN_PCIE1_BASE 0x120 +#define DCRN_PCIE2_BASE 0x140 + +#define PCIE0_SDR 0x300 +#define PCIE1_SDR 0x340 +#define PCIE2_SDR 0x370 +#endif + +#if defined(CONFIG_405EX) +#define CFG_PCIE_NR_PORTS 2 + +#define CFG_PCIE_ADDR_HIGH 0x00000000 + +#define DCRN_PCIE0_BASE 0x040 +#define DCRN_PCIE1_BASE 0x060 + +#define PCIE0_SDR 0x400 +#define PCIE1_SDR 0x440 +#endif + +#define PCIE0 DCRN_PCIE0_BASE +#define PCIE1 DCRN_PCIE1_BASE +#define PCIE2 DCRN_PCIE2_BASE + +#define DCRN_PEGPL_CFGBAH(base) (base + 0x00) +#define DCRN_PEGPL_CFGBAL(base) (base + 0x01) +#define DCRN_PEGPL_CFGMSK(base) (base + 0x02) +#define DCRN_PEGPL_MSGBAH(base) (base + 0x03) +#define DCRN_PEGPL_MSGBAL(base) (base + 0x04) +#define DCRN_PEGPL_MSGMSK(base) (base + 0x05) +#define DCRN_PEGPL_OMR1BAH(base) (base + 0x06) +#define DCRN_PEGPL_OMR1BAL(base) (base + 0x07) +#define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08) +#define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09) +#define DCRN_PEGPL_REGBAH(base) (base + 0x12) +#define DCRN_PEGPL_REGBAL(base) (base + 0x13) +#define DCRN_PEGPL_REGMSK(base) (base + 0x14) +#define DCRN_PEGPL_SPECIAL(base) (base + 0x15) +#define DCRN_PEGPL_CFG(base) (base + 0x16) + +/* + * System DCRs (SDRs) + */ +#define PESDR0_PLLLCT1 0x03a0 +#define PESDR0_PLLLCT2 0x03a1 +#define PESDR0_PLLLCT3 0x03a2 + +/* common regs, at least for 405EX and 440SPe */ +#define SDRN_PESDR_UTLSET1(n) (sdr_base(n) + 0x00) +#define SDRN_PESDR_UTLSET2(n) (sdr_base(n) + 0x01) +#define SDRN_PESDR_DLPSET(n) (sdr_base(n) + 0x02) +#define SDRN_PESDR_LOOP(n) (sdr_base(n) + 0x03) +#define SDRN_PESDR_RCSSET(n) (sdr_base(n) + 0x04) +#define SDRN_PESDR_RCSSTS(n) (sdr_base(n) + 0x05) + +#if defined(CONFIG_440SPE) +#define SDRN_PESDR_HSSL0SET1(n) (sdr_base(n) + 0x06) +#define SDRN_PESDR_HSSL0SET2(n) (sdr_base(n) + 0x07) +#define SDRN_PESDR_HSSL0STS(n) (sdr_base(n) + 0x08) +#define SDRN_PESDR_HSSL1SET1(n) (sdr_base(n) + 0x09) +#define SDRN_PESDR_HSSL1SET2(n) (sdr_base(n) + 0x0a) +#define SDRN_PESDR_HSSL1STS(n) (sdr_base(n) + 0x0b) +#define SDRN_PESDR_HSSL2SET1(n) (sdr_base(n) + 0x0c) +#define SDRN_PESDR_HSSL2SET2(n) (sdr_base(n) + 0x0d) +#define SDRN_PESDR_HSSL2STS(n) (sdr_base(n) + 0x0e) +#define SDRN_PESDR_HSSL3SET1(n) (sdr_base(n) + 0x0f) +#define SDRN_PESDR_HSSL3SET2(n) (sdr_base(n) + 0x10) +#define SDRN_PESDR_HSSL3STS(n) (sdr_base(n) + 0x11) + +#define PESDR0_UTLSET1 0x0300 +#define PESDR0_UTLSET2 0x0301 +#define PESDR0_DLPSET 0x0302 +#define PESDR0_LOOP 0x0303 +#define PESDR0_RCSSET 0x0304 +#define PESDR0_RCSSTS 0x0305 +#define PESDR0_HSSL0SET1 0x0306 +#define PESDR0_HSSL0SET2 0x0307 +#define PESDR0_HSSL0STS 0x0308 +#define PESDR0_HSSL1SET1 0x0309 +#define PESDR0_HSSL1SET2 0x030a +#define PESDR0_HSSL1STS 0x030b +#define PESDR0_HSSL2SET1 0x030c +#define PESDR0_HSSL2SET2 0x030d +#define PESDR0_HSSL2STS 0x030e +#define PESDR0_HSSL3SET1 0x030f +#define PESDR0_HSSL3SET2 0x0310 +#define PESDR0_HSSL3STS 0x0311 +#define PESDR0_HSSL4SET1 0x0312 +#define PESDR0_HSSL4SET2 0x0313 +#define PESDR0_HSSL4STS 0x0314 +#define PESDR0_HSSL5SET1 0x0315 +#define PESDR0_HSSL5SET2 0x0316 +#define PESDR0_HSSL5STS 0x0317 +#define PESDR0_HSSL6SET1 0x0318 +#define PESDR0_HSSL6SET2 0x0319 +#define PESDR0_HSSL6STS 0x031a +#define PESDR0_HSSL7SET1 0x031b +#define PESDR0_HSSL7SET2 0x031c +#define PESDR0_HSSL7STS 0x031d +#define PESDR0_HSSCTLSET 0x031e +#define PESDR0_LANE_ABCD 0x031f +#define PESDR0_LANE_EFGH 0x0320 + +#define PESDR1_UTLSET1 0x0340 +#define PESDR1_UTLSET2 0x0341 +#define PESDR1_DLPSET 0x0342 +#define PESDR1_LOOP 0x0343 +#define PESDR1_RCSSET 0x0344 +#define PESDR1_RCSSTS 0x0345 +#define PESDR1_HSSL0SET1 0x0346 +#define PESDR1_HSSL0SET2 0x0347 +#define PESDR1_HSSL0STS 0x0348 +#define PESDR1_HSSL1SET1 0x0349 +#define PESDR1_HSSL1SET2 0x034a +#define PESDR1_HSSL1STS 0x034b +#define PESDR1_HSSL2SET1 0x034c +#define PESDR1_HSSL2SET2 0x034d +#define PESDR1_HSSL2STS 0x034e +#define PESDR1_HSSL3SET1 0x034f +#define PESDR1_HSSL3SET2 0x0350 +#define PESDR1_HSSL3STS 0x0351 +#define PESDR1_HSSCTLSET 0x0352 +#define PESDR1_LANE_ABCD 0x0353 + +#define PESDR2_UTLSET1 0x0370 +#define PESDR2_UTLSET2 0x0371 +#define PESDR2_DLPSET 0x0372 +#define PESDR2_LOOP 0x0373 +#define PESDR2_RCSSET 0x0374 +#define PESDR2_RCSSTS 0x0375 +#define PESDR2_HSSL0SET1 0x0376 +#define PESDR2_HSSL0SET2 0x0377 +#define PESDR2_HSSL0STS 0x0378 +#define PESDR2_HSSL1SET1 0x0379 +#define PESDR2_HSSL1SET2 0x037a +#define PESDR2_HSSL1STS 0x037b +#define PESDR2_HSSL2SET1 0x037c +#define PESDR2_HSSL2SET2 0x037d +#define PESDR2_HSSL2STS 0x037e +#define PESDR2_HSSL3SET1 0x037f +#define PESDR2_HSSL3SET2 0x0380 +#define PESDR2_HSSL3STS 0x0381 +#define PESDR2_HSSCTLSET 0x0382 +#define PESDR2_LANE_ABCD 0x0383 + +#elif defined(CONFIG_405EX) + +#define SDRN_PESDR_PHYSET1(n) (sdr_base(n) + 0x06) +#define SDRN_PESDR_PHYSET2(n) (sdr_base(n) + 0x07) +#define SDRN_PESDR_BIST(n) (sdr_base(n) + 0x08) +#define SDRN_PESDR_LPB(n) (sdr_base(n) + 0x0b) +#define SDRN_PESDR_PHYSTA(n) (sdr_base(n) + 0x0c) + +#define PESDR0_UTLSET1 0x0400 +#define PESDR0_UTLSET2 0x0401 +#define PESDR0_DLPSET 0x0402 +#define PESDR0_LOOP 0x0403 +#define PESDR0_RCSSET 0x0404 +#define PESDR0_RCSSTS 0x0405 +#define PESDR0_PHYSET1 0x0406 +#define PESDR0_PHYSET2 0x0407 +#define PESDR0_BIST 0x0408 +#define PESDR0_LPB 0x040B +#define PESDR0_PHYSTA 0x040C + +#define PESDR1_UTLSET1 0x0440 +#define PESDR1_UTLSET2 0x0441 +#define PESDR1_DLPSET 0x0442 +#define PESDR1_LOOP 0x0443 +#define PESDR1_RCSSET 0x0444 +#define PESDR1_RCSSTS 0x0445 +#define PESDR1_PHYSET1 0x0446 +#define PESDR1_PHYSET2 0x0447 +#define PESDR1_BIST 0x0448 +#define PESDR1_LPB 0x044B +#define PESDR1_PHYSTA 0x044C + +#endif + +/* + * UTL register offsets + */ +#define PEUTL_PBCTL 0x00 +#define PEUTL_PBBSZ 0x20 +#define PEUTL_OPDBSZ 0x68 +#define PEUTL_IPHBSZ 0x70 +#define PEUTL_IPDBSZ 0x78 +#define PEUTL_OUTTR 0x90 +#define PEUTL_INTR 0x98 +#define PEUTL_PCTL 0xa0 +#define PEUTL_RCSTA 0xb0 +#define PEUTL_RCIRQEN 0xb8 + +/* + * Config space register offsets + */ +#define PECFG_BAR0LMPA 0x210 +#define PECFG_BAR0HMPA 0x214 +#define PECFG_BAR1MPA 0x218 +#define PECFG_BAR2LMPA 0x220 +#define PECFG_BAR2HMPA 0x224 + +#define PECFG_PIMEN 0x33c +#define PECFG_PIM0LAL 0x340 +#define PECFG_PIM0LAH 0x344 +#define PECFG_PIM1LAL 0x348 +#define PECFG_PIM1LAH 0x34c +#define PECFG_PIM01SAL 0x350 +#define PECFG_PIM01SAH 0x354 + +#define PECFG_POM0LAL 0x380 +#define PECFG_POM0LAH 0x384 + +#define SDR_READ(offset) ({\ + mtdcr(DCRN_SDR0_CFGADDR, offset); \ + mfdcr(DCRN_SDR0_CFGDATA);}) + +#define SDR_WRITE(offset, data) ({\ + mtdcr(DCRN_SDR0_CFGADDR, offset); \ + mtdcr(DCRN_SDR0_CFGDATA,data);}) + +#define GPL_DMER_MASK_DISA 0x02000000 + +#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL)) +#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32)) + +/* + * Prototypes + */ +int ppc4xx_init_pcie(void); +int ppc4xx_init_pcie_rootport(int port); +int ppc4xx_init_pcie_endport(int port); +void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port); +int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port); +int pcie_hose_scan(struct pci_controller *hose, int bus); + +/* + * Function to determine root port or endport from env variable. + */ +static inline int is_end_point(int port) +{ + char s[10], *tk; + char *pcie_mode = getenv("pcie_mode"); + + if (pcie_mode == NULL) + return 0; + + strcpy(s, pcie_mode); + tk = strtok(s, ":"); + + switch (port) { + case 0: + if (tk != NULL) { + if (!(strcmp(tk, "ep") && strcmp(tk, "EP"))) + return 1; + else + return 0; + } + else + return 0; + + case 1: + tk = strtok(NULL, ":"); + if (tk != NULL) { + if (!(strcmp(tk, "ep") && strcmp(tk, "EP"))) + return 1; + else + return 0; + } + else + return 0; + + case 2: + tk = strtok(NULL, ":"); + if (tk != NULL) + tk = strtok(NULL, ":"); + if (tk != NULL) { + if (!(strcmp(tk, "ep") && strcmp(tk, "EP"))) + return 1; + else + return 0; + } + else + return 0; + } + + return 0; +} + +static inline void mdelay(int n) +{ + u32 ms = n; + + while (ms--) + udelay(1000); +} + +static inline u32 sdr_base(int port) +{ + switch (port) { + default: /* to satisfy compiler */ + case 0: + return PCIE0_SDR; + case 1: + return PCIE1_SDR; +#if CFG_PCIE_NR_PORTS > 2 + case 2: + return PCIE2_SDR; +#endif + } +} + +#endif /* __4XX_PCIE_H */ diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h index 5befab4d53..e29bfc2a7b 100644 --- a/include/asm-ppc/cache.h +++ b/include/asm-ppc/cache.h @@ -8,15 +8,24 @@ #include <asm/processor.h> /* bytes per L1 cache line */ -#if !defined(CONFIG_8xx) || defined(CONFIG_8260) +#if !(defined(CONFIG_8xx) || defined(CONFIG_IOP480)) #if defined(CONFIG_PPC64BRIDGE) -#define L1_CACHE_BYTES 128 +#define L1_CACHE_SHIFT 7 #else -#define L1_CACHE_BYTES 32 +#define L1_CACHE_SHIFT 5 #endif /* PPC64 */ #else -#define L1_CACHE_BYTES 16 -#endif /* !8xx || 8260 */ +#define L1_CACHE_SHIFT 4 +#endif /* !(8xx || IOP480) */ + +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) + +/* + * For compatibility reasons support the CFG_CACHELINE_SIZE too + */ +#ifndef CFG_CACHELINE_SIZE +#define CFG_CACHELINE_SIZE L1_CACHE_BYTES +#endif #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) #define L1_CACHE_PAGES 8 @@ -35,6 +44,8 @@ extern void flush_dcache_range(unsigned long start, unsigned long stop); extern void clean_dcache_range(unsigned long start, unsigned long stop); extern void invalidate_dcache_range(unsigned long start, unsigned long stop); +extern void flush_dcache(void); +extern void invalidate_dcache(void); #ifdef CFG_INIT_RAM_LOCK extern void unlock_ram_in_cache(void); #endif /* CFG_INIT_RAM_LOCK */ diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index 4676e2c408..05aee74949 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -107,6 +107,9 @@ typedef struct global_data { unsigned int dp_alloc_base; unsigned int dp_alloc_top; #endif +#if defined(CONFIG_4xx) + u32 uart_clk; +#endif /* CONFIG_4xx */ #if defined(CFG_GT_6426x) unsigned int mirror_hack[16]; #endif diff --git a/include/asm-ppc/gpio.h b/include/asm-ppc/gpio.h index c9b6a36b4f..d0c3eba884 100644 --- a/include/asm-ppc/gpio.h +++ b/include/asm-ppc/gpio.h @@ -21,6 +21,9 @@ * MA 02111-1307 USA */ +#ifndef __ASM_PPC_GPIO_H +#define __ASM_PPC_GPIO_H + /* 4xx PPC's have 2 GPIO controllers */ #if defined(CONFIG_405EZ) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ @@ -30,6 +33,36 @@ #define GPIO_GROUP_MAX 1 #endif +/* Offsets */ +#define GPIOx_OR 0x00 /* GPIO Output Register */ +#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */ +#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */ +#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */ +#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */ +#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */ +#define GPIOx_ODR 0x18 /* GPIO Open drain Register */ +#define GPIOx_IR 0x1C /* GPIO Input Register */ +#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */ +#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */ +#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */ +#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */ +#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */ +#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */ +#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */ +#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */ +#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */ + +#define GPIO_OR(x) (x+GPIOx_OR) /* GPIO Output Register */ +#define GPIO_TCR(x) (x+GPIOx_TCR) /* GPIO Three-State Control Register */ +#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Select Register High or Low */ +#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */ +#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */ +#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */ +#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */ + +#define GPIO0 0 +#define GPIO1 1 + #define GPIO_MAX 32 #define GPIO_ALT1_SEL 0x40000000 #define GPIO_ALT2_SEL 0x80000000 @@ -56,3 +89,5 @@ void gpio_config(int pin, int in_out, int gpio_alt, int out_val); void gpio_write_bit(int pin, int val); int gpio_read_out_bit(int pin); void gpio_set_chip_configuration(void); + +#endif /* __ASM_PPC_GPIO_H */ diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index b3cfa9b372..edcb3b9ca3 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -648,6 +648,7 @@ unsigned long mftlb3(unsigned long index); void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); void remove_tlb(u32 vaddr, u32 size); +void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_440 */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 0a160e2513..f58b38aace 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -91,6 +91,11 @@ /* Special Purpose Registers (SPRNs)*/ +/* PPC440 Architecture is BOOK-E */ +#ifdef CONFIG_440 +#define CONFIG_BOOKE +#endif + #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ #define SPRN_CTR 0x009 /* Count Register */ #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ @@ -765,6 +770,10 @@ #define PVR_405EP_RA 0x51210950 #define PVR_405GPR_RB 0x50910951 #define PVR_405EZ_RA 0x41511460 +#define PVR_405EXR1_RA 0x12911473 /* 405EXr rev A with Security */ +#define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A without Security */ +#define PVR_405EX1_RA 0x12911477 /* 405EX rev A with Security */ +#define PVR_405EX2_RA 0x12911475 /* 405EX rev A without Security */ #define PVR_440GP_RB 0x40120440 #define PVR_440GP_RC 0x40120481 #define PVR_440EP_RA 0x42221850 diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h index 464f6b5756..bd9b6f70dd 100644 --- a/include/asm-ppc/u-boot.h +++ b/include/asm-ppc/u-boot.h @@ -84,6 +84,7 @@ typedef struct bd_info { defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || \ defined(CONFIG_405EZ) || \ + defined(CONFIG_405EX) || \ defined(CONFIG_440) unsigned char bi_s_version[4]; /* Version of this structure */ unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */ |