summaryrefslogtreecommitdiff
path: root/include/configs/B4860QDS.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/configs/B4860QDS.h')
-rw-r--r--include/configs/B4860QDS.h7
1 files changed, 1 insertions, 6 deletions
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 7d3ebf33c7..3ad9f80ce1 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -50,9 +50,6 @@
#endif
/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500 /* BOOKE e500 family */
-#define CONFIG_E500MC /* BOOKE e500mc family */
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_MP /* support multiple processors */
@@ -65,7 +62,7 @@
#endif
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_FSL_IFC /* Enable IFC Support */
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
#define CONFIG_PCIE1 /* PCIE controller 1 */
@@ -225,13 +222,11 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_SYS_FSL_DDR3
#ifndef CONFIG_SPL_BUILD
#define CONFIG_FSL_DDR_INTERACTIVE
#endif