diff options
Diffstat (limited to 'include/configs')
58 files changed, 1451 insertions, 944 deletions
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 275d4f2af6..c28dfe0068 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -52,7 +52,7 @@ #define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */ #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 #define CONFIG_SPL_MAX_SIZE (4 * 1024) -#define CONFIG_SPL_PAD_TO 0xfff04000 +#define CONFIG_SPL_PAD_TO 0x4000 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 diff --git a/include/configs/PCIPPC2.h b/include/configs/PCIPPC2.h deleted file mode 100644 index 90cee881ae..0000000000 --- a/include/configs/PCIPPC2.h +++ /dev/null @@ -1,251 +0,0 @@ -/* - * (C) Copyright 2002-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * - * Configuration settings for the PCIPPC-2 board. - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_PREBOOT "" -#define CONFIG_BOOTDELAY 5 - -#ifndef __ASSEMBLY__ -#include <galileo/core.h> -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BSP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SNTP - -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size - */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -#define CONFIG_SYS_MAXARGS 64 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFF00000 -#define CONFIG_SYS_FLASH_MAX_SIZE 0x00100000 -/* Maximum amount of RAM. - */ -#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 /* 512Mb */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_SDRAM_BASE && \ - CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_INIT_RAM_LOCK - -/* - * Temporary buffer for serial data until the real serial driver - * is initialised (memtest will destroy this buffer) - */ -#define CONFIG_SYS_SCONSOLE_ADDR CONFIG_SYS_INIT_RAM_ADDR -#define CONFIG_SYS_SCONSOLE_SIZE 0x0002000 - -/* SDRAM 0 - 256MB - */ -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT0U (CONFIG_SYS_SDRAM_BASE | \ - BATU_BL_256M | BATU_VS | BATU_VP) -/* SDRAM 1 - 256MB - */ -#define CONFIG_SYS_DBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \ - BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \ - BATU_BL_256M | BATU_VS | BATU_VP) - -/* Init RAM in the CPU DCache (no backing memory) - */ -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_INIT_RAM_ADDR | \ - BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_INIT_RAM_ADDR | \ - BATU_BL_128K | BATU_VS | BATU_VP) - -/* I/O and PCI memory at 0xf0000000 - */ -#define CONFIG_SYS_DBAT3L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT0L CONFIG_SYS_DBAT0L -#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U -#define CONFIG_SYS_IBAT1L CONFIG_SYS_DBAT1L -#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U -#define CONFIG_SYS_IBAT2L CONFIG_SYS_DBAT2L -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U -#define CONFIG_SYS_IBAT3L CONFIG_SYS_DBAT3L -#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the PCIPPC2 user's manual. - */ -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_BUS_CLK 100000000 /* bus speed - 100 mhz */ -#define CONFIG_SYS_CPU_CLK 300000000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 16 /* Max number of sectors in one bank */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -/* - * Note: environment is not EMBEDDED in the U-Boot code. - * It's stored in flash separately. - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x70000) -#define CONFIG_ENV_SIZE 0x1000 /* Size of the Environment */ -#define CONFIG_ENV_SECT_SIZE 0x10000 /* Size of the Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * L2 cache - */ -#undef CONFIG_SYS_L2 -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -/*----------------------------------------------------------------------- - RTC m48t59 -*/ -#define CONFIG_RTC_MK48T59 - -#define CONFIG_WATCHDOG - - -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_TULIP - -#endif /* __CONFIG_H */ diff --git a/include/configs/PCIPPC6.h b/include/configs/PCIPPC6.h deleted file mode 100644 index 10b81c1a7f..0000000000 --- a/include/configs/PCIPPC6.h +++ /dev/null @@ -1,265 +0,0 @@ -/* - * (C) Copyright 2002-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * - * Configuration settings for the PCIPPC-6 board. - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_PREBOOT "" -#define CONFIG_BOOTDELAY 5 - -#ifndef __ASSEMBLY__ -#include <galileo/core.h> -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BSP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SCSI -#define CONFIG_CMD_SNTP - - -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size - */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -#define CONFIG_SYS_MAXARGS 64 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFF00000 -#define CONFIG_SYS_FLASH_MAX_SIZE 0x00100000 -/* Maximum amount of RAM. - */ -#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 /* 512Mb */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_SDRAM_BASE && \ - CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_INIT_RAM_LOCK - -/* - * Temporary buffer for serial data until the real serial driver - * is initialised (memtest will destroy this buffer) - */ -#define CONFIG_SYS_SCONSOLE_ADDR CONFIG_SYS_INIT_RAM_ADDR -#define CONFIG_SYS_SCONSOLE_SIZE 0x0002000 - -/* SDRAM 0 - 256MB - */ -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT0U (CONFIG_SYS_SDRAM_BASE | \ - BATU_BL_256M | BATU_VS | BATU_VP) -/* SDRAM 1 - 256MB - */ -#define CONFIG_SYS_DBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \ - BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \ - BATU_BL_256M | BATU_VS | BATU_VP) - -/* Init RAM in the CPU DCache (no backing memory) - */ -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_INIT_RAM_ADDR | \ - BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_INIT_RAM_ADDR | \ - BATU_BL_128K | BATU_VS | BATU_VP) - -/* I/O and PCI memory at 0xf0000000 - */ -#define CONFIG_SYS_DBAT3L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT0L CONFIG_SYS_DBAT0L -#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U -#define CONFIG_SYS_IBAT1L CONFIG_SYS_DBAT1L -#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U -#define CONFIG_SYS_IBAT2L CONFIG_SYS_DBAT2L -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U -#define CONFIG_SYS_IBAT3L CONFIG_SYS_DBAT3L -#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the PCIPPC2 user's manual. - */ -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_BUS_CLK 100000000 /* bus speed - 100 mhz */ -#define CONFIG_SYS_CPU_CLK 300000000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 16 /* Max number of sectors in one bank */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -/* - * Note: environment is not EMBEDDED in the U-Boot code. - * It's stored in flash separately. - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x70000) -#define CONFIG_ENV_SIZE 0x1000 /* Size of the Environment */ -#define CONFIG_ENV_SECT_SIZE 0x10000 /* Size of the Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * L2 cache - */ -#undef CONFIG_SYS_L2 -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -/*----------------------------------------------------------------------- - RTC m48t59 -*/ -#define CONFIG_RTC_MK48T59 - -#define CONFIG_WATCHDOG - - -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_TULIP - - -#define CONFIG_SCSI_SYM53C8XX -#define CONFIG_SCSI_DEV_ID 0x000B /* 53c896 */ -#define CONFIG_SYS_SCSI_MAX_LUN 8 /* number of supported LUNs */ -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 15 /* maximum SCSI ID (0..6) */ -#define CONFIG_SYS_SCSI_MAX_DEVICE CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN /* maximum Target devices */ -#define CONFIG_SYS_SCSI_SPIN_UP_TIME 2 -#define CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 0 -#define CONFIG_DOS_PARTITION -#define CONFIG_MAC_PARTITION -#define CONFIG_ISO_PARTITION - -#endif /* __CONFIG_H */ diff --git a/include/configs/R360MPI.h b/include/configs/R360MPI.h index 868a0b8044..60cccffc45 100644 --- a/include/configs/R360MPI.h +++ b/include/configs/R360MPI.h @@ -39,6 +39,7 @@ #define CONFIG_SYS_TEXT_BASE 0x40000000 #define CONFIG_LCD +#define CONFIG_MPC8XX_LCD #undef CONFIG_EDT32F10 #define CONFIG_SHARP_LQ057Q3DC02 diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h index b042c67020..d4bcc62e45 100644 --- a/include/configs/RBC823.h +++ b/include/configs/RBC823.h @@ -47,6 +47,7 @@ #endif #define CONFIG_KEYBOARD 1 /* This board has a custom keybpard */ #define CONFIG_LCD 1 /* use LCD controller ... */ +#define CONFIG_MPC8XX_LCD #define CONFIG_HITACHI_SP19X001_Z1A /* The LCD type we use */ #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ diff --git a/include/configs/RPXlite_DW.h b/include/configs/RPXlite_DW.h index 67ab1e962b..d8e28d5ea9 100644 --- a/include/configs/RPXlite_DW.h +++ b/include/configs/RPXlite_DW.h @@ -54,6 +54,7 @@ #define CONFIG_SYS_TEXT_BASE 0xff000000 #ifdef CONFIG_LCD /* with LCD controller ? */ +#define CONFIG_MPC8XX_LCD #define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ #endif diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h index e2b22f0bae..e2ea016387 100644 --- a/include/configs/RRvision.h +++ b/include/configs/RRvision.h @@ -110,7 +110,9 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#ifndef CONFIG_LCD +#ifdef CONFIG_LCD +#define CONFIG_MPC8XX_LCD +#else #define CONFIG_VIDEO 1 /* To enable the video initialization */ /* Video related */ diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index 9fac5d15c7..cccf3afb62 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -39,6 +39,7 @@ #define CONFIG_SYS_TEXT_BASE 0x40000000 #ifdef CONFIG_LCD /* with LCD controller ? */ +#define CONFIG_MPC8XX_LCD #define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */ #define CONFIG_LCD_INFO 1 /* ... and some board info */ #define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index 932f158b2c..b2d1af0dd1 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -39,6 +39,7 @@ #define CONFIG_SYS_TEXT_BASE 0x40000000 #ifdef CONFIG_LCD /* with LCD controller ? */ +#define CONFIG_MPC8XX_LCD /* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */ #endif diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index fb7d922257..2b3d59f726 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -77,6 +77,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_BSP #define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_YAFFS #define CONFIG_BOARD_LATE_INIT diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h index df3b4ae90a..13f32267e9 100644 --- a/include/configs/a3m071.h +++ b/include/configs/a3m071.h @@ -26,15 +26,22 @@ #define CONFIG_MPC5200 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_A3M071 /* ... on A3M071 board */ -#define CONFIG_MPC5200_DDR /* ... use DDR RAM */ #define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */ +#define CONFIG_SPL_TARGET "u-boot-img.bin" + #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ #define CONFIG_MISC_INIT_R #define CONFIG_SYS_LOWBOOT /* Enable lowboot */ +#ifdef CONFIG_A4M2K +#define CONFIG_HOSTNAME a4m2k +#else +#define CONFIG_HOSTNAME a3m071 +#endif + /* * Serial console configuration */ @@ -50,9 +57,6 @@ #define CONFIG_CMD_BSP #define CONFIG_CMD_CACHE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_REGINFO @@ -61,7 +65,11 @@ */ #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ /* define for 66MHz speed - undef for 33MHz PCI clock speed */ +#ifdef CONFIG_A4M2K +#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 +#else #undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 +#endif /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT @@ -76,33 +84,10 @@ #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" /* - * I2C configuration - */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* - * RTC configuration - */ -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -/* * NOR flash configuration */ #define CONFIG_SYS_FLASH_BASE 0xfc000000 -#define CONFIG_SYS_FLASH_SIZE 0x01000000 +#define CONFIG_SYS_FLASH_SIZE 0x02000000 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) #define CONFIG_SYS_MAX_FLASH_BANKS 1 @@ -153,7 +138,11 @@ */ #define CONFIG_MPC5xxx_FEC #define CONFIG_MPC5xxx_FEC_MII100 +#ifdef CONFIG_A4M2K +#define CONFIG_PHY_ADDR 0x01 +#else #define CONFIG_PHY_ADDR 0x00 +#endif /* * GPIO configuration @@ -166,19 +155,28 @@ * 2 means fpga ok */ +#ifdef CONFIG_A4M2K +#define CONFIG_SYS_GPS_PORT_CONFIG 0x0005C805 +#else /* for failsave-level 0 - full failsave */ #define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C005 /* for failsave-level 1 - only digiboard ok */ #define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C005 /* for failsave-level 2 - all ok */ #define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C005 +#endif + +#define CONFIG_WDOG_GPIO_PIN GPIO_WKUP_7 +#if defined(CONFIG_A4M2K) && !defined(CONFIG_SPL_BUILD) +#define CONFIG_HW_WATCHDOG /* Use external HW-Watchdog */ +#endif /* * Configuration matrix * MSB LSB - * failsave 0 0x1005C005 00010000000001011100000001100101 ( full failsave ) - * failsave 1 0x1005C005 00010000000001011100000001100101 ( digib.-ver ok ) - * failsave 2 0x1005C005 00010000000001011100000001100101 ( all ok ) + * failsave 0 0x1005C005 00010000000001011100000000000101 ( full failsave ) + * failsave 1 0x1005C005 00010000000001011100000000000101 ( digib.-ver ok ) + * failsave 2 0x1005C005 00010000000001011100000000000101 ( all ok ) * || ||| || | ||| | | | | * || ||| || | ||| | | | | bit rev name * ++-+++-++--+---+++-+---+---+---+- 0 31 CS1 @@ -254,30 +252,47 @@ #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE + +#ifdef CONFIG_A4M2K +/* external MRAM */ +#define CONFIG_SYS_CS1_START 0xf1000000 +#define CONFIG_SYS_CS1_SIZE (512 << 10) /* 512KiB MRAM */ +#endif + #define CONFIG_SYS_CS2_START 0xe0000000 #define CONFIG_SYS_CS2_SIZE 0x00100000 -/* FPGA slave io (512kiB) - see ticket #66 */ +/* FPGA slave io (512kiB / 1MiB) - see ticket #66 */ #define CONFIG_SYS_CS3_START 0xE9000000 +#ifdef CONFIG_A4M2K +#define CONFIG_SYS_CS3_SIZE 0x00100000 +#else #define CONFIG_SYS_CS3_SIZE 0x00080000 +#endif /* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */ #define CONFIG_SYS_CS3_CFG 0x0032B900 +#ifndef CONFIG_A4M2K /* Diagnosis Interface - see ticket #63 */ #define CONFIG_SYS_CS4_START 0xEA000000 #define CONFIG_SYS_CS4_SIZE 0x00000001 /* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0002B900 */ #define CONFIG_SYS_CS4_CFG 0x0002B900 +#endif -/* FPGA master io (64kiB) - see ticket #66 */ +/* FPGA master io (64kiB / 1MiB) - see ticket #66 */ #define CONFIG_SYS_CS5_START 0xE8000000 +#ifdef CONFIG_A4M2K +#define CONFIG_SYS_CS5_SIZE 0x00100000 +#else #define CONFIG_SYS_CS5_SIZE 0x00010000 +#endif /* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */ #define CONFIG_SYS_CS5_CFG 0x0032B900 #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for pci_clk = 66 MHz */ #define CONFIG_SYS_BOOTCS_CFG 0x0006F900 -#define CONFIG_SYS_CS1_CFG 0x0004FB00 +#define CONFIG_SYS_CS1_CFG 0x0008FD00 #define CONFIG_SYS_CS2_CFG 0x0006F90C #else /* for pci_clk = 33 MHz */ #define CONFIG_SYS_BOOTCS_CFG 0x0002F900 @@ -311,17 +326,25 @@ #define CONFIG_SYS_OS_BASE 0xfc080000 #define CONFIG_SYS_FDT_BASE 0xfc060000 -#define xstr(s) str(s) -#define str(s) #s - #define CONFIG_EXTRA_ENV_SETTINGS \ + "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ "netdev=eth0\0" \ "verify=no\0" \ + "loadaddr=200000\0" \ + "kernel_addr=" __stringify(CONFIG_SYS_OS_BASE) "\0" \ + "kernel_addr_r=1000000\0" \ + "fdt_addr=" __stringify(CONFIG_SYS_FDT_BASE) "\0" \ + "fdt_addr_r=1800000\0" \ + "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ + "fdtfile=" __stringify(CONFIG_HOSTNAME) "/" \ + __stringify(CONFIG_HOSTNAME) ".dtb\0" \ + "rootpath=/opt/eldk-5.2.1/powerpc/" \ + "core-image-minimal-mtdutils-dropbear-generic\0" \ "consoledev=ttyPSC0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "mtdargs=setenv bootargs root=/dev/mtdblock4 rw rootfstype=jffs2\0"\ + "mtdargs=setenv bootargs root=/dev/mtdblock4 rw rootfstype=jffs2\0" \ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ @@ -332,18 +355,18 @@ "flash_mtd=run mtdargs addip addtty;" \ "bootm ${kernel_addr} - ${fdtaddr}\0" \ "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0" \ - "net_nfs=sleep 2; tftp ${loadaddr} ${bootfile};" \ - "tftp c00000 ${fdtfile};" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${fdt_addr_r} ${fdtfile};" \ "run nfsargs addip addtty;" \ - "bootm ${loadaddr} - c00000\0" \ - "load=tftp ${loadaddr} u-boot.bin\0" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME) \ + "/u-boot-img.bin\0" \ "update=protect off fc000000 fc03ffff; " \ - "era fc000000 fc03ffff; cp.b ${loadaddr} fc000000 40000\0"\ + "era fc000000 fc03ffff; cp.b ${loadaddr} fc000000 40000\0" \ "upd=run load;run update\0" \ - "fdtaddr=" xstr(CONFIG_SYS_FDT_BASE) "\0" \ - "fdtfile=dtbFile\0" \ - "kernel_addr=" xstr(CONFIG_SYS_OS_BASE) "\0" \ + "bootdelay=3\0" \ + "bootcmd=run net_nfs\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_mtd" @@ -353,6 +376,7 @@ */ #define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NOR_SUPPORT #define CONFIG_SPL_TEXT_BASE 0xfc000000 #define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/mpc5xxx" diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h new file mode 100644 index 0000000000..ac7e877388 --- /dev/null +++ b/include/configs/ac14xx.h @@ -0,0 +1,591 @@ +/* + * (C) Copyright 2009 Wolfgang Denk <wd@denx.de> + * (C) Copyright 2010 DAVE Srl <www.dave.eu> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * ifm AC14xx (MPC5121e based) board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_AC14XX 1 +/* + * Memory map for the ifm AC14xx board: + * + * 0x0000_0000-0x0FFF_FFFF DDR RAM (256 MB) + * 0x3000_0000-0x3001_FFFF On Chip SRAM (128 KB) + * 0x8000_0000-0x803F_FFFF IMMR (4 MB) + * 0xE000_0000-0xEFFF_FFFF several LPB attached hardware (CSx) + * 0xFC00_0000-0xFFFF_FFFF NOR Boot FLASH (64 MB) + */ + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ +#define CONFIG_MPC512X 1 /* MPC512X family */ + +#define CONFIG_SYS_TEXT_BASE 0xFFF00000 + +#if defined(CONFIG_VIDEO) +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#endif + +#define CONFIG_SYS_MPC512X_CLKIN 25000000 /* in Hz */ +#define SCFR1_IPS_DIV 2 +#define SCFR1_LPC_DIV 2 +#define SCFR1_NFC_DIV 2 +#define SCFR1_DIU_DIV 240 + +#define CONFIG_MISC_INIT_R + +#define CONFIG_SYS_IMMR 0x80000000 +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR + 0x2100) + +/* more aggressive 'mtest' over a wider address range */ +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x0FE00000 + +/* + * DDR Setup - manually set all parameters as there's no SPD etc. + */ +#define CONFIG_SYS_DDR_SIZE 256 /* MB */ +#define CONFIG_SYS_DDR_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 + +/* + * DDR Controller Configuration XXX TODO + * + * SYS_CFG: + * [31:31] MDDRC Soft Reset: Diabled + * [30:30] DRAM CKE pin: Enabled + * [29:29] DRAM CLK: Enabled + * [28:28] Command Mode: Enabled (For initialization only) + * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] + * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] + * [20:19] Read Test: DON'T USE + * [18:18] Self Refresh: Enabled + * [17:17] 16bit Mode: Disabled + * [16:13] Ready Delay: 2 + * [12:12] Half DQS Delay: Disabled + * [11:11] Quarter DQS Delay: Disabled + * [10:08] Write Delay: 2 + * [07:07] Early ODT: Disabled + * [06:06] On DIE Termination: Disabled + * [05:05] FIFO Overflow Clear: DON'T USE here + * [04:04] FIFO Underflow Clear: DON'T USE here + * [03:03] FIFO Overflow Pending: DON'T USE here + * [02:02] FIFO Underlfow Pending: DON'T USE here + * [01:01] FIFO Overlfow Enabled: Enabled + * [00:00] FIFO Underflow Enabled: Enabled + * TIME_CFG0 + * [31:16] DRAM Refresh Time: 0 CSB clocks + * [15:8] DRAM Command Time: 0 CSB clocks + * [07:00] DRAM Precharge Time: 0 CSB clocks + * TIME_CFG1 + * [31:26] DRAM tRFC: + * [25:21] DRAM tWR1: + * [20:17] DRAM tWRT1: + * [16:11] DRAM tDRR: + * [10:05] DRAM tRC: + * [04:00] DRAM tRAS: + * TIME_CFG2 + * [31:28] DRAM tRCD: + * [27:23] DRAM tFAW: + * [22:19] DRAM tRTW1: + * [18:15] DRAM tCCD: + * [14:10] DRAM tRTP: + * [09:05] DRAM tRP: + * [04:00] DRAM tRPA + */ + +/* + * NOTE: although this board uses DDR1 only, the common source brings defaults + * for DDR2 init sequences, that's why we have to keep those here as well + */ + +/* DDR1 -- 32bit, drive strength (pad configuration) 3 for control and data */ +#define CONFIG_SYS_IOCTRL_MUX_DDR ((0 << 6) | (3 << 3) | (3 << 0)) + +#define CONFIG_SYS_MDDRC_SYS_CFG (/* 0xEAA09100 */ 0 \ + | (1 << 31) /* RST_B */ \ + | (1 << 30) /* CKE */ \ + | (1 << 29) /* CLK_ON */ \ + | (0 << 28) /* CMD_MODE */ \ + | (5 << 25) /* DRAM_ROW_SELECT */ \ + | (5 << 21) /* DRAM_BANK_SELECT */ \ + | (0 << 18) /* SELF_REF_EN */ \ + | (0 << 17) /* 16BIT_MODE */ \ + | (4 << 13) /* RDLY */ \ + | (1 << 12) /* HALF_DQS_DLY */ \ + | (0 << 11) /* QUART_DQS_DLY */ \ + | (1 << 8) /* WDLY */ \ + | (0 << 7) /* EARLY_ODT */ \ + | (0 << 6) /* ON_DIE_TERMINATE */ \ + | (0 << 5) /* FIFO_OV_CLEAR */ \ + | (0 << 4) /* FIFO_UV_CLEAR */ \ + | (0 << 1) /* FIFO_OV_EN */ \ + | (0 << 0) /* FIFO_UV_EN */ \ + ) + +#define CONFIG_SYS_MDDRC_TIME_CFG0 0x04E03124 +#define CONFIG_SYS_MDDRC_TIME_CFG1 0x30CA1147 +#define CONFIG_SYS_MDDRC_TIME_CFG2 0x32B10864 + +/* register address only, i.e. template without values */ +#define CONFIG_SYS_MICRON_BMODE 0x01000000 +#define CONFIG_SYS_MICRON_EMODE 0x01010000 +#define CONFIG_SYS_MICRON_EMODE2 0x01020000 +#define CONFIG_SYS_MICRON_EMODE3 0x01030000 +/* + * values for mode registers (without mode register address) + */ +/* CAS 2.5 (6), burst seq (0) and length 4 (2) */ +#define CONFIG_SYS_MICRON_BMODE_PARAM 0x00000062 +#define CONFIG_SYS_MICRON_BMODE_RSTDLL 0x00000100 +/* DLL enable, reduced drive strength */ +#define CONFIG_SYS_MICRON_EMODE_PARAM 0x00000002 + +#define CONFIG_SYS_DDRCMD_NOP 0x01380000 +#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 +#define CONFIG_SYS_MICRON_EMR ((1 << 24) | /* CMD_REQ */ \ + (0 << 22) | /* DRAM_CS */ \ + (0 << 21) | /* DRAM_RAS */ \ + (0 << 20) | /* DRAM_CAS */ \ + (0 << 19) | /* DRAM_WEB */ \ + (1 << 16) | /* DRAM_BS[2:0] */ \ + (0 << 15) | /* */ \ + (0 << 12) | /* A12->out */ \ + (0 << 11) | /* A11->RDQS */ \ + (0 << 10) | /* A10->DQS# */ \ + (0 << 7) | /* OCD program */ \ + (0 << 6) | /* Rtt1 */ \ + (0 << 3) | /* posted CAS# */ \ + (0 << 2) | /* Rtt0 */ \ + (1 << 1) | /* ODS */ \ + (0 << 0) /* DLL */ \ + ) +#define CONFIG_SYS_MICRON_EMR2 0x01020000 +#define CONFIG_SYS_MICRON_EMR3 0x01030000 +#define CONFIG_SYS_DDRCMD_RFSH 0x01080000 +#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 +#define CONFIG_SYS_MICRON_EMR_OCD ((1 << 24) | /* CMD_REQ */ \ + (0 << 22) | /* DRAM_CS */ \ + (0 << 21) | /* DRAM_RAS */ \ + (0 << 20) | /* DRAM_CAS */ \ + (0 << 19) | /* DRAM_WEB */ \ + (1 << 16) | /* DRAM_BS[2:0] */ \ + (0 << 15) | /* */ \ + (0 << 12) | /* A12->out */ \ + (0 << 11) | /* A11->RDQS */ \ + (1 << 10) | /* A10->DQS# */ \ + (7 << 7) | /* OCD program */ \ + (0 << 6) | /* Rtt1 */ \ + (0 << 3) | /* posted CAS# */ \ + (1 << 2) | /* Rtt0 */ \ + (0 << 1) | /* ODS */ \ + (0 << 0) /* DLL */ \ + ) + +/* + * Backward compatible definitions, + * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c + */ +#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2) +#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3) +#define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR) +#define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD) + +/* DDR Priority Manager Configuration */ +#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 +#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 +#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 +#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC +#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA +#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 +#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 +#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 +#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 +#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 +#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 +#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 +#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa +#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa +#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 +#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 +#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 + +/* + * NOR FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_CFI /* use the CFI code */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size */ + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_FLASH_BANKS_LIST { \ + CONFIG_SYS_FLASH_BASE + 0 * CONFIG_SYS_FLASH_SIZE, \ + } +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_PROTECTION + +/* + * SRAM support + */ +#define CONFIG_SYS_SRAM_BASE 0x30000000 +#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ + +/* + * CS related parameters + * TODO document these + */ +/* CS0 Flash */ +#define CONFIG_SYS_CS0_CFG 0x00031110 +#define CONFIG_SYS_CS0_START 0xFC000000 +#define CONFIG_SYS_CS0_SIZE 0x04000000 +/* CS1 FRAM */ +#define CONFIG_SYS_CS1_CFG 0x00011000 +#define CONFIG_SYS_CS1_START 0xE0000000 +#define CONFIG_SYS_CS1_SIZE 0x00010000 +/* CS2 AS-i 1 */ +#define CONFIG_SYS_CS2_CFG 0x00009100 +#define CONFIG_SYS_CS2_START 0xE0100000 +#define CONFIG_SYS_CS2_SIZE 0x00080000 +/* CS3 netX */ +#define CONFIG_SYS_CS3_CFG 0x000A1140 +#define CONFIG_SYS_CS3_START 0xE0300000 +#define CONFIG_SYS_CS3_SIZE 0x00020000 +/* CS5 safety */ +#define CONFIG_SYS_CS5_CFG 0x0011F000 +#define CONFIG_SYS_CS5_START 0xE0400000 +#define CONFIG_SYS_CS5_SIZE 0x00010000 +/* CS6 AS-i 2 */ +#define CONFIG_SYS_CS6_CFG 0x00009100 +#define CONFIG_SYS_CS6_START 0xE0200000 +#define CONFIG_SYS_CS6_SIZE 0x00080000 + +/* Don't use alternative CS timing for any CS */ +#define CONFIG_SYS_CS_ALETIMING 0x00000000 +#define CONFIG_SYS_CS_BURST 0x00000000 +#define CONFIG_SYS_CS_DEADCYCLE 0x00000020 +#define CONFIG_SYS_CS_HOLDCYCLE 0x00000020 + +/* Use SRAM for initial stack */ +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE +#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE + +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) + +#ifdef CONFIG_FSL_DIU_FB +#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) +#else +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) +#endif + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */ +#define CONFIG_SYS_PSC3 +#if CONFIG_PSC_CONSOLE != 3 +#error CONFIG_PSC_CONSOLE must be 3 +#endif + +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE +#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR +#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE +#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR + +/* + * Clocks in use + */ +#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ + CLOCK_SCCR1_LPC_EN | \ + CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ + CLOCK_SCCR1_PSC_EN(7) | \ + CLOCK_SCCR1_PSCFIFO_EN | \ + CLOCK_SCCR1_DDR_EN | \ + CLOCK_SCCR1_FEC_EN | \ + CLOCK_SCCR1_TPR_EN) + +#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ + CLOCK_SCCR2_SPDIF_EN | \ + CLOCK_SCCR2_DIU_EN | \ + CLOCK_SCCR2_I2C_EN) + + +#define CONFIG_CMDLINE_EDITING 1 /* command line history */ + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_I2C_MULTI_BUS + +/* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0x7F + +/* + * EEPROM configuration for Atmel AT24C01: + * 8-bit addresses, 30ms write delay, 32-Byte Page Write Mode + */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 30 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 + +/* + * Ethernet configuration + */ +#define CONFIG_MPC512x_FEC 1 +#define CONFIG_NET_MULTI +#define CONFIG_PHY_ADDR 0x1F +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_FEC_AN_TIMEOUT 1 +#define CONFIG_HAS_ETH0 + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +/* This has to be a multiple of the flash sector size */ +#define CONFIG_ENV_ADDR 0xFFF40000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#define CONFIG_LOADS_ECHO 1 +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 + +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#undef CONFIG_CMD_FUSE +#define CONFIG_CMD_I2C +#undef CONFIG_CMD_IDE +#undef CONFIG_CMD_EXT2 +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +#if defined(CONFIG_PCI) +#define CONFIG_CMD_PCI +#endif + +#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_ISO_PARTITION +#endif /* defined(CONFIG_CMD_IDE) */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "ac14xx> " /* Monitor Command Prompt */ + +#ifdef CONFIG_CMD_KGDB +# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 32 +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* decrementer freq: 1ms ticks */ +#define CONFIG_SYS_HZ 1000 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* Cache Configuration */ +#define CONFIG_SYS_DCACHE_SIZE 32768 +#define CONFIG_SYS_CACHELINE_SIZE 32 +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of 32 */ +#endif + +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ICE) +#define CONFIG_SYS_HID2 HID2_HBE + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 +#define BOOTFLAG_WARM 0x02 + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_TIMESTAMP + +#define CONFIG_HOSTNAME ac14xx +#define CONFIG_BOOTFILE "ac14xx/uImage" +#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx" + +/* default load addr for tftp and bootm */ +#define CONFIG_LOADADDR 400000 + +#define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */ + +/* XXX TODO need to specify the builtin environment */ +#define CONFIG_PREBOOT "echo;" \ + "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo" + +#define CONFIG_EXTRA_ENV_SETTINGS_DEVEL \ + "muster_nr=00\0" \ + "fromram=run ramargs addip addtty; " \ + "tftp ${fdt_addr_r} k6m2/ac14xx.dtb-${muster_nr}; " \ + "tftp ${kernel_addr_r} k6m2/uImage-${muster_nr}; " \ + "tftp ${ramdisk_addr_r} k6m2/uFS-${muster_nr}; " \ + "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \ + "fromnfs=run nfsargs addip addtty; " \ + "tftp ${fdt_addr_r} k6m2/ac14xx.dtb-${muster_nr}; " \ + "tftp ${kernel_addr_r} k6m2/uImage-${muster_nr}; " \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "fromflash=run nfsargs addip addtty; " \ + "bootm fc020000 - fc000000\0" \ + "mtdargsrec=setenv bootargs root=/dev/mtdblock1 ro\0" \ + "recovery=run mtdargsrec addip addtty; " \ + "bootm ffd20000 - ffee0000\0" \ + "production=run ramargs addip addtty; " \ + "bootm fc020000 fc400000 fc000000\0" \ + "mtdargs=setenv bootargs root=/dev/mtdblock1 ro\0" \ + "prodmtd=run mtdargs addip addtty; " \ + "bootm fc020000 - fc000000\0" \ + "" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "u-boot_addr_r=200000\0" \ + "kernel_addr_r=600000\0" \ + "fdt_addr_r=a00000\0" \ + "ramdisk_addr_r=b00000\0" \ + "u-boot_addr=FFF00000\0" \ + "kernel_addr=FC020000\0" \ + "fdt_addr=FC000000\0" \ + "ramdisk_addr=FC400000\0" \ + "verify=n\0" \ + "ramdiskfile=ac14xx/uRamdisk\0" \ + "u-boot=ac14xx/u-boot.bin\0" \ + "bootfile=ac14xx/uImage\0" \ + "fdtfile=ac14xx/ac14xx.dtb\0" \ + "rootpath=/opt/eldk/ppc_6xx\n" \ + "netdev=eth0\0" \ + "consdev=ttyPSC0\0" \ + "hostname=ac14xx\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}-${muster_nr}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} " \ + "console=${consdev},${baudrate}\0" \ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${fdt_addr_r} ${fdtfile};" \ + "run nfsargs addip addtty;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "net_self=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ + "tftp ${fdt_addr_r} ${fdtfile};" \ + "run ramargs addip addtty;" \ + "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ + "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ + "update=protect off ${u-boot_addr} +${filesize};" \ + "era ${u-boot_addr} +${filesize};" \ + "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ + CONFIG_EXTRA_ENV_SETTINGS_DEVEL \ + "upd=run load update\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run production" + +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1 + +#define OF_CPU "PowerPC,5121@0" +#define OF_SOC_COMPAT "fsl,mpc5121-immr" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc@80000000/serial@11300" + +#endif /* __CONFIG_H */ diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 9eada95c04..ef00306a55 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -18,8 +18,7 @@ #define CONFIG_AM33XX -#include <asm/arch/cpu.h> -#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> #define CONFIG_DMA_COHERENT #define CONFIG_DMA_COHERENT_SIZE (1 << 20) @@ -40,6 +39,8 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG +#define CONFIG_SYS_CACHELINE_SIZE 64 + /* commands to include */ #include <config_cmd_default.h> @@ -56,13 +57,20 @@ "fdtaddr=0x80F80000\0" \ "fdt_high=0xffffffff\0" \ "rdaddr=0x81000000\0" \ - "bootfile=/boot/uImage\0" \ + "bootdir=/boot\0" \ + "bootfile=uImage\0" \ "fdtfile=\0" \ "console=ttyO0,115200n8\0" \ "optargs=\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "dfu_alt_info_mmc=" DFU_ALT_INFO_MMC "\0" \ + "dfu_alt_info_emmc=rawemmc mmc 0 3751936\0" \ + "dfu_alt_info_nand=" DFU_ALT_INFO_NAND "\0" \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 ro\0" \ "mmcrootfstype=ext4 rootwait\0" \ + "bootpart=0:2\0" \ "nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \ "nandrootfstype=ubifs rootwait=1\0" \ "nandsrcaddr=0x280000\0" \ @@ -96,19 +104,19 @@ "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ "ip=dhcp\0" \ "bootenv=uEnv.txt\0" \ - "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ "importbootenv=echo Importing environment from mmc ...; " \ "env import -t $loadaddr $filesize\0" \ "ramargs=setenv bootargs console=${console} " \ "${optargs} " \ "root=${ramroot} " \ "rootfstype=${ramrootfstype}\0" \ - "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ - "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \ - "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \ + "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ + "loaduimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ - "bootm ${loadaddr}\0" \ + "bootm ${loadaddr} - ${fdtaddr}\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ "nand read ${loadaddr} ${nandsrcaddr} ${nandimgsize}; " \ @@ -122,14 +130,17 @@ "setenv autoload no; " \ "dhcp; " \ "tftp ${loadaddr} ${bootfile}; " \ + "tftp ${fdtaddr} ${fdtfile}; " \ "run netargs; " \ - "bootm ${loadaddr}\0" \ + "bootm ${loadaddr} - ${fdtaddr}\0" \ "ramboot=echo Booting from ramdisk ...; " \ "run ramargs; " \ - "bootm ${loadaddr}\0" \ + "bootm ${loadaddr} ${rdaddr} ${fdtaddr}\0" \ "findfdt="\ "if test $board_name = A335BONE; then " \ "setenv fdtfile am335x-bone.dtb; fi; " \ + "if test $board_name = A335BNLT; then " \ + "setenv fdtfile am335x-boneblack.dtb; fi; " \ "if test $board_name = A33515BB; then " \ "setenv fdtfile am335x-evm.dtb; fi; " \ "if test $board_name = A335X_SK; then " \ @@ -138,6 +149,7 @@ #endif #define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "echo SD/MMC found on device ${mmcdev};" \ "if run loadbootenv; then " \ @@ -149,6 +161,7 @@ "run uenvcmd;" \ "fi;" \ "if run loaduimage; then " \ + "run loadfdt;" \ "run mmcboot;" \ "fi;" \ "else " \ @@ -161,8 +174,8 @@ #define CONFIG_CMD_ECHO -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 +/* We set the max number of command args high to avoid HUSH bugs. */ +#define CONFIG_SYS_MAXARGS 64 /* Console I/O Buffer Size */ #define CONFIG_SYS_CBSIZE 512 @@ -191,7 +204,10 @@ #define CONFIG_CMD_MMC #define CONFIG_DOS_PARTITION #define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE #define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FS_GENERIC #define CONFIG_SPI #define CONFIG_OMAP3_SPI @@ -201,6 +217,38 @@ #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED (24000000) +/* USB Composite download gadget - g_dnl */ +#define CONFIG_USB_GADGET +#define CONFIG_USBDOWNLOAD_GADGET + +/* USB TI's IDs */ +#define CONFIG_USBD_HS +#define CONFIG_G_DNL_VENDOR_NUM 0x0403 +#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00 +#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments" + +/* USB Device Firmware Update support */ +#define CONFIG_DFU_FUNCTION +#define CONFIG_DFU_MMC +#define CONFIG_DFU_NAND +#define CONFIG_CMD_DFU +#define DFU_ALT_INFO_MMC \ + "boot part 0 1;" \ + "rootfs part 0 2;" \ + "MLO fat 0 1;" \ + "MLO.raw mmc 100 100;" \ + "u-boot.img.raw mmc 300 3C0;" \ + "u-boot.img fat 0 1;" \ + "uEnv.txt fat 0 1" +#define DFU_ALT_INFO_NAND \ + "SPL part 0 1;" \ + "SPL.backup1 part 0 2;" \ + "SPL.backup2 part 0 3;" \ + "SPL.backup3 part 0 4;" \ + "u-boot part 0 5;" \ + "kernel part 0 7;" \ + "rootfs part 0 8" + /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ #define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ @@ -344,7 +392,9 @@ #define CONFIG_ARCH_MISC_INIT #define CONFIG_MUSB_GADGET #define CONFIG_MUSB_PIO_ONLY +#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT #define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 #define CONFIG_MUSB_HOST #define CONFIG_AM335X_USB0 #define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL @@ -416,6 +466,13 @@ /* NAND support */ #ifdef CONFIG_NAND #define CONFIG_CMD_NAND +#define CONFIG_CMD_MTDPARTS +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \ + "128k(SPL.backup1)," \ + "128k(SPL.backup2)," \ + "128k(SPL.backup3),1920k(u-boot)," \ + "128k(u-boot-env),5m(kernel),-(rootfs)" #define CONFIG_NAND_OMAP_GPMC #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */ diff --git a/include/configs/aria.h b/include/configs/aria.h index 0b31c50daf..b4253996a0 100644 --- a/include/configs/aria.h +++ b/include/configs/aria.h @@ -64,7 +64,6 @@ #define CONFIG_SYS_MPC512X_CLKIN 33000000 /* in Hz */ -#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R #define CONFIG_SYS_IMMR 0x80000000 @@ -266,11 +265,16 @@ #define CONFIG_SYS_ARIA_SRAM_BASE (CONFIG_SYS_SRAM_BASE + \ CONFIG_SYS_SRAM_SIZE) #define CONFIG_SYS_ARIA_SRAM_SIZE 0x00100000 /* reserve 1MB-window */ +#define CONFIG_SYS_CS6_START CONFIG_SYS_ARIA_SRAM_BASE +#define CONFIG_SYS_CS6_SIZE CONFIG_SYS_ARIA_SRAM_SIZE #define CONFIG_SYS_ARIA_FPGA_BASE (CONFIG_SYS_ARIA_SRAM_BASE + \ CONFIG_SYS_ARIA_SRAM_SIZE) #define CONFIG_SYS_ARIA_FPGA_SIZE 0x20000 /* 128 KB */ +#define CONFIG_SYS_CS2_START CONFIG_SYS_ARIA_FPGA_BASE +#define CONFIG_SYS_CS2_SIZE CONFIG_SYS_ARIA_FPGA_SIZE + #define CONFIG_SYS_CS0_CFG 0x05059150 #define CONFIG_SYS_CS2_CFG ( (5 << 24) | \ (5 << 16) | \ @@ -643,4 +647,21 @@ #define FSL_ATA_CTRL_DMA_WRITE 0x02000000 #define FSL_ATA_CTRL_IORDY_EN 0x01000000 +/* Clocks in use */ +#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ + CLOCK_SCCR1_LPC_EN | \ + CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ + CLOCK_SCCR1_PSCFIFO_EN | \ + CLOCK_SCCR1_DDR_EN | \ + CLOCK_SCCR1_FEC_EN | \ + CLOCK_SCCR1_NFC_EN | \ + CLOCK_SCCR1_PATA_EN | \ + CLOCK_SCCR1_PCI_EN | \ + CLOCK_SCCR1_TPR_EN) + +#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ + CLOCK_SCCR2_SPDIF_EN | \ + CLOCK_SCCR2_DIU_EN | \ + CLOCK_SCCR2_I2C_EN) + #endif /* __CONFIG_H */ diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index 55dc83da6a..6a99175211 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -60,7 +60,7 @@ #define CONFIG_SYS_MMC_ENV_PART 2 /* SPI */ -#define CONFIG_TEGRA_SLINK +#define CONFIG_TEGRA20_SLINK #define CONFIG_TEGRA_SLINK_CTRLS 6 #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_WINBOND diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 8d79ffd48a..726714dd21 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -344,5 +344,9 @@ #define LCD_BPP LCD_COLOR16 #define CONFIG_LCD +#define CONFIG_SPLASH_SCREEN +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_SPLASH_SCREEN_PREPARE #endif /* __CONFIG_H */ diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index 49f05decc0..a4aa8f7453 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -179,6 +179,8 @@ #define CONFIG_CMD_SAVEENV #define CONFIG_CMD_SETGETDCR #define CONFIG_CMD_SOURCE +#define CONFIG_CMD_TIME +#define CONFIG_CMD_GETTIME #define CONFIG_CMD_XIMG #define CONFIG_CMD_SCSI @@ -257,10 +259,16 @@ /*----------------------------------------------------------------------- * FLASH configuration */ +#define CONFIG_ICH_SPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SPI_FLASH_GIGADEVICE #define CONFIG_SYS_NO_FLASH -#undef CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_MAX_FLASH_SECT 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_CMD_SF +#define CONFIG_CMD_SF_TEST +#define CONFIG_CMD_SPI +#define CONFIG_SPI /*----------------------------------------------------------------------- * Environment configuration @@ -273,6 +281,23 @@ */ #define CONFIG_PCI +/*----------------------------------------------------------------------- + * USB configuration + */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_PCI +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 12 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL + +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX + +#define CONFIG_CMD_USB + #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_STD_DEVICES_SETTINGS diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index b1a6e34eba..7b68f7ca98 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -50,10 +50,31 @@ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_CMD_I2C -#define CONFIG_ENV_IS_NOWHERE +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET ((4096 * 1024) - CONFIG_ENV_SIZE) #define MACH_TYPE_DALMORE 4304 /* not yet in mach-types.h */ +/* SPI */ +#define CONFIG_TEGRA114_SPI +#define CONFIG_TEGRA114_SPI_CTRLS 6 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 10a493995f..28a306ba8e 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -28,6 +28,8 @@ #ifndef __CONFIG_DRA7XX_EVM_H #define __CONFIG_DRA7XX_EVM_H +#define CONFIG_ENV_IS_NOWHERE /* For now. */ + #include <configs/omap5_common.h> #define CONFIG_DRA7XX /* in a TI DRA7XX core */ diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index cabd2f2524..496a1947b2 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -33,6 +33,7 @@ #include <asm/arch/cpu.h> /* get chip and board defs */ +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_ARCH_CPU_INIT #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -45,6 +46,10 @@ /* Keep L2 Cache Disabled */ #define CONFIG_SYS_DCACHE_OFF +/* Enable ACE acceleration for SHA1 and SHA256 */ +#define CONFIG_EXYNOS_ACE_SHA +#define CONFIG_SHA_HW_ACCEL + #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define CONFIG_SYS_TEXT_BASE 0x43E00000 @@ -113,10 +118,16 @@ #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_CMD_NET +#define CONFIG_CMD_HASH #define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK +/* Thermal Management Unit */ +#define CONFIG_EXYNOS_TMU +#define CONFIG_CMD_DTT +#define CONFIG_TMU_CMD_DTT + /* USB */ #define CONFIG_CMD_USB #define CONFIG_USB_EHCI @@ -296,6 +307,7 @@ #ifdef CONFIG_CMD_SOUND #define CONFIG_SOUND #define CONFIG_I2S +#define CONFIG_SOUND_MAX98095 #define CONFIG_SOUND_WM8994 #endif @@ -318,4 +330,7 @@ #define LCD_BPP LCD_COLOR16 #endif +/* Enable Time Command */ +#define CONFIG_CMD_TIME + #endif /* __CONFIG_H */ diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index 559e3759de..1d8090bf6a 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -55,7 +55,8 @@ #define CONFIG_INITRD_TAG 1 #define CONFIG_REVISION_TAG 1 -#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ /* * NS16550 Configuration @@ -68,9 +69,6 @@ #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -/* define to avoid U-Boot to hang while waiting for TEMT */ -#define CONFIG_SYS_NS16550_BROKEN_TEMT - /* select serial console configuration */ #define CONFIG_CONS_INDEX 3 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h index 564b418fa7..905b279ab6 100644 --- a/include/configs/integrator-common.h +++ b/include/configs/integrator-common.h @@ -41,6 +41,7 @@ #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_OF_LIBFDT /* enable passing a Device Tree */ #define CONFIG_MISC_INIT_R /* call misc_init_r during start up */ /* diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index 796f33080d..3b15c4e691 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -24,10 +24,6 @@ #ifndef __CONFIG_KEYMILE_H #define __CONFIG_KEYMILE_H -/* Do boardspecific init for all boards */ -#define CONFIG_BOARD_EARLY_INIT_R -#define CONFIG_LAST_STAGE_INIT - #define CONFIG_BOOTCOUNT_LIMIT /* diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h index bd5bdbcb48..b84f12dbeb 100644 --- a/include/configs/km/km-powerpc.h +++ b/include/configs/km/km-powerpc.h @@ -24,6 +24,10 @@ #ifndef __CONFIG_KEYMILE_POWERPC_H #define __CONFIG_KEYMILE_POWERPC_H +/* Do boardspecific init for all boards */ +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_LAST_STAGE_INIT + #define CONFIG_BOOTCOUNT_LIMIT #define CONFIG_CMD_DTT diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 549278d8b0..766d76e188 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -50,6 +50,9 @@ #define CONFIG_MACH_TYPE MACH_TYPE_KM_KIRKWOOD +#define CONFIG_NAND_ECC_BCH +#define CONFIG_BCH + /* include common defines/options for all Keymile boards */ #include "keymile-common.h" @@ -320,6 +323,6 @@ int get_scl(void); #define CONFIG_CMD_DIAG /* we do the whole PCIe FPGA config stuff here */ -#define BOARD_LATE_INIT +#define CONFIG_BOARD_LATE_INIT #endif /* _CONFIG_KM_ARM_H */ diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index 762cc10b88..83bb7aad3d 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -98,6 +98,14 @@ #define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ #define CONFIG_KM_PIGGY4_88E6061 +/* KM_SUV31 */ +#elif defined(CONFIG_KM_SUV31) +#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ +#define CONFIG_IDENT_STRING "\nKeymile SUV31" +#define CONFIG_HOSTNAME kmsuv31 +#define CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_KM_FPGA_CONFIG + #else #error ("Board unsupported") #endif diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h index 5886a155dc..b99a05690e 100644 --- a/include/configs/lubbock.h +++ b/include/configs/lubbock.h @@ -38,6 +38,7 @@ #define CONFIG_LUBBOCK 1 /* on an LUBBOCK Board */ #define CONFIG_LCD 1 #ifdef CONFIG_LCD +#define CONFIG_PXA_LCD #define CONFIG_SHARP_LM8V31 #endif #define CONFIG_MMC diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h index df4978161e..3c02b73d8b 100644 --- a/include/configs/lwmon.h +++ b/include/configs/lwmon.h @@ -54,6 +54,7 @@ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ #define CONFIG_LCD 1 /* use LCD controller ... */ +#define CONFIG_MPC8XX_LCD #define CONFIG_HLD1045 1 /* ... with a HLD1045 display */ #define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */ diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h index cafc273c8c..af302573e6 100644 --- a/include/configs/mecp5123.h +++ b/include/configs/mecp5123.h @@ -191,6 +191,10 @@ #define CONFIG_SYS_SRAM_BASE 0x30000000 #define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ +/* Initialize Local Window for NOR FLASH access */ +#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE + /* ALE active low, data size 4bytes */ #define CONFIG_SYS_CS0_CFG 0x05051150 @@ -201,6 +205,9 @@ #define CONFIG_SYS_CS1_CFG 0x1f1f3090 #define CONFIG_SYS_VPC3_BASE 0x82000000 /* start of VPC3 space */ #define CONFIG_SYS_VPC3_SIZE 0x00010000 /* max VPC3 size */ +/* Initialize Local Window for VPC3 access */ +#define CONFIG_SYS_CS1_START CONFIG_SYS_VPC3_BASE +#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_VPC3_SIZE /* Use SRAM for initial stack */ #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Init RAM addr */ @@ -235,6 +242,23 @@ #define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR +/* + * Clocks in use + */ +#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ + CLOCK_SCCR1_LPC_EN | \ + CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ + CLOCK_SCCR1_PSCFIFO_EN | \ + CLOCK_SCCR1_DDR_EN | \ + CLOCK_SCCR1_FEC_EN | \ + CLOCK_SCCR1_NFC_EN | \ + CLOCK_SCCR1_PCI_EN | \ + CLOCK_SCCR1_TPR_EN) + +#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ + CLOCK_SCCR2_I2C_EN) + + #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ /* Use the HUSH parser */ #define CONFIG_SYS_HUSH_PARSER diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index 3f55d354ef..6e6af62cca 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -258,6 +258,8 @@ */ #define CONFIG_SYS_CPLD_BASE 0x82000000 #define CONFIG_SYS_CPLD_SIZE 0x00010000 /* 64 KB */ +#define CONFIG_SYS_CS2_START CONFIG_SYS_CPLD_BASE +#define CONFIG_SYS_CS2_SIZE CONFIG_SYS_CPLD_SIZE #define CONFIG_SYS_SRAM_BASE 0x30000000 #define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ @@ -310,6 +312,27 @@ #endif /* + * Clocks in use + */ +#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ + CLOCK_SCCR1_DDR_EN | \ + CLOCK_SCCR1_FEC_EN | \ + CLOCK_SCCR1_LPC_EN | \ + CLOCK_SCCR1_NFC_EN | \ + CLOCK_SCCR1_PATA_EN | \ + CLOCK_SCCR1_PCI_EN | \ + CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ + CLOCK_SCCR1_PSCFIFO_EN | \ + CLOCK_SCCR1_TPR_EN) + +#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \ + CLOCK_SCCR2_I2C_EN | \ + CLOCK_SCCR2_MEM_EN | \ + CLOCK_SCCR2_SPDIF_EN | \ + CLOCK_SCCR2_USB1_EN | \ + CLOCK_SCCR2_USB2_EN) + +/* * PCI */ #ifdef CONFIG_PCI diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 34e429577e..1754595850 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -45,7 +45,16 @@ #define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS -#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CONFIG_SPL +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" +#define CONFIG_SPL_MAX_SIZE 2048 +#define CONFIG_SPL_NAND_SUPPORT + +#define CONFIG_SPL_TEXT_BASE 0x87dc0000 +#define CONFIG_SYS_TEXT_BASE 0x87e00000 + +#ifndef CONFIG_SPL_BUILD #define CONFIG_SKIP_LOWLEVEL_INIT #endif @@ -60,8 +69,6 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE -#define CONFIG_HW_WATCHDOG -#define CONFIG_IMX_WATCHDOG #define CONFIG_MXC_GPIO #define CONFIG_HARD_SPI @@ -116,7 +123,7 @@ "bootcmd=run bootcmd_net\0" \ "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \ "tftpboot 0x81000000 uImage-mx31; bootm\0" \ - "prg_uboot=tftpboot 0x81000000 u-boot-nand.bin; " \ + "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \ "nand erase 0x0 0x40000; " \ "nand write 0x81000000 0x0 0x40000\0" @@ -163,7 +170,7 @@ #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_GBL_DATA_OFFSET) + CONFIG_SYS_INIT_RAM_SIZE) /*----------------------------------------------------------------------- * FLASH and environment organization @@ -189,10 +196,10 @@ /* NAND configuration for the NAND_SPL */ /* Start copying real U-boot from the second page */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800 /* Load U-Boot to this address */ -#define CONFIG_SYS_NAND_U_BOOT_DST 0x87f00000 +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index 62cb42bc4c..148f7a2003 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -41,6 +41,16 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_MXC_GPIO +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI +#define CONFIG_NAND_MXC +#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI +#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR +#define CONFIG_SYS_NAND_LARGEPAGE +#define CONFIG_MXC_NAND_HWECC +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_CMD_NAND + #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 8506604a76..965330aa38 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -148,6 +148,7 @@ #define CONFIG_CMDLINE_EDITING /* add command line history */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_CMD_BOOTMENU /* ANSI terminal Boot Menu */ #define CONFIG_CMD_CLEAR /* ANSI terminal clear screen command */ #ifdef ONENAND_SUPPORT @@ -287,8 +288,6 @@ int rx51_kp_getc(void); #endif /* Environment information */ -#define CONFIG_BOOTDELAY 3 - #define CONFIG_EXTRA_ENV_SETTINGS \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ "usbtty=cdc_acm\0" \ @@ -360,10 +359,40 @@ int rx51_kp_getc(void); "fi\0" \ "emmcboot=setenv mmcnum 1; run trymmcboot\0" \ "sdboot=setenv mmcnum 0; run trymmcboot\0" \ + "menucmd=bootmenu\0" \ + "bootmenu_0=Attached kernel=run attachboot\0" \ + "bootmenu_1=Internal eMMC=run emmcboot\0" \ + "bootmenu_2=External SD card=run sdboot\0" \ + "bootmenu_3=U-Boot boot order=boot\0" \ + "bootmenu_delay=30\0" \ "" #define CONFIG_PREBOOT \ - "if run slide; then true; else run attachboot; fi;" \ + "setenv mmcnum 1; setenv mmcpart 1;" \ + "setenv mmcscriptfile bootmenu.scr;" \ + "if run switchmmc; then " \ + "setenv mmcdone true;" \ + "setenv mmctype fat;" \ + "if run scriptload; then true; else " \ + "setenv mmctype ext2;" \ + "if run scriptload; then true; else " \ + "setenv mmctype ext4;" \ + "if run scriptload; then true; else " \ + "setenv mmcdone false;" \ + "fi;" \ + "fi;" \ + "fi;" \ + "if ${mmcdone}; then " \ + "run scriptboot;" \ + "fi;" \ + "fi;" \ + "if run slide; then true; else " \ + "setenv bootmenu_delay 0;" \ + "setenv bootdelay 0;" \ + "fi" + +#define CONFIG_POSTBOOTMENU \ + "echo;" \ "echo Extra commands:;" \ "echo run sercon - Use serial port for control.;" \ "echo run usbcon - Use usbtty for control.;" \ @@ -379,6 +408,11 @@ int rx51_kp_getc(void); "run attachboot;" \ "echo" +#define CONFIG_BOOTDELAY 30 +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_MENU +#define CONFIG_MENU_SHOW + /* * Miscellaneous configurable options */ diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h index 1abf2590ef..04e8d3ad51 100644 --- a/include/configs/omap2420h4.h +++ b/include/configs/omap2420h4.h @@ -67,6 +67,7 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 #define CONFIG_REVISION_TAG 1 +#define CONFIG_OF_LIBFDT /* * Size of malloc() pool @@ -189,7 +190,7 @@ #define CONFIG_SYS_TIMERBASE OMAP2420_GPT2 #define CONFIG_SYS_PTV V_PTV /* 2^(PTV+1) */ -#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) +#define CONFIG_SYS_HZ 1000 /*----------------------------------------------------------------------- * Physical Memory Map @@ -220,7 +221,7 @@ #define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_OFFSET 0x80000 /* environment starts here */ #else -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + SZ_128K) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + SZ_256K) #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE #define CONFIG_ENV_OFFSET ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */ diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index 6ae6a0f435..1fd3097d75 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -138,6 +138,10 @@ */ #define CONFIG_BOOTDELAY 3 +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 #define CONFIG_ENV_OVERWRITE @@ -145,6 +149,10 @@ "loadaddr=0x82000000\0" \ "console=ttyO2,115200n8\0" \ "fdt_high=0xffffffff\0" \ + "fdtaddr=0x80f80000\0" \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ "usbtty=cdc_acm\0" \ "vram=16M\0" \ "mmcdev=0\0" \ @@ -160,12 +168,19 @@ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \ "env import -t ${loadaddr} ${filesize}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ "mmcboot=echo Booting from mmc${mmcdev} ...; " \ "run mmcargs; " \ - "bootm ${loadaddr}\0" \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ + "findfdt="\ + "if test $board_name = sdp4430; then " \ + "setenv fdtfile omap4-sdp.dtb; fi; " \ + "if test $board_name = panda; then " \ + "setenv fdtfile omap4-panda-es.dtb; fi\0" \ + "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ #define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "echo SD/MMC found on device ${mmcdev};" \ "if run loadbootscript; then " \ @@ -179,7 +194,8 @@ "run uenvcmd;" \ "fi;" \ "fi;" \ - "if run loaduimage; then " \ + "if run loadimage; then " \ + "run loadfdt;" \ "run mmcboot; " \ "fi; " \ "fi" diff --git a/include/configs/omap5912osk.h b/include/configs/omap5912osk.h index 40ca9bb98d..c5797a238f 100644 --- a/include/configs/omap5912osk.h +++ b/include/configs/omap5912osk.h @@ -134,7 +134,7 @@ */ #define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */ #define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */ -#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) +#define CONFIG_SYS_HZ 1000 /*----------------------------------------------------------------------- * Physical Memory Map @@ -178,12 +178,15 @@ */ #define CONFIG_ENV_IS_IN_FLASH 1 /* addr of environment */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */ +#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ +#define CONFIG_ENV_OFFSET 0x40000 /* environment starts here */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR PHYS_SRAM +#define CONFIG_SYS_INIT_RAM_SIZE (250 * 1024) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE) #endif /* __CONFIG_H */ diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h index af97564011..c21c387cba 100644 --- a/include/configs/omap5_common.h +++ b/include/configs/omap5_common.h @@ -85,8 +85,7 @@ #define CONFIG_SYS_NS16550_COM3 UART3_BASE #define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} + /* I2C */ #define CONFIG_HARD_I2C #define CONFIG_SYS_I2C_SPEED 100000 @@ -94,19 +93,12 @@ #define CONFIG_DRIVER_OMAP34XX_I2C #define CONFIG_I2C_MULTI_BUS - /* MMC */ #define CONFIG_GENERIC_MMC #define CONFIG_MMC #define CONFIG_OMAP_HSMMC #define CONFIG_DOS_PARTITION -/* MMC ENV related defines */ -#define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ -#define CONFIG_ENV_OFFSET 0xE0000 -#define CONFIG_CMD_SAVEENV - #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Flash */ @@ -124,7 +116,6 @@ #define CONFIG_CMD_FAT /* FAT support */ #define CONFIG_CMD_I2C /* I2C serial bus support */ #define CONFIG_CMD_MMC /* MMC support */ -#define CONFIG_CMD_SAVEENV /* Disabled commands */ #undef CONFIG_CMD_NET @@ -137,17 +128,31 @@ */ #define CONFIG_BOOTDELAY 3 +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 #define CONFIG_ENV_OVERWRITE +#ifndef PARTS_DEFAULT +#define PARTS_DEFAULT +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "console=ttyO2,115200n8\0" \ + "fdt_high=0xffffffff\0" \ + "fdtaddr=0x80f80000\0" \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ "usbtty=cdc_acm\0" \ "vram=16M\0" \ + "partitions=" PARTS_DEFAULT "\0" \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext3 rootwait\0" \ + "mmcrootfstype=ext4 rootwait\0" \ "mmcargs=setenv bootargs console=${console} " \ "vram=${vram} " \ "root=${mmcroot} " \ @@ -155,19 +160,35 @@ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ + "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \ + "env import -t ${loadaddr} ${filesize}\0" \ + "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ "mmcboot=echo Booting from mmc${mmcdev} ...; " \ "run mmcargs; " \ - "bootm ${loadaddr}\0" \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ + "findfdt="\ + "if test $board_name = omap5_uevm; then " \ + "setenv fdtfile omap5-uevm.dtb; fi;\0 " \ + "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \ #define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "fi; " \ + "if run loadbootenv; then " \ + "run importbootenv; " \ + "fi;" \ + "if test -n ${uenvcmd}; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "fi;" \ + "if run loadimage; then " \ + "run loadfdt; " \ + "run mmcboot; " \ "fi; " \ "fi" diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_uevm.h index 22a8e13f48..240fdfcb47 100644 --- a/include/configs/omap5_evm.h +++ b/include/configs/omap5_uevm.h @@ -28,6 +28,11 @@ #ifndef __CONFIG_OMAP5_EVM_H #define __CONFIG_OMAP5_EVM_H +/* Define the default GPT table for eMMC */ +#define PARTS_DEFAULT \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}" + #include <configs/omap5_common.h> /* TWL6035 */ @@ -35,6 +40,18 @@ #define CONFIG_TWL6035_POWER #endif +/* MMC ENV related defines */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ +#define CONFIG_ENV_OFFSET 0xE0000 +#define CONFIG_CMD_SAVEENV + +/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART + #define CONFIG_SYS_PROMPT "OMAP5430 EVM # " #endif /* __CONFIG_OMAP5_EVM_H */ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 964bfcd440..7ed634b701 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -164,7 +164,7 @@ #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" #define CONFIG_SPL_TEXT_BASE 0xfffff000 -#define CONFIG_SPL_MAX_SIZE (4 * 1024) +#define CONFIG_SPL_MAX_SIZE 4096 #ifdef CONFIG_SYS_INIT_L2_ADDR /* We multiply CONFIG_SPL_MAX_SIZE by two to leave some room for BSS. */ diff --git a/include/configs/palmld.h b/include/configs/palmld.h index 3f9802ca0f..4ee2e46cd2 100644 --- a/include/configs/palmld.h +++ b/include/configs/palmld.h @@ -72,6 +72,7 @@ #define CONFIG_CMD_MMC #define CONFIG_CMD_IDE #define CONFIG_LCD +#define CONFIG_PXA_LCD /* * MMC Card Configuration diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h index 64771e7e8d..70fe05c519 100644 --- a/include/configs/palmtc.h +++ b/include/configs/palmtc.h @@ -74,6 +74,7 @@ #define CONFIG_CMD_ENV #define CONFIG_CMD_MMC #define CONFIG_LCD +#define CONFIG_PXA_LCD /* * MMC Card Configuration diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index 63ab12329b..d0ea74e0b4 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -21,8 +21,7 @@ #define CONFIG_AM33XX -#include <asm/arch/cpu.h> -#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> #define CONFIG_DMA_COHERENT #define CONFIG_DMA_COHERENT_SIZE (1 << 20) diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h index 671e9eb1e5..306abcc8e1 100644 --- a/include/configs/pdm360ng.h +++ b/include/configs/pdm360ng.h @@ -68,7 +68,6 @@ #define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */ -#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R #define CONFIG_SYS_IMMR 0x80000000 @@ -206,6 +205,9 @@ #define CONFIG_SYS_SRAM_BASE 0x50000000 #define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ +#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH1_BASE +#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE + /* ALE active low, data size 4 bytes */ #define CONFIG_SYS_CS0_CFG 0x05059350 /* ALE active low, data size 4 bytes */ @@ -213,6 +215,9 @@ #define CONFIG_SYS_MRAM_BASE 0x50040000 #define CONFIG_SYS_MRAM_SIZE 0x00020000 +#define CONFIG_SYS_CS2_START CONFIG_SYS_MRAM_BASE +#define CONFIG_SYS_CS2_SIZE CONFIG_SYS_MRAM_SIZE + /* ALE active low, data size 4 bytes */ #define CONFIG_SYS_CS2_CFG 0x05059110 @@ -296,6 +301,23 @@ #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC6_RX_ADDR /* + * Clocks in use + */ +#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ + CLOCK_SCCR1_LPC_EN | \ + CLOCK_SCCR1_NFC_EN | \ + CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ + CLOCK_SCCR1_PSCFIFO_EN | \ + CLOCK_SCCR1_DDR_EN | \ + CLOCK_SCCR1_FEC_EN | \ + CLOCK_SCCR1_TPR_EN) + +#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ + CLOCK_SCCR2_SPDIF_EN | \ + CLOCK_SCCR2_DIU_EN | \ + CLOCK_SCCR2_I2C_EN) + +/* * Used PSC UART devices */ #define CONFIG_SYS_PSC1 diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h index 5a15af6b6a..39c167fc6f 100644 --- a/include/configs/pxa255_idp.h +++ b/include/configs/pxa255_idp.h @@ -59,6 +59,7 @@ #undef CONFIG_LCD #ifdef CONFIG_LCD +#define CONFIG_PXA_LCD #define CONFIG_SHARP_LM8V31 #endif diff --git a/include/configs/rpi_b.h b/include/configs/rpi_b.h index cf62e45e8b..c18b35b057 100644 --- a/include/configs/rpi_b.h +++ b/include/configs/rpi_b.h @@ -23,6 +23,7 @@ #define CONFIG_ARM1176 #define CONFIG_BCM2835 #define CONFIG_ARCH_CPU_INIT +#define CONFIG_SYS_DCACHE_OFF /* * 2835 is a SKU in a series for which the 2708 is the first or primary SoC, * so 2708 has historically been used rather than a dedicated 2835 ID. @@ -30,7 +31,7 @@ #define CONFIG_MACH_TYPE MACH_TYPE_BCM2708 /* Timer */ -#define CONFIG_SYS_HZ 1000000 +#define CONFIG_SYS_HZ 1000 /* Memory layout */ #define CONFIG_NR_DRAM_BANKS 1 @@ -50,6 +51,7 @@ #define CONFIG_SYS_MALLOC_LEN SZ_4M #define CONFIG_SYS_MEMTEST_START 0x00100000 #define CONFIG_SYS_MEMTEST_END 0x00200000 +#define CONFIG_LOADADDR 0x00200000 /* Flash */ #define CONFIG_SYS_NO_FLASH @@ -57,6 +59,24 @@ /* Devices */ /* GPIO */ #define CONFIG_BCM2835_GPIO +/* LCD */ +#define CONFIG_LCD +#define LCD_BPP LCD_COLOR16 +/* + * Prevent allocation of RAM for FB; the real FB address is queried + * dynamically from the VideoCore co-processor, and comes from RAM + * not owned by the ARM CPU. + */ +#define CONFIG_FB_ADDR 0 +#define CONFIG_VIDEO_BCM2835 +#define CONFIG_SYS_WHITE_ON_BLACK + +/* SD/MMC configuration */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_MMC_SDHCI_IO_ACCESSORS +#define CONFIG_BCM2835_SDHCI /* Console UART */ #define CONFIG_PL011_SERIAL @@ -73,7 +93,59 @@ /* Environment */ #define CONFIG_ENV_SIZE SZ_16K #define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_VARS_UBOOT_CONFIG #define CONFIG_SYS_LOAD_ADDR 0x1000000 +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +/* + * Memory layout for where various images get loaded by boot scripts: + * + * scriptaddr can be pretty much anywhere that doesn't conflict with something + * else. Put it low in memory to avoid conflicts. + * + * kernel_addr_r must be within the first 128M of RAM in order for the + * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will + * decompress itself to 0x8000 after the start of RAM, kernel_addr_r + * should not overlap that area, or the kernel will have to copy itself + * somewhere else before decompression. Similarly, the address of any other + * data passed to the kernel shouldn't overlap the start of RAM. Pushing + * this up to 16M allows for a sizable kernel to be decompressed below the + * compressed load address. + * + * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for + * the compressed kernel to be up to 16M too. + * + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "stdin=serial\0" \ + "stderr=serial,lcd\0" \ + "stdout=serial,lcd\0" \ + "scriptaddr=0x00000000\0" \ + "kernel_addr_r=0x01000000\0" \ + "fdt_addr_r=0x02000000\0" \ + "ramdisk_addr_r=0x02100000\0" \ + "boot_targets=mmc0\0" \ + \ + "script_boot=" \ + "if fatload ${devtype} ${devnum}:1 " \ + "${scriptaddr} boot.scr.uimg; then " \ + "source ${scriptaddr}; " \ + "fi;\0" \ + \ + "mmc_boot=" \ + "setenv devtype mmc; " \ + "if mmc dev ${devnum}; then " \ + "run script_boot; " \ + "fi\0" \ + \ + "bootcmd_mmc0=setenv devnum 0; run mmc_boot\0" \ + +#define CONFIG_BOOTCOMMAND \ + "for target in ${boot_targets}; do run bootcmd_${target}; done" + +#define CONFIG_BOOTDELAY 2 /* Shell */ #define CONFIG_SYS_HUSH_PARSER @@ -88,6 +160,13 @@ #include <config_cmd_default.h> #define CONFIG_CMD_BOOTZ #define CONFIG_CMD_GPIO +#define CONFIG_CMD_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT /* Some things don't make sense on this HW or yet */ #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_NET diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h deleted file mode 100644 index d4dc8ef82d..0000000000 --- a/include/configs/smdk6400.h +++ /dev/null @@ -1,296 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * Gary Jennejohn <garyj@denx.de> - * David Mueller <d.mueller@elsoft.ch> - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> - * - * Configuation settings for the SAMSUNG SMDK6400(mDirac-III) board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_S3C6400 1 /* in a SAMSUNG S3C6400 SoC */ -#define CONFIG_S3C64XX 1 /* in a SAMSUNG S3C64XX Family */ -#define CONFIG_SMDK6400 1 /* on a SAMSUNG SMDK6400 Board */ - -#define CONFIG_PERIPORT_REMAP -#define CONFIG_PERIPORT_BASE 0x70000000 -#define CONFIG_PERIPORT_SIZE 0x13 - -#define CONFIG_SYS_IRAM_BASE 0x0c000000 /* Internal SRAM base address */ -#define CONFIG_SYS_IRAM_SIZE 0x2000 /* 8 KB of internal SRAM memory */ -#define CONFIG_SYS_IRAM_END (CONFIG_SYS_IRAM_BASE + CONFIG_SYS_IRAM_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IRAM_END - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_SDRAM_BASE 0x50000000 - -/* input clock of PLL: SMDK6400 has 12MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 12000000 - -#if !defined(CONFIG_NAND_SPL) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000) -#define CONFIG_ENABLE_MMU -#endif - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG - -/* - * Architecture magic and machine type - */ -#define CONFIG_MACH_TYPE 1270 - -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) - -/* - * Hardware drivers - */ -#define CONFIG_CS8900 /* we have a CS8900 on-board */ -#define CONFIG_CS8900_BASE 0x18800300 -#define CONFIG_CS8900_BUS16 /* follow the Linux driver */ - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK6400 */ - -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#define CONFIG_CMDLINE_EDITING - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - -/*********************************************************** - * Command definition - ***********************************************************/ -#include <config_cmd_default.h> - -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_NAND -#if defined(CONFIG_BOOT_ONENAND) -#define CONFIG_CMD_ONENAND -#endif -#define CONFIG_CMD_PING -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 - -#define CONFIG_BOOTDELAY 3 - -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#if (CONFIG_COMMANDS & CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "SMDK6400 # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x7e00000) /* 126MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default load address */ - -#define CONFIG_SYS_HZ 1000 - -/********************************** - Support Clock Settings - ********************************** - Setting SYNC ASYNC - ---------------------------------- - 667_133_66 X O - 533_133_66 O O - 400_133_66 X O - 400_100_50 O O - **********************************/ - -/*#define CONFIG_CLK_667_133_66*/ -#define CONFIG_CLK_533_133_66 -/* -#define CONFIG_CLK_400_100_50 -#define CONFIG_CLK_400_133_66 -#define CONFIG_SYNC_MODE -*/ - -/* SMDK6400 has 2 banks of DRAM, but we use only one in U-Boot */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB in Bank #1 */ - -#define CONFIG_SYS_FLASH_BASE 0x10000000 -#define CONFIG_SYS_MONITOR_BASE 0x00000000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -/* AM29LV160B has 35 sectors, AM29LV800B - 19 */ -#define CONFIG_SYS_MAX_FLASH_SECT 40 - -#define CONFIG_AMD_LV800 -#define CONFIG_SYS_FLASH_CFI 1 /* Use CFI parameters (needed?) */ -/* Use drivers/cfi_flash.c, even though the flash is not CFI-compliant */ -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_FLASH_CFI_LEGACY -#define CONFIG_SYS_FLASH_LEGACY_512Kx16 - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (5 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (5 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* - * SMDK6400 board specific data - */ - -#define CONFIG_IDENT_STRING " for SMDK6400" - -/* base address for uboot */ -#define CONFIG_SYS_PHY_UBOOT_BASE (CONFIG_SYS_SDRAM_BASE + 0x07e00000) -/* total memory available to uboot */ -#define CONFIG_SYS_UBOOT_SIZE (1024 * 1024) - -/* Put environment copies after the end of U-Boot owned RAM */ -#define CONFIG_NAND_ENV_DST (CONFIG_SYS_UBOOT_BASE + CONFIG_SYS_UBOOT_SIZE) - -#ifdef CONFIG_ENABLE_MMU -#define CONFIG_SYS_MAPPED_RAM_BASE 0xc0000000 -#define CONFIG_BOOTCOMMAND "nand read 0xc0018000 0x60000 0x1c0000;" \ - "bootm 0xc0018000" -#else -#define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE -#define CONFIG_BOOTCOMMAND "nand read 0x50018000 0x60000 0x1c0000;" \ - "bootm 0x50018000" -#endif - -/* NAND U-Boot load and start address */ -#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_MAPPED_RAM_BASE + 0x07e00000) - -#define CONFIG_ENV_OFFSET 0x0040000 - -/* NAND configuration */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x70200010 -#define CONFIG_SYS_S3C_NAND_HWECC - -#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ -#define CONFIG_SYS_NAND_WP 1 -#define CONFIG_SYS_NAND_YAFFS_WRITE 1 /* support yaffs write */ -#define CONFIG_SYS_NAND_BBT_2NDPAGE 1 /* bad-block markers in 1st and 2nd pages */ - -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_PHY_UBOOT_BASE /* NUB load-addr */ -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* NUB start-addr */ - -#define CONFIG_SYS_NAND_U_BOOT_OFFS (4 * 1024) /* Offset to RAM U-Boot image */ -#define CONFIG_SYS_NAND_U_BOOT_SIZE (252 * 1024) /* Size of RAM U-Boot image */ - -/* NAND chip page size */ -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -/* NAND chip block size */ -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -/* NAND chip page per block count */ -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -/* Location of the bad-block label */ -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 -/* Extra address cycle for > 128MiB */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE - -/* Size of the block protected by one OOB (Spare Area in Samsung terminology) */ -#define CONFIG_SYS_NAND_ECCSIZE CONFIG_SYS_NAND_PAGE_SIZE -/* Number of ECC bytes per OOB - S3C6400 calculates 4 bytes ECC in 1-bit mode */ -#define CONFIG_SYS_NAND_ECCBYTES 4 -/* Size of a single OOB region */ -#define CONFIG_SYS_NAND_OOBSIZE 64 -/* ECC byte positions */ -#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \ - 48, 49, 50, 51, 52, 53, 54, 55, \ - 56, 57, 58, 59, 60, 61, 62, 63} - -/* Boot configuration (define only one of next 3) */ -#define CONFIG_BOOT_NAND -/* None of these are currently implemented. Left from the original Samsung - * version for reference -#define CONFIG_BOOT_NOR -#define CONFIG_BOOT_MOVINAND -#define CONFIG_BOOT_ONENAND -*/ - -#define CONFIG_NAND -#define CONFIG_NAND_S3C64XX -/* Unimplemented or unsupported. See comment above. -#define CONFIG_ONENAND -#define CONFIG_MOVINAND -*/ - -/* Settings as above boot configuration */ -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_BOOTARGS "console=ttySAC,115200" - -#if !defined(CONFIG_ENABLE_MMU) -#define CONFIG_CMD_USB 1 -#define CONFIG_USB_S3C64XX -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x74300000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "s3c6400" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 - -#define CONFIG_USB_STORAGE 1 -#endif -#define CONFIG_DOS_PARTITION 1 - -#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_ENABLE_MMU) -# error "usb_ohci.c is currently broken with MMU enabled." -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/snow.h b/include/configs/snow.h new file mode 100644 index 0000000000..b8460fd1b4 --- /dev/null +++ b/include/configs/snow.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * + * Configuration settings for the SAMSUNG EXYNOS5 Snow board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_SNOW_H +#define __CONFIG_SNOW_H + +#include <configs/exynos5250-dt.h> + +#undef CONFIG_DEFAULT_DEVICE_TREE +#define CONFIG_DEFAULT_DEVICE_TREE exynos5250-snow + +#endif /* __CONFIG_SNOW_H */ diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h index 2b24997f80..3c8c74d59a 100644 --- a/include/configs/svm_sc8xx.h +++ b/include/configs/svm_sc8xx.h @@ -38,6 +38,7 @@ /* SC85T,SC860T, FEL8xx-AT(855T/860T) */ /*#define CONFIG_FEL8xx_AT */ /*#define CONFIG_LCD */ +/*#define CONFIG_MPC8XX_LCD*/ /* if core > 50MHz , un-comment CONFIG_BUS_DIV2 */ /* #define CONFIG_50MHz */ /* #define CONFIG_66MHz */ diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index f2a70b1a35..bf186995ed 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -150,6 +150,10 @@ MEM_LAYOUT_ENV_SETTINGS \ BOOTCMDS_COMMON +#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI) +#define CONFIG_FDT_SPI +#endif + /* overrides for SPL build here */ #ifdef CONFIG_SPL_BUILD diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 4cc35e5a88..036ded0c79 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -167,6 +167,7 @@ #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SYS_GENERIC_BOARD /* Misc utility code */ #define CONFIG_BOUNCE_BUFFER diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index e464e06173..395a657584 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -28,6 +28,7 @@ /* * Errata configuration */ +#define CONFIG_ARM_ERRATA_716044 #define CONFIG_ARM_ERRATA_742230 #define CONFIG_ARM_ERRATA_751472 diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h new file mode 100644 index 0000000000..16547e3314 --- /dev/null +++ b/include/configs/ti814x_evm.h @@ -0,0 +1,221 @@ +/* + * ti814x_evm.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __CONFIG_TI814X_EVM_H +#define __CONFIG_TI814X_EVM_H + +#define CONFIG_TI81XX +#define CONFIG_TI814X +#define CONFIG_SYS_NO_FLASH + +#include <asm/arch/omap.h> + +#define CONFIG_DMA_COHERENT +#define CONFIG_DMA_COHERENT_SIZE (1 << 20) + +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_SYS_MALLOC_LEN (1024 << 10) +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* Use HUSH for command parsing */ +#define CONFIG_SYS_PROMPT "U-Boot# " +#define CONFIG_SYS_NO_FLASH +#define CONFIG_MACH_TYPE MACH_TYPE_TI8148EVM + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG /* for ramdisk support */ + +/* commands to include */ +# include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_VERSION_VARIABLE + +#define CONFIG_BOOTDELAY 1 /* negative for no autoboot */ +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x80200000\0" \ + "fdtaddr=0x80F80000\0" \ + "rdaddr=0x81000000\0" \ + "bootfile=/boot/uImage\0" \ + "fdtfile=\0" \ + "console=ttyO0,115200n8\0" \ + "optargs=\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 ro\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ + "ramrootfstype=ext2\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "ramargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${ramroot} " \ + "rootfstype=${ramrootfstype}\0" \ + "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ + "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \ + "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "ramboot=echo Booting from ramdisk ...; " \ + "run ramargs; " \ + "bootm ${loadaddr}\0" \ + "fdtfile=ti814x-evm.dtb\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loaduimage; then " \ + "run mmcboot;" \ + "fi;" \ + "fi;" \ + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#define CONFIG_CMD_ECHO + +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START PHYS_DRAM_1 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \ + + PHYS_DRAM_1_SIZE - (8 << 12)) + +#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default */ +#define CONFIG_SYS_HZ 1000 /* 1ms clock */ + +#define CONFIG_OMAP_GPIO +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_CMD_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 + +/** + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 banks of DRAM */ +#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ +#define PHYS_DRAM_1_SIZE 0x20000000 /* 512MB */ +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1024MB */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) + +/** + * Platform/Board specific defs + */ +#define CONFIG_SYS_TIMERBASE 0x4802E000 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK (48000000) +#define CONFIG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +#define CONFIG_ENV_IS_NOWHERE + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x40300000 +#define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024) +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +#define CONFIG_SPL_BOARD_INIT + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80800000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80800000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + +/* + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* Unsupported features */ +#undef CONFIG_USE_IRQ + +#endif /* ! __CONFIG_TI814X_EVM_H */ diff --git a/include/configs/trats.h b/include/configs/trats.h index 63745ac8f1..fd58558beb 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -199,6 +199,7 @@ "splfile=falcon.bin\0" \ "spl_export=" \ "setexpr spl_imgsize ${splsize} + 8 ;" \ + "setenv spl_imgsize 0x${spl_imgsize};" \ "setexpr spl_imgaddr ${spladdr} - 8 ;" \ "setexpr spl_addr_tmp ${spladdr} - 4 ;" \ "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \ @@ -316,4 +317,9 @@ #define CONFIG_VIDEO_BMP_GZIP #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 120 * 4) + (1 << 12)) +#define CONFIG_CMD_USB_MASS_STORAGE +#if defined(CONFIG_CMD_USB_MASS_STORAGE) +#define CONFIG_USB_GADGET_MASS_STORAGE +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index ebd7a257f3..4c75cc52f3 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -125,6 +125,8 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ +#define CONFIG_NAND_OMAP_BCH8 +#define CONFIG_BCH /* commands to include */ #include <config_cmd_default.h> @@ -290,7 +292,7 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ -#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ +#define CONFIG_SPL_MAX_SIZE (55 * 1024) /* 7 KB for stack */ #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ @@ -303,11 +305,14 @@ #define CONFIG_SYS_NAND_OOBSIZE 64 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ - 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCPOS {12, 13, 14, 15, 16, 17, 18, 19, 20,\ + 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\ + 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46,\ + 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,\ + 60, 61, 62, 63} #define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_ECCBYTES 13 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index 0644f7a5b8..b92531477e 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -46,7 +46,7 @@ #define CONFIG_BOARD_EARLY_INIT_F /* SPI */ -#define CONFIG_TEGRA_SPI +#define CONFIG_TEGRA20_SFLASH #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 diff --git a/include/configs/tx25.h b/include/configs/tx25.h index 80194d824c..e72f8f66b1 100644 --- a/include/configs/tx25.h +++ b/include/configs/tx25.h @@ -21,6 +21,7 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include <asm/arch/imx-regs.h> /* * KARO TX25 board - SoC Configuration @@ -31,8 +32,14 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */ -/* NAND BOOT is the only boot method */ -#define CONFIG_NAND_U_BOOT +#define CONFIG_SPL +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" +#define CONFIG_SPL_MAX_SIZE 2048 +#define CONFIG_SPL_NAND_SUPPORT + +#define CONFIG_SPL_TEXT_BASE 0x810c0000 +#define CONFIG_SYS_TEXT_BASE 0x81200000 #ifndef MACH_TYPE_TX25 #define MACH_TYPE_TX25 2177 @@ -40,16 +47,16 @@ #define CONFIG_MACH_TYPE MACH_TYPE_TX25 -#ifdef CONFIG_NAND_SPL +#ifdef CONFIG_SPL_BUILD /* Start copying real U-boot from the second page */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 -#define CONFIG_SYS_NAND_U_BOOT_DST (0x81200000) +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST #define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_SPARE_SIZE 64 +#define CONFIG_SYS_NAND_OOBSIZE 64 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_SIZE (128 * 1024 * 1024) @@ -173,7 +180,6 @@ /* additions for new relocation code, must be added to all boards */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (IMX_RAM_BASE + IMX_RAM_SIZE) #endif /* __CONFIG_H */ diff --git a/include/configs/v37.h b/include/configs/v37.h index e36d2491cc..f9965db3cb 100644 --- a/include/configs/v37.h +++ b/include/configs/v37.h @@ -39,6 +39,7 @@ #define CONFIG_SYS_TEXT_BASE 0x40000000 #define CONFIG_LCD +#define CONFIG_MPC8XX_LCD #define CONFIG_SHARP_LQ084V1DG21 #undef CONFIG_LCD_LOGO diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index b92f70b538..f79dd3bbd8 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -103,6 +103,7 @@ #ifdef CONFIG_CMD_SPI #define CONFIG_SOFT_SPI #define CONFIG_LCD +#define CONFIG_PXA_LCD #define CONFIG_LMS283GF05 #define CONFIG_VIDEO_LOGO #define CONFIG_CMD_BMP |