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-rw-r--r--include/configs/MPC8548CDS.h5
-rw-r--r--include/configs/MPC8572DS.h5
-rw-r--r--include/configs/MPC8641HPCN.h2
-rw-r--r--include/configs/P1010RDB.h5
-rw-r--r--include/configs/P2041RDB.h5
-rw-r--r--include/configs/T102xRDB.h5
-rw-r--r--include/configs/T104xRDB.h3
-rw-r--r--include/configs/T208xQDS.h5
-rw-r--r--include/configs/T208xRDB.h5
-rw-r--r--include/configs/T4240RDB.h3
-rw-r--r--include/configs/controlcenterd.h5
-rw-r--r--include/configs/corenet_ds.h5
-rw-r--r--include/configs/cyrus.h5
-rw-r--r--include/configs/kmp204x.h3
-rw-r--r--include/configs/p1_p2_rdb_pc.h5
-rw-r--r--include/configs/qemu-ppce500.h3
-rw-r--r--include/configs/sandbox.h5
-rw-r--r--include/configs/t4qds.h3
-rw-r--r--include/configs/uniphier.h24
19 files changed, 6 insertions, 95 deletions
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 1cb62ae849..4b40129197 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -43,11 +43,6 @@ extern unsigned long get_clock_freq(void);
*/
#define CONFIG_ENABLE_36BIT_PHYS 1
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-#endif
-
#define CONFIG_SYS_CCSRBAR 0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index b4e5e3b3e2..429dae19af 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -45,11 +45,6 @@
#define CONFIG_ENABLE_36BIT_PHYS 1
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-#endif
-
/*
* Config the L2 Cache as L2 SRAM
*/
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index a7f02aef29..1560b61387 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -19,7 +19,6 @@
/* High Level Configuration Options */
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
-#define CONFIG_ADDR_MAP 1 /* Use addr map */
/*
* default CCSRBAR is at 0xff700000
@@ -47,7 +46,6 @@
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
-#define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */
#define CONFIG_ALTIVEC 1
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 8f709a6cac..fc74d57497 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -196,11 +196,6 @@
#define CONFIG_ENABLE_36BIT_PHYS
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-#endif
-
/* DDR Setup */
#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_DDR_SPD
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 94cbe10dd3..c6a64ee479 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -70,11 +70,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_ENABLE_36BIT_PHYS
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-
#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
/*
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index f5d9657444..efd9b6b5e1 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -17,11 +17,6 @@
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_ENABLE_36BIT_PHYS
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 4237dfcd6c..8f9de56f07 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -186,9 +186,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
#define CONFIG_ENABLE_36BIT_PHYS
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-
/*
* Config the L3 Cache as L3 SRAM
*/
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index c54f7f53e5..f32e6680b3 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -26,11 +26,6 @@
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_ENABLE_36BIT_PHYS
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 70eafc3e28..e666e4f4a4 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -20,11 +20,6 @@
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
#define CONFIG_ENABLE_36BIT_PHYS
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 9832f85405..ebe7a9cf92 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -80,9 +80,6 @@
#define CONFIG_ENABLE_36BIT_PHYS
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-
/*
* Config the L3 Cache as L3 SRAM
*/
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index 823586cc09..512d8e16ee 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -41,11 +41,6 @@
#define CONFIG_ENABLE_36BIT_PHYS
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-#endif
-
#define CONFIG_L2_CACHE
#define CONFIG_BTB
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index a49f9056c5..d7812bd886 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -84,11 +84,6 @@
#define CONFIG_ENABLE_36BIT_PHYS
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-
#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
/*
diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h
index 052e6018a3..b587cb8d77 100644
--- a/include/configs/cyrus.h
+++ b/include/configs/cyrus.h
@@ -70,11 +70,6 @@
#define CONFIG_ENABLE_36BIT_PHYS
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#endif
-
/* test POST memory test */
#undef CONFIG_POST
diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h
index e43b2f7513..6cd77edf70 100644
--- a/include/configs/kmp204x.h
+++ b/include/configs/kmp204x.h
@@ -64,9 +64,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_ENABLE_36BIT_PHYS
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-
#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */
/*
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 6b57be912a..a33f2f30ca 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -233,11 +233,6 @@
#define CONFIG_ENABLE_36BIT_PHYS
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-#endif
-
#define CONFIG_SYS_CCSRBAR 0xffe00000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h
index 03b08968f6..b3ec43073c 100644
--- a/include/configs/qemu-ppce500.h
+++ b/include/configs/qemu-ppce500.h
@@ -21,9 +21,6 @@
#define CONFIG_ENABLE_36BIT_PHYS
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-
/* Needed to fill the ccsrbar pointer */
/* Virtual address to CCSRBAR */
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 1a981a7c37..0353a19c97 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -47,8 +47,11 @@
#define CONFIG_PHYSMEM
/* Size of our emulated memory */
+#define SB_CONCAT(x, y) x ## y
+#define SB_TO_UL(s) SB_CONCAT(s, UL)
#define CONFIG_SYS_SDRAM_BASE 0
-#define CONFIG_SYS_SDRAM_SIZE (128 << 20)
+#define CONFIG_SYS_SDRAM_SIZE \
+ (SB_TO_UL(CONFIG_SANDBOX_RAM_SIZE_MB) << 20)
#define CONFIG_SYS_MONITOR_BASE 0
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index 3da7ee7b3a..1f6ae462ae 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -42,9 +42,6 @@
#define CONFIG_ENABLE_36BIT_PHYS
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-
/*
* Config the L3 Cache as L3 SRAM
*/
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 55fa85ed62..03bbbab3cf 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -41,32 +41,12 @@
#define CONFIG_ARMV7_PSCI_1_0
-/*-----------------------------------------------------------------------
- * MMU and Cache Setting
- *----------------------------------------------------------------------*/
-
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
#define CONFIG_TIMESTAMP
-/* FLASH related */
-
-#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_MONITOR_BASE 0
-#define CONFIG_SYS_MONITOR_LEN 0x000d0000 /* 832KB */
-#define CONFIG_SYS_FLASH_BASE 0
-
-/*
- * flash_toggle does not work for our support card.
- * We need to use flash_status_poll.
- */
-#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
-
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
-
-/* serial console configuration */
+#define CONFIG_SYS_MONITOR_LEN 0x00200000 /* 2MB */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
/* Boot Argument Buffer Size */
@@ -221,7 +201,7 @@
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
/* only for SPL */
-#define CONFIG_SPL_STACK (0x00200000)
+#define CONFIG_SPL_STACK (0x00100000)
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
generated by cgit (git 2.34.1) at 2025-01-08 08:15:50 +0000