diff options
Diffstat (limited to 'include/configs')
41 files changed, 1111 insertions, 62 deletions
diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h index 6eb466a725..c0b1d86224 100644 --- a/include/configs/ISPAN.h +++ b/include/configs/ISPAN.h @@ -84,6 +84,10 @@ * GPIO pins used for bit-banged MII communications */ #define MDIO_PORT 3 /* Port D */ +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE + #define CONFIG_SYS_MDIO_PIN 0x00040000 /* PD13 */ #define CONFIG_SYS_MDC_PIN 0x00080000 /* PD12 */ diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index 39b8b8fce4..ffd37fd933 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -150,6 +150,9 @@ * GPIO pins used for bit-banged MII communications */ #define MDIO_PORT 2 /* Port C */ +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS #define CONFIG_SYS_MDIO_PIN 0x00002000 /* PC18 */ diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h index b0162c3971..55d77f808b 100644 --- a/include/configs/MPC8266ADS.h +++ b/include/configs/MPC8266ADS.h @@ -96,6 +96,10 @@ * Port pins used for bit-banged MII communictions (if applicable). */ #define MDIO_PORT 2 /* Port C */ +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE + #define MDIO_ACTIVE (iop->pdir |= 0x00400000) #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) #define MDIO_READ ((iop->pdat & 0x00400000) != 0) diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 8ddce5c699..df59acae31 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -363,6 +363,10 @@ * GPIO pins used for bit-banged MII communications */ #define MDIO_PORT 2 /* Port C */ +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE + #define MDIO_ACTIVE (iop->pdir |= 0x00400000) #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) #define MDIO_READ ((iop->pdat & 0x00400000) != 0) diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 761932800e..7cb4ccdc19 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -102,8 +102,6 @@ #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ #define CONFIG_VERY_BIG_RAM -#define MPC86xx_DDR_SDRAM_CLK_CNTL - #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index b0ae25c224..a46f7c8bdd 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -141,8 +141,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ #define CONFIG_VERY_BIG_RAM -#define MPC86xx_DDR_SDRAM_CLK_CNTL - #define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 8e97ad0681..310242e0bd 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -43,6 +43,22 @@ #define CONFIG_P2020 #endif +#ifdef CONFIG_MK_NAND +#define CONFIG_NAND_U_BOOT 1 +#define CONFIG_RAMBOOT_NAND 1 +#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000 +#endif + +#ifdef CONFIG_MK_SDCARD +#define CONFIG_RAMBOOT_SDCARD 1 +#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000 +#endif + +#ifdef CONFIG_MK_SPIFLASH +#define CONFIG_RAMBOOT_SPIFLASH 1 +#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000 +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ @@ -82,16 +98,34 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_MEMTEST_END 0x1fffffff #define CONFIG_PANIC_HANG /* do not reset board on panic */ + /* + * Config the L2 Cache as L2 SRAM + */ +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull +#else +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#endif +#define CONFIG_SYS_L2_SIZE (512 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) + /* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of */ /* CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ /* CONFIG_SYS_IMMR */ + +#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) +#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR +#else +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#endif + #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) @@ -158,6 +192,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \ + || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_EMPTY_INFO @@ -177,7 +218,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ +#ifndef CONFIG_NAND_SPL #define CONFIG_SYS_NAND_BASE 0xffa00000 +#else +#define CONFIG_SYS_NAND_BASE 0xfff00000 +#endif #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} #define CONFIG_SYS_MAX_NAND_DEVICE 1 @@ -187,6 +232,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) +/* NAND boot: 4K NAND loader config */ +#define CONFIG_SYS_NAND_SPL_SIZE 0x1000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) +#define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) +#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) + /* NAND flash config */ #define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ @@ -202,10 +256,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); | OR_FCM_TRLX \ | OR_FCM_EHTR) +#ifdef CONFIG_RAMBOOT_NAND +#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ +#else #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ #define CONFIG_SYS_BR1_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ #define CONFIG_SYS_OR1_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#endif #define CONFIG_SYS_VSC7385_BASE 0xffb00000 @@ -371,14 +432,26 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * Environment */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 +#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_RAMBOOT_NAND) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE + #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) + #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) + #define CONFIG_ENV_SIZE 0x2000 +#endif #else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) + #define CONFIG_ENV_IS_IN_FLASH 1 + #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 + #define CONFIG_ENV_ADDR 0xfff80000 + #else + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) + #endif + #define CONFIG_ENV_SIZE 0x2000 + #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h index 5b6f27186b..e630afef01 100644 --- a/include/configs/Rattler.h +++ b/include/configs/Rattler.h @@ -103,6 +103,10 @@ * GPIO pins used for bit-banged MII communications */ #define MDIO_PORT 2 /* Port C */ +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE + #define MDIO_ACTIVE (iop->pdir |= 0x00400000) #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) #define MDIO_READ ((iop->pdat & 0x00400000) != 0) diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 7cde39bf2a..1989e5aea6 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -290,6 +290,10 @@ * GPIO pins used for bit-banged MII communications */ #define MDIO_PORT 2 /* Port C */ + #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) + #define MDC_DECLARE MDIO_DECLARE + #define MDIO_ACTIVE (iop->pdir |= 0x00400000) #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) #define MDIO_READ ((iop->pdat & 0x00400000) != 0) diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h index 6c462af53c..6eaa61d563 100644 --- a/include/configs/TQM8272.h +++ b/include/configs/TQM8272.h @@ -219,6 +219,9 @@ * GPIO pins used for bit-banged MII communications */ #define MDIO_PORT 2 /* Port C */ +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE #if STK82xx_150 #define CONFIG_SYS_MDIO_PIN 0x00008000 /* PC16 */ diff --git a/include/configs/VoVPN-GW.h b/include/configs/VoVPN-GW.h index b2d75e3c1c..36141843a8 100644 --- a/include/configs/VoVPN-GW.h +++ b/include/configs/VoVPN-GW.h @@ -124,6 +124,11 @@ #define CONFIG_BITBANGMII #define MDIO_PORT 1 /* Port B */ + +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE + #define CONFIG_SYS_MDIO_PIN 0x00002000 /* PB18 */ #define CONFIG_SYS_MDC_PIN 0x00001000 /* PB19 */ #define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN) diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h index 9cda3f9bdf..8ae765c7c3 100644 --- a/include/configs/ZPC1900.h +++ b/include/configs/ZPC1900.h @@ -86,6 +86,10 @@ * GPIO pins used for bit-banged MII communications */ #define MDIO_PORT 2 /* Port C */ +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE + #define MDIO_ACTIVE (iop->pdir |= 0x00400000) #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) #define MDIO_READ ((iop->pdat & 0x00400000) != 0) diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h new file mode 100644 index 0000000000..4ef8566ea2 --- /dev/null +++ b/include/configs/cpu9260.h @@ -0,0 +1,453 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop@leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * Ilko Iliev <www.ronetix.at> + * + * (C) Copyright 2009 + * Eric Benard <eric@eukrea.com> + * + * Configuration settings for the Eukrea CPU9260 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_DISPLAY_CPUINFO 1 + +#define AT91_MAIN_CLOCK 18432000 +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_ARM926EJS 1 + +#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9260) +#define CONFIG_CPU9260 1 +#elif defined(CONFIG_CPU9G20_128M) || defined(CONFIG_CPU9G20) +#define CONFIG_CPU9G20 1 +#endif + +#if defined(CONFIG_CPU9G20) +#define CONFIG_AT91SAM9G20 1 +#elif defined(CONFIG_CPU9260) +#define CONFIG_AT91SAM9260 1 +#else +#error "Unknown board" +#endif + +#define CONFIG_ARCH_CPU_INIT +#undef CONFIG_USE_IRQ + +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* clocks */ +#if defined(CONFIG_CPU9G20) +#define MASTER_PLL_DIV 0x01 +#define MASTER_PLL_MUL 0x2B +#elif defined(CONFIG_CPU9260) +#define MASTER_PLL_DIV 0x09 +#define MASTER_PLL_MUL 0x61 +#endif + +/* CKGR_MOR - enable main osc. */ +#define CONFIG_SYS_MOR_VAL \ + (AT91_PMC_MOSCEN | \ + (255 << 8)) /* Main Oscillator Start-up Time */ +#if defined(CONFIG_CPU9G20) +#define CONFIG_SYS_PLLAR_VAL \ + (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) +#elif defined(CONFIG_CPU9260) +#define CONFIG_SYS_PLLAR_VAL \ + (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ + AT91_PMC_OUT | \ + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) +#endif + +#if defined(CONFIG_CPU9G20) +#define CONFIG_SYS_MCKR1_VAL \ + (AT91_PMC_CSS_PLLA | \ + AT91_PMC_PRES_1 | \ + AT91SAM9_PMC_MDIV_6 | \ + AT91_PMC_PDIV_2) +#define CONFIG_SYS_MCKR2_VAL \ + CONFIG_SYS_MCKR1_VAL +#elif defined(CONFIG_CPU9260) +#define CONFIG_SYS_MCKR1_VAL \ + (AT91_PMC_CSS_SLOW | \ + AT91_PMC_PRES_1 | \ + AT91SAM9_PMC_MDIV_2 | \ + AT91_PMC_PDIV_1) +#define CONFIG_SYS_MCKR2_VAL \ + (AT91_PMC_CSS_PLLA | \ + AT91_PMC_PRES_1 | \ + AT91SAM9_PMC_MDIV_2 | \ + AT91_PMC_PDIV_1) +#endif + +/* define PDC[31:16] as DATA[31:16] */ +#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 +/* no pull-up for D[31:16] */ +#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000 + +/* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ +#define CONFIG_SYS_MATRIX_EBICSA_VAL \ + (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC |\ + AT91_MATRIX_CS3A_SMC_SMARTMEDIA | AT91_MATRIX_VDDIOMSEL) + +/* SDRAM */ +/* SDRAMC_MR Mode register */ +#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL +/* SDRAMC_TR - Refresh Timer register */ +#define CONFIG_SYS_SDRC_TR_VAL1 0x287 +/* SDRAMC_CR - Configuration register*/ +#if defined(CONFIG_CPU9G20) +#define CONFIG_SYS_SDRC_CR_VAL_64MB \ + (AT91_SDRAMC_NC_9 | \ + AT91_SDRAMC_NR_13 | \ + AT91_SDRAMC_NB_4 | \ + AT91_SDRAMC_CAS_2 | \ + AT91_SDRAMC_DBW_32 | \ + (2 << 8) | /* Write Recovery Delay */ \ + (9 << 12) | /* Row Cycle Delay */ \ + (3 << 16) | /* Row Precharge Delay */ \ + (3 << 20) | /* Row to Column Delay */ \ + (6 << 24) | /* Active to Precharge Delay */ \ + (10 << 28)) /* Exit Self Refresh to Active Delay */ + +#define CONFIG_SYS_SDRC_CR_VAL_128MB \ + (AT91_SDRAMC_NC_10 | \ + AT91_SDRAMC_NR_13 | \ + AT91_SDRAMC_NB_4 | \ + AT91_SDRAMC_CAS_2 | \ + AT91_SDRAMC_DBW_32 | \ + (2 << 8) | /* Write Recovery Delay */ \ + (9 << 12) | /* Row Cycle Delay */ \ + (3 << 16) | /* Row Precharge Delay */ \ + (3 << 20) | /* Row to Column Delay */ \ + (6 << 24) | /* Active to Precharge Delay */ \ + (10 << 28)) /* Exit Self Refresh to Active Delay */ +#elif defined(CONFIG_CPU9260) +#define CONFIG_SYS_SDRC_CR_VAL_64MB \ + (AT91_SDRAMC_NC_9 | \ + AT91_SDRAMC_NR_13 | \ + AT91_SDRAMC_NB_4 | \ + AT91_SDRAMC_CAS_2 | \ + AT91_SDRAMC_DBW_32 | \ + (2 << 8) | /* Write Recovery Delay */ \ + (7 << 12) | /* Row Cycle Delay */ \ + (2 << 16) | /* Row Precharge Delay */ \ + (2 << 20) | /* Row to Column Delay */ \ + (5 << 24) | /* Active to Precharge Delay */ \ + (8 << 28)) /* Exit Self Refresh to Active Delay */ + +#define CONFIG_SYS_SDRC_CR_VAL_128MB \ + (AT91_SDRAMC_NC_10 | \ + AT91_SDRAMC_NR_13 | \ + AT91_SDRAMC_NB_4 | \ + AT91_SDRAMC_CAS_2 | \ + AT91_SDRAMC_DBW_32 | \ + (2 << 8) | /* Write Recovery Delay */ \ + (7 << 12) | /* Row Cycle Delay */ \ + (2 << 16) | /* Row Precharge Delay */ \ + (2 << 20) | /* Row to Column Delay */ \ + (5 << 24) | /* Active to Precharge Delay */ \ + (8 << 28)) /* Exit Self Refresh to Active Delay */ +#endif + +/* Memory Device Register -> SDRAM */ +#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ + +/* setup SMC0, CS0 (NOR Flash) - 16-bit */ +#if defined(CONFIG_CPU9G20) +#define CONFIG_SYS_SMC0_SETUP0_VAL \ + (AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | \ + AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)) +#define CONFIG_SYS_SMC0_PULSE0_VAL \ + (AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(8) | \ + AT91_SMC_NRDPULSE_(14) | AT91_SMC_NCS_RDPULSE_(14)) +#define CONFIG_SYS_SMC0_CYCLE0_VAL \ + (AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(14)) +#define CONFIG_SYS_SMC0_MODE0_VAL \ + (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ + AT91_SMC_DBW_16 | \ + AT91_SMC_TDFMODE | \ + AT91_SMC_TDF_(3)) +#elif defined(CONFIG_CPU9260) +#define CONFIG_SYS_SMC0_SETUP0_VAL \ + (AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | \ + AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)) +#define CONFIG_SYS_SMC0_PULSE0_VAL \ + (AT91_SMC_NWEPULSE_(6) | AT91_SMC_NCS_WRPULSE_(6) | \ + AT91_SMC_NRDPULSE_(10) | AT91_SMC_NCS_RDPULSE_(10)) +#define CONFIG_SYS_SMC0_CYCLE0_VAL \ + (AT91_SMC_NWECYCLE_(6) | AT91_SMC_NRDCYCLE_(10)) +#define CONFIG_SYS_SMC0_MODE0_VAL \ + (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ + AT91_SMC_DBW_16 | \ + AT91_SMC_TDFMODE | \ + AT91_SMC_TDF_(2)) +#endif + +/* user reset enable */ +#define CONFIG_SYS_RSTC_RMR_VAL \ + (AT91_RSTC_KEY | \ + AT91_RSTC_PROCRST | \ + AT91_RSTC_RSTTYP_WAKEUP | \ + AT91_RSTC_RSTTYP_WATCHDOG) + +/* Disable Watchdog */ +#define CONFIG_SYS_WDTC_WDMR_VAL \ + (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ + AT91_WDT_WDV | \ + AT91_WDT_WDDIS | \ + AT91_WDT_WDD) + +/* + * Hardware drivers + */ +#define CONFIG_ATMEL_USART 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_IMLS + +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_NAND 1 +#define CONFIG_CMD_USB 1 +#define CONFIG_CMD_FAT 1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M) +#define PHYS_SDRAM_SIZE 0x08000000 /* 128 MB */ +#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_128MB +#else +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 MB */ +#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_64MB +#endif + +/* NAND flash */ +#define CONFIG_NAND_ATMEL 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) + +/* NOR flash */ +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define PHYS_FLASH_1 0x10000000 +#define PHYS_FLASH_2 0x12000000 +#define CONFIG_SYS_FLASH_BANKS_LIST \ + { PHYS_FLASH_1, PHYS_FLASH_2 } +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MAX_FLASH_SECT (255+4) +#define CONFIG_SYS_MAX_FLASH_BANKS 2 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_EMPTY_INFO 1 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +#define CONFIG_SYS_FLASH_PROTECTION 1 +#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 + +/* Ethernet */ +#define CONFIG_MACB 1 +#define CONFIG_RMII 1 +#define CONFIG_RESET_PHY_R 1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY 1 + +/* LEDS */ +/* Status LED */ +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED 1 +#define STATUS_LED_RED 0 +#define STATUS_LED_GREEN 1 +#define STATUS_LED_YELLOW 2 +#define STATUS_LED_BLUE 3 +/* Red */ +#define STATUS_LED_BIT STATUS_LED_RED +#define STATUS_LED_STATE STATUS_LED_OFF +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) +/* Green */ +#define STATUS_LED_BIT1 STATUS_LED_GREEN +#define STATUS_LED_STATE1 STATUS_LED_OFF +#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) +/* Yellow */ +#define STATUS_LED_BIT2 STATUS_LED_YELLOW +#define STATUS_LED_STATE2 STATUS_LED_OFF +#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) +/* Blue */ +#define STATUS_LED_BIT3 STATUS_LED_BLUE +#define STATUS_LED_STATE3 STATUS_LED_ON +#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2) +/* Optional value */ +#define STATUS_LED_BOOT STATUS_LED_BIT + +#define CONFIG_RED_LED AT91_PIN_PC11 +#define CONFIG_GREEN_LED AT91_PIN_PC12 +#define CONFIG_YELLOW_LED AT91_PIN_PC7 +#define CONFIG_BLUE_LED AT91_PIN_PC9 + +/* USB */ +#define CONFIG_USB_ATMEL 1 +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE 1 + +#define CONFIG_SYS_LOAD_ADDR 0x21000000 + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END 0x21e00000 + +#undef CONFIG_SYS_USE_NANDFLASH +#define CONFIG_SYS_USE_FLASH 1 + +#if defined(CONFIG_SYS_USE_FLASH) +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_OVERWRITE 1 + +#define CONFIG_BOOTCOMMAND "run flashboot" + +#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand" +#define MTDPARTS_DEFAULT \ + "mtdparts=physmap-flash.0:" \ + "256k(u-boot)ro," \ + "128k(u-boot-env)ro," \ + "1792k(kernel)," \ + "-(rootfs);" \ + "atmel_nand:-(nand)" + +#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 " + +#if defined(CONFIG_CPU9G20) +#define CONFIG_SYS_BASEDIR "cpu9G20" +#elif defined(CONFIG_CPU9260) +#define CONFIG_SYS_BASEDIR "cpu9260" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "partition=nand0,0\0" \ + "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ + "ramboot=tftpboot 0x22000000 cpu9260/uImage;" \ + "run ramargs;bootm 22000000\0" \ + "flashboot=run ramargs;bootm 0x10060000\0" \ + "basedir=" CONFIG_SYS_BASEDIR "\0" \ + "updtub=tftp 0x24000000 $(basedir)/u-boot.bin;protect " \ + "off 0x10000000 0x1003ffff;erase 0x10000000 " \ + "0x1003ffff;cp.b 0x24000000 0x10000000 " \ + "$(filesize)\0" \ + "updtui=tftp 0x24000000 $(basedir)/uImage;protect off" \ + " 0x10060000 0x1021ffff;erase 0x10060000 " \ + "0x1021ffff;cp.b 0x24000000 0x10060000 " \ + "$(filesize)\0" \ + "updtrfs=tftp 0x24000000 $(basedir)/rootfs.jffs2; " \ + "protect off 0x10220000 0x13ffffff;erase " \ + "0x10220000 0x13ffffff;cp.b 0x24000000 " \ + "0x10220000 $(filesize)\0" \ + "" +#endif + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#if defined(CONFIG_CPU9G20) +#define CONFIG_SYS_PROMPT "CPU9G20=> " +#elif defined(CONFIG_CPU9260) +#define CONFIG_SYS_PROMPT "CPU9260=> " +#endif +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SILENT_CONSOLE 1 +#define CONFIG_NETCONSOLE 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN \ + ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +#define CONFIG_STACKSIZE (32 * 1024) + +#if defined(CONFIG_USE_IRQ) +#error CONFIG_USE_IRQ not supported +#endif + +#endif diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h new file mode 100644 index 0000000000..0d3acf61ae --- /dev/null +++ b/include/configs/cpuat91.h @@ -0,0 +1,228 @@ +/* + * CPUAT91 by (C) Copyright 2006 Eric Benard + * eric@eukrea.com + * + * Configuration settings for the CPUAT91 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#ifdef CONFIG_CPUAT91_RAM +#define CONFIG_SKIP_LOWLEVEL_INIT 1 +#define CONFIG_SKIP_RELOCATE_UBOOT 1 +#define CONFIG_CPUAT91 1 +#else +#define CONFIG_BOOTDELAY 1 +#endif + +#define AT91C_MAIN_CLOCK 179712000 +#define AT91C_MASTER_CLOCK 59904000 + +#define AT91_SLOW_CLOCK 32768 + +#define CONFIG_ARM920T 1 +#define CONFIG_AT91RM9200 1 + +#undef CONFIG_USE_IRQ +#define USE_920T_MMU 1 + +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 +/* flash */ +#define CONFIG_SYS_MC_PUIA_VAL 0x00000000 +#define CONFIG_SYS_MC_PUP_VAL 0x00000000 +#define CONFIG_SYS_MC_PUER_VAL 0x00000000 +#define CONFIG_SYS_MC_ASR_VAL 0x00000000 +#define CONFIG_SYS_MC_AASR_VAL 0x00000000 +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 +#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ + +/* clocks */ +#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ +#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz for USB */ +#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock */ + +/* sdram */ +#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as D16/D31 */ +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 +#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ +#define CONFIG_SYS_SDRC_CR_VAL 0x2188C155 /* set up the SDRAM */ +#define CONFIG_SYS_SDRAM 0x20000000 /* address of the SDRAM */ +#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the SDRAM */ +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to SDRAM */ +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + +/* define one of these to choose the DBGU, USART0 or USART1 as console */ +#define CONFIG_AT91RM9200_USART 1 +#define CONFIG_DBGU 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 + +#define CONFIG_HARD_I2C 1 + +#if defined(CONFIG_HARD_I2C) +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 +#endif + +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +#include <config_cmd_default.h> + +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_MII 1 +#define CONFIG_CMD_CACHE 1 +#undef CONFIG_CMD_USB +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_NFS + +#if defined(CONFIG_HARD_I2C) +#define CONFIG_CMD_EEPROM 1 +#define CONFIG_CMD_I2C 1 +#endif + +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x02000000 + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END \ + (CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 512 * 1024) + +#define CONFIG_DRIVER_ETHER 1 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_AT91C_USE_RMII 1 +#define CONFIG_PHY_ADDRESS (1 << 5) +#define CONFIG_KS8721_PHY 1 + +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_EMPTY_INFO 1 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_PROTECTION 1 +#define PHYS_FLASH_1 0x10000000 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MAX_FLASH_SECT 128 + +#if defined(CONFIG_CMD_USB) +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_USB_STORAGE 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_AT91C_PQFP_UHPBU 1 +#undef CONFIG_SYS_USB_OHCI_BOARD_INIT +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 +#endif + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_SECT_SIZE 0x20000 + +#define CONFIG_SYS_LOAD_ADDR 0x21000000 + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } + +#define CONFIG_SYS_PROMPT "CPUAT91=> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SYS_LONGHELP 1 + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) + +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_STACKSIZE (32 * 1024) + +#if defined(CONFIG_USE_IRQ) +#error CONFIG_USE_IRQ not supported +#endif + +#define CONFIG_DEVICE_NULLDEV 1 +#define CONFIG_SILENT_CONSOLE 1 + +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_STOP_STR " " +#define CONFIG_AUTOBOOT_DELAY_STR "d" + +#define CONFIG_VERSION_VARIABLE 1 + +#define MTDIDS_DEFAULT "nor0=physmap-flash.0" +#define MTDPARTS_DEFAULT \ + "mtdparts=physmap-flash.0:" \ + "128k(u-boot)ro," \ + "128k(u-boot-env)," \ + "1408k(kernel)," \ + "-(rootfs)" + +#define CONFIG_BOOTARGS \ + "root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,115200" + +#define CONFIG_BOOTCOMMAND "run flashboot" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtdid=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "flub=tftp 21000000 cpuat91/u-boot.bin; protect off 10000000 " \ + "1001FFFF; erase 10000000 1001FFFF; cp.b 21000000 " \ + "10000000 ${filesize}\0" \ + "flui=tftp 21000000 cpuat91/uImage; protect off 10040000 " \ + "1019ffff; erase 10040000 1019ffff; cp.b 21000000 " \ + "10040000 ${filesize}\0" \ + "flrfs=tftp 21000000 cpuat91/rootfs.jffs2; protect off " \ + "101a0000 10ffffff; erase 101a0000 10ffffff; cp.b " \ + "21000000 101A0000 ${filesize}\0" \ + "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ + "flashboot=run ramargs;bootm 10040000\0" \ + "netboot=run ramargs;tftpboot 21000000 cpuat91/uImage;" \ + "bootm 21000000\0" +#endif /* __CONFIG_H */ diff --git a/include/configs/davinci_dm355evm.h b/include/configs/davinci_dm355evm.h index c35f5c933f..d092fb8325 100644 --- a/include/configs/davinci_dm355evm.h +++ b/include/configs/davinci_dm355evm.h @@ -19,7 +19,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/sizes.h> /* Spectrum Digital TMS320DM355 EVM board */ #define DAVINCI_DM355EVM @@ -40,7 +39,7 @@ /* Memory Info */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 0x80000000 -#define PHYS_SDRAM_1_SIZE SZ_128M +#define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */ /* Serial Driver info: UART0 for console */ #define CONFIG_SYS_NS16550 @@ -66,9 +65,10 @@ #define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */ /* NAND: socketed, two chipselects, normally 2 GBytes */ -/* NYET -- #define CONFIG_NAND_DAVINCI */ -#define CONFIG_SYS_NAND_HW_ECC +#define CONFIG_NAND_DAVINCI #define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST +#define CONFIG_SYS_NAND_PAGE_2K #define CONFIG_SYS_NAND_LARGEPAGE #define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, } @@ -96,15 +96,12 @@ #ifdef CONFIG_NAND_DAVINCI #define CONFIG_CMD_MTDPARTS #define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE #define CONFIG_CMD_NAND #define CONFIG_CMD_UBI #define CONFIG_RBTREE #endif -/* TEMPORARY -- no safe place to save env, yet */ -#define CONFIG_ENV_IS_NOWHERE -#undef CONFIG_CMD_SAVEENV - #ifdef CONFIG_USB_DAVINCI #define CONFIG_MUSB_HCD #define CONFIG_CMD_USB @@ -130,9 +127,14 @@ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_LONGHELP -#define CONFIG_ENV_SIZE SZ_16K +#ifdef CONFIG_NAND_DAVINCI +#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x3C0000 +#undef CONFIG_ENV_IS_IN_FLASH +#endif -/* NYET -- #define CONFIG_BOOTDELAY 5 */ +#define CONFIG_BOOTDELAY 5 #define CONFIG_BOOTCOMMAND \ "dhcp;bootm" #define CONFIG_BOOTARGS \ @@ -146,8 +148,8 @@ #define CONFIG_NET_RETRY_COUNT 10 /* U-Boot memory configuration */ -#define CONFIG_STACKSIZE SZ_256K /* regular stack */ -#define CONFIG_SYS_MALLOC_LEN SZ_512K /* malloc() arena */ +#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */ +#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */ #define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */ #define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */ #define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */ diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h index 47cb554329..2797f827e9 100644 --- a/include/configs/davinci_dm365evm.h +++ b/include/configs/davinci_dm365evm.h @@ -18,7 +18,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/sizes.h> /* Spectrum Digital TMS320DM365 EVM board */ #define DAVINCI_DM365EVM @@ -38,7 +37,7 @@ /* Memory Info */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 0x80000000 -#define PHYS_SDRAM_1_SIZE SZ_128M +#define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */ /* Serial Driver info: UART0 for console */ #define CONFIG_SYS_NS16550 @@ -74,7 +73,6 @@ /* NAND: socketed, two chipselects, normally 2 GBytes */ #define CONFIG_NAND_DAVINCI -#define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST #define CONFIG_SYS_NAND_PAGE_2K @@ -98,7 +96,6 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_PING #define CONFIG_CMD_SAVES -#define CONFIG_CMD_SAVEENV #ifdef CONFIG_NAND_DAVINCI #define CONFIG_CMD_MTDPARTS @@ -125,7 +122,7 @@ #define CONFIG_SYS_LONGHELP #ifdef CONFIG_NAND_DAVINCI -#define CONFIG_ENV_SIZE SZ_256K +#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET 0x3C0000 #undef CONFIG_ENV_IS_IN_FLASH @@ -143,8 +140,8 @@ #define CONFIG_TIMESTAMP /* U-Boot memory configuration */ -#define CONFIG_STACKSIZE SZ_256K /* regular stack */ -#define CONFIG_SYS_MALLOC_LEN SZ_1M /* malloc() arena */ +#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */ +#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */ #define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */ #define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */ #define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */ diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index 96b6afc351..f7d23990c4 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -19,7 +19,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/sizes.h> /* * Define this to make U-Boot skip low level initialization when loaded @@ -120,8 +119,9 @@ #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ #ifdef CONFIG_SYS_NAND_SMALLPAGE #define CONFIG_ENV_SECT_SIZE 512 /* Env sector Size */ -#define CONFIG_ENV_SIZE SZ_16K +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ #define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE #define CONFIG_CMD_MTDPARTS #define MTDIDS_DEFAULT \ "nand0=davinci_nand.0" @@ -129,7 +129,7 @@ "mtdparts=davinci_nand.0:384k(bootloader)ro,4m(kernel),-(filesystem)" #else #define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */ -#define CONFIG_ENV_SIZE SZ_128K +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ #endif #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ #define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h index 79095694ad..9384cddd4d 100644 --- a/include/configs/davinci_schmoogie.h +++ b/include/configs/davinci_schmoogie.h @@ -19,7 +19,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/sizes.h> /*=======*/ /* Board */ @@ -86,7 +85,7 @@ #define CONFIG_NAND_DAVINCI #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ #define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */ -#define CONFIG_ENV_SIZE SZ_128K +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ #define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ #define CONFIG_SYS_NAND_BASE 0x02000000 diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h index 531baf1af9..71d48fb912 100644 --- a/include/configs/davinci_sffsdr.h +++ b/include/configs/davinci_sffsdr.h @@ -22,7 +22,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/sizes.h> /* Board */ #define SFFSDR @@ -81,7 +80,7 @@ #define CONFIG_NAND_DAVINCI #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ #define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */ -#define CONFIG_ENV_SIZE SZ_128K +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ #define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ #define CONFIG_SYS_NAND_BASE 0x02000000 diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index 82901b3933..5a55c569dd 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -19,7 +19,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/sizes.h> /* * Define this to make U-Boot skip low level initialization when loaded @@ -119,7 +118,7 @@ #define CONFIG_SYS_NO_FLASH #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ #define CONFIG_ENV_SECT_SIZE 512 /* Env sector Size */ -#define CONFIG_ENV_SIZE SZ_16K +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ #define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ #define CONFIG_SYS_NAND_BASE 0x02000000 diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index cd40da6320..a8ac786c64 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -98,6 +98,7 @@ #define CONFIG_DOS_PARTITION 1 /* I2C */ +#define CONFIG_HARD_I2C 1 #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 1 #define CONFIG_SYS_I2C_BUS 0 diff --git a/include/configs/ep8248.h b/include/configs/ep8248.h index cb4185a67b..a738425f4f 100644 --- a/include/configs/ep8248.h +++ b/include/configs/ep8248.h @@ -92,6 +92,7 @@ * GPIO pins used for bit-banged MII communications */ #define MDIO_PORT 0 /* Not used - implemented in BCSR */ + #define MDIO_ACTIVE (*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB) #define MDIO_TRISTATE (*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04) #define MDIO_READ (*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1) diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h index 239ff67330..c737f10ec9 100644 --- a/include/configs/ep82xxm.h +++ b/include/configs/ep82xxm.h @@ -85,6 +85,7 @@ * GPIO pins used for bit-banged MII communications */ #define MDIO_PORT 0 /* Not used - implemented in BCSR */ + #define MDIO_ACTIVE (*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB) #define MDIO_TRISTATE (*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04) #define MDIO_READ (*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1) diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h index 3b67ea90bc..931acfbc77 100644 --- a/include/configs/galaxy5200.h +++ b/include/configs/galaxy5200.h @@ -210,7 +210,7 @@ /* Chip Select configuration for NAND flash */ #define CONFIG_SYS_CS1_START 0x20000000 #define CONFIG_SYS_CS1_SIZE 0x90000 -#define CONFIG_SYS_CS1_CFG 0x0002d900 +#define CONFIG_SYS_CS1_CFG 0x00025b00 /* Chip Select configuration for Epson S1D13513 */ #define CONFIG_SYS_CS3_START 0x10000000 diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h index 53a001d211..9ed38463cd 100644 --- a/include/configs/gw8260.h +++ b/include/configs/gw8260.h @@ -212,6 +212,11 @@ * Port pins used for bit-banged MII communictions (if applicable). */ #define MDIO_PORT 2 /* Port C */ + +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE + #define MDIO_ACTIVE (iop->pdir |= 0x00400000) #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) #define MDIO_READ ((iop->pdat & 0x00400000) != 0) diff --git a/include/configs/hymod.h b/include/configs/hymod.h index 284672b338..5a282ff941 100644 --- a/include/configs/hymod.h +++ b/include/configs/hymod.h @@ -93,6 +93,10 @@ # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) # define MDIO_PORT 0 /* Port A */ +# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +# define MDC_DECLARE MDIO_DECLARE + # define MDIO_DATA_PINMASK 0x00040000 /* Pin 13 */ # define MDIO_CLCK_PINMASK 0x00080000 /* Pin 12 */ @@ -110,6 +114,10 @@ # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) # define MDIO_PORT 0 /* Port A */ +# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +# define MDC_DECLARE MDIO_DECLARE + # define MDIO_DATA_PINMASK 0x00000040 /* Pin 25 */ # define MDIO_CLCK_PINMASK 0x00000080 /* Pin 24 */ @@ -127,6 +135,10 @@ # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) # define MDIO_PORT 0 /* Port A */ +# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +# define MDC_DECLARE MDIO_DECLARE + # define MDIO_DATA_PINMASK 0x00000100 /* Pin 23 */ # define MDIO_CLCK_PINMASK 0x00000200 /* Pin 22 */ diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index e5812ee8a2..7ef6385ef8 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -398,7 +398,7 @@ #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5) #elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9) #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5) -#elif +#else #error "Wrong QUART expander number." #endif diff --git a/include/configs/meesc.h b/include/configs/meesc.h index 825317201d..b996854f43 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -36,13 +36,14 @@ #define CONFIG_MEESC 1 /* Board is esd MEESC */ #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_AT91SAM9263 1 /* It's an AT91SAM9263 SoC */ -#define CONFIG_ENV_OVERWRITE 1 /* necessary on prototypes */ #define CONFIG_DISPLAY_BOARDINFO 1 #define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info and speed */ #define CONFIG_PREBOOT /* enable preboot variable */ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 +#define CONFIG_SERIAL_TAG 1 +#define CONFIG_REVISION_TAG 1 #undef CONFIG_USE_IRQ /* don't need IRQ/FIQ stuff */ #define CONFIG_SKIP_LOWLEVEL_INIT @@ -138,12 +139,13 @@ #define CONFIG_SYS_USE_DATAFLASH 1 #undef CONFIG_SYS_USE_NANDFLASH -#ifdef CONFIG_SYS_USE_DATAFLASH - /* CAN */ #define CONFIG_AT91_CAN 1 -/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +/* hw-controller addresses */ +#define CONFIG_ET1100_BASE 0x70000000 + +/* bootstrap + u-boot + env in dataflash on CS0 */ #define CONFIG_ENV_IS_IN_DATAFLASH 1 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ 0x8400) @@ -151,18 +153,6 @@ #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ CONFIG_ENV_OFFSET) #define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_BOOTCOMMAND "cp.b C0042000 22000000 210000; bootm" - -#else /* CONFIG_SYS_USE_NANDFLASH */ - -/* bootstrap + u-boot + env + linux in nandflash */ -#define CONFIG_ENV_IS_IN_NAND 1 -#define CONFIG_ENV_OFFSET 0x60000 -#define CONFIG_ENV_OFFSET_REDUND 0x80000 -#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ -#define CONFIG_BOOTCOMMAND "nand read 22000000 A0000 200000; bootm" - -#endif #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } @@ -178,7 +168,8 @@ /* * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN 0x2D000 +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ + 128*1024, 0x1000) #define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ #define CONFIG_STACKSIZE (32 * 1024) /* regular stack */ diff --git a/include/configs/muas3001.h b/include/configs/muas3001.h index c94daa3d03..43f46bffee 100644 --- a/include/configs/muas3001.h +++ b/include/configs/muas3001.h @@ -101,6 +101,10 @@ * GPIO pins used for bit-banged MII communications */ #define MDIO_PORT 0 /* Port A */ +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE + #define CONFIG_SYS_MDIO_PIN 0x00200000 /* PA10 */ #define CONFIG_SYS_MDC_PIN 0x00400000 /* PA9 */ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 61629f8c4a..55eeb947fe 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -123,6 +123,7 @@ #undef CONFIG_CMD_NFS /* NFS support */ #define CONFIG_SYS_NO_FLASH +#define CONFIG_HARD_I2C 1 #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 1 #define CONFIG_SYS_I2C_BUS 0 diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 9f0f34bd85..72e9626963 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -121,6 +121,7 @@ #undef CONFIG_CMD_IMLS /* List all found images */ #define CONFIG_SYS_NO_FLASH +#define CONFIG_HARD_I2C 1 #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 1 #define CONFIG_SYS_I2C_BUS 0 diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 07a031bc87..1a9192135e 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -28,7 +28,7 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ -#define CONFIG_OMAP3_OVERO 1 /* working with overo */ +#define CONFIG_OMAP3_OVERO 1 /* working with overo */ #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap3.h> @@ -105,10 +105,11 @@ #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ #undef CONFIG_CMD_IMI /* iminfo */ #undef CONFIG_CMD_IMLS /* List all found images */ -#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ #undef CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ #define CONFIG_SYS_NO_FLASH +#define CONFIG_HARD_I2C 1 #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 1 #define CONFIG_SYS_I2C_BUS 0 @@ -293,4 +294,17 @@ extern unsigned int boot_flash_sec; extern unsigned int boot_flash_type; #endif +#if defined(CONFIG_CMD_NET) +/*---------------------------------------------------------------------------- + * SMSC9211 Ethernet from SMSC9118 family + *---------------------------------------------------------------------------- + */ + +#define CONFIG_NET_MULTI +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_32_BIT +#define CONFIG_SMC911X_BASE 0x2C000000 + +#endif /* (CONFIG_CMD_NET) */ + #endif /* __CONFIG_H */ diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 1cfd7e9694..064c0bc690 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -112,6 +112,7 @@ #undef CONFIG_CMD_NFS /* NFS support */ #define CONFIG_SYS_NO_FLASH +#define CONFIG_HARD_I2C 1 #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 1 #define CONFIG_SYS_I2C_BUS 0 diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 61a41e7255..b55b8f0222 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -119,6 +119,7 @@ #undef CONFIG_CMD_NFS /* NFS support */ #define CONFIG_SYS_NO_FLASH +#define CONFIG_HARD_I2C 1 #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 1 #define CONFIG_SYS_I2C_BUS 0 diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index 03f92f58e7..75ab98098c 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -140,6 +140,7 @@ #undef CONFIG_CMD_NFS /* NFS support */ #define CONFIG_SYS_NO_FLASH +#define CONFIG_HARD_I2C 1 #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 1 #define CONFIG_SYS_I2C_BUS 0 diff --git a/include/configs/openrd_base.h b/include/configs/openrd_base.h new file mode 100644 index 0000000000..2aba0cbe98 --- /dev/null +++ b/include/configs/openrd_base.h @@ -0,0 +1,220 @@ +/* + * (C) Copyright 2009 + * Net Insight <www.netinsight.net> + * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net> + * + * Based on sheevaplug.h: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_OPENRD_BASE_H +#define _CONFIG_OPENRD_BASE_H + +/* + * Version number information + */ +#define CONFIG_IDENT_STRING "\nOpenRD_base" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_MARVELL 1 +#define CONFIG_ARM926EJS 1 /* Basic Architecture */ +#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ +#define CONFIG_KW88F6281 1 /* SOC Name */ +#define CONFIG_MACH_OPENRD_BASE /* Machine type */ + +#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ +#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ +#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ + +/* + * CLKs configurations + */ +#define CONFIG_SYS_HZ 1000 + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE + +/* + * Serial Port configuration + * The following definitions let you select what serial you want to use + * for your console driver. + */ + +#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ + 115200,230400, 460800, 921600 } +/* auto boot */ +#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ + +#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#include <config_cmd_default.h> +#define CONFIG_CMD_AUTOSCRIPT +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FAT +#define CONFIG_CMD_NAND +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB + +/* + * NAND configuration + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_KIRKWOOD +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */ +#define NAND_ALLOW_ERASE_ALL 1 +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ +#endif + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ +#else +#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ +#endif +/* + * max 4k env size is enough, but in case of nand + * it has to be rounded to sector size + */ +#define CONFIG_ENV_SIZE 0x20000 /* 128k */ +#define CONFIG_ENV_ADDR 0x60000 +#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ + "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ + "${x_bootcmd_usb}; bootm 0x6400000;" + +#define MTDIDS_DEFAULT "nand0=nand_mtd" +#define MTDPARTS_DEFAULT "mtdparts=nand_mtd:0x100000@0x000000(uboot),"\ + "0x400000@0x100000(uImage),"\ + "0x1fb00000@0x500000(rootfs)" + +#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ + "=ttyS0,115200 "MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \ + "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \ + "x_bootcmd_usb=usb start\0" \ + "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" \ + "mtdids="MTDIDS_DEFAULT"\0" \ + "mtdparts="MTDPARTS_DEFAULT"\0" + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* 1MiB for malloc() */ +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Other required minimal configurations + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ +#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ +#define CONFIG_NR_DRAM_BANKS 4 +#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */ +#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ +#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ +#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ +#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI /* specify more that one ports available */ +#define CONFIG_MII /* expose smi ove miiphy interface */ +#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */ +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ +#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */ +#define CONFIG_PHY_BASE_ADR 0x8 +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ +#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ +#endif /* CONFIG_CMD_NET */ + +/* + * USB/EHCI + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI /* Enable EHCI USB support */ +#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */ +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION +#define CONFIG_SUPPORT_VFAT +#endif /* CONFIG_CMD_USB */ + +/* + * File system + */ +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO + +#endif /* _CONFIG_OPENRD_BASE_H */ diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h index ff7d61439b..f387601861 100644 --- a/include/configs/ppmc8260.h +++ b/include/configs/ppmc8260.h @@ -182,6 +182,10 @@ * Port pins used for bit-banged MII communictions (if applicable). */ #define MDIO_PORT 2 /* Port C */ +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE + #define MDIO_ACTIVE (iop->pdir |= 0x00400000) #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) #define MDIO_READ ((iop->pdat & 0x00400000) != 0) diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h index 0ab6fc31ea..b0198aa06b 100644 --- a/include/configs/sacsng.h +++ b/include/configs/sacsng.h @@ -179,6 +179,10 @@ */ #define MDIO_PORT 2 /* Port A=0, B=1, C=2, D=3 */ +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE + #define MDIO_ACTIVE (iop->pdir |= 0x40000000) #define MDIO_TRISTATE (iop->pdir &= ~0x40000000) #define MDIO_READ ((iop->pdat & 0x40000000) != 0) diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h index 26ed55795e..3fa80a80ec 100644 --- a/include/configs/sbc8260.h +++ b/include/configs/sbc8260.h @@ -201,6 +201,10 @@ * Port pins used for bit-banged MII communictions (if applicable). */ #define MDIO_PORT 2 /* Port C */ +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE + #define MDIO_ACTIVE (iop->pdir |= 0x00400000) #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) #define MDIO_READ ((iop->pdat & 0x00400000) != 0) diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index a6b15f74c9..dab4f801d8 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -293,6 +293,10 @@ * GPIO pins used for bit-banged MII communications */ #define MDIO_PORT 2 /* Port C */ + #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) + #define MDC_DECLARE MDIO_DECLARE + #define MDIO_ACTIVE (iop->pdir |= 0x00400000) #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) #define MDIO_READ ((iop->pdat & 0x00400000) != 0) diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 2865df55e9..682d241d3b 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -121,8 +121,6 @@ #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ #define CONFIG_VERY_BIG_RAM -#define MPC86xx_DDR_SDRAM_CLK_CNTL - #define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) |