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-rw-r--r--include/configs/jetson-tk1.h5
-rw-r--r--include/configs/nyan-big.h14
-rw-r--r--include/configs/tegra-common-post.h4
-rw-r--r--include/configs/tegra-common.h3
-rw-r--r--include/configs/tegra114-common.h7
-rw-r--r--include/configs/tegra124-common.h7
-rw-r--r--include/configs/tegra20-common.h7
-rw-r--r--include/configs/tegra30-common.h7
8 files changed, 33 insertions, 21 deletions
diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h
index 8c016b7955..aeafbd5a6c 100644
--- a/include/configs/jetson-tk1.h
+++ b/include/configs/jetson-tk1.h
@@ -79,4 +79,9 @@
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
+#define CONFIG_ARMV7_PSCI 1
+/* Reserve top 1M for secure RAM */
+#define CONFIG_ARMV7_SECURE_BASE 0xfff00000
+#define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000
+
#endif /* __CONFIG_H */
diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h
index 5397599911..caca98b5a9 100644
--- a/include/configs/nyan-big.h
+++ b/include/configs/nyan-big.h
@@ -21,6 +21,8 @@
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_CMD_I2C
@@ -37,6 +39,18 @@
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
+#define CONFIG_I2C_EDID
+
+/* LCD support */
+#define CONFIG_LCD
+#define CONFIG_PWM_TEGRA
+#define CONFIG_AS3722_POWER
+#define LCD_BPP LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+
+/* Align LCD to 1MB boundary */
+#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
+
/* SPI */
#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */
#define CONFIG_TEGRA114_SPI_CTRLS 6
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
index c3ad8beb90..0cea795de1 100644
--- a/include/configs/tegra-common-post.h
+++ b/include/configs/tegra-common-post.h
@@ -34,7 +34,7 @@
#define STDIN_KBD_USB ""
#endif
-#ifdef CONFIG_VIDEO_TEGRA
+#ifdef CONFIG_LCD
#define STDOUT_LCD ",lcd"
#else
#define STDOUT_LCD ""
@@ -50,6 +50,8 @@
#define BOARD_EXTRA_ENV_SETTINGS
#endif
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
#define CONFIG_EXTRA_ENV_SETTINGS \
TEGRA_DEVICE_SETTINGS \
MEM_LAYOUT_ENV_SETTINGS \
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 2cf1f68404..7ae1792354 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -89,6 +89,9 @@
#define CONFIG_CONSOLE_MUX
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_STDIO_DEREGISTER
+#endif
/*
* Miscellaneous configurable options
diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h
index 9eba5d517d..252e607d73 100644
--- a/include/configs/tegra114-common.h
+++ b/include/configs/tegra114-common.h
@@ -26,13 +26,9 @@
*/
#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
-/* Environment information, boards can override if required */
-#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
-
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */
#define CONFIG_STACKBASE 0x82800000 /* 40MB */
/*-----------------------------------------------------------------------
@@ -64,10 +60,11 @@
* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
*/
+#define CONFIG_LOADADDR 0x81000000
#define MEM_LAYOUT_ENV_SETTINGS \
"scriptaddr=0x90000000\0" \
"pxefile_addr_r=0x90100000\0" \
- "kernel_addr_r=0x81000000\0" \
+ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
"fdt_addr_r=0x82000000\0" \
"ramdisk_addr_r=0x82100000\0"
diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h
index f2b3774da8..1aee5c89f4 100644
--- a/include/configs/tegra124-common.h
+++ b/include/configs/tegra124-common.h
@@ -18,13 +18,9 @@
*/
#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
-/* Environment information, boards can override if required */
-#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
-
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */
#define CONFIG_STACKBASE 0x82800000 /* 40MB */
/*-----------------------------------------------------------------------
@@ -56,10 +52,11 @@
* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
*/
+#define CONFIG_LOADADDR 0x81000000
#define MEM_LAYOUT_ENV_SETTINGS \
"scriptaddr=0x90000000\0" \
"pxefile_addr_r=0x90100000\0" \
- "kernel_addr_r=0x81000000\0" \
+ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
"fdt_addr_r=0x82000000\0" \
"ramdisk_addr_r=0x82100000\0"
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index 6330281df7..0841f33bfc 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -24,13 +24,9 @@
*/
#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
-/* Environment information, boards can override if required */
-#define CONFIG_LOADADDR 0x00408000 /* def. location for kernel */
-
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LOAD_ADDR 0x00A00800 /* default */
#define CONFIG_STACKBASE 0x02800000 /* 40MB */
/*-----------------------------------------------------------------------
@@ -62,10 +58,11 @@
* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
*/
+#define CONFIG_LOADADDR 0x01000000
#define MEM_LAYOUT_ENV_SETTINGS \
"scriptaddr=0x10000000\0" \
"pxefile_addr_r=0x10100000\0" \
- "kernel_addr_r=0x01000000\0" \
+ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
"fdt_addr_r=0x02000000\0" \
"ramdisk_addr_r=0x02100000\0"
diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
index bfdbeb70d2..3e8e3c1e5b 100644
--- a/include/configs/tegra30-common.h
+++ b/include/configs/tegra30-common.h
@@ -23,13 +23,9 @@
*/
#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
-/* Environment information, boards can override if required */
-#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
-
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */
#define CONFIG_STACKBASE 0x82800000 /* 40MB */
/*-----------------------------------------------------------------------
@@ -61,10 +57,11 @@
* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
*/
+#define CONFIG_LOADADDR 0x81000000
#define MEM_LAYOUT_ENV_SETTINGS \
"scriptaddr=0x90000000\0" \
"pxefile_addr_r=0x90100000\0" \
- "kernel_addr_r=0x81000000\0" \
+ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
"fdt_addr_r=0x82000000\0" \
"ramdisk_addr_r=0x82100000\0"
generated by cgit (git 2.34.1) at 2025-01-31 04:55:14 +0000