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-rw-r--r--include/configs/arcangel4-be.h91
-rw-r--r--include/configs/arcangel4.h12
-rw-r--r--include/configs/axs101.h15
-rw-r--r--include/configs/db-mv784mp-gp.h49
-rw-r--r--include/configs/maxbcm.h49
-rw-r--r--include/configs/sheevaplug.h7
-rw-r--r--include/configs/tb100.h10
-rw-r--r--include/configs/uniphier.h19
8 files changed, 116 insertions, 136 deletions
diff --git a/include/configs/arcangel4-be.h b/include/configs/arcangel4-be.h
deleted file mode 100644
index 76163ab2a0..0000000000
--- a/include/configs/arcangel4-be.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _CONFIG_ARCANGEL4_H_
-#define _CONFIG_ARCANGEL4_H_
-
-/*
- * CPU configuration
- */
-#define CONFIG_SYS_BIG_ENDIAN
-#define CONFIG_ARC700
-#define CONFIG_ARC_MMU_VER 3
-#define CONFIG_SYS_CACHELINE_SIZE 64
-#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
-
-/*
- * Board configuration
- */
-#define CONFIG_SYS_GENERIC_BOARD
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */
-
-#define CONFIG_ARCH_EARLY_INIT_R
-
-/*
- * Memory configuration
- */
-#define CONFIG_SYS_TEXT_BASE 0x81000000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */
-
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */
-#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */
-#define CONFIG_SYS_LOAD_ADDR 0x82000000
-
-#define CONFIG_SYS_NO_FLASH
-
-/*
- * UART configuration
- *
- */
-#define CONFIG_ARC_SERIAL
-#define CONFIG_ARC_UART_BASE 0xC0FC1000
-#define CONFIG_BAUDRATE 115200
-
-/*
- * Command line configuration
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-
-#define CONFIG_OF_LIBFDT
-
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_MAXARGS 16
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */
-#define CONFIG_ENV_OFFSET 0
-
-/*
- * Environment configuration
- */
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_BOOTARGS "console=ttyARC0,115200n8"
-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
-
-/*
- * Console configuration
- */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT "arcangel4# "
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-
-#endif /* _CONFIG_ARCANGEL4_H_ */
diff --git a/include/configs/arcangel4.h b/include/configs/arcangel4.h
index 81934a45a8..5e4097fb82 100644
--- a/include/configs/arcangel4.h
+++ b/include/configs/arcangel4.h
@@ -10,23 +10,11 @@
/*
* CPU configuration
*/
-#define CONFIG_ARC700
-#define CONFIG_ARC_MMU_VER 3
-#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/*
- * Board configuration
- */
-#define CONFIG_SYS_GENERIC_BOARD
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */
-
-#define CONFIG_ARCH_EARLY_INIT_R
-
-/*
* Memory configuration
*/
-#define CONFIG_SYS_TEXT_BASE 0x81000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
diff --git a/include/configs/axs101.h b/include/configs/axs101.h
index c61ddd6fb7..5fb8aca4bc 100644
--- a/include/configs/axs101.h
+++ b/include/configs/axs101.h
@@ -10,22 +10,8 @@
/*
* CPU configuration
*/
-#define CONFIG_ARC700
-#define CONFIG_ARC_MMU_VER 3
-#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
-/* NAND controller DMA doesn't work correctly with D$ enabled */
-#define CONFIG_SYS_DCACHE_OFF
-
-/*
- * Board configuration
- */
-#define CONFIG_SYS_GENERIC_BOARD
-#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */
-
-#define CONFIG_ARCH_EARLY_INIT_R
-
#define ARC_FPGA_PERIPHERAL_BASE 0xE0000000
#define ARC_APB_PERIPHERAL_BASE 0xF0000000
#define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000)
@@ -34,7 +20,6 @@
/*
* Memory configuration
*/
-#define CONFIG_SYS_TEXT_BASE 0x81000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index cb03e33b6e..1683a1582f 100644
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -11,6 +11,8 @@
* High Level Configuration Options (easy to change)
*/
#define CONFIG_ARMADA_XP /* SOC Family Name */
+#define CONFIG_DB_784MP_GP /* Board target name for DDR training */
+
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO_LATE
@@ -65,4 +67,51 @@
*/
#include "mv-common.h"
+/*
+ * Memory layout while starting into the bin_hdr via the
+ * BootROM:
+ *
+ * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
+ * 0x4000.4030 bin_hdr start address
+ * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
+ * 0x4007.fffc BootROM stack top
+ *
+ * The address space between 0x4007.fffc and 0x400f.fff is not locked in
+ * L2 cache thus cannot be used.
+ */
+
+/* SPL */
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x40004030
+#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
+
+#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
+#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
+
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
+ CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10)
+
+#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mvebu-common/u-boot-spl.lds"
+
+/* SPL related SPI defines */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+
+/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
+#define CONFIG_SYS_MVEBU_DDR
+#define CONFIG_SPD_EEPROM 0x4e
+
#endif /* _CONFIG_DB_MV7846MP_GP_H */
diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h
index 72217bdb57..5999d60146 100644
--- a/include/configs/maxbcm.h
+++ b/include/configs/maxbcm.h
@@ -43,6 +43,8 @@
#define CONFIG_SF_DEFAULT_SPEED 1000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_BAR
/* Environment in SPI NOR flash */
#define CONFIG_ENV_IS_IN_SPI_FLASH
@@ -65,4 +67,51 @@
*/
#include "mv-common.h"
+/*
+ * Memory layout while starting into the bin_hdr via the
+ * BootROM:
+ *
+ * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
+ * 0x4000.4030 bin_hdr start address
+ * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
+ * 0x4007.fffc BootROM stack top
+ *
+ * The address space between 0x4007.fffc and 0x400f.fff is not locked in
+ * L2 cache thus cannot be used.
+ */
+
+/* SPL */
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x40004030
+#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
+
+#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
+#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
+
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
+ CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10)
+
+#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mvebu-common/u-boot-spl.lds"
+
+/* SPL related SPI defines */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+
+/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
+#define CONFIG_SYS_MVEBU_DDR
+#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */
+
#endif /* _CONFIG_DB_MV7846MP_GP_H */
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
index 21c8bda9f3..84029cb399 100644
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -33,6 +33,11 @@
#define CONFIG_LZO
/*
+ * Enable device tree support
+ */
+#define CONFIG_OF_LIBFDT
+
+/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
@@ -51,6 +56,7 @@
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
+
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
@@ -141,6 +147,5 @@
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_MTDPARTS
-#define CONFIG_LZO
#endif /* _CONFIG_SHEEVAPLUG_H */
diff --git a/include/configs/tb100.h b/include/configs/tb100.h
index e9218f7d81..46df40661d 100644
--- a/include/configs/tb100.h
+++ b/include/configs/tb100.h
@@ -12,21 +12,11 @@
/*
* CPU configuration
*/
-#define CONFIG_ARC700
-#define CONFIG_ARC_MMU_VER 3
-#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/*
- * Board configuration
- */
-#define CONFIG_SYS_GENERIC_BOARD
-#define CONFIG_ARCH_EARLY_INIT_R
-
-/*
* Memory configuration
*/
-#define CONFIG_SYS_TEXT_BASE 0x84000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 9ad47f6933..9420e6b48b 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2012-2014 Panasonic Corporation
+ * Copyright (C) 2012-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -95,6 +95,8 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_MISC_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_BOARD_LATE_INIT
@@ -235,11 +237,16 @@
"image_offset=0x00080000\0" \
"image_size=0x00f00000\0" \
"verify=n\0" \
- "norboot=run add_default_bootargs;" \
+ "nandupdate=nand erase 0 0x100000 &&" \
+ "tftpboot u-boot-spl.bin &&" \
+ "nand write $loadaddr 0 0x10000 &&" \
+ "tftpboot u-boot-dtb.img &&" \
+ "nand write $loadaddr 0x10000 0xf0000\0" \
+ "norboot=run add_default_bootargs &&" \
"bootm $image_offset\0" \
- "nandboot=run add_default_bootargs;" \
- "nand read $loadaddr $image_offset $image_size;" \
- "bootm\0" \
+ "nandboot=run add_default_bootargs &&" \
+ "nand read $loadaddr $image_offset $image_size &&" \
+ "bootm\0" \
"add_default_bootargs=setenv bootargs $bootargs" \
" console=ttyS0,$baudrate\0" \
@@ -269,8 +276,6 @@
#define CONFIG_SPL_TEXT_BASE 0x00100000
#endif
-#define CONFIG_BOARD_POSTCLK_INIT
-
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
generated by cgit (git 2.34.1) at 2025-01-31 02:44:10 +0000