diff options
Diffstat (limited to 'include/configs')
94 files changed, 5070 insertions, 781 deletions
diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 9e0ee371c2..9adbba9544 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -53,9 +53,13 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 + #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ @@ -144,40 +148,18 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ - -#define CFG_NAND_LEGACY - -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) - -#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */ -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ + +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_QUIET 1 /*----------------------------------------------------------------------- * PCI stuff diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h index 62a2eaa236..0321650f3d 100644 --- a/include/configs/CATcenter.h +++ b/include/configs/CATcenter.h @@ -399,6 +399,8 @@ #define CFG_ENV_ADDR_REDUND 0xFFFFA000 #define CFG_ENV_SIZE_REDUND 0x2000 +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + #define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ #define CFG_NVRAM_SIZE 242 /* NVRAM size */ diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index 08ef9b5da6..21cd9c1f26 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -90,8 +90,6 @@ #define CONFIG_CMD_EEPROM -#define CFG_NAND_LEGACY - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ @@ -157,36 +155,18 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) - -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ + +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_QUIET 1 /*----------------------------------------------------------------------- * PCI stuff diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index 0a4e1e9d30..1b948f6382 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -92,8 +92,6 @@ #define CONFIG_SUPPORT_VFAT -#define CFG_NAND_LEGACY - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index ceeba6e122..fb71c5fb04 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -114,8 +114,6 @@ #define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ #endif -#define CFG_NAND_LEGACY - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index 1aefbbac68..49943195b7 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -100,9 +100,6 @@ #define CONFIG_SUPPORT_VFAT -#define CFG_NAND_LEGACY - - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index e2652e6aa6..29f9292447 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -111,8 +111,6 @@ #undef CONFIG_AUTO_UPDATE /* autoupdate via compactflash */ -#define CFG_NAND_LEGACY - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h index a8697ec88d..dae5295dd1 100644 --- a/include/configs/EB+MCF-EV123.h +++ b/include/configs/EB+MCF-EV123.h @@ -40,9 +40,8 @@ #define CONFIG_MISC_INIT_R -#define FEC_ENET -#define CONFIG_ETHADDR 00:CF:52:82:EB:01 - +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 9600 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } @@ -84,7 +83,39 @@ #include <config_cmd_default.h> #undef CONFIG_CMD_LOADB +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET + +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif +#ifdef CONFIG_MCFFEC +# define CONFIG_ETHADDR 00:CF:52:82:EB:01 +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* CONFIG_MCFFEC */ #define CONFIG_BOOTDELAY 5 #define CFG_PROMPT "\nEV123 U-Boot> " @@ -122,9 +153,6 @@ */ #define CFG_MBAR 0x40000000 -#define CFG_DISCOVER_PHY -/* #define CFG_ENET_BD_BASE 0x380000 */ - /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ @@ -151,6 +179,7 @@ #define CFG_FLASH_BASE 0xFFE00000 #define CFG_INT_FLASH_BASE 0xF0000000 +#define CFG_INT_FLASH_ENABLE 0x21 /* If M5282 port is fully implemented the monitor base will be behind * the vector table. */ diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h index a562b2fa4e..f810af2cec 100644 --- a/include/configs/FADS823.h +++ b/include/configs/FADS823.h @@ -206,6 +206,7 @@ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ #define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- * Cache Configuration diff --git a/include/configs/FADS850SAR.h b/include/configs/FADS850SAR.h index c8ce25957b..a09c0e0393 100644 --- a/include/configs/FADS850SAR.h +++ b/include/configs/FADS850SAR.h @@ -156,6 +156,7 @@ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ #define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- * Cache Configuration diff --git a/include/configs/FPS850L.h b/include/configs/FPS850L.h index 322158c7b8..3b0ddb4ec6 100644 --- a/include/configs/FPS850L.h +++ b/include/configs/FPS850L.h @@ -39,28 +39,44 @@ #undef CONFIG_8xx_CONS_SMC1 #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ #undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 19200 -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_BOOTCOMMAND "bootm 40020000" /* autoboot command */ +#define CONFIG_BAUDRATE 115200 -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ +#define CONFIG_BOOTCOUNT_LIMIT + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOARD_TYPES 1 /* support board types */ -#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ - "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ - "nfsaddrs=10.0.0.99:10.0.0.2" +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_8xx\0" \ + "bootfile=/tftpboot/fps850L/uImage\0" \ + "fdt_addr=40040000\0" \ + "kernel_addr=40060000\0" \ + "ramdisk_addr=40200000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ #undef CONFIG_WATCHDOG /* watchdog disabled */ - /* * BOOTP options */ @@ -80,24 +96,32 @@ #define CONFIG_BOOTP_NTPSERVER #define CONFIG_BOOTP_TIMEOFFSET +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ /* * Command line configuration. */ #include <config_cmd_default.h> -#undef CONFIG_CMD_CONSOLE -#undef CONFIG_CMD_BDI -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_LOADB -#undef CONFIG_CMD_CACHE +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + #if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else diff --git a/include/configs/FPS860L.h b/include/configs/FPS860L.h index f8698b5708..6fec07540c 100644 --- a/include/configs/FPS860L.h +++ b/include/configs/FPS860L.h @@ -40,18 +40,37 @@ #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 115200 -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else + +#define CONFIG_BOOTCOUNT_LIMIT + #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif -#define CONFIG_BOOTCOMMAND "bootm 40040000" /* autoboot command */ #define CONFIG_BOARD_TYPES 1 /* support board types */ -#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ - "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ - "nfsaddrs=10.0.0.99:10.0.0.2" +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_8xx\0" \ + "bootfile=/tftpboot/fps850L/uImage\0" \ + "fdt_addr=40040000\0" \ + "kernel_addr=40060000\0" \ + "ramdisk_addr=40200000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ @@ -79,11 +98,11 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - /* * Command line configuration. */ #include <config_cmd_default.h> + #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP @@ -95,7 +114,14 @@ * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + #if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 00f481c4b5..8967b3fc60 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -141,8 +141,6 @@ #define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ #undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */ -#define CFG_NAND_LEGACY - #undef CONFIG_BZIP2 /* include support for bzip2 compressed images */ #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -209,36 +207,18 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) - -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ + +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_QUIET 1 /*----------------------------------------------------------------------- * PCI stuff diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index 661b895f9a..1ff7108130 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -147,38 +147,18 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_NAND_LEGACY - -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) - -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ + +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_QUIET 1 /*----------------------------------------------------------------------- * PCI stuff diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h index 27a5bc302f..da54cef534 100644 --- a/include/configs/ICU862.h +++ b/include/configs/ICU862.h @@ -234,6 +234,7 @@ #define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment sector */ #define CFG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */ +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- * Cache Configuration diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index 532615485c..4c16d22959 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -178,12 +178,9 @@ #endif /* CONFIG_MPC5200 */ /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,5200@0" #define OF_SOC "soc5200@f0000000" #define OF_TBCLK (bd->bi_busfreq / 4) diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h new file mode 100644 index 0000000000..7f544c839f --- /dev/null +++ b/include/configs/M5235EVB.h @@ -0,0 +1,261 @@ +/* + * Configuation settings for the Freescale MCF5329 FireEngine board. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M5235EVB_H +#define _M5235EVB_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCF523x /* define processor family */ +#define CONFIG_M5235 /* define processor type */ + +#undef DEBUG + +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* Command line configuration */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS + +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif + +/* Timer */ +#define CONFIG_MCFTMR +#undef CONFIG_MCFPIT + +/* I2C */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C /* I2C with hw support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 80000 +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_OFFSET 0x00000300 +#define CFG_IMMR CFG_MBAR + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ +#define CONFIG_BOOTFILE "u-boot.bin" +#ifdef CONFIG_MCFFEC +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* FEC_ENET */ + +#define CONFIG_HOSTNAME M5235EVB +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=10000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off ffe00000 ffe3ffff;" \ + "era ffe00000 ffe3ffff;" \ + "cp.b ${loadaddr} ffe00000 ${filesize};"\ + "save\0" \ + "" + +#define CONFIG_PRAM 512 /* 512 KB */ +#define CFG_PROMPT "-> " +#define CFG_LONGHELP /* undef to save memory */ + +#if defined(CONFIG_KGDB) +# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE+0x20000) + +#define CFG_HZ 1000 +#define CFG_CLK 75000000 +#define CFG_CPU_CLK CFG_CLK * 2 + +#define CFG_MBAR 0x40000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x20000000 +#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ +#define CFG_INIT_RAM_CTRL 0x21 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE - 0x10) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ + +#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 +#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) + +#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +#define CFG_BOOTPARAMS_LEN 64*1024 +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +/* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_FLASH_CFI +#ifdef CFG_FLASH_CFI +# define CFG_FLASH_CFI_DRIVER 1 +# define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */ +#ifdef NORFLASH_PS32BIT +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT +#else +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#endif +# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +#endif + +#define CFG_FLASH_BASE (CFG_CS0_BASE << 16) + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_IS_EMBEDDED 1 +#ifdef NORFLASH_PS32BIT +# define CFG_ENV_OFFSET (0x8000) +# define CFG_ENV_SIZE 0x4000 +# define CFG_ENV_SECT_SIZE 0x4000 +#else +# define CFG_ENV_OFFSET (0x4000) +# define CFG_ENV_SIZE 0x2000 +# define CFG_ENV_SECT_SIZE 0x2000 +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 + +/*----------------------------------------------------------------------- + * Chipselect bank definitions + */ +/* + * CS0 - NOR Flash 1, 2, 4, or 8MB + * CS1 - Available + * CS2 - Available + * CS3 - Available + * CS4 - Available + * CS5 - Available + * CS6 - Available + * CS7 - Available + */ +#ifdef NORFLASH_PS32BIT +# define CFG_CS0_BASE 0xFFC0 +# define CFG_CS0_MASK 0x003f0001 +# define CFG_CS0_CTRL 0x1D00 +#else +# define CFG_CS0_BASE 0xFFE0 +# define CFG_CS0_MASK 0x001f0001 +# define CFG_CS0_CTRL 0x1D80 +#endif + +#endif /* _M5329EVB_H */ diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h new file mode 100644 index 0000000000..de7ea42930 --- /dev/null +++ b/include/configs/M5249EVB.h @@ -0,0 +1,194 @@ +/* + * Configuation settings for the esd TASREG board. + * + * (C) Copyright 2004 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M5249EVB_H +#define _M5249EVB_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCF52x2 /* define processor family */ +#define CONFIG_M5249 /* define processor type */ + +#define CONFIG_MCFTMR + +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) +#define CONFIG_BAUDRATE 19200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG + +#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ + +/* + * BOOTP options + */ +#undef CONFIG_BOOTP_BOOTFILESIZE +#undef CONFIG_BOOTP_BOOTPATH +#undef CONFIG_BOOTP_GATEWAY +#undef CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_NET + +#define CFG_PROMPT "=> " +#define CFG_LONGHELP /* undef to save memory */ + +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup */ +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ + +#define CFG_LOAD_ADDR 0x200000 /* default load address */ + +#define CFG_MEMTEST_START 0x400 +#define CFG_MEMTEST_END 0x380000 + +#define CFG_HZ 1000 + +/* + * Clock configuration: enable only one of the following options + */ + +#undef CFG_PLL_BYPASS /* bypass PLL for test purpose */ +#define CFG_FAST_CLK 1 /* MCF5249 can run at 140MHz */ +#define CFG_CLK 132025600 /* MCF5249 can run at 140MHz */ + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CFG_MBAR 0x10000000 /* Register Base Addrs */ +#define CFG_MBAR2 0x80000000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x20000000 +#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x4000 /* Address of Environment Sector*/ +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x2000 /* see README - env sector total size */ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_FLASH_BASE (CFG_CSAR0 << 16) + +#if 0 /* test-only */ +#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ +#endif + +#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) + +#define CFG_MONITOR_LEN 0x20000 +#define CFG_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */ +#define CFG_BOOTPARAMS_LEN 64*1024 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_FLASH_CFI +#ifdef CFG_FLASH_CFI + +# define CFG_FLASH_CFI_DRIVER 1 +# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +# define CFG_FLASH_CHECKSUM +# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 + +/*----------------------------------------------------------------------- + * Memory bank definitions + */ + +/* CS0 - AMD Flash, address 0xffc00000 */ +#define CFG_CSAR0 0xffe0 +#define CFG_CSCR0 0x1980 /* WS=0110, AA=1, PS=10 */ +/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ +#define CFG_CSMR0 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ + +/* CS1 - FPGA, address 0xe0000000 */ +#define CFG_CSAR1 0xe000 +#define CFG_CSCR1 0x0d80 /* WS=0011, AA=1, PS=10 */ +#define CFG_CSMR1 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ + +/*----------------------------------------------------------------------- + * Port configuration + */ +#define CFG_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ +#define CFG_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ +#define CFG_GPIO_EN 0x00000008 /* Set gpio output enable */ +#define CFG_GPIO1_EN 0x00c70000 /* Set gpio output enable */ +#define CFG_GPIO_OUT 0x00000008 /* Set outputs to default state */ +#define CFG_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ +#define CFG_GPIO1_LED 0x00400000 /* user led */ + +#endif /* M5249 */ diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h new file mode 100644 index 0000000000..48170e7a35 --- /dev/null +++ b/include/configs/M5253EVBE.h @@ -0,0 +1,212 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Hayden Fraser (Hayden.Fraser@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _M5253EVBE_H +#define _M5253EVBE_H + +#define CONFIG_MCF52x2 /* define processor family */ +#define CONFIG_M5253 /* define processor type */ +#define CONFIG_M5253EVBE /* define board type */ + +#define CONFIG_MCFTMR + +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) +#define CONFIG_BAUDRATE 19200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG /* disable watchdog */ + +#define CONFIG_BOOTDELAY 5 + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ +#ifndef CONFIG_MONITOR_IS_IN_RAM +#define CFG_ENV_OFFSET 0x4000 +#define CFG_ENV_SECT_SIZE 0x2000 +#define CFG_ENV_IS_IN_FLASH 1 +#else +#define CFG_ENV_ADDR 0xffe04000 +#define CFG_ENV_SECT_SIZE 0x2000 +#define CFG_ENV_IS_IN_FLASH 1 +#endif + +/* + * BOOTP options + */ +#undef CONFIG_BOOTP_BOOTFILESIZE +#undef CONFIG_BOOTP_BOOTPATH +#undef CONFIG_BOOTP_GATEWAY +#undef CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_NET +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_IDE +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC + +/* ATA */ +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_IDE_RESET 1 +#define CONFIG_IDE_PREINIT 1 +#define CONFIG_ATAPI +#undef CONFIG_LBA48 + +#define CFG_IDE_MAXBUS 1 +#define CFG_IDE_MAXDEVICE 2 + +#define CFG_ATA_BASE_ADDR (CFG_MBAR2 + 0x800) +#define CFG_ATA_IDE0_OFFSET 0 + +#define CFG_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ +#define CFG_ATA_STRIDE 4 /* Interval between registers */ +#define _IO_BASE 0 + +#define CFG_PROMPT "=> " +#define CFG_LONGHELP /* undef to save memory */ + +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_LOAD_ADDR 0x00100000 + +#define CFG_MEMTEST_START 0x400 +#define CFG_MEMTEST_END 0x380000 + +#define CFG_HZ 1000 + +#undef CFG_PLL_BYPASS /* bypass PLL for test purpose */ +#define CFG_FAST_CLK +#ifdef CFG_FAST_CLK +# define CFG_PLLCR 0x1243E054 +# define CFG_CLK 140000000 +#else +# define CFG_PLLCR 0x135a4140 +# define CFG_CLK 70000000 +#endif + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +#define CFG_MBAR 0x10000000 /* Register Base Addrs */ +#define CFG_MBAR2 0x80000000 /* Module Base Addrs 2 */ + +/* + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x20000000 +#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ + +#ifdef CONFIG_MONITOR_IS_IN_RAM +#define CFG_MONITOR_BASE 0x20000 +#else +#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#endif + +#define CFG_MONITOR_LEN 0x40000 +#define CFG_MALLOC_LEN (256 << 10) +#define CFG_BOOTPARAMS_LEN (64*1024) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) + +/* FLASH organization */ +#define CFG_FLASH_BASE 0xffe00000 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 1000 + +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#define CFG_FLASH_SIZE 0x200000 +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +/* Cache Configuration */ +#define CFG_CACHELINE_SIZE 16 + +/* Port configuration */ +#define CFG_FECI2C 0xF0 + +#define CFG_CSAR0 0xFFE0 +#define CFG_CSMR0 0x001F0021 +#define CFG_CSCR0 0x1D80 + +#define CFG_CSAR1 0 +#define CFG_CSMR1 0 +#define CFG_CSCR1 0 + +#define CFG_CSAR2 0 +#define CFG_CSMR2 0 +#define CFG_CSCR2 0 + +#define CFG_CSAR3 0 +#define CFG_CSMR3 0 +#define CFG_CSCR3 0 + +/*----------------------------------------------------------------------- + * Port configuration + */ +#define CFG_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ +#define CFG_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ +#define CFG_GPIO_EN 0x00000008 /* Set gpio output enable */ +#define CFG_GPIO1_EN 0x00c70000 /* Set gpio output enable */ +#define CFG_GPIO_OUT 0x00000008 /* Set outputs to default state */ +#define CFG_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ +#define CFG_GPIO1_LED 0x00400000 /* user led */ + +#endif /* _M5253EVB_H */ diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h index 885a8821bf..798ec0c7a4 100644 --- a/include/configs/M5271EVB.h +++ b/include/configs/M5271EVB.h @@ -31,7 +31,6 @@ #ifndef _M5271EVB_H #define _M5271EVB_H -#define DEBUG #undef DEBUG /* @@ -41,29 +40,26 @@ #define CONFIG_M5271 /* define processor type */ #define CONFIG_M5271EVB /* define board type */ -#define CONFIG_IPADDR 192.168.30.1 -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_ETHADDR 00:06:3b:01:41:55 +#define CONFIG_MCFTMR +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 19200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } #undef CONFIG_WATCHDOG /* disable watchdog */ -#define CONFIG_BOOTDELAY 5 - /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash */ #ifndef CONFIG_MONITOR_IS_IN_RAM #define CFG_ENV_OFFSET 0x4000 -#define CFG_ENV_SECT_SIZE 0x2000 -#define CFG_ENV_IS_IN_FLASH 1 #else #define CFG_ENV_ADDR 0xffe04000 +#endif #define CFG_ENV_SECT_SIZE 0x2000 #define CFG_ENV_IS_IN_FLASH 1 -#endif +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /* * BOOTP options @@ -73,7 +69,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - /* * Command line configuration. */ @@ -81,22 +76,83 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_LOADB +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif + +/* I2C */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C /* I2C with hw support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 80000 +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_OFFSET 0x00000300 +#define CFG_IMMR CFG_MBAR + +#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ +#define CONFIG_BOOTFILE "u-boot.bin" +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_RETRY_COUNT 5 +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* FEC_ENET */ + +#define CONFIG_HOSTNAME M5235EVB +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=10000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off ffe00000 ffe2ffff;" \ + "era ffe00000 ffe2ffff;" \ + "cp.b ${loadaddr} 0 ${filesize};" \ + "save\0" \ + "" #define CFG_PROMPT "=> " -#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LONGHELP /* undef to save memory */ #if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_LOAD_ADDR 0x00100000 @@ -114,16 +170,11 @@ #define CFG_MBAR 0x40000000 /* Register Base Addrs */ -/* Enable FEC ethernet */ -#define FEC_ENET -#define CONFIG_NET_RETRY_COUNT 5 -#define CFG_ENET_BD_BASE 0x480000 - /* * Definitions for initial stack pointer and data area (in DPRAM) */ #define CFG_INIT_RAM_ADDR 0x20000000 -#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -134,7 +185,7 @@ * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ #define CFG_FLASH_BASE 0xffe00000 #ifdef CONFIG_MONITOR_IS_IN_RAM @@ -152,11 +203,11 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) /* FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ #define CFG_FLASH_ERASE_TOUT 1000 #define CFG_FLASH_CFI 1 @@ -169,4 +220,4 @@ /* Port configuration */ #define CFG_FECI2C 0xF0 -#endif /* _M5271EVB_H */ +#endif /* _M5271EVB_H */ diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index cc456dc08a..2b8734b4c6 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -33,18 +33,20 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5272 /* define processor type */ +#define CONFIG_MCF52x2 /* define processor family */ +#define CONFIG_M5272 /* define processor type */ -#define FEC_ENET +#define CONFIG_MCFTMR +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 19200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } -#define CONFIG_WATCHDOG +#undef CONFIG_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ -#define CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ +#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -60,7 +62,6 @@ #define CFG_ENV_IS_IN_FLASH 1 #endif - /* * BOOTP options */ @@ -69,37 +70,82 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - /* * Command line configuration. */ #include <config_cmd_default.h> #define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_MISC +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_MEMORY #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_LOADB - #define CONFIG_BOOTDELAY 5 +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif + +#ifdef CONFIG_MCFFEC +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* CONFIG_MCFFEC */ + +#define CONFIG_HOSTNAME M5272C3 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=10000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off ffe00000 ffe3ffff;" \ + "era ffe00000 ffe3ffff;" \ + "cp.b ${loadaddr} ffe00000 ${filesize};"\ + "save\0" \ + "" #define CFG_PROMPT "-> " -#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LONGHELP /* undef to save memory */ #if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_LOAD_ADDR 0x20000 - #define CFG_MEMTEST_START 0x400 #define CFG_MEMTEST_END 0x380000 - #define CFG_HZ 1000 #define CFG_CLK 66000000 @@ -108,20 +154,15 @@ * (address mappings, register initial values, etc.) * You should know what you are doing if you make changes here. */ - #define CFG_MBAR 0x10000000 /* Register Base Addrs */ - #define CFG_SCR 0x0003; #define CFG_SPR 0xffff; -#define CFG_DISCOVER_PHY -#define CFG_ENET_BD_BASE 0x380000 - /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ #define CFG_INIT_RAM_ADDR 0x20000000 -#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -132,7 +173,7 @@ * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */ +#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */ #define CFG_FLASH_BASE 0xffe00000 #ifdef CONFIG_MONITOR_IS_IN_RAM @@ -150,13 +191,13 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ #define CFG_FLASH_ERASE_TOUT 1000 /*----------------------------------------------------------------------- @@ -169,25 +210,18 @@ */ #define CFG_BR0_PRELIM 0xFFE00201 #define CFG_OR0_PRELIM 0xFFE00014 - #define CFG_BR1_PRELIM 0 #define CFG_OR1_PRELIM 0 - #define CFG_BR2_PRELIM 0x30000001 #define CFG_OR2_PRELIM 0xFFF80000 - #define CFG_BR3_PRELIM 0 #define CFG_OR3_PRELIM 0 - #define CFG_BR4_PRELIM 0 #define CFG_OR4_PRELIM 0 - #define CFG_BR5_PRELIM 0 #define CFG_OR5_PRELIM 0 - #define CFG_BR6_PRELIM 0 #define CFG_OR6_PRELIM 0 - #define CFG_BR7_PRELIM 0x00000701 #define CFG_OR7_PRELIM 0xFFC0007C @@ -197,9 +231,8 @@ #define CFG_PACNT 0x00000000 #define CFG_PADDR 0x0000 #define CFG_PADAT 0x0000 -#define CFG_PBCNT 0x55554155 /* Ethernet/UART configuration */ +#define CFG_PBCNT 0x55554155 /* Ethernet/UART configuration */ #define CFG_PBDDR 0x0000 #define CFG_PBDAT 0x0000 #define CFG_PDCNT 0x00000000 - -#endif /* _M5272C3_H */ +#endif /* _M5272C3_H */ diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index f2a7644930..3c17c1ea14 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -33,15 +33,17 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5282 /* define processor type */ +#define CONFIG_MCF52x2 /* define processor family */ +#define CONFIG_M5282 /* define processor type */ -#define FEC_ENET +#define CONFIG_MCFTMR +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 19200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } -#define CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ +#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -50,7 +52,6 @@ #define CFG_ENV_SIZE 0x2000 #define CFG_ENV_IS_IN_FLASH 1 - /* * BOOTP options */ @@ -59,29 +60,73 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - /* * Command line configuration. */ #include <config_cmd_default.h> +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_LOADB +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif #define CONFIG_BOOTDELAY 5 +#ifdef CONFIG_MCFFEC +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* CONFIG_MCFFEC */ + +#define CONFIG_HOSTNAME M5272C3 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=10000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off ffe00000 ffe3ffff;" \ + "era ffe00000 ffe3ffff;" \ + "cp.b ${loadaddr} ffe00000 ${filesize};"\ + "save\0" \ + "" #define CFG_PROMPT "-> " -#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LONGHELP /* undef to save memory */ #if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_LOAD_ADDR 0x20000 @@ -91,6 +136,10 @@ #define CFG_HZ 1000000 #define CFG_CLK 64000000 +/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ + +#define CFG_MFD 0x02 /* PLL Multiplication Factor Devider */ +#define CFG_RFD 0x00 /* PLL Reduce Frecuency Devider */ /* * Low Level Configuration Settings @@ -99,15 +148,12 @@ */ #define CFG_MBAR 0x40000000 -#undef CFG_DISCOVER_PHY -#define CFG_ENET_BD_BASE 0x380000 - /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CFG_INIT_RAM_ADDR 0x20000000 -#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_INIT_RAM_ADDR 0x20000000 +#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -117,49 +163,88 @@ * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */ +#define CFG_SDRAM_SIZE 8 /* SDRAM size in MB */ #define CFG_FLASH_BASE 0xffe00000 #define CFG_INT_FLASH_BASE 0xf0000000 +#define CFG_INT_FLASH_ENABLE 0x21 /* If M5282 port is fully implemented the monitor base will be behind * the vector table. */ -/* #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) */ -#define CFG_MONITOR_BASE 0x20000 +#if (TEXT_BASE != CFG_INT_FLASH_BASE) +#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#else +#define CFG_MONITOR_BASE (TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */ +#endif #define CFG_MONITOR_LEN 0x20000 #define CFG_MALLOC_LEN (256 << 10) #define CFG_BOOTPARAMS_LEN 64*1024 - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_SECT 35 -#define CFG_MAX_FLASH_BANKS 1 -#define CFG_FLASH_ERASE_TOUT 10000000 +#define CFG_FLASH_CFI +#ifdef CFG_FLASH_CFI + +# define CFG_FLASH_CFI_DRIVER 1 +# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +# define CFG_FLASH_CHECKSUM +# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#endif /*----------------------------------------------------------------------- * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 - /*----------------------------------------------------------------------- * Memory bank definitions */ - - +#define CFG_CS0_BASE CFG_FLASH_BASE +#define CFG_CS0_SIZE 2*1024*1024 +#define CFG_CS0_WIDTH 16 +#define CFG_CS0_RO 0 +#define CFG_CS0_WS 6 +/* +#define CFG_CS3_BASE 0xE0000000 +#define CFG_CS3_SIZE 1*1024*1024 +#define CFG_CS3_WIDTH 16 +#define CFG_CS3_RO 0 +#define CFG_CS3_WS 6 +*/ /*----------------------------------------------------------------------- * Port configuration */ +#define CFG_PACNT 0x0000000 /* Port A D[31:24] */ +#define CFG_PADDR 0x0000000 +#define CFG_PADAT 0x0000000 + +#define CFG_PBCNT 0x0000000 /* Port B D[23:16] */ +#define CFG_PBDDR 0x0000000 +#define CFG_PBDAT 0x0000000 + +#define CFG_PCCNT 0x0000000 /* Port C D[15:08] */ +#define CFG_PCDDR 0x0000000 +#define CFG_PCDAT 0x0000000 + +#define CFG_PDCNT 0x0000000 /* Port D D[07:00] */ +#define CFG_PCDDR 0x0000000 +#define CFG_PCDAT 0x0000000 +#define CFG_PEHLPAR 0xC0 +#define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ +#define CFG_DDRUA 0x05 +#define CFG_PJPAR 0xFF; -#endif /* _CONFIG_M5282EVB_H */ +#endif /* _CONFIG_M5282EVB_H */ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h new file mode 100644 index 0000000000..d3b160505b --- /dev/null +++ b/include/configs/M5329EVB.h @@ -0,0 +1,267 @@ +/* + * Configuation settings for the Freescale MCF5329 FireEngine board. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M5329EVB_H +#define _M5329EVB_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCF532x /* define processor family */ +#define CONFIG_M5329 /* define processor type */ + +#undef DEBUG + +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ + +/* Command line configuration */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +#ifdef NANDFLASH_SIZE +# define CONFIG_CMD_NAND +#endif + +#define CFG_UNIFY_CACHE + +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif + +#define CONFIG_MCFRTC +#undef RTC_DEBUG + +/* Timer */ +#define CONFIG_MCFTMR +#undef CONFIG_MCFPIT + +/* I2C */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C /* I2C with hw support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 80000 +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_OFFSET 0x58000 +#define CFG_IMMR CFG_MBAR + +#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ +#define CONFIG_UDP_CHECKSUM + +#ifdef CONFIG_MCFFEC +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* FEC_ENET */ + +#define CONFIG_HOSTNAME M5329EVB +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=40010000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off 0 2ffff;" \ + "era 0 2ffff;" \ + "cp.b ${loadaddr} 0 ${filesize};" \ + "save\0" \ + "" + +#define CONFIG_PRAM 512 /* 512 KB */ +#define CFG_PROMPT "-> " +#define CFG_LONGHELP /* undef to save memory */ + +#ifdef CONFIG_CMD_KGDB +# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x40010000 + +#define CFG_HZ 1000 +#define CFG_CLK 80000000 +#define CFG_CPU_CLK CFG_CLK * 3 + +#define CFG_MBAR 0xFC000000 + +#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000) + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x80000000 +#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ +#define CFG_INIT_RAM_CTRL 0x221 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x40000000 +#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SDRAM_CFG1 0x53722730 +#define CFG_SDRAM_CFG2 0x56670000 +#define CFG_SDRAM_CTRL 0xE1092000 +#define CFG_SDRAM_EMOD 0x40010000 +#define CFG_SDRAM_MODE 0x018D0000 + +#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 +#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) + +#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +#define CFG_BOOTPARAMS_LEN 64*1024 +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_FLASH_CFI +#ifdef CFG_FLASH_CFI +# define CFG_FLASH_CFI_DRIVER 1 +# define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +#endif + +#ifdef NANDFLASH_SIZE +# define CFG_MAX_NAND_DEVICE 1 +# define CFG_NAND_BASE (CFG_CS2_BASE << 16) +# define CFG_NAND_SIZE 1 +# define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +# define NAND_MAX_CHIPS 1 +# define NAND_ALLOW_ERASE_ALL 1 +# define CONFIG_JFFS2_NAND 1 +# define CONFIG_JFFS2_DEV "nand0" +# define CONFIG_JFFS2_PART_SIZE (CFG_CS2_MASK & ~1) +# define CONFIG_JFFS2_PART_OFFSET 0x00000000 +#endif + +#define CFG_FLASH_BASE (CFG_CS0_BASE << 16) + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ +#define CFG_ENV_OFFSET 0x4000 +#define CFG_ENV_SECT_SIZE 0x2000 +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_IS_EMBEDDED 1 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 + +/*----------------------------------------------------------------------- + * Chipselect bank definitions + */ +/* + * CS0 - NOR Flash 1, 2, 4, or 8MB + * CS1 - CompactFlash and registers + * CS2 - NAND Flash 16, 32, or 64MB + * CS3 - Available + * CS4 - Available + * CS5 - Available + */ +#define CFG_CS0_BASE 0 +#define CFG_CS0_MASK 0x007f0001 +#define CFG_CS0_CTRL 0x00001fa0 + +#define CFG_CS1_BASE 0x1000 +#define CFG_CS1_MASK 0x001f0001 +#define CFG_CS1_CTRL 0x002A3780 + +#ifdef NANDFLASH_SIZE +#define CFG_CS2_BASE 0x2000 +#define CFG_CS2_MASK ((NANDFLASH_SIZE << 20) | 1) +#define CFG_CS2_CTRL 0x00001f60 +#endif + +#endif /* _M5329EVB_H */ diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h new file mode 100644 index 0000000000..6f4859c238 --- /dev/null +++ b/include/configs/M54455EVB.h @@ -0,0 +1,391 @@ +/* + * Configuation settings for the Freescale MCF54455 EVB board. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _JAMICA54455_H +#define _JAMICA54455_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCF5445x /* define processor family */ +#define CONFIG_M54455 /* define processor type */ +#define CONFIG_M54455EVB /* M54455EVB board */ + +#undef DEBUG + +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* Command line configuration */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS + +/* Network configuration */ +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CONFIG_CF_DOMII +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC1_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +# define CONFIG_HAS_ETH1 + +# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ +# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 +# define CONFIG_ETHPRIME "FEC0" +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE + +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif + +#define CONFIG_HOSTNAME M54455EVB +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \ + "loadaddr=40010000\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off 0 2ffff;" \ + "era 0 2ffff;" \ + "cp.b ${loadaddr} 0 ${filesize};" \ + "save\0" \ + "" + +/* ATA configuration */ +#define CONFIG_ISO_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_IDE_RESET 1 +#define CONFIG_IDE_PREINIT 1 +#define CONFIG_ATAPI +#undef CONFIG_LBA48 + +#define CFG_IDE_MAXBUS 1 +#define CFG_IDE_MAXDEVICE 2 + +#define CFG_ATA_BASE_ADDR 0x90000000 +#define CFG_ATA_IDE0_OFFSET 0 + +#define CFG_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ +#define CFG_ATA_STRIDE 4 /* Interval between registers */ +#define _IO_BASE 0 + +/* Realtime clock */ +#define CONFIG_MCFRTC +#undef RTC_DEBUG +#define CFG_RTC_OSCILLATOR (32 * CFG_HZ) + +/* Timer */ +#define CONFIG_MCFTMR +#undef CONFIG_MCFPIT + +/* I2c */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 80000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_OFFSET 0x58000 +#define CFG_IMMR CFG_MBAR + +/* PCI */ +#define CONFIG_PCI 1 + +#define CFG_PCI_MEM_BUS 0xA0000000 +#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS +#define CFG_PCI_MEM_SIZE 0x10000000 + +#define CFG_PCI_IO_BUS 0xB1000000 +#define CFG_PCI_IO_PHYS CFG_PCI_IO_BUS +#define CFG_PCI_IO_SIZE 0x01000000 + +#define CFG_PCI_CFG_BUS 0xB0000000 +#define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS +#define CFG_PCI_CFG_SIZE 0x01000000 + +/* FPGA - Spartan 2 */ +/* experiment +#define CONFIG_FPGA CFG_SPARTAN3 +#define CONFIG_FPGA_COUNT 1 +#define CFG_FPGA_PROG_FEEDBACK +#define CFG_FPGA_CHECK_CTRLC +*/ + +/* Input, PCI, Flexbus, and VCO */ +#define CONFIG_EXTRA_CLOCK + +#define CONFIG_PRAM 512 /* 512 KB */ + +#define CFG_PROMPT "-> " +#define CFG_LONGHELP /* undef to save memory */ + +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x10000) + +#define CFG_HZ 1000 + +#define CFG_MBAR 0xFC000000 + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x80000000 +#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ +#define CFG_INIT_RAM_CTRL 0x221 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 16) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x40000000 +#define CFG_SDRAM_BASE1 0x48000000 +#define CFG_SDRAM_SIZE 256 /* SDRAM size in MB */ +#define CFG_SDRAM_CFG1 0x65311610 +#define CFG_SDRAM_CFG2 0x59670000 +#define CFG_SDRAM_CTRL 0xEA0B2000 +#define CFG_SDRAM_EMOD 0x40010000 +#define CFG_SDRAM_MODE 0x00010033 + +#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 +#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) + +#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#define CFG_BOOTPARAMS_LEN 64*1024 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +/* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ +#define CFG_ENV_OFFSET 0x4000 +#define CFG_ENV_SECT_SIZE 0x2000 +#define CFG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OVERWRITE 1 +#undef CFG_ENV_IS_EMBEDDED + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#ifdef CFG_ATMEL_BOOT +# define CFG_FLASH_BASE 0 +# define CFG_FLASH0_BASE CFG_CS0_BASE +# define CFG_FLASH1_BASE CFG_CS1_BASE +#else +# define CFG_FLASH_BASE CFG_FLASH0_BASE +# define CFG_FLASH0_BASE CFG_CS1_BASE +# define CFG_FLASH1_BASE CFG_CS0_BASE +#endif + +/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system +/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system + keep reset. */ +#undef CFG_FLASH_CFI +#ifdef CFG_FLASH_CFI + +# define CFG_FLASH_CFI_DRIVER 1 +# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT +# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +# define CFG_FLASH_CHECKSUM +# define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE, CFG_CS1_BASE } + +#else + +# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ + +# define CFG_ATMEL_REGION 4 +# define CFG_ATMEL_TOTALSECT 11 +# define CFG_ATMEL_SECT {1, 2, 1, 7} +# define CFG_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} +# define CFG_INTEL_SECT 137 + +/* max number of sectors on one chip */ +# define CFG_MAX_FLASH_SECT (CFG_ATMEL_TOTALSECT + CFG_INTEL_SECT) +# define CFG_FLASH_ERASE_TOUT 2000 /* Atmel needs longer timeout */ +# define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ +# define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ +# define CFG_FLASH_UNLOCK_TOUT 100 /* Timeout for Flash Clear Lock Bits (in ms) */ +# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +# define CFG_FLASH_CHECKSUM + +#endif + +/* + * This is setting for JFFS2 support in u-boot. + * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. + */ +#ifdef CFG_ATMEL_BOOT +# define CONFIG_JFFS2_DEV "nor0" +# define CONFIG_JFFS2_PART_SIZE 0x01000000 +# define CONFIG_JFFS2_PART_OFFSET CFG_FLASH1_BASE +#else +# define CONFIG_JFFS2_DEV "nor0" +# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) +# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000) +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 + +/*----------------------------------------------------------------------- + * Memory bank definitions + */ +/* + * CS0 - NOR Flash 1, 2, 4, or 8MB + * CS1 - CompactFlash and registers + * CS2 - CPLD + * CS3 - FPGA + * CS4 - Available + * CS5 - Available + */ + +#ifdef CFG_ATMEL_BOOT + /* Atmel Flash */ +#define CFG_CS0_BASE 0 +#define CFG_CS0_MASK 0x00070001 +#define CFG_CS0_CTRL 0x00001140 +/* Intel Flash */ +#define CFG_CS1_BASE 0x04000000 +#define CFG_CS1_MASK 0x01FF0001 +#define CFG_CS1_CTRL 0x003F3D60 + +#define CFG_ATMEL_BASE CFG_CS0_BASE +#else +/* Intel Flash */ +#define CFG_CS0_BASE 0 +#define CFG_CS0_MASK 0x01FF0001 +#define CFG_CS0_CTRL 0x003F3D60 + /* Atmel Flash */ +#define CFG_CS1_BASE 0x04000000 +#define CFG_CS1_MASK 0x00070001 +#define CFG_CS1_CTRL 0x00001140 + +#define CFG_ATMEL_BASE CFG_CS1_BASE +#endif + +/* CPLD */ +#define CFG_CS2_BASE 0x08000000 +#define CFG_CS2_MASK 0x00070001 +#define CFG_CS2_CTRL 0x003f1140 + +/* FPGA */ +#define CFG_CS3_BASE 0x09000000 +#define CFG_CS3_MASK 0x00070001 +#define CFG_CS3_CTRL 0x00000020 + +#endif /* _JAMICA54455_H */ diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 81db96f466..6568fe13b8 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -113,12 +113,12 @@ /* 0x03200064 */ #if defined(CONFIG_DDR_2T_TIMING) #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ - | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ | SDRAM_CFG_2T_EN \ | SDRAM_CFG_DBW_32 ) #else #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ - | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ | SDRAM_CFG_32_BE ) /* 0x43080000 */ #endif @@ -228,12 +228,9 @@ #define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8313@0" #define OF_SOC "soc8313@e0000000" #define OF_TBCLK (bd->bi_busfreq / 4) @@ -310,6 +307,8 @@ #define CONFIG_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 0x1c #define TSEC2_PHY_ADDR 4 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 @@ -507,6 +506,7 @@ #define CONFIG_ETHADDR 00:E0:0C:00:95:01 #define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH0 #define CONFIG_ETH1ADDR 00:E0:0C:00:95:02 #define CONFIG_IPADDR 10.0.0.2 diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index f62ca2c42b..c9c6d88cf0 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -30,6 +30,8 @@ #define CONFIG_MPC83XX 1 /* MPC83xx family */ #define CONFIG_MPC832X 1 /* MPC832x CPU specific */ #define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */ +#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */ +#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */ /* * System Clock Setup @@ -87,6 +89,7 @@ #define CFG_SICRL 0x00000000 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ +#define CONFIG_BOARD_EARLY_INIT_R /* * IMMR new address @@ -315,12 +318,9 @@ #endif /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8323@0" #define OF_SOC "soc8323@e0000000" #define OF_QE "qe@e0100000" diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 1567fcfae3..92555bac42 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -339,12 +339,9 @@ #endif /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8349@0" #define OF_SOC "soc8349@e0000000" #define OF_TBCLK (bd->bi_busfreq / 4) @@ -440,6 +437,8 @@ #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" @@ -699,6 +698,7 @@ #if defined(CONFIG_TSEC_ENET) #define CONFIG_ETHADDR 00:04:9f:ef:23:33 #define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH0 #define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21 #endif diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 44649d0509..54cab528bd 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -296,12 +296,9 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8349@0" #define OF_SOC "soc8349@e0000000" #define OF_TBCLK (bd->bi_busfreq / 4) @@ -378,10 +375,12 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_TSEC1 #ifdef CONFIG_TSEC1 +#define CONFIG_HAS_ETH0 #define CONFIG_TSEC1_NAME "TSEC0" #define CFG_TSEC1_OFFSET 0x24000 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ #define TSEC1_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT #endif #ifdef CONFIG_TSEC2 @@ -391,6 +390,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ #define TSEC2_PHY_ADDR 4 #define TSEC2_PHYIDX 0 +#define TSEC2_FLAGS TSEC_GIGABIT #endif #define CONFIG_ETHPRIME "Freescale TSEC" diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 4b32a140e8..41f062ce72 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -32,6 +32,8 @@ #define CONFIG_MPC83XX 1 /* MPC83XX family */ #define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ #define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */ +#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */ +#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */ /* * System Clock Setup @@ -88,6 +90,7 @@ #define CFG_SICRL 0x40000000 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ +#define CONFIG_BOARD_EARLY_INIT_R /* * IMMR new address @@ -309,13 +312,13 @@ /* * CS4 on Local Bus, to PIB */ -#define CFG_BR4_PRELIM 0xf8008801 /* CS4 base address at 0xf8008000 */ +#define CFG_BR4_PRELIM 0xf8010801 /* CS4 base address at 0xf8010000 */ #define CFG_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ /* * CS5 on Local Bus, to PIB */ -#define CFG_BR5_PRELIM 0xf8010801 /* CS5 base address at 0xf8010000 */ +#define CFG_BR5_PRELIM 0xf8008801 /* CS5 base address at 0xf8008000 */ #define CFG_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ /* @@ -348,10 +351,6 @@ #define CONFIG_OF_HAS_BD_T 1 #define CONFIG_OF_HAS_UBOOT_ENV 1 - -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8360@0" #define OF_SOC "soc8360@e0000000" #define OF_QE "qe@e0100000" diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 5a7c879a53..be603ac117 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -301,9 +301,6 @@ #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8540@0" #define OF_SOC "soc8540@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) @@ -374,6 +371,8 @@ #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #if CONFIG_HAS_FEC @@ -381,6 +380,7 @@ #define CONFIG_MPC85XX_FEC_NAME "FEC" #define FEC_PHY_ADDR 3 #define FEC_PHYIDX 0 +#define FEC_FLAGS 0 #endif /* Options are: TSEC[0-1], FEC */ @@ -489,6 +489,7 @@ /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index 0ce25cf24e..e376c11656 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -213,10 +213,13 @@ #define CONFIG_NET_MULTI 1 #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_TSEC1 1 +#define CONFIG_HAS_ETH0 #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 +#define CONFIG_HAS_ETH1 #define CONFIG_TSEC2_NAME "TSEC1" #define CONFIG_MPC85XX_FEC 1 +#define CONFIG_HAS_ETH2 #define CONFIG_MPC85XX_FEC_NAME "FEC" #define TSEC1_PHY_ADDR 7 #define TSEC2_PHY_ADDR 4 @@ -224,6 +227,10 @@ #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 #define FEC_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT +#define FEC_FLAGS 0 + /* Options are: TSEC[0-1], FEC */ #define CONFIG_ETHPRIME "TSEC0" diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 50d3b6b872..4e061bd9ff 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -312,9 +312,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8541@0" #define OF_SOC "soc8541@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) @@ -350,6 +347,13 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI2_IO_PHYS 0xe2100000 #define CFG_PCI2_IO_SIZE 0x100000 /* 1M */ +#ifdef CONFIG_LEGACY +#define BRIDGE_ID 17 +#define VIA_ID 2 +#else +#define BRIDGE_ID 28 +#define VIA_ID 4 +#endif #if defined(CONFIG_PCI) @@ -377,13 +381,12 @@ extern unsigned long get_clock_freq(void); #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 -#define FEC_PHY_ADDR 3 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 -#define FEC_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" @@ -475,6 +478,7 @@ extern unsigned long get_clock_freq(void); /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index d0f94a3e22..f580ccadee 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -34,14 +34,14 @@ #define CONFIG_MPC8544 1 #define CONFIG_MPC8544DS 1 -#undef CONFIG_PCI /* Enable PCI/PCIE */ -#undef CONFIG_PCI1 /* PCI controller 1 */ -#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ -#undef CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ -#undef CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */ -#undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */ - -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#define CONFIG_PCI1 1 /* PCI controller 1 */ +#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ +#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ + +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #undef CONFIG_DDR_DLL @@ -52,6 +52,7 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_DDR_ECC_CMD +#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ /* * When initializing flash, if we cannot find the manufacturer ID, @@ -70,7 +71,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ #define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ @@ -86,13 +87,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ #define CFG_MEMTEST_END 0x00400000 #define CFG_ALT_MEMTEST -#define CONFIG_PANIC_HANG /* do not reset board on panic */ +#define CONFIG_PANIC_HANG /* do not reset board on panic */ /* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ @@ -180,6 +181,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ +#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ #define PIXIS_ID 0x0 /* Board ID at offset 0 */ #define PIXIS_VER 0x1 /* Board version at offset 1 */ @@ -251,9 +253,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8544@0" #define OF_SOC "soc8544@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) @@ -281,7 +280,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CFG_PCI1_IO_BASE 0x00000000 #define CFG_PCI1_IO_PHYS 0xe1000000 -#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ +#define CFG_PCI1_IO_SIZE 0x00010000 /* 64k */ /* PCI view of System Memory */ #define CFG_PCI_MEMORY_BUS 0x00000000 @@ -293,27 +292,27 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE #define CFG_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CFG_PCIE2_IO_BASE 0x00000000 -#define CFG_PCIE2_IO_PHYS 0xe2000000 -#define CFG_PCIE2_IO_SIZE 0x00100000 /* 1M */ +#define CFG_PCIE2_IO_PHYS 0xe1010000 +#define CFG_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 2,tgtid 2, Base address a000 */ #define CFG_PCIE1_MEM_BASE 0xa0000000 #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE -#define CFG_PCIE1_MEM_SIZE 0x08000000 /* 128M */ -#define CFG_PCIE1_MEM_BASE2 0xa8000000 -#define CFG_PCIE1_MEM_PHYS2 CFG_PCIE1_MEM_BASE2 -#define CFG_PCIE1_MEM_SIZE2 0x04000000 /* 64M */ -#define CFG_PCIE1_IO_BASE 0x00000000 /* reuse mem LAW */ -#define CFG_PCIE1_IO_PHYS 0xaf000000 -#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ +#define CFG_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCIE1_IO_BASE 0x00000000 +#define CFG_PCIE1_IO_PHYS 0xe1020000 +#define CFG_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 3, direct to uli, tgtid 3, Base address b000 */ #define CFG_PCIE3_MEM_BASE 0xb0000000 #define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE -#define CFG_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCIE3_MEM_SIZE 0x00100000 /* 1M */ #define CFG_PCIE3_IO_BASE 0x00000000 -#define CFG_PCIE3_IO_PHYS 0xe3000000 +#define CFG_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ #define CFG_PCIE3_IO_SIZE 0x00100000 /* 1M */ +#define CFG_PCIE3_MEM_BASE2 0xb0200000 +#define CFG_PCIE3_MEM_PHYS2 CFG_PCIE3_MEM_BASE2 +#define CFG_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ #if defined(CONFIG_PCI) @@ -344,7 +343,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SATA_ULI5288 #define CFG_SCSI_MAX_SCSI_ID 4 #define CFG_SCSI_MAX_LUN 1 -#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) +#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) #define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE #endif /* SCSCI */ @@ -354,7 +353,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #endif #define CONFIG_MII 1 /* MII PHY management */ @@ -363,18 +362,19 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_TSEC1_NAME "eTSEC1" #define CONFIG_TSEC3 1 #define CONFIG_TSEC3_NAME "eTSEC3" -#undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC3_PHY_ADDR 1 +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + #define TSEC1_PHYIDX 0 #define TSEC3_PHYIDX 0 #define CONFIG_ETHPRIME "eTSEC1" #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ - #endif /* CONFIG_TSEC_ENET */ /* @@ -392,7 +392,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - /* * BOOTP options */ @@ -415,6 +414,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CMD_PCI #define CONFIG_CMD_BEDBUG #define CONFIG_CMD_NET + #define CONFIG_CMD_SCSI + #define CONFIG_CMD_EXT2 #endif @@ -441,10 +442,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ /* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 +#define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 #if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ @@ -469,6 +470,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD @@ -482,7 +484,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_HOSTNAME 8544ds_unknown #define CONFIG_ROOTPATH /nfs/mpc85xx -#define CONFIG_BOOTFILE 8544ds_tmt/uImage.uboot +#define CONFIG_BOOTFILE 8544ds/uImage.uboot +#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ #define CONFIG_SERVERIP 192.168.0.1 #define CONFIG_GATEWAYIP 192.168.0.1 @@ -491,7 +494,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ #define CONFIG_BAUDRATE 115200 @@ -499,10 +502,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define PCIE_ENV \ "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ - "pcie1regs=setenv a e000a; run pciereg\0" \ - "pcie2regs=setenv a e0009; run pciereg\0" \ - "pcie3regs=setenv a e000b; run pciereg\0" \ - "pcieerr=md ${a}020 1; md ${a}e00;" \ + "pcieerr=md ${a}020 1; md ${a}e00 e;" \ "pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ "pci d.w $b.0 56 1;" \ "pci d $b.0 104 1;pci d $b.0 110 1;pci d $b.0 130 1\0" \ @@ -511,12 +511,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); "pci w $b.0 104 ffffffff; pci w $b.0 110 ffffffff;" \ "pci w $b.0 130 ffffffff\0" \ "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ - "pcie1err=setenv a e000a; run pcieerr\0" \ - "pcie2err=setenv a e0009; run pcieerr\0" \ - "pcie3err=setenv a e000b; run pcieerr\0" \ - "pcie1errc=setenv a e000a; run pcieerrc\0" \ - "pcie2errc=setenv a e0009; run pcieerrc\0" \ - "pcie3errc=setenv a e000b; run pcieerrc\0" + "pcie1regs=setenv a e000a; run pciereg\0" \ + "pcie2regs=setenv a e0009; run pciereg\0" \ + "pcie3regs=setenv a e000b; run pciereg\0" \ + "pcie1cfg=setenv b 3; run pciecfg\0" \ + "pcie2cfg=setenv b 5; run pciecfg\0" \ + "pcie3cfg=setenv b 0; run pciecfg\0" \ + "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \ + "pcie2err=setenv a e0009; setenv b 5; run pcieerr\0" \ + "pcie3err=setenv a e000b; setenv b 0; run pcieerr\0" \ + "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0" \ + "pcie2errc=setenv a e0009; setenv b 5; run pcieerrc\0" \ + "pcie3errc=setenv a e000b; setenv b 0; run pcieerrc\0" #else #define PCIE_ENV "" #endif @@ -524,14 +530,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #if defined(CONFIG_PCI1) #define PCI_ENV \ "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ - "echo e;md ${a}e00 9\0" \ + "echo e;md ${a}e00 9\0" \ "pci1regs=setenv a e0008; run pcireg\0" \ "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ "pci d.w $b.0 56 1\0" \ - "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ - "pci w.w $b.0 56 ffff\0" \ - "pci1err=setenv a e0008; run pcierr\0" \ - "pci1errc=setenv a e0008; run pcierrc\0" + "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \ + "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0" \ + "pci1err=setenv a e0008; setenv b 7; run pcierr\0" \ + "pci1errc=setenv a e0008; setenv b 7; run pcierrc\0" #else #define PCI_ENV "" #endif @@ -551,25 +557,39 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define ENET_ENV "" #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ - "ramdiskfile=8544ds_tmt/ramdisk.uboot\0" \ - "fdtaddr=400000\0" \ - "fdtfile=8544ds_tmt/mpc8544ds.dtb\0" \ - "eoi=mw e00400b0 0\0" \ - "iack=md e00400a0 1\0" \ + "ramdiskfile=8544ds/ramdisk.uboot\0" \ + "dtbaddr=c00000\0" \ + "dtbfile=8544ds/mpc8544ds.dtb\0" \ + "bdev=sda3\0" \ + "eoi=mw e00400b0 0\0" \ + "iack=md e00400a0 1\0" \ "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \ "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \ - "ddrregs=setenv a e0002; run ddrreg\0" \ + "ddrregs=setenv a e0002; run ddrreg\0" \ "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \ - "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \ - "guregs=setenv a e00e0; run gureg\0" \ + "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \ + "guregs=setenv a e00e0; run gureg\0" \ "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \ - "ecmregs=setenv a e0001; run ecmreg\0" \ - PCIE_ENV \ - PCI_ENV \ + "ecmregs=setenv a e0001; run ecmreg\0" \ + "lawregs=md e0000c08 4b\0" \ + "lbcregs=md e0005000 36\0" \ + "dma0regs=md e0021100 12\0" \ + "dma1regs=md e0021180 12\0" \ + "dma2regs=md e0021200 12\0" \ + "dma3regs=md e0021280 12\0" \ + PCIE_ENV \ + PCI_ENV \ ENET_ENV @@ -579,23 +599,23 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr - $dtbaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr $ramdiskaddr $dtbaddr" -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/sda3 rw " \ +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr - $dtbaddr" #endif /* __CONFIG_H */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 2e84fc8748..6083715189 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004, 2007 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -11,7 +11,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -36,8 +36,14 @@ #define CONFIG_MPC8548 1 /* MPC8548 specific */ #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ -#define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_PCI /* enable any pci type devices */ +#define CONFIG_PCI1 /* PCI controller 1 */ +#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ +#undef CONFIG_RIO +#undef CONFIG_PCI2 +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ + +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ @@ -46,6 +52,7 @@ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ /* @@ -65,16 +72,16 @@ extern unsigned long get_clock_freq(void); /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ +#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ /* * Only possible on E500 Version 2 or newer cores. */ #define CONFIG_ENABLE_36BIT_PHYS 1 - #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #undef CFG_DRAM_TEST /* memory test, takes time */ @@ -85,10 +92,14 @@ extern unsigned long get_clock_freq(void); * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ +#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) +#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) +#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) + /* * DDR Setup */ @@ -106,7 +117,6 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_CLOCKS_IN_MHZ - /* * Local Bus Definitions */ @@ -124,9 +134,9 @@ extern unsigned long get_clock_freq(void); * Use GPCM = BRx[24:26] = 000 * Valid = BRx[31] = 1 * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 - * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 + * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 * * OR0, OR1: * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 @@ -137,11 +147,12 @@ extern unsigned long get_clock_freq(void); * TRLX = use relaxed timing = ORx[29] = 1 * EAD = use external address latch delay = OR[31] = 1 * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx */ -#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */ +#define CFG_BOOT_BLOCK 0xff000000 /* boot TLB block */ +#define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 16M */ #define CFG_BR0_PRELIM 0xff801001 #define CFG_BR1_PRELIM 0xff001001 @@ -156,7 +167,7 @@ extern unsigned long get_clock_freq(void); #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI @@ -166,7 +177,12 @@ extern unsigned long get_clock_freq(void); /* * SDRAM on the Local Bus */ -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ +#define CFG_LBC_CACHE_SIZE 64 +#define CFG_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */ +#define CFG_LBC_NONCACHE_SIZE 64 + +#define CFG_LBC_SDRAM_BASE CFG_LBC_CACHE_BASE /* Localbus SDRAM */ #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ /* @@ -180,14 +196,14 @@ extern unsigned long get_clock_freq(void); * SDRAM for MSEL = BR2[24:26] = 011 * Valid = BR[31] = 1 * - * 0 4 8 12 16 20 24 28 + * 0 4 8 12 16 20 24 28 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 * * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into * FIXME: the top 17 bits of BR2. */ -#define CFG_BR2_PRELIM 0xf0001861 +#define CFG_BR2_PRELIM 0xf0001861 /* * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. @@ -196,19 +212,19 @@ extern unsigned long get_clock_freq(void); * 64MB mask for AM, OR2[0:7] = 1111 1100 * XAM, OR2[17:18] = 11 * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 + * 13 rows OR2[23-25] = 100 * EAD set for extra time OR[31] = 1 * - * 0 4 8 12 16 20 24 28 + * 0 4 8 12 16 20 24 28 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 */ #define CFG_OR2_PRELIM 0xfc006901 -#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ +#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ /* * LSDMR masks @@ -236,7 +252,7 @@ extern unsigned long get_clock_freq(void); /* * Common settings for all Local Bus SDRAM commands. * At run time, either BSMA1516 (for CPU 1.1) - * or BSMA1617 (for CPU 1.0) (old) + * or BSMA1617 (for CPU 1.0) (old) * is OR'ed in too. */ #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ @@ -256,61 +272,63 @@ extern unsigned long get_clock_freq(void); * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 * port-size = 8-bits = BR[19:20] = 01 * no parity checking = BR[21:22] = 00 - * GPMC for MSEL = BR[24:26] = 000 - * Valid = BR[31] = 1 + * GPMC for MSEL = BR[24:26] = 000 + * Valid = BR[31] = 1 * - * 0 4 8 12 16 20 24 28 + * 0 4 8 12 16 20 24 28 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 * * For OR3, need: - * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 + * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 * disable buffer ctrl OR[19] = 0 - * CSNT OR[20] = 1 - * ACS OR[21:22] = 11 - * XACS OR[23] = 1 + * CSNT OR[20] = 1 + * ACS OR[21:22] = 11 + * XACS OR[23] = 1 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe - * SETA OR[28] = 0 - * TRLX OR[29] = 1 - * EHTR OR[30] = 1 - * EAD extra time OR[31] = 1 + * SETA OR[28] = 0 + * TRLX OR[29] = 1 + * EHTR OR[30] = 1 + * EAD extra time OR[31] = 1 * - * 0 4 8 12 16 20 24 28 + * 0 4 8 12 16 20 24 28 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 */ #define CADMUS_BASE_ADDR 0xf8000000 -#define CFG_BR3_PRELIM 0xf8000801 -#define CFG_OR3_PRELIM 0xfff00ff7 +#define CFG_BR3_PRELIM 0xf8000801 +#define CFG_OR3_PRELIM 0xfff00ff7 #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_LOCK 1 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ -#define CONFIG_CONS_INDEX 2 +#define CONFIG_CONS_INDEX 2 #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CFG_NS16550 #define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_REG_SIZE 1 #define CFG_NS16550_CLK get_bus_freq(0) -#define CFG_BAUDRATE_TABLE \ +#define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) /* Use the HUSH parser */ #define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif @@ -318,9 +336,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8548@0" #define OF_SOC "soc8548@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) @@ -331,55 +346,74 @@ extern unsigned long get_clock_freq(void); */ #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3000 /* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ +#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */ + #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CFG_PCI1_IO_BASE 0x00000000 #define CFG_PCI1_IO_PHYS 0xe2000000 -#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */ +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ -#define CFG_PCI2_MEM_BASE 0x90000000 +#ifdef CONFIG_PCI2 +#define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE -#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ #define CFG_PCI2_IO_BASE 0x00000000 #define CFG_PCI2_IO_PHYS 0xe2800000 -#define CFG_PCI2_IO_SIZE 0x00800000 /* 8M */ +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ +#endif -#define CFG_PEX_MEM_BASE 0xa0000000 -#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE -#define CFG_PEX_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PEX_IO_BASE 0x00000000 -#define CFG_PEX_IO_PHYS 0xe3000000 -#define CFG_PEX_IO_SIZE 0x01000000 /* 16M */ +#ifdef CONFIG_PCIE1 +#define CFG_PCIE1_MEM_BASE 0xa0000000 +#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE +#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCIE1_IO_BASE 0x00000000 +#define CFG_PCIE1_IO_PHYS 0xe3000000 +#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ +#endif +#ifdef CONFIG_RIO /* * RapidIO MMU */ #define CFG_RIO_MEM_BASE 0xC0000000 #define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */ +#endif + +#ifdef CONFIG_LEGACY +#define BRIDGE_ID 17 +#define VIA_ID 2 +#else +#define BRIDGE_ID 28 +#define VIA_ID 4 +#endif #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_85XX_PCI2 +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 #endif /* CONFIG_PCI */ @@ -387,7 +421,7 @@ extern unsigned long get_clock_freq(void); #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #endif #define CONFIG_MII 1 /* MII PHY management */ @@ -397,7 +431,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_TSEC2_NAME "eTSEC1" #define CONFIG_TSEC3 1 #define CONFIG_TSEC3_NAME "eTSEC2" -#undef CONFIG_TSEC4 +#define CONFIG_TSEC4 #define CONFIG_TSEC4_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC @@ -410,10 +444,14 @@ extern unsigned long get_clock_freq(void); #define TSEC2_PHYIDX 0 #define TSEC3_PHYIDX 0 #define TSEC4_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) /* Options are: eTSEC[0-3] */ #define CONFIG_ETHPRIME "eTSEC0" - +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ #endif /* CONFIG_TSEC_ENET */ /* @@ -473,7 +511,7 @@ extern unsigned long get_clock_freq(void); * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ /* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 @@ -501,58 +539,154 @@ extern unsigned long get_clock_freq(void); /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) -#define CONFIG_ETHADDR 00:E0:0C:00:00:FD +#define CONFIG_HAS_ETH0 +#define CONFIG_ETHADDR 00:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD +#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD #define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD #define CONFIG_HAS_ETH3 -#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD +#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD #endif -#define CONFIG_IPADDR 192.168.1.253 +#define CONFIG_IPADDR 192.168.1.253 -#define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH /nfsroot -#define CONFIG_BOOTFILE your.uImage +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH /nfsroot +#define CONFIG_BOOTFILE 8548cds/uImage.uboot +#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ -#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_SERVERIP 192.168.1.1 #define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ +#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ #define CONFIG_BAUDRATE 115200 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS1\0" \ - "ramdiskaddr=600000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=400000\0" \ - "fdtfile=your.fdt.dtb\0" +#if defined(CONFIG_PCIE1) +#define PCIE_ENV \ + "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ + "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ + "pcieerr=md ${a}020 1; md ${a}e00 e; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ + "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ + "pci d $b.0 130 1\0" \ + "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;" \ + "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;"\ + "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ + "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ + "pcie1regs=setenv a e000a; run pciereg\0" \ + "pcie1cfg=setenv b 3; run pciecfg\0" \ + "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \ + "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0" +#else +#define PCIE_ENV "" +#endif + +#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2) +#define PCI_ENV \ + "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ + "echo e;md ${a}e00 9\0" \ + "pcierr=md ${a}e00 8; pci d.b $b.0 7 1;pci d.w $b.0 1e 1;" \ + "pci d.w $b.0 56 1\0" \ + "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \ + "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0" +#else +#define PCI_ENV "" +#endif +#if defined(CONFIG_PCI1) +#define PCI_ENV1 \ + "pci1regs=setenv a e0008; run pcireg\0" \ + "pci1err=setenv a e0008; setenv b 0; run pcierr\0" \ + "pci1errc=setenv a e0008; setenv b 0; run pcierrc\0" +#else +#define PCI_ENV1 "" +#endif -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ +#if defined(CONFIG_PCI2) +#define PCI_ENV2 \ + "pci2regs=setenv a e0009; run pcireg\0" \ + "pci2err=setenv a e0009; setenv b 123; run pcierr\0" \ + "pci2errc=setenv a e0009; setenv b 123; run pcierrc\0" +#else +#define PCI_ENV2 "" +#endif + +#if defined(CONFIG_TSEC_ENET) +#define ENET_ENV \ + "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \ + "md ${a}098 2\0" \ + "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \ + "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \ + "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \ + "echo mib;md ${a}680 31\0" \ + "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \ + "enet1regs=setenv a e0024; run enetreg\0" \ + "enet2regs=setenv a e0025; run enetreg\0" \ + "enet3regs=setenv a e0026; run enetreg\0" \ + "enet4regs=setenv a e0027; run enetreg\0" +#else +#define ENET_ENV "" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "consoledev=ttyS1\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=mpc8548cds.dtb\0" \ + "eoi=mw e00400b0 0\0" \ + "iack=md e00400a0 1\0" \ + "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \ + "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \ + "ddrregs=setenv a e0002; run ddrreg\0" \ + "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \ + "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \ + "guregs=setenv a e00e0; run gureg\0" \ + "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \ + "ecmregs=setenv a e0001; run ecmreg\0" \ + "lawregs=md e0000c08 4b\0" \ + "lbcregs=md e0005000 36\0" \ + "dma0regs=md e0021100 12\0" \ + "dma1regs=md e0021180 12\0" \ + "dma2regs=md e0021200 12\0" \ + "dma3regs=md e0021280 12\0" \ + PCIE_ENV \ + PCI_ENV \ + PCI_ENV1 \ + PCI_ENV2 \ + ENET_ENV + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND #endif /* __CONFIG_H */ diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index a3025bd715..1d1b7c9079 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -312,9 +312,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8555@0" #define OF_SOC "soc8555@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) @@ -350,6 +347,13 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI2_IO_PHYS 0xe2100000 #define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ +#ifdef CONFIG_LEGACY +#define BRIDGE_ID 17 +#define VIA_ID 2 +#else +#define BRIDGE_ID 28 +#define VIA_ID 4 +#endif #if defined(CONFIG_PCI) @@ -377,13 +381,12 @@ extern unsigned long get_clock_freq(void); #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 -#define FEC_PHY_ADDR 3 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 -#define FEC_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" @@ -475,6 +478,7 @@ extern unsigned long get_clock_freq(void); /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index c10e551e40..a8f362fa13 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -292,9 +292,6 @@ #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8560@0" #define OF_SOC "soc8560@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) @@ -360,11 +357,12 @@ #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" @@ -521,6 +519,7 @@ /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index eef168c252..ba744e99f8 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -28,20 +28,21 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ #define CONFIG_MPC8568 1 /* MPC8568 specific */ #define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ -#undef CONFIG_PCI +#define CONFIG_PCI #define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_QE /* Enable QE */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ /*#define CONFIG_DDR_2T_TIMING Sets the 2T timing bit */ /*#define CONFIG_DDR_ECC*/ /* only for ECC DDR module */ -/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */ +/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef @@ -62,9 +63,9 @@ extern unsigned long get_clock_freq(void); /* * These can be toggled for performance analysis, otherwise use default. */ -/*#define CONFIG_L2_CACHE*/ /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ /* * Only possible on E500 Version 2 or newer cores. @@ -292,11 +293,9 @@ extern unsigned long get_clock_freq(void); #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8568@0" #define OF_SOC "soc8568@e0000000" +#define OF_QE "qe@e0080000" #define OF_TBCLK (bd->bi_busfreq / 8) #define OF_STDOUT_PATH "/soc8568@e0000000/serial@4600" @@ -306,11 +305,14 @@ extern unsigned long get_clock_freq(void); #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_EEPROM_ADDR 0x57 +#define CFG_I2C_EEPROM_ADDR 0x52 #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 /* * General PCI @@ -318,7 +320,7 @@ extern unsigned long get_clock_freq(void); */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CFG_PCI1_IO_BASE 0x00000000 #define CFG_PCI1_IO_PHYS 0xe2000000 #define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */ @@ -337,6 +339,44 @@ extern unsigned long get_clock_freq(void); #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ +#ifdef CONFIG_QE +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#ifndef CONFIG_TSEC_ENET +#define CONFIG_ETHPRIME "FSL UEC0" +#endif +#define CONFIG_PHY_MODE_NEED_CHANGE +#define CONFIG_eTSEC_MDIO_BUS + +#ifdef CONFIG_eTSEC_MDIO_BUS +#define CONFIG_MIIM_ADDRESS 0xE0024520 +#endif + +#define CONFIG_UEC_ETH1 /* GETH1 */ + +#ifdef CONFIG_UEC_ETH1 +#define CFG_UEC1_UCC_NUM 0 /* UCC1 */ +#define CFG_UEC1_RX_CLK QE_CLK_NONE +#define CFG_UEC1_TX_CLK QE_CLK16 +#define CFG_UEC1_ETH_TYPE GIGA_ETH +#define CFG_UEC1_PHY_ADDR 7 +#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII +#endif + +#define CONFIG_UEC_ETH2 /* GETH2 */ + +#ifdef CONFIG_UEC_ETH2 +#define CFG_UEC2_UCC_NUM 1 /* UCC2 */ +#define CFG_UEC2_RX_CLK QE_CLK_NONE +#define CFG_UEC2_TX_CLK QE_CLK16 +#define CFG_UEC2_ETH_TYPE GIGA_ETH +#define CFG_UEC2_PHY_ADDR 1 +#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII +#endif +#endif /* CONFIG_QE */ + #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -345,21 +385,17 @@ extern unsigned long get_clock_freq(void); #endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) - #ifndef CONFIG_NET_MULTI #define CONFIG_NET_MULTI 1 #endif +#if defined(CONFIG_TSEC_ENET) + #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_TSEC1 1 #define CONFIG_TSEC1_NAME "eTSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "eTSEC1" -#undef CONFIG_TSEC3 -#undef CONFIG_TSEC4 -#undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 2 #define TSEC2_PHY_ADDR 3 @@ -367,7 +403,10 @@ extern unsigned long get_clock_freq(void); #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 -/* Options are: eTSEC[0-3] */ +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT + +/* Options are: eTSEC[0-1] */ #define CONFIG_ETHPRIME "eTSEC0" #endif /* CONFIG_TSEC_ENET */ @@ -457,12 +496,15 @@ extern unsigned long get_clock_freq(void); */ /* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) +#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD #define CONFIG_HAS_ETH2 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD +#define CONFIG_HAS_ETH3 +#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD #endif #define CONFIG_IPADDR 192.168.1.253 diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 64dcbd0109..7d8a380dc0 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -185,6 +185,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ +#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ #define PIXIS_ID 0x0 /* Board ID at offset 0 */ #define PIXIS_VER 0x1 /* Board version at offset 1 */ @@ -268,9 +269,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8641@0" #define OF_SOC "soc8641@f8000000" #define OF_TBCLK (bd->bi_busfreq / 4) @@ -417,6 +415,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define TSEC2_PHYIDX 0 #define TSEC3_PHYIDX 0 #define TSEC4_PHYIDX 0 +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) #define CONFIG_ETHPRIME "eTSEC1" @@ -604,6 +606,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD #endif +#define CONFIG_HAS_ETH0 1 #define CONFIG_HAS_ETH1 1 #define CONFIG_HAS_ETH2 1 #define CONFIG_HAS_ETH3 1 diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 54703731af..652210c19d 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -96,7 +96,6 @@ #define CONFIG_SUPPORT_VFAT #define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ -#define CONFIG_AUTO_UPDATE_SHOW 1 /* use board show routine */ #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -168,38 +167,18 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_NAND_LEGACY +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) - -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_QUIET 1 /*----------------------------------------------------------------------- * PCI stuff @@ -276,11 +255,6 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#if 0 /* test-only */ -#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ -#endif - /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) @@ -306,9 +280,6 @@ #define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ /* total size of a CAT24WC16 is 2048 bytes */ -#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CFG_NVRAM_SIZE 242 /* NVRAM size */ - /*----------------------------------------------------------------------- * I2C EEPROM (CAT24WC16) for environment */ @@ -317,7 +288,7 @@ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ -#if 1 /* test-only */ + /* CAT24WC08/16... */ #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ /* mask of address bits that overflow into the "EEPROM chip address" */ @@ -325,15 +296,6 @@ #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ /* 16 byte page write mode using*/ /* last 4 bits of the address */ -#else -/* CAT24WC32/64... */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 -#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ - /* 32 byte page write mode using*/ - /* last 5 bits of the address */ -#endif #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE diff --git a/include/configs/PM854.h b/include/configs/PM854.h index dbf94228ae..a6a1e738a8 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -270,15 +270,19 @@ #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #define CONFIG_MPC85XX_FEC 1 #define CONFIG_MPC85XX_FEC_NAME "FEC" #define FEC_PHY_ADDR 3 #define FEC_PHYIDX 0 +#define FEC_FLAGS 0 /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" +#define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 1 #define CONFIG_HAS_ETH2 1 diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 6bdfa5d8f1..9a17e3d733 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -262,11 +262,12 @@ #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #endif /* CONFIG_TSEC_ENET */ @@ -391,6 +392,7 @@ /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:40:42:01:00:00 #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:40:42:01:00:01 diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index dd1decdcd9..8a74c4f5c9 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -429,6 +429,8 @@ #define CFG_ENV_ADDR_REDUND 0xFFFFA000 #define CFG_ENV_SIZE_REDUND 0x2000 +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + #endif /* ENVIRONMENT_IN_EEPROM */ diff --git a/include/configs/R360MPI.h b/include/configs/R360MPI.h index 516ec643d6..a98b4af29e 100644 --- a/include/configs/R360MPI.h +++ b/include/configs/R360MPI.h @@ -233,6 +233,7 @@ #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment */ #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */ #define CFG_ENV_SIZE 0x4000 /* Used Size of Environment sector */ +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- * Cache Configuration diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h index 1e6e8c0aa2..32e2285454 100644 --- a/include/configs/RRvision.h +++ b/include/configs/RRvision.h @@ -235,6 +235,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Cache Configuration */ diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h index 2b2ae01f63..dccdf0ca9b 100644 --- a/include/configs/TASREG.h +++ b/include/configs/TASREG.h @@ -43,6 +43,10 @@ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ +#define CONFIG_MCFTMR + +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 19200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 3d9850023d..e0c9d81be0 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -701,11 +701,9 @@ * Open firmware flat tree support *----------------------------------------------------------------------- */ -#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 #define OF_CPU "PowerPC,5200@0" #define OF_SOC "soc5200@f0000000" #define OF_TBCLK (bd->bi_busfreq / 4) diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index 2bdcf2cf95..7a3801026f 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -70,8 +70,9 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM823L/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ + "fdt_addr=40040000\0" \ + "kernel_addr=40060000\0" \ + "ramdisk_addr=40200000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -205,6 +206,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Hardware Information Block */ diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index 58bc5d3f95..e8b6a80b19 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -70,8 +70,9 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM823M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ + "fdt_addr=40080000\0" \ + "kernel_addr=400A0000\0" \ + "ramdisk_addr=40280000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -202,6 +203,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Hardware Information Block */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 661712b227..01472529d0 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -253,6 +253,8 @@ extern int tqm834x_num_flash_banks; #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" @@ -499,6 +501,7 @@ extern int tqm834x_num_flash_banks; */ #if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR D2:DA:5E:44:BC:29 #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 1E:F3:40:21:92:53 diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index 74b16c7cf9..beeca6343e 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -66,8 +66,9 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM850L/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ + "fdt_addr=40040000\0" \ + "kernel_addr=40060000\0" \ + "ramdisk_addr=40200000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -192,6 +193,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Hardware Information Block */ diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h index e3936c3304..d5609c1d48 100644 --- a/include/configs/TQM850M.h +++ b/include/configs/TQM850M.h @@ -64,8 +64,9 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM850M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ + "fdt_addr=40080000\0" \ + "kernel_addr=400A0000\0" \ + "ramdisk_addr=40280000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -191,6 +192,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Hardware Information Block */ diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index ae22b77d7f..e35b5b2ac1 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -69,8 +69,9 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM855L/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ + "fdt_addr=40040000\0" \ + "kernel_addr=40060000\0" \ + "ramdisk_addr=40200000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -196,6 +197,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Hardware Information Block */ diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h index 5d54f876c8..cd5212eff8 100644 --- a/include/configs/TQM855M.h +++ b/include/configs/TQM855M.h @@ -69,8 +69,9 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM855M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ + "fdt_addr=40080000\0" \ + "kernel_addr=400A0000\0" \ + "ramdisk_addr=40280000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -231,6 +232,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Hardware Information Block */ diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index d5ce3ba716..6dbd3924bd 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -94,7 +94,6 @@ */ #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE -#define CONFIG_ADD_RAM_INFO 1 /* print additional info*/ #if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) /* TQM8540 & 8560 need DLL-override */ @@ -266,8 +265,12 @@ #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #define FEC_PHY_ADDR 3 #define FEC_PHYIDX 0 +#define FEC_FLAGS 0 +#define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_HAS_ETH2 @@ -446,7 +449,7 @@ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_EXTRA_ENV_SETTINGS \ - CFG_BOOTFILE \ + "bootfile="CFG_BOOTFILE_PATH"\0" \ "netdev=eth0\0" \ "consdev=ttyS0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index 40c0940d5a..d5838dbf37 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -69,8 +69,9 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM860L/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ + "fdt_addr=40040000\0" \ + "kernel_addr=40060000\0" \ + "ramdisk_addr=40200000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -199,6 +200,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Hardware Information Block */ diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index 481e3d0d53..684b86f2ef 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -69,8 +69,9 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM860M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ + "fdt_addr=40080000\0" \ + "kernel_addr=400A0000\0" \ + "ramdisk_addr=40280000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -198,6 +199,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Hardware Information Block */ diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index bb3b1cc541..f09d3d1654 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -72,8 +72,9 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM862L/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ + "fdt_addr=40040000\0" \ + "kernel_addr=40060000\0" \ + "ramdisk_addr=40200000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -200,6 +201,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Hardware Information Block */ diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index d687d082c9..039aa3af42 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -72,8 +72,9 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM862M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ + "fdt_addr=40080000\0" \ + "kernel_addr=400A0000\0" \ + "ramdisk_addr=40280000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -201,6 +202,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Hardware Information Block */ diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index ff00c13308..0d778919a2 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -81,8 +81,9 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ "bootfile=/tftpboot/TQM866M/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40180000\0" \ + "fdt_addr=40080000\0" \ + "kernel_addr=400A0000\0" \ + "ramdisk_addr=40280000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -241,6 +242,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Hardware Information Block */ diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 34f0ebdcfa..14848abe5b 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -153,38 +153,18 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_NAND_LEGACY - -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) - -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ + +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ +#define CFG_NAND_QUIET 1 /*----------------------------------------------------------------------- * PCI stuff diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index c1b3da863e..656784aa0c 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -145,38 +145,16 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_NAND_LEGACY - -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ - -#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) -#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) -#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) -#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) -#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) -#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) -#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) - -#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) -#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) -#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) - -#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */ +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_BIG_DELAY_US 25 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ + #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ /*----------------------------------------------------------------------- diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h index ecfa21d828..a65c5f3422 100644 --- a/include/configs/at91rm9200dk.h +++ b/include/configs/at91rm9200dk.h @@ -163,6 +163,11 @@ #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_AT91C_USE_RMII +/* AC Characteristics */ +/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ +#define DATAFLASH_TCSS (0xC << 16) +#define DATAFLASH_TCHS (0x1 << 24) + #define CONFIG_HAS_DATAFLASH 1 #define CFG_SPI_WRITE_TOUT (5*CFG_HZ) #define CFG_MAX_DATAFLASH_BANKS 2 diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index 572ac23d3e..265264efbb 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -201,10 +201,9 @@ #define CFG_LONGHELP 1 #define CFG_MEMTEST_START \ - ({ DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start; }) + ({ gd->bd->bi_dram[0].start; }) #define CFG_MEMTEST_END \ ({ \ - DECLARE_GLOBAL_DATA_PTR; \ gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; \ }) #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index 19b29aaf36..14c563808b 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -222,6 +222,8 @@ #define CFG_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */ #define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51} #define CFG_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */ +#define CONFIG_PROG_SDRAM_TLB +#undef CFG_DRAM_TEST /*----------------------------------------------------------------------- * I2C diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h index 56c0ecb4d9..d554348021 100644 --- a/include/configs/cm5200.h +++ b/include/configs/cm5200.h @@ -31,7 +31,6 @@ #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ #define CONFIG_CM5200 1 /* ... on CM5200 platform */ - /* * Supported commands */ @@ -60,7 +59,6 @@ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } #define CONFIG_SILENT_CONSOLE 1 /* needed to silence i2c_init() */ - /* * Ethernet configuration */ @@ -71,7 +69,6 @@ #define CONFIG_MISC_INIT_R 1 #define CONFIG_MAC_OFFSET 0x35 /* MAC address offset in I2C EEPROM */ - /* * POST support */ @@ -80,11 +77,9 @@ /* List of I2C addresses to be verified by POST */ #define I2C_ADDR_LIST { CFG_I2C_SLAVE, CFG_I2C_IO, CFG_I2C_EEPROM } - /* display image timestamps */ #define CONFIG_TIMESTAMP 1 - /* * Autobooting */ @@ -137,19 +132,16 @@ "" #define CONFIG_BOOTCOMMAND "run flash_flash" - /* * Low level configuration */ - /* * Clock configuration */ #define CFG_MPC5XXX_CLKIN 33000000 /* SYS_XTAL_IN = 33MHz */ #define CFG_IPBCLK_EQUALS_XLBCLK 1 /* IPB = 133MHz */ - /* * Memory map */ @@ -184,7 +176,7 @@ */ #define CFG_FLASH_CFI 1 #define CFG_FLASH_CFI_DRIVER 1 -#define CFG_FLASH_BASE 0xfc000000 +#define CFG_FLASH_BASE 0xfc000000 /* we need these despite using CFI */ #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CFG_MAX_FLASH_SECT 256 /* max num of sectors on one chip */ @@ -215,7 +207,6 @@ #define CFG_CS_BURST 0x00000000 #define CFG_CS_DEADCYCLE 0x00000001 - /* * SDRAM configuration * settings for k4s561632E-xx75, assuming XLB = 132 MHz @@ -225,8 +216,6 @@ #define SDRAM_CONFIG1 0xE2333900 #define SDRAM_CONFIG2 0x8EE70000 - - /* * MTD configuration */ @@ -238,7 +227,6 @@ "2m(kernel),27904k(rootfs)," \ "-(config)" - /* * I2C configuration */ @@ -249,13 +237,11 @@ #define CFG_I2C_IO 0x38 /* PCA9554AD I2C I/O port address */ #define CFG_I2C_EEPROM 0x53 /* I2C EEPROM device address */ - /* * RTC configuration */ #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ - /* * USB configuration */ @@ -284,7 +270,6 @@ #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - /* * Pin multiplexing configuration */ @@ -302,7 +287,6 @@ */ #define CFG_GPS_PORT_CONFIG 0x10559C44 - /* * Miscellaneous configurable options */ @@ -322,7 +306,6 @@ #define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - /* * Various low-level settings */ @@ -334,7 +317,6 @@ #define CFG_XLB_PIPELINING 1 /* enable transaction pipeling */ - /* * Cache Configuration */ @@ -343,7 +325,6 @@ #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif - /* * Flat Device Tree support */ diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h index cd92af2352..a869364c60 100644 --- a/include/configs/cmi_mpc5xx.h +++ b/include/configs/cmi_mpc5xx.h @@ -59,6 +59,8 @@ */ #include <config_cmd_default.h> +#undef CONFIG_CMD_NET /* disabeled - causes compile errors */ + #define CONFIG_CMD_MEMORY #define CONFIG_CMD_LOADB #define CONFIG_CMD_REGINFO @@ -169,8 +171,9 @@ #define CFG_ENV_IS_IN_FLASH 1 #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */ -#define CFG_ENV_SIZE 0x00010000 /* Set whole sector as env */ +#define CFG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */ +#define CFG_ENV_SIZE 0x00010000 /* Set whole sector as env */ +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ #endif /*----------------------------------------------------------------------- diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 510524ad36..104d94ec14 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -65,8 +65,10 @@ * Enable use of Ethernet * --- */ +#define CONFIG_MCFFEC -#define FEC_ENET +/* Enable Dma Timer */ +#define CONFIG_MCFTMR /* --- * Define baudrate for UART1 (console output, tftp, ...) @@ -76,6 +78,8 @@ * --- */ +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 19200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } @@ -151,6 +155,26 @@ #undef CONFIG_CMD_LOADB #undef CONFIG_CMD_MII +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif /* *----------------------------------------------------------------------------- diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h new file mode 100644 index 0000000000..577f459e29 --- /dev/null +++ b/include/configs/hcu4.h @@ -0,0 +1,348 @@ +/* + *(C) Copyright 2005-2007 Netstal Maschinen AG + * Niklaus Giger (Niklaus.Giger@netstal.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * hcu4.h - configuration for HCU4 board (similar to hcu5.h) + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_HCU4 1 /* Board is HCU4 */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_405GPr 1 /* HCU4 has a 405GPr */ +#define CONFIG_405GP 1 +#define CONFIG_4xx 1 + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) +*----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ + + +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */ +#define CFG_MONITOR_BASE TEXT_BASE + +/* ... with on-chip memory here (4KBytes) */ +#define CFG_OCM_DATA_ADDR 0xF4000000 +#define CFG_OCM_DATA_SIZE 0x00001000 +/* Do not set up locked dcache as init ram. */ +#undef CFG_INIT_DCACHE_CS + +/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */ +#define CFG_TEMP_STACK_OCM 1 + +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* OCM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +/* + * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. + * If CFG_405_UART_ERRATA_59, then UART divisor is 31. + * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. + * The Linux BASE_BAUD define should match this configuration. + * baseBaud = cpuClock/(uartDivisor*16) + * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, + * set Linux BASE_BAUD to 403200. + */ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#undef CONFIG_SERIAL_MULTI /* needed to be able to define + CONFIG_SERIAL_SOFTWARE_FIFO */ +#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ +#define CFG_BASE_BAUD 691200 + +/* Size (bytes) of interrupt driven serial port buffer. + * Set to 0 to use polling instead of interrupts. + * Setting to 0 will also disable RTS/CTS handshaking. + */ +#undef CONFIG_SERIAL_SOFTWARE_FIFO + +/* Set console baudrate to 9600 */ +#define CONFIG_BAUDRATE 9600 + + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ + +#undef CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_IS_IN_EEPROM +#undef CFG_ENV_IS_NOWHERE + +#ifdef CFG_ENV_IS_IN_EEPROM +/* Put the environment after the SDRAM configuration */ +#define PROM_SIZE 2048 +#define CFG_ENV_OFFSET 512 +#define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET) +#endif + +#ifdef CFG_ENV_IS_IN_FLASH +/* Put the environment in Flash */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif + +/*----------------------------------------------------------------------- + * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the + * the first internal I2C controller of the PPC440EPx + *----------------------------------------------------------------------*/ +#define CFG_SPD_BUS_NUM 0 + +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/* This is the 7bit address of the device, not including P. */ +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_I2C_EEPROM_ADDR_LEN 1 + +/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#undef CFG_I2C_MULTI_EEPROMS + + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +/* Setup some board specific values for the default environment variables */ +#define CONFIG_HOSTNAME hcu4 +#define CONFIG_IPADDR 172.25.1.42 +#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE +#define CONFIG_SERVERIP 172.25.1.3 + +#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=0x01000000\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/home/diagnose/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/hcu4/uImage\0" \ + "load=tftp 100000 hcu4/u-boot.bin\0" \ + "update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \ + "cp.b 100000 FFFa0000 60000\0" \ + "upd=run load;run update\0" \ + "vx=tftp ${loadaddr} hcu4_vx_rom;" \ + "setenv bootargs emac(0,0)hcu4_vx_rom e=${ipaddr} " \ + " h=${serverip} u=dpu pw=netstal8752 tn=hcu4 f=0x3008;" \ + "bootvx ${loadaddr}\0" \ + "" +#define CONFIG_BOOTCOMMAND "run vx" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 1 /* PHY address */ + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ + +#define CONFIG_HAS_ETH0 +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BSP +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM + +/* SPD EEPROM (sdram speed config) disabled */ +#define CONFIG_SPD_EEPROM 1 +#define SPD_EEPROM_ADDRESS 0x50 + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash Bank 0) initialization */ +#define CFG_EBC_PB0AP 0x02005400 +#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */ + +#define CFG_EBC_PB1AP 0x03041200 +#define CFG_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */ + +#define CFG_EBC_PB2AP 0x02054500 +#define CFG_EBC_PB2CR 0x78018000 /* BAS=,BS=MB,BU=R/W,BW=bit */ + +#define CFG_EBC_PB3AP 0x01840300 +#define CFG_EBC_PB3CR 0x7c0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */ + +#define CFG_EBC_PB4AP 0x01800300 +#define CFG_EBC_PB4CR 0x7e0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */ + +#define CFG_GPIO0_TCR 0x7ffe0000 /* GPIO value */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/* Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ + + +/* Configuration Port location */ +#define CONFIG_PORT_ADDR 0xF0000500 + + +/*----------------------------------------------------------------------- + * Cache Configuration + *----------------------------------------------------------------------*/ +#define CFG_DCACHE_SIZE 16384 /* For IBM 405GPr CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h new file mode 100644 index 0000000000..90858819b6 --- /dev/null +++ b/include/configs/hcu5.h @@ -0,0 +1,391 @@ +/* + * (C) Copyright 2007 Netstal Maschinen AG + * Niklaus Giger (Niklaus.Giger@netstal.com) + * + * (C) Copyright 2006-2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2006 + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * hcu5.h - configuration for HCU5 board (derived from sequoia.h) + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_HCU5 1 /* Board is HCU5 */ +#define CONFIG_440EPX 1 /* Specific PPC440EPx */ +#define CONFIG_440 1 /* ... PPC440 family */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ + +#define CFG_BOOT_BASE_ADDR 0xfff00000 +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_OCM_BASE 0xe0010000 /* ocm */ +#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 + +/* Don't change either of these */ +#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ + +#define CFG_USB2D0_BASE 0xe0000100 +#define CFG_USB_DEVICE 0xe0000000 +#define CFG_USB_HOST 0xe0000400 + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer + *----------------------------------------------------------------------*/ +/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ +#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ + +#define CFG_INIT_RAM_END (4 << 10) +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#define CONFIG_BAUDRATE 9600 +#undef CONFIG_SERIAL_MULTI /* needed to be able to define + CONFIG_SERIAL_SOFTWARE_FIFO, but + CONFIG_SERIAL_SOFTWARE_FIFO (16) does not work */ +/* Size (bytes) of interrupt driven serial port buffer. + * Set to 0 to use polling instead of interrupts. + * Setting to 0 will also disable RTS/CTS handshaking. + */ +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#undef CONFIG_UART1_CONSOLE + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ + +#undef CFG_ENV_IS_IN_NVRAM +#undef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_IS_IN_EEPROM +#undef CFG_ENV_IS_NOWHERE + +#ifdef CFG_ENV_IS_IN_EEPROM +/* Put the environment after the SDRAM and bootstrap configuration */ +#define PROM_SIZE 2048 +#define CFG_BOOSTRAP_OPTION_OFFSET 512 +#define CFG_ENV_OFFSET (CFG_BOOSTRAP_OPTION_OFFSET + 0x10) +#define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET) +#endif + +#ifdef CFG_ENV_IS_IN_FLASH +/* Put the environment in Flash */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CFG_MBYTES_SDRAM (128) /* 128 MB or 256 MB */ +#define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */ +#undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */ +#define CONFIG_DDR_ECC 1 /* enable ECC */ + +/*----------------------------------------------------------------------- + * I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the + * the second internal I2C controller of the PPC440EPx + *----------------------------------------------------------------------*/ +#define CFG_SPD_BUS_NUM 1 + +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/* This is the 7bit address of the device, not including P. */ +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_I2C_EEPROM_ADDR_LEN 1 + +/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#undef CFG_I2C_MULTI_EEPROMS + + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run nfs\" to mount Linux root filesystem over NFS;"\ + "echo" + +#undef CONFIG_BOOTARGS + +/* Setup some board specific values for the default environment variables */ +#define CONFIG_HOSTNAME hcu5 +#define CONFIG_IPADDR 172.25.1.42 +#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE +#define CONFIG_SERVERIP 172.25.1.3 + +#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=0x01000000\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "bootfile=hcu5/uImage\0" \ + "rootpath=/home/hcu/eldk/ppc_4xxFP\0" \ + "load=tftp 100000 hcu5/u-boot.bin\0" \ + "update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \ + "cp.b 100000 FFFa0000 60000\0" \ + "upd=run load;run update\0" \ + "vx=tftp ${loadaddr} hcu5/hcu5_vx_rom;" \ + "setenv bootargs emac(0,0)hcu5_vx_rom e=${ipaddr} " \ + " h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008;" \ + "bootvx ${loadaddr}\0" \ + "" +#define CONFIG_BOOTCOMMAND "run vx" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_M88E1111_PHY 1 +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ + +#define CONFIG_HAS_ETH0 +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NET_MULTI 1 +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY1_ADDR 1 + +/* USB */ +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE + +/* Comment this out to enable USB 1.1 device */ +#define USB_2_0_DEVICE + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BSP +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_USB + +#define CONFIG_SUPPORT_VFAT + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------*/ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ + +/* Board-specific PCI */ +#define CFG_PCI_TARGET_INIT +#define CFG_PCI_MASTER_INIT + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ +#define CFG_FLASH CFG_FLASH_BASE +#define CFG_CS_1 0xC8000000 /* CAN */ +#define CFG_CS_2 0xCC000000 /* CPLD and IMC-Bus Standard */ +#define CFG_CPLD CFG_CS_2 +#define CFG_CS_3 0xCD000000 /* CPLD and IMC-Bus Fast */ + +/*----------------------------------------------------------------------- + * FLASH organization + * Memory Bank 0 (BOOT-FLASH) initialization + */ +#define CFG_BOOTFLASH_CS 0 /* Boot Flash chip connected to CSx */ +#define CFG_EBC_PB0AP 0x02005400 +#define CFG_EBC_PB0CR 0xFFF18000 /* (CFG_FLASH | 0xda000) */ +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */ + + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/* Memory Bank 1 CAN-Chips initialization */ +#define CFG_EBC_PB1AP 0x02054500 +#define CFG_EBC_PB1CR 0xC8018000 + +/* Memory Bank 2 CPLD/IMC-Bus standard initialization */ +#define CFG_EBC_PB2AP 0x01840300 +#define CFG_EBC_PB2CR 0xCC0BA000 + +/* Memory Bank 3 IMC-Bus fast mode initialization */ +#define CFG_EBC_PB3AP 0x01800300 +#define CFG_EBC_PB3CR 0xCE0BA000 + +/* Memory Bank 4 (not used) initialization */ +#undef CFG_EBC_PB4AP +#undef CFG_EBC_PB4CR + +/* Memory Bank 5 (not used) initialization */ +#undef CFG_EBC_PB5AP +#undef CFG_EBC_PB5CR + +#define HCU_CPLD_VERSION_REGISTER ( CFG_CPLD + 0x0F00000 ) +#define HCU_HW_VERSION_REGISTER ( CFG_CPLD + 0x1400000 ) + +/*----------------------------------------------------------------------- + * Cache Configuration + *----------------------------------------------------------------------*/ +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER + #define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/hymod.h b/include/configs/hymod.h index 2f64ec238c..2547afb3cf 100644 --- a/include/configs/hymod.h +++ b/include/configs/hymod.h @@ -406,6 +406,7 @@ #define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ #define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */ #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- * Cache Configuration diff --git a/include/configs/idmr.h b/include/configs/idmr.h index 1ab7b27a5d..3821ebcf0d 100644 --- a/include/configs/idmr.h +++ b/include/configs/idmr.h @@ -44,6 +44,8 @@ */ #define CONFIG_BOOTCOMMAND "run net_nfs" #define CONFIG_BOOTDELAY 5 +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 19200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } #define CONFIG_ETHADDR 00:06:3b:01:41:55 @@ -58,6 +60,8 @@ #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root " \ "filesystem over NFS; echo" +#define CONFIG_MCFTMR + #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ @@ -121,6 +125,8 @@ #define CFG_ENV_IS_IN_FLASH #endif /* !CONFIG_MONITOR_IS_IN_RAM */ +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + #define CFG_PROMPT "=> " #define CFG_LONGHELP /* undef to save memory */ @@ -147,11 +153,27 @@ /* * Ethernet */ -#define FEC_ENET -#define CONFIG_NET_RETRY_COUNT 5 -#define CFG_ENET_BD_BASE 0x480000 -#define CFG_DISCOVER_PHY 1 +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 #define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif /* * Definitions for initial stack pointer and data area (in DPRAM) @@ -186,7 +208,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) /* FLASH organization */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ @@ -216,7 +238,7 @@ "-(user)"; #if defined(CONFIG_CMD_MII) -#error MII commands don't work on iDMR board and sholud not be enabled. +#error "MII commands don't work on iDMR board and should not be enabled." #endif #endif /* _IDMR_H */ diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h index b68c5aa46e..b7100e986c 100644 --- a/include/configs/jupiter.h +++ b/include/configs/jupiter.h @@ -145,12 +145,9 @@ #if 0 /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,5200@0" #define OF_SOC "soc5200@f0000000" #define OF_TBCLK (bd->bi_busfreq / 8) diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 110ad44ee1..7908e5a474 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -42,7 +42,6 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ -#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ #undef CONFIG_SHOW_BOOT_PROGRESS /*----------------------------------------------------------------------- @@ -67,11 +66,11 @@ #define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ #define CFG_PCIE0_CFGBASE 0xc0000000 -#define CFG_PCIE0_XCFGBASE 0xc0000400 -#define CFG_PCIE1_CFGBASE 0xc0001000 -#define CFG_PCIE1_XCFGBASE 0xc0001400 -#define CFG_PCIE2_CFGBASE 0xc0002000 -#define CFG_PCIE2_XCFGBASE 0xc0002400 +#define CFG_PCIE1_CFGBASE 0xc1000000 +#define CFG_PCIE2_CFGBASE 0xc2000000 +#define CFG_PCIE0_XCFGBASE 0xc3000000 +#define CFG_PCIE1_XCFGBASE 0xc3001000 +#define CFG_PCIE2_XCFGBASE 0xc3002000 /* System RAM mapped to PCI space */ #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE @@ -202,6 +201,7 @@ "setenv filesize;saveenv\0" \ "upd=run load;run update\0" \ "kozio=bootm ffc60000\0" \ + "pciconfighost=1\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -323,7 +323,7 @@ #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ -#undef CONFIG_PCI_CONFIG_HOST_BRIDGE +#define CONFIG_PCI_CONFIG_HOST_BRIDGE /* Board-specific PCI */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ diff --git a/include/configs/luan.h b/include/configs/luan.h index 72aae09d03..a09dd74733 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -39,7 +39,6 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ -#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the @@ -136,7 +135,6 @@ #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ #define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/ #define CONFIG_DDR_ECC 1 /* with ECC support */ -#define CFG_44x_DDR2_CKTR_180 1 /* use 180 deg advance */ /*----------------------------------------------------------------------- * I2C @@ -213,7 +211,6 @@ #define CONFIG_HW_WATCHDOG /* watchdog */ #endif - /* * BOOTP options */ @@ -222,7 +219,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - /* * Command line configuration. */ @@ -230,7 +226,6 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_EEPROM #define CONFIG_CMD_I2C #define CONFIG_CMD_IRQ @@ -242,7 +237,6 @@ #define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM - /* * Miscellaneous configurable options */ diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index ef9ab22b60..00c34d5d7b 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -34,8 +34,8 @@ #define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ -#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the @@ -46,7 +46,7 @@ #define CFG_BOOT_BASE_ADDR 0xf0000000 #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ +#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH */ #define CFG_MONITOR_BASE TEXT_BASE #define CFG_LIME_BASE_0 0xc0000000 #define CFG_LIME_BASE_1 0xc1000000 @@ -72,13 +72,14 @@ * Initial RAM & stack pointer *----------------------------------------------------------------------*/ /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ -#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */ #define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ +#define CFG_OCM_DATA_ADDR CFG_OCM_BASE #define CFG_INIT_RAM_END (4 << 10) #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR /*----------------------------------------------------------------------- * Serial Port @@ -103,9 +104,11 @@ #define CFG_FLASH_CFI /* The flash is CFI compatible */ #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH0 0xFC000000 +#define CFG_FLASH1 0xF8000000 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 } -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ @@ -133,35 +136,63 @@ #define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */ #if 0 /* test-only: disable ECC for now */ #define CONFIG_DDR_ECC 1 /* enable ECC */ +#define CFG_POST_ECC_ON CFG_POST_ECC +#else +#define CFG_POST_ECC_ON 0 #endif +/* POST support */ +#define CONFIG_POST (CFG_POST_CACHE | \ + CFG_POST_CPU | \ + CFG_POST_ECC_ON | \ + CFG_POST_ETHER | \ + CFG_POST_FPU | \ + CFG_POST_I2C | \ + CFG_POST_MEMORY | \ + CFG_POST_RTC | \ + CFG_POST_SPR | \ + CFG_POST_UART) + +#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */ +#define CONFIG_LOGBUFFER +#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ + /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_EEPROM_ADDR (0xa8>>1) -#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_I2C_EEPROM_ADDR 0x53 /* EEPROM AT24C128 */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ +#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */ + /* 64 byte page write mode using*/ + /* last 6 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 #define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */ #define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */ +#define CFG_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */ + +#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */ +#if 0 +#define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */ +#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n" +#define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */ +#endif -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" +#define CONFIG_PREBOOT "setenv bootdelay 15" #undef CONFIG_BOOTARGS #define CONFIG_EXTRA_ENV_SETTINGS \ "hostname=lwmon5\0" \ "netdev=eth0\0" \ + "unlock=yes\0" \ + "logversion=2\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ @@ -169,12 +200,13 @@ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ + "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\ + "flash_nfs=run nfsargs addip addtty addmisc;" \ "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ + "flash_self=run ramargs addip addtty addmisc;" \ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ + "net_nfs=tftp 200000 ${bootfile};" \ + "run nfsargs addip addtty addmisc;bootm\0" \ "rootpath=/opt/eldk/ppc_4xxFP\0" \ "bootfile=/tftpboot/lwmon5/uImage\0" \ "kernel_addr=FC000000\0" \ @@ -183,6 +215,8 @@ "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \ "cp.b 200000 FFF80000 80000\0" \ "upd=run load;run update\0" \ + "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \ + "autoscr 200000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -200,6 +234,7 @@ #define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_RESET_DELAY 300 #define CONFIG_HAS_ETH0 #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ @@ -223,7 +258,6 @@ #define CONFIG_DOS_PARTITION #define CONFIG_ISO_PARTITION - /* * BOOTP options */ @@ -232,7 +266,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - /* * Command line configuration. */ @@ -247,6 +280,7 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_I2C #define CONFIG_CMD_IRQ +#define CONFIG_CMD_LOG #define CONFIG_CMD_MII #define CONFIG_CMD_NET #define CONFIG_CMD_NFS @@ -259,7 +293,6 @@ #define CONFIG_CMD_USB #endif - /*----------------------------------------------------------------------- * Miscellaneous configurable options *----------------------------------------------------------------------*/ @@ -306,7 +339,12 @@ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ +#if 0 +/* + * ToDo: Watchdog is not test fully, so exclude it for now + */ #define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */ +#endif /* * For booting Linux, the board info and command line data @@ -322,7 +360,7 @@ /* Memory Bank 0 (NOR-FLASH) initialization */ #define CFG_EBC_PB0AP 0x03050200 -#define CFG_EBC_PB0CR (CFG_FLASH | 0xdc000) +#define CFG_EBC_PB0CR (CFG_FLASH | 0xfc000) /* Memory Bank 1 (Lime) initialization */ #define CFG_EBC_PB1AP 0x01004380 @@ -342,14 +380,24 @@ * Graphics (Fujitsu Lime) *----------------------------------------------------------------------*/ /* SDRAM Clock frequency adjustment register */ -#define CFG_LIME_SDRAM_CLOCK 0xC1FC0000 -/* Lime Clock frequency is to set 133MHz */ +#define CFG_LIME_SDRAM_CLOCK 0xC1FC0038 +/* Lime Clock frequency is to set 100MHz */ +#define CFG_LIME_CLOCK_100MHZ 0x00000 +#if 0 +/* Lime Clock frequency for 133MHz */ #define CFG_LIME_CLOCK_133MHZ 0x10000 +#endif /* SDRAM Parameter register */ #define CFG_LIME_MMR 0xC1FCFFFC -/* SDRAM parameter value */ +/* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars + and pixel flare on display when 133MHz was configured. According to + SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */ +#ifdef CFG_LIME_CLOCK_133MHZ +#define CFG_LIME_MMR_VALUE 0x414FB7F3 +#else #define CFG_LIME_MMR_VALUE 0x414FB7F2 +#endif /*----------------------------------------------------------------------- * GPIO Setup @@ -357,9 +405,11 @@ #define CFG_GPIO_PHY1_RST 12 #define CFG_GPIO_FLASH_WP 14 #define CFG_GPIO_PHY0_RST 22 -#define CFG_GPIO_WATCHDOG 58 +#define CFG_GPIO_EEPROM_EXT_WP 55 +#define CFG_GPIO_EEPROM_INT_WP 57 #define CFG_GPIO_LIME_S 59 #define CFG_GPIO_LIME_RST 60 +#define CFG_GPIO_WATCHDOG 63 /*----------------------------------------------------------------------- * PPC440 GPIO Configuration @@ -428,7 +478,7 @@ {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO58 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \ diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index e0a827fdd7..9a21632162 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -417,11 +417,9 @@ extern void __led_set(led_id_t id, int state); #define CFG_RESET_ADDRESS 0xfff00100 /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 #define OF_CPU "PowerPC,5200@0" #define OF_SOC "soc5200@f0000000" #define OF_TBCLK (bd->bi_busfreq / 4) diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index f4f33f3e08..bd3107ab23 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -80,9 +80,6 @@ #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,7448@0" #define OF_TSI "tsi108@c0000000" #define OF_TBCLK (bd->bi_busfreq / 8) diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h index 8ae38cb277..bec442d983 100644 --- a/include/configs/p3mx.h +++ b/include/configs/p3mx.h @@ -60,7 +60,6 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ -#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 8e51d2d3c0..7653ba1d24 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -266,7 +266,10 @@ #define CONFIG_CMD_DIAG #define CONFIG_CMD_EEPROM #define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT #define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE #define CONFIG_CMD_IRQ #define CONFIG_CMD_MII #define CONFIG_CMD_NET @@ -274,12 +277,10 @@ #define CONFIG_CMD_PCI #define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO +#define CONFIG_CMD_REISER #define CONFIG_CMD_SDRAM -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT #define CONFIG_CMD_USB - #define CONFIG_SUPPORT_VFAT /* @@ -488,10 +489,4 @@ /* Offset for alternate registers */ #define CFG_ATA_ALT_OFFSET (0x0000) -/* These addresses need to be shifted one place to the left - * ( bus per_addr 20 -30 is connectsd on CF bus A10-A0) - * These values are shifted - */ -#define CFG_ATA_PORT_ADDR(port) ((port) << 1) - #endif /* __CONFIG_H */ diff --git a/include/configs/r5200.h b/include/configs/r5200.h index 0e743bb2e4..fc7658b9f2 100644 --- a/include/configs/r5200.h +++ b/include/configs/r5200.h @@ -39,13 +39,10 @@ #define CONFIG_M5271 /* define processor type */ #define CONFIG_R5200 /* define board type */ -#define FEC_ENET -#define CONFIG_NET_RETRY_COUNT 5 - -#define CONFIG_IPADDR 192.168.0.172 -#define CONFIG_SERVERIP 192.168.0.148 -#define CONFIG_ETHADDR 00:06:3b:00:44:55 +#define CONFIG_MCFTMR +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 19200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } @@ -87,6 +84,27 @@ #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_LOADB +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif /* Note: We only copy one sectors worth of application code from location * 10200000 for speed purposes. Increase the size if necessary */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 1831bef0de..e7d8a5a662 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -313,9 +313,6 @@ #define CONFIG_OF_FLAT_TREE 1 #define CONFIG_OF_BOARD_SETUP 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,8349@0" #define OF_SOC "soc8349@e0000000" #define OF_TBCLK (bd->bi_busfreq / 4) @@ -410,6 +407,8 @@ #define TSEC2_PHY_ADDR 0x1a #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" @@ -660,6 +659,7 @@ #define CONFIG_ENV_OVERWRITE #if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:a0:1e:a0:13:8d #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:a0:1e:a0:13:8e diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h new file mode 100644 index 0000000000..54eac38b86 --- /dev/null +++ b/include/configs/sbc8641d.h @@ -0,0 +1,606 @@ +/* + * Copyright 2007 Wind River Systems <www.windriver.com> + * Copyright 2007 Embedded Specialties, Inc. + * Joe Hamman <joe.hamman@embeddedspecialties.com> + * + * Copyright 2006 Freescale Semiconductor. + * + * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * SBC8641D board configuration file + * + * Make sure you change the MAC address and other network params first, + * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_MPC86xx 1 /* MPC86xx */ +#define CONFIG_MPC8641 1 /* MPC8641 specific */ +#define CONFIG_SBC8641D 1 /* SBC8641D board specific */ +#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ +#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ + +#ifdef RUN_DIAG +#define CFG_DIAG_ADDR 0xff800000 +#endif + +#define CFG_RESET_ADDRESS 0xfff00100 + +#define CONFIG_PCI 1 /* Enable PCIE */ +#define CONFIG_PCI1 1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_PCI2 1 /* PCIE controler 2 (slot 2) */ +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ + +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE + +#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ +#undef CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CACHE_LINE_INTERLEAVING 0x20000000 +#define PAGE_INTERLEAVING 0x21000000 +#define BANK_INTERLEAVING 0x22000000 +#define SUPER_BANK_INTERLEAVING 0x23000000 + + +#define CONFIG_ALTIVEC 1 + +/* + * L2CR setup -- make sure this is right for your board! + */ +#define CFG_L2 +#define L2_INIT 0 +#define L2_ENABLE (L2CR_L2E) + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) +#endif + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest region */ +#define CFG_MEMTEST_END 0x00400000 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) +#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) + +/* + * DDR Setup + */ +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CFG_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#define CFG_SDRAM_BASE2 CFG_DDR_SDRAM_BASE2 +#define CONFIG_VERY_BIG_RAM + +#define MPC86xx_DDR_SDRAM_CLK_CNTL + +#if defined(CONFIG_SPD_EEPROM) + /* + * Determine DDR configuration from I2C interface. + */ + #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ + #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ + +#else + /* + * Manually set up DDR1 & DDR2 parameters + */ + + #define CFG_SDRAM_SIZE 512 /* DDR is 512MB */ + + #define CFG_DDR_CS0_BNDS 0x0000000F + #define CFG_DDR_CS1_BNDS 0x00000000 + #define CFG_DDR_CS2_BNDS 0x00000000 + #define CFG_DDR_CS3_BNDS 0x00000000 + #define CFG_DDR_CS0_CONFIG 0x80010102 + #define CFG_DDR_CS1_CONFIG 0x00000000 + #define CFG_DDR_CS2_CONFIG 0x00000000 + #define CFG_DDR_CS3_CONFIG 0x00000000 + #define CFG_DDR_EXT_REFRESH 0x00000000 + #define CFG_DDR_TIMING_0 0x00220802 + #define CFG_DDR_TIMING_1 0x38377322 + #define CFG_DDR_TIMING_2 0x002040c7 + #define CFG_DDR_CFG_1A 0x43008008 + #define CFG_DDR_CFG_2 0x24401000 + #define CFG_DDR_MODE_1 0x23c00542 + #define CFG_DDR_MODE_2 0x00000000 + #define CFG_DDR_MODE_CTL 0x00000000 + #define CFG_DDR_INTERVAL 0x05080100 + #define CFG_DDR_DATA_INIT 0x00000000 + #define CFG_DDR_CLK_CTRL 0x03800000 + #define CFG_DDR_CFG_1B 0xC3008008 + + #define CFG_DDR2_CS0_BNDS 0x0010001F + #define CFG_DDR2_CS1_BNDS 0x00000000 + #define CFG_DDR2_CS2_BNDS 0x00000000 + #define CFG_DDR2_CS3_BNDS 0x00000000 + #define CFG_DDR2_CS0_CONFIG 0x80010102 + #define CFG_DDR2_CS1_CONFIG 0x00000000 + #define CFG_DDR2_CS2_CONFIG 0x00000000 + #define CFG_DDR2_CS3_CONFIG 0x00000000 + #define CFG_DDR2_EXT_REFRESH 0x00000000 + #define CFG_DDR2_TIMING_0 0x00220802 + #define CFG_DDR2_TIMING_1 0x38377322 + #define CFG_DDR2_TIMING_2 0x002040c7 + #define CFG_DDR2_CFG_1A 0x43008008 + #define CFG_DDR2_CFG_2 0x24401000 + #define CFG_DDR2_MODE_1 0x23c00542 + #define CFG_DDR2_MODE_2 0x00000000 + #define CFG_DDR2_MODE_CTL 0x00000000 + #define CFG_DDR2_INTERVAL 0x05080100 + #define CFG_DDR2_DATA_INIT 0x00000000 + #define CFG_DDR2_CLK_CTRL 0x03800000 + #define CFG_DDR2_CFG_1B 0xC3008008 + + +#endif + +/* #define CFG_ID_EEPROM 1 +#define ID_EEPROM_ADDR 0x57 */ + +/* + * The SBC8641D contains 16MB flash space at ff000000. + */ +#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ + +/* Flash */ +#define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */ +#define CFG_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */ + +/* 64KB EEPROM */ +#define CFG_BR1_PRELIM 0xf0000801 /* port size 16bit */ +#define CFG_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */ + +/* EPLD - User switches, board id, LEDs */ +#define CFG_BR2_PRELIM 0xf1000801 /* port size 16bit */ +#define CFG_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */ + +/* Local bus SDRAM 128MB */ +#define CFG_BR3_PRELIM 0xe0001861 /* port size ?bit */ +#define CFG_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */ +#define CFG_BR4_PRELIM 0xe4001861 /* port size ?bit */ +#define CFG_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */ + +/* Disk on Chip (DOC) 128MB */ +#define CFG_BR5_PRELIM 0xe8001001 /* port size ?bit */ +#define CFG_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */ + +/* LCD */ +#define CFG_BR6_PRELIM 0xf4000801 /* port size ?bit */ +#define CFG_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ + +/* Control logic & misc peripherals */ +#define CFG_BR7_PRELIM 0xf2000801 /* port size ?bit */ +#define CFG_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 131 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_WRITE_SWAPPED_DATA +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_PROTECTION + +#undef CONFIG_CLOCKS_IN_MHZ + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#ifndef CFG_INIT_RAM_LOCK +#define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ +#else +#define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ +#endif +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* + * Pass open firmware flat tree to kernel + */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +#define OF_CPU "PowerPC,8641@0" +#define OF_SOC "soc@f8000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc@f8000000/serial@4500" + +#define CFG_64BIT_VSPRINTF 1 +#define CFG_64BIT_STRTOUL 1 + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3100 + +/* + * RapidIO MMU + */ +#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ +#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE +#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + +#define CFG_PCI2_MEM_BASE 0xa0000000 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI2_IO_BASE 0xe3000000 +#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE +#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ + +#if defined(CONFIG_PCI) + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +#undef CFG_SCSI_SCAN_BUS_REVERSE + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +#define CONFIG_DOS_PARTITION +#undef CONFIG_SCSI_AHCI + +#ifdef CONFIG_SCSI_AHCI +#define CONFIG_SATA_ULI5288 +#define CFG_SCSI_MAX_SCSI_ID 4 +#define CFG_SCSI_MAX_LUN 1 +#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) +#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE +#endif + +#endif /* CONFIG_PCI */ + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +/* #define CONFIG_MII 1 */ /* MII PHY management */ + +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" +#define CONFIG_TSEC4 1 +#define CONFIG_TSEC4_NAME "eTSEC4" + +#define TSEC1_PHY_ADDR 0x1F +#define TSEC2_PHY_ADDR 0x00 +#define TSEC3_PHY_ADDR 0x01 +#define TSEC4_PHY_ADDR 0x02 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 +#define TSEC4_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC3_FLAGS TSEC_GIGABIT +#define TSEC4_FLAGS TSEC_GIGABIT + +#define CFG_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ + +#define CONFIG_ETHPRIME "eTSEC1" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * BAT0 2G Cacheable, non-guarded + * 0x0000_0000 2G DDR + */ +#define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) +#define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) +#define CFG_IBAT0U CFG_DBAT0U + +/* + * BAT1 1G Cache-inhibited, guarded + * 0x8000_0000 512M PCI-Express 1 Memory + * 0xa000_0000 512M PCI-Express 2 Memory + * Changed it for operating from 0xd0000000 + */ +#define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT1U CFG_DBAT1U + +/* + * BAT2 512M Cache-inhibited, guarded + * 0xc000_0000 512M RapidIO Memory + */ +#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT2U CFG_DBAT2U + +/* + * BAT3 4M Cache-inhibited, guarded + * 0xf800_0000 4M CCSR + */ +#define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) +#define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT3U CFG_DBAT3U + +/* + * BAT4 32M Cache-inhibited, guarded + * 0xe200_0000 16M PCI-Express 1 I/O + * 0xe300_0000 16M PCI-Express 2 I/0 + * Note that this is at 0xe0000000 + */ +#define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT4U CFG_DBAT4U + +/* + * BAT5 128K Cacheable, non-guarded + * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) + */ +#define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_IBAT5L CFG_DBAT5L +#define CFG_IBAT5U CFG_DBAT5U + +/* + * BAT6 32M Cache-inhibited, guarded + * 0xfe00_0000 32M FLASH + */ +#define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_IBAT6U CFG_DBAT6U + +#define CFG_DBAT7L 0x00000000 +#define CFG_DBAT7U 0x00000000 +#define CFG_IBAT7L 0x00000000 +#define CFG_IBAT7U 0x00000000 + +/* + * Environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ +#define CFG_ENV_SIZE 0x2000 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#include <config_cmd_default.h> + #define CONFIG_CMD_PING + #define CONFIG_CMD_I2C + +#if defined(CONFIG_PCI) + #define CONFIG_CMD_PCI +#endif + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if defined(CONFIG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if defined(CONFIG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 02:E0:0C:00:00:01 +#define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD +#define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD +#define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD +#endif + +#define CONFIG_HAS_ETH0 1 +#define CONFIG_HAS_ETH1 1 +#define CONFIG_HAS_ETH2 1 +#define CONFIG_HAS_ETH3 1 + +#define CONFIG_IPADDR 192.168.0.50 + +#define CONFIG_HOSTNAME sbc8641d +#define CONFIG_ROOTPATH /opt/eldk/ppc_74xx +#define CONFIG_BOOTFILE uImage + +#define CONFIG_SERVERIP 192.168.0.2 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_NETMASK 255.255.255.0 + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=uRamdisk\0" \ + "dtbaddr=400000\0" \ + "dtbfile=sbc8641d.dtb\0" \ + "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ + "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ + "maxcpus=1" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr - $dtbaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $dtbaddr $dtbfile;" \ + "bootm $loadaddr $ramdiskaddr $dtbaddr" + +#define CONFIG_FLASHBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "bootm ffd00000 ffb00000 ffa00000" + +#define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 3f75a441a0..c2e1386217 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -343,6 +343,11 @@ #define CONFIG_CMD_USB #endif +#ifndef CONFIG_RAINIER +#define CFG_POST_FPU_ON CFG_POST_FPU +#else +#define CFG_POST_FPU_ON 0 +#endif /* POST support */ #define CONFIG_POST (CFG_POST_MEMORY | \ @@ -350,7 +355,7 @@ CFG_POST_UART | \ CFG_POST_I2C | \ CFG_POST_CACHE | \ - CFG_POST_FPU | \ + CFG_POST_FPU_ON | \ CFG_POST_ETHER | \ CFG_POST_SPR) @@ -395,7 +400,8 @@ *----------------------------------------------------------------------*/ /* General PCI */ #define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h index b4ab9ad972..2efc8f10ec 100644 --- a/include/configs/spc1920.h +++ b/include/configs/spc1920.h @@ -31,14 +31,9 @@ #undef CONFIG_8xx_CONS_NONE #define CONFIG_MII -/* #define MII_DEBUG */ -/* #define CONFIG_FEC_ENET */ #undef CONFIG_ETHER_ON_FEC1 #define CONFIG_ETHER_ON_FEC2 #define FEC_ENET -/* #define CONFIG_FEC2_PHY_NORXERR */ -/* #define CFG_DISCOVER_PHY */ -/* #define CONFIG_PHY_ADDR 0x1 */ #define CONFIG_FEC2_PHY 1 #define CONFIG_BAUDRATE 19200 @@ -100,14 +95,12 @@ #define CONFIG_CMD_ECHO #define CONFIG_CMD_IMMAP #define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_NET #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_I2C #define CONFIG_CMD_MII -#undef CONFIG_CMD_NET - - /* * Miscellaneous configurable options */ diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 1f41cf7699..c5ae0cde36 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -234,12 +234,13 @@ #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "TSEC1" -#undef CONFIG_MPS85XX_FEC #define TSEC1_PHY_ADDR 2 #define TSEC2_PHY_ADDR 4 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #define CONFIG_ETHPRIME "TSEC0" #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ @@ -378,6 +379,7 @@ /*Note: change below for your network setting!!! */ #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:e0:0c:07:9b:8a #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 55e2c8da20..b41dafaf98 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -230,7 +230,7 @@ #define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */ #if defined(CONFIG_PCI) /* PCI Ethernet card */ - +#define CONFIG_MPC85XX_PCI2 1 #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ @@ -260,12 +260,13 @@ #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "TSEC1" -#define CONFIG_MPS85XX_FEC #define TSEC1_PHY_ADDR 2 #define TSEC2_PHY_ADDR 4 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC2_FLAGS TSEC_GIGABIT #define CONFIG_ETHPRIME "TSEC0" #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ @@ -406,6 +407,7 @@ /*Note: change below for your network setting!!! */ #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) +#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:e0:0c:07:9b:8a #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h index 0dbf4b7feb..b035857dce 100644 --- a/include/configs/stxxtc.h +++ b/include/configs/stxxtc.h @@ -592,9 +592,6 @@ typedef unsigned int led_id_t; /* pass open firmware flat tree */ #define CONFIG_OF_FLAT_TREE 1 -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - #define OF_CPU "PowerPC,MPC870@0" #define OF_TBCLK (MPC8XX_HZ / 16) #define CONFIG_OF_HAS_BD_T 1 diff --git a/include/configs/taihu.h b/include/configs/taihu.h new file mode 100644 index 0000000000..d623e56009 --- /dev/null +++ b/include/configs/taihu.h @@ -0,0 +1,476 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2005-2007 + * Beijing UD Technology Co., Ltd., taihusupport@amcc.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + + +#define CONFIG_405EP 1 /* this is a PPC405 CPU */ +#define CONFIG_4xx 1 /* member of PPC4xx family */ +#define CONFIG_TAIHU 1 /* on a taihu board */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f */ + +#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ + +#define CONFIG_NO_SERIAL_EEPROM + +/*----------------------------------------------------------------------------*/ +#ifdef CONFIG_NO_SERIAL_EEPROM + +/* +!------------------------------------------------------------------------------- +! PLL settings for 333MHz CPU, 111MHz PLB/SDRAM, 55MHz EBC, 33MHz PCI, +! assuming a 33MHz input clock to the 405EP from the C9531. +!------------------------------------------------------------------------------- +*/ +#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_3) +#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) +#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_1) +#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) + +#define PLLMR0_DEFAULT PLLMR0_333_111_55_37 +#define PLLMR1_DEFAULT PLLMR1_333_111_55_37 +#define PLLMR0_DEFAULT_PCI66 PLLMR0_333_111_55_111 +#define PLLMR1_DEFAULT_PCI66 PLLMR1_333_111_55_111 + +#endif +/*----------------------------------------------------------------------------*/ + +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootfile=/tftpboot/taihu/uImage\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "kernel_addr=FC000000\0" \ + "ramdisk_addr=FC180000\0" \ + "load=tftp 200000 /tftpboot/taihu/u-boot.bin\0" \ + "update=protect off FFFC0000 FFFFFFFF;era FFFC0000 FFFFFFFF;" \ + "cp.b 200000 FFFC0000 40000\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0x14 /* PHY address */ +#define CONFIG_HAS_ETH1 +#define CONFIG_PHY1_ADDR 0x10 /* EMAC1 PHY address */ +#define CONFIG_NET_MULTI 1 +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ +#define CONFIG_PHY_RESET 1 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_SPI + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#undef CONFIG_SPD_EEPROM /* use SPD EEPROM for setup */ +#define CFG_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */ +#define CFG_SDRAM_BANKS 2 + +/* + * SDRAM configuration (please see cpu/ppc/sdram.[ch]) + */ +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ +#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */ + +/* SDRAM timings used in datasheet */ +#define CFG_SDRAM_CL 3 /* CAS latency */ +#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */ +#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */ +#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ +#define CFG_SDRAM_tRFC 66 /* Auto refresh period */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +/* + * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. + * If CFG_405_UART_ERRATA_59, then UART divisor is 31. + * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. + * The Linux BASE_BAUD define should match this configuration. + * baseBaud = cpuClock/(uartDivisor*16) + * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, + * set Linux BASE_BAUD to 403200. + */ +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ +#define CFG_BASE_BAUD 691200 + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_UART1_CONSOLE 1 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * I2C stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ + +#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ + +#define CONFIG_SOFT_SPI +#define SPI_SCL spi_scl +#define SPI_SDA spi_sda +#define SPI_READ spi_read() +#define SPI_DELAY udelay(2) +#ifndef __ASSEMBLY__ +void spi_scl(int); +void spi_sda(int); +unsigned char spi_read(void); +#endif + +/* standard dtt sensor configuration */ +#define CONFIG_DTT_DS1775 1 +#define CONFIG_DTT_SENSORS { 0 } + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ +#define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ +#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ +#define CONFIG_EEPRO100 1 + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFE00000 +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ +#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ + +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_ADDR0 0x555 +#define CFG_FLASH_ADDR1 0x2aa +#define CFG_FLASH_WORD_SIZE unsigned short + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif /* CFG_ENV_IS_IN_FLASH */ + +/*----------------------------------------------------------------------- + * NVRAM organization + */ +#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ +#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */ + +#ifdef CFG_ENV_IS_IN_NVRAM +#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ +#define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env*/ +#endif + +/*----------------------------------------------------------------------- + * PPC405 GPIO Configuration + */ +#define CFG_440_GPIO_TABLE { /* GPIO Alternate1 */ \ +{ \ +/* GPIO Core 0 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast SPI CS */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 SPI SCLK */ \ +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 SPI DI */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 SPI DO */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 PCI INTA */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 PCI INTB */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 PCI INTC */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 PCI INTD */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 USB */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 EBC */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 unused */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD UART1 */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \ +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx UART0 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 User LED1 */ \ +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 User LED2 */ \ +} \ +} + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */ +#define CFG_CACHELINE_SIZE 32 +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0xFC000000 /* FLASH bank #1 */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory (OCM) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash/SRAM) initialization */ +#define CFG_EBC_PB0AP 0x03815600 +#define CFG_EBC_PB0CR 0xFFE3A000 /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (NVRAM/RTC) initialization */ +#define CFG_EBC_PB1AP 0x05815600 +#define CFG_EBC_PB1CR 0xFC0BA000 /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */ + +/* Memory Bank 2 (USB device) initialization */ +#define CFG_EBC_PB2AP 0x03016600 +#define CFG_EBC_PB2CR 0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 3 (LCM and D-flip-flop) initialization */ +#define CFG_EBC_PB3AP 0x158FF600 +#define CFG_EBC_PB3CR 0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */ + +/* Memory Bank 4 (not install) initialization */ +#define CFG_EBC_PB4AP 0x158FF600 +#define CFG_EBC_PB4CR 0x5021A000 + +/*----------------------------------------------------------------------- + * Definitions for GPIO setup (PPC405EP specific) + * + * GPIO0[0] - External Bus Controller BLAST output + * GPIO0[1-9] - Instruction trace outputs + * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs + * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs + * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs + * GPIO0[24-27] - UART0 control signal inputs/outputs + * GPIO0[28-29] - UART1 data signal input/output + * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs + */ +#define CFG_GPIO0_OSRH 0x15555550 /* output select high/low */ +#define CFG_GPIO0_OSRL 0x00000110 +#define CFG_GPIO0_ISR1H 0x00000001 /* input select high/low */ +#define CFG_GPIO0_ISR1L 0x15545440 +#define CFG_GPIO0_TSRH 0x00000000 /* three-state select high/low */ +#define CFG_GPIO0_TSRL 0x00000000 +#define CFG_GPIO0_TCR 0xFFFE8117 /* three-state control */ +#define CFG_GPIO0_ODR 0x00000000 /* open drain */ + +#define GPIO0 0 /* GPIO controller 0 */ + +/* the GPIO macros in include/ppc405.h for High/Low registers are backwards */ + +#define GPIOx_OSL (GPIO0_OSRH-GPIO_BASE) +#define GPIOx_TSL (GPIO0_TSRH-GPIO_BASE) +#define GPIOx_IS1L (GPIO0_ISR1H-GPIO_BASE) +#define GPIOx_IS2L (GPIO0_ISR1H-GPIO_BASE) +#define GPIOx_IS3L (GPIO0_ISR1H-GPIO_BASE) + +#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO output select */ +#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO three-state select */ +#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO input select */ +#define GPIO_IS2(x) (x+GPIOx_IS1L) +#define GPIO_IS3(x) (x+GPIOx_IS1L) + +#define CPLD_REG0_ADDR 0x50100000 +#define CPLD_REG1_ADDR 0x50100001 +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/trab.h b/include/configs/trab.h index dbccea28ad..b9088a89ab 100644 --- a/include/configs/trab.h +++ b/include/configs/trab.h @@ -419,6 +419,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /* Initial value of the on-board touch screen brightness */ #define CFG_BRIGHTNESS 0x20 diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h new file mode 100644 index 0000000000..84998d4392 --- /dev/null +++ b/include/configs/trizepsiv.h @@ -0,0 +1,325 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Gmbh, sbabic@denx.de + * + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * Configuation settings for the LUBBOCK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */ + +#define LITTLEENDIAN 1 /* used by usb_ohci.c */ + +#define CONFIG_MMC 1 +#define BOARD_LATE_INIT 1 + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define RTC + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_FFUART 1 /* we use FFUART on Conxs */ +#define CONFIG_BTUART 1 /* we use BTUART on Conxs */ +#define CONFIG_STUART 1 /* we use STUART on Conxs */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 38400 + +#define CONFIG_DOS_PARTITION 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_MMC +#define CONFIG_CMD_FAT +#define CONFIG_CMD_IMLS +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ + +#undef CONFIG_SHOW_BOOT_PROGRESS + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_SERVERIP 192.168.1.99 +#define CONFIG_BOOTCOMMAND "run boot_flash" +#define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\ + " rw root=/dev/ram initrd=0xa0800000,5m" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "program_boot_mmc=" \ + "mw.b 0xa0010000 0xff 0x20000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0010000 u-boot.bin; " \ + "then " \ + "protect off 0x0 0x1ffff; " \ + "erase 0x0 0x1ffff; " \ + "cp.b 0xa0010000 0x0 0x20000; " \ + "fi\0" \ + "program_uzImage_mmc=" \ + "mw.b 0xa0010000 0xff 0x180000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0010000 uzImage; " \ + "then " \ + "protect off 0x40000 0x1bffff; " \ + "erase 0x40000 0x1bffff; " \ + "cp.b 0xa0010000 0x40000 0x180000; " \ + "fi\0" \ + "program_ramdisk_mmc=" \ + "mw.b 0xa0010000 0xff 0x500000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0010000 ramdisk.gz; " \ + "then " \ + "protect off 0x1c0000 0x6bffff; " \ + "erase 0x1c0000 0x6bffff; " \ + "cp.b 0xa0010000 0x1c0000 0x500000; " \ + "fi\0" \ + "boot_mmc=" \ + "if mmcinit && " \ + "fatload mmc 0 0xa0030000 uzImage && " \ + "fatload mmc 0 0xa0800000 ramdisk.gz; " \ + "then " \ + "bootm 0xa0030000; " \ + "fi\0" \ + "boot_flash=" \ + "cp.b 0x1c0000 0xa0800000 0x500000; " \ + "bootm 0x40000\0" \ + +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +/* #define CONFIG_INITRD_TAG 1 */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CFG_LONGHELP /* undef to save memory */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT "$ " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#endif +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_DEVICE_NULLDEV 1 + +#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0xa1000000 /* default load address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_MMC_BASE 0xF0000000 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +#define CFG_DRAM_BASE 0xa0000000 +#define CFG_DRAM_SIZE 0x04000000 + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/* + * GPIO settings + */ +#define CFG_GPSR0_VAL 0x00018000 +#define CFG_GPSR1_VAL 0x00000000 +#define CFG_GPSR2_VAL 0x400dc000 +#define CFG_GPSR3_VAL 0x00000000 +#define CFG_GPCR0_VAL 0x00000000 +#define CFG_GPCR1_VAL 0x00000000 +#define CFG_GPCR2_VAL 0x00000000 +#define CFG_GPCR3_VAL 0x00000000 +#define CFG_GPDR0_VAL 0x00018000 +#define CFG_GPDR1_VAL 0x00028801 +#define CFG_GPDR2_VAL 0x520dc000 +#define CFG_GPDR3_VAL 0x0001E000 +#define CFG_GAFR0_L_VAL 0x801c0000 +#define CFG_GAFR0_U_VAL 0x00000013 +#define CFG_GAFR1_L_VAL 0x6990100A +#define CFG_GAFR1_U_VAL 0x00000008 +#define CFG_GAFR2_L_VAL 0xA0000000 +#define CFG_GAFR2_U_VAL 0x010900F2 +#define CFG_GAFR3_L_VAL 0x54000003 +#define CFG_GAFR3_U_VAL 0x00002401 +#define CFG_GRER0_VAL 0x00000000 +#define CFG_GRER1_VAL 0x00000000 +#define CFG_GRER2_VAL 0x00000000 +#define CFG_GRER3_VAL 0x00000000 +#define CFG_GFER0_VAL 0x00000000 +#define CFG_GFER1_VAL 0x00000000 +#define CFG_GFER2_VAL 0x00000000 +#define CFG_GFER3_VAL 0x00000020 + + +#define CFG_PSSR_VAL 0x20 /* CHECK */ + +/* + * Clock settings + */ +#define CFG_CKEN 0x01FFFFFF /* CHECK */ +#define CFG_CCCR 0x02000290 /* 520Mhz */ + +/* + * Memory settings + */ + +#define CFG_MSC0_VAL 0x4df84df0 +#define CFG_MSC1_VAL 0x7ff87ff4 +#define CFG_MSC2_VAL 0xa26936d4 +#define CFG_MDCNFG_VAL 0x880009C9 +#define CFG_MDREFR_VAL 0x20ca201e +#define CFG_MDMRS_VAL 0x00220022 + +#define CFG_FLYCNFG_VAL 0x00000000 +#define CFG_SXCNFG_VAL 0x40044004 + +/* + * PCMCIA and CF Interfaces + */ +#define CFG_MECR_VAL 0x00000001 +#define CFG_MCMEM0_VAL 0x00004204 +#define CFG_MCMEM1_VAL 0x00010204 +#define CFG_MCATT0_VAL 0x00010504 +#define CFG_MCATT1_VAL 0x00010504 +#define CFG_MCIO0_VAL 0x00008407 +#define CFG_MCIO1_VAL 0x0000c108 + +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x08000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE+0x8004) +/* #define CONFIG_DM9000_USE_8BIT */ +/* #define CONFIG_DM9000_USE_16BIT */ +#define CONFIG_DM9000_USE_32BIT + +#define CONFIG_USB_OHCI_NEW 1 +#define CFG_USB_OHCI_BOARD_INIT 1 +#define CFG_USB_OHCI_MAX_ROOT_PORTS 3 +#define CFG_USB_OHCI_REGS_BASE 0x4C000000 +#define CFG_USB_OHCI_SLOT_NAME "trizepsiv" +#define CONFIG_USB_STORAGE 1 +#define CFG_USB_OHCI_CPU_INIT 1 + +/* + * FLASH and environment organization + */ + +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER 1 + +#define CFG_MONITOR_BASE 0 +#define CFG_MONITOR_LEN 0x40000 + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ + +/* write flash less slowly */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 + +/* Flash environment locations */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */ +#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment */ +#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +#endif /* __CONFIG_H */ diff --git a/include/configs/uc101.h b/include/configs/uc101.h index 3b471d0a97..aed80ec1e5 100644 --- a/include/configs/uc101.h +++ b/include/configs/uc101.h @@ -332,7 +332,6 @@ #define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ #define CONFIG_IDE_PREINIT 1 -/* #define CONFIG_IDE_RESET 1 beispile siehe tqm5200.c */ #define CFG_ATA_IDE0_OFFSET 0x0000 diff --git a/include/configs/virtlab2.h b/include/configs/virtlab2.h index 561a8bc47b..edae6f4b98 100644 --- a/include/configs/virtlab2.h +++ b/include/configs/virtlab2.h @@ -207,6 +207,8 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ + /*----------------------------------------------------------------------- * Hardware Information Block */ diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 9c536fd12d..74033b4aef 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -46,7 +46,6 @@ #define EXTCLK_83 83333333 #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ -#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ #undef CONFIG_SHOW_BOOT_PROGRESS #undef CONFIG_STRESS @@ -69,11 +68,11 @@ #define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ #define CFG_PCIE0_CFGBASE 0xc0000000 -#define CFG_PCIE0_XCFGBASE 0xc0000400 -#define CFG_PCIE1_CFGBASE 0xc0001000 -#define CFG_PCIE1_XCFGBASE 0xc0001400 -#define CFG_PCIE2_CFGBASE 0xc0002000 -#define CFG_PCIE2_XCFGBASE 0xc0002400 +#define CFG_PCIE1_CFGBASE 0xc1000000 +#define CFG_PCIE2_CFGBASE 0xc2000000 +#define CFG_PCIE0_XCFGBASE 0xc3000000 +#define CFG_PCIE1_XCFGBASE 0xc3001000 +#define CFG_PCIE2_XCFGBASE 0xc3002000 /* System RAM mapped to PCI space */ #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE @@ -183,6 +182,7 @@ "cp.b ${fileaddr} FFFB0000 ${filesize};" \ "setenv filesize;saveenv\0" \ "upd=run load;run update\0" \ + "pciconfighost=1\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -298,7 +298,7 @@ #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ -#undef CONFIG_PCI_CONFIG_HOST_BRIDGE +#define CONFIG_PCI_CONFIG_HOST_BRIDGE /* Board-specific PCI */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ diff --git a/include/configs/zeus.h b/include/configs/zeus.h new file mode 100644 index 0000000000..605755a87e --- /dev/null +++ b/include/configs/zeus.h @@ -0,0 +1,382 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * zeus.h - configuration for Zeus board + ***********************************************************************/ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_ZEUS 1 /* Board is Zeus */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_405EP 1 /* Specifc 405EP support*/ + +#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +#define PLLMR0_DEFAULT PLLMR0_333_111_55_111 +#define PLLMR1_DEFAULT PLLMR1_333_111_55_111 + +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0x01 /* PHY address */ +#define CONFIG_HAS_ETH1 1 +#define CONFIG_PHY1_ADDR 0x11 /* EMAC1 PHY address */ +#define CONFIG_NET_MULTI 1 +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ +#define CONFIG_PHY_RESET 1 +#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_LOG +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +/* POST support */ +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_CPU | \ + CFG_POST_CACHE | \ + CFG_POST_UART | \ + CFG_POST_ETHER) + +#define CFG_POST_ETHER_EXT_LOOPBACK /* eth POST using ext loopack connector */ + +/* Define here the base-addresses of the UARTs to test in POST */ +#define CFG_POST_UART_TABLE {UART0_BASE} + +#define CONFIG_LOGBUFFER +#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */ + +#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/*----------------------------------------------------------------------- + * SDRAM + *----------------------------------------------------------------------*/ +/* + * SDRAM configuration (please see cpu/ppc/sdram.[ch]) + */ +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ +#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */ + +/* SDRAM timings used in datasheet */ +#define CFG_SDRAM_CL 3 /* CAS latency */ +#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */ +#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */ +#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ +#define CFG_SDRAM_tRFC 66 /* Auto refresh period */ + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#define CFG_BASE_BAUD 691200 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/* these are for the ST M24C02 2kbit serial i2c eeprom */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* base address */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 + +#define CFG_EEPROM_PAGE_WRITE_ENABLE 1 /* write eeprom in pages */ +#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* 8 byte write page size */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ + +/* + * The layout of the I2C EEPROM, used for bootstrap setup and for board- + * specific values, like ethaddr... that can be restored via the sw-reset + * button + */ +#define FACTORY_RESET_I2C_EEPROM 0x50 +#define FACTORY_RESET_ENV_OFFS 0x80 +#define FACTORY_RESET_ENV_SIZE 0x80 + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFF000000 +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ +#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory (OCM) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of OCM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +/* reserve some memory for POST and BOOT limit info */ +#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16) + +/* extra data in OCM */ +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4) +#define CFG_POST_MAGIC (CFG_OCM_DATA_ADDR + CFG_GBL_DATA_OFFSET - 8) +#define CFG_POST_VAL (CFG_OCM_DATA_ADDR + CFG_GBL_DATA_OFFSET - 12) + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ + +/* Memory Bank 0 (Flash 16M) initialization */ +#define CFG_EBC_PB0AP 0x05815600 +#define CFG_EBC_PB0CR 0xFF09A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */ + +/*----------------------------------------------------------------------- + * Definitions for GPIO setup (PPC405EP specific) + * + * GPIO0[0] - External Bus Controller BLAST output + * GPIO0[1-9] - Instruction trace outputs + * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs + * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs + * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs + * GPIO0[24-27] - UART0 control signal inputs/outputs + * GPIO0[28-29] - UART1 data signal input/output + * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs + */ +#define CFG_GPIO0_OSRH 0x15555550 /* Chip selects */ +#define CFG_GPIO0_OSRL 0x00000110 /* UART_DTR-pin 27 alt out */ +#define CFG_GPIO0_ISR1H 0x10000041 /* Pin 2, 12 is input */ +#define CFG_GPIO0_ISR1L 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */ +#define CFG_GPIO0_TSRH 0x00000000 +#define CFG_GPIO0_TSRL 0x00000000 +#define CFG_GPIO0_TCR 0xBFF68317 /* 3-state OUT: 22/23/29; 12,2 is not 3-state */ +#define CFG_GPIO0_ODR 0x00000000 + +#define CFG_GPIO_SW_RESET 1 +#define CFG_GPIO_ZEUS_PE 12 +#define CFG_GPIO_LED_RED 22 +#define CFG_GPIO_LED_GREEN 23 + +/* Time in milli-seconds */ +#define CFG_TIME_POST 5000 +#define CFG_TIME_FACTORY_RESET 10000 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* ENVIRONMENT VARS */ + +#define CONFIG_PREBOOT "echo;echo Welcome to Bulletendpoints board v1.1;echo" +#define CONFIG_IPADDR 192.168.1.10 +#define CONFIG_SERVERIP 192.168.1.100 +#define CONFIG_GATEWAYIP 192.168.1.100 +#define CONFIG_ETHADDR 50:00:00:00:06:00 +#define CONFIG_ETH1ADDR 50:00:00:00:06:01 +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "logversion=2\0" \ + "hostname=zeus\0" \ + "netdev=eth0\0" \ + "ethact=ppc_4xx_eth0\0" \ + "netmask=255.255.255.0\0" \ + "ramdisk_size=50000\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw" \ + " nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw" \ + " ramdisk=${ramdisk_size}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0," \ + "${baudrate}\0" \ + "net_nfs=tftp ${kernel_mem_addr} ${file_kernel};" \ + "run nfsargs addip addtty;bootm\0" \ + "net_ram=tftp ${kernel_mem_addr} ${file_kernel};" \ + "tftp ${ramdisk_mem_addr} ${file_fs};" \ + "run ramargs addip addtty;" \ + "bootm ${kernel_mem_addr} ${ramdisk_mem_addr}\0" \ + "rootpath=/target_fs/zeus\0" \ + "kernel_fl_addr=ff000000\0" \ + "kernel_mem_addr=200000\0" \ + "ramdisk_fl_addr=ff300000\0" \ + "ramdisk_mem_addr=4000000\0" \ + "uboot_fl_addr=fffc0000\0" \ + "uboot_mem_addr=100000\0" \ + "file_uboot=/zeus/u-boot.bin\0" \ + "tftp_uboot=tftp 100000 ${file_uboot}\0" \ + "update_uboot=protect off fffc0000 ffffffff;" \ + "era fffc0000 ffffffff;cp.b 100000 fffc0000 40000;" \ + "protect on fffc0000 ffffffff\0" \ + "upd_uboot=run tftp_uboot;run update_uboot\0" \ + "file_kernel=/zeus/uImage_ba\0" \ + "tftp_kernel=tftp 100000 ${file_kernel}\0" \ + "update_kernel=protect off ff000000 ff17ffff;" \ + "era ff000000 ff17ffff;cp.b 100000 ff000000 180000\0" \ + "upd_kernel=run tftp_kernel;run update_kernel\0" \ + "file_fs=/zeus/rootfs_ba.img\0" \ + "tftp_fs=tftp 100000 ${file_fs}\0" \ + "update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\ + "cp.b 100000 ff300000 580000\0" \ + "upd_fs=run tftp_fs;run update_fs\0" \ + "bootcmd=chkreset;run ramargs addip addtty addmisc;" \ + "bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0" \ + "" + +#endif /* __CONFIG_H */ |