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-rw-r--r--include/configs/crownbay.h2
-rw-r--r--include/configs/galileo.h3
-rw-r--r--include/configs/minnowmax.h6
-rw-r--r--include/configs/qemu-x86.h77
-rw-r--r--include/configs/x86-chromebook.h1
-rw-r--r--include/configs/x86-common.h7
6 files changed, 82 insertions, 14 deletions
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
index 4fef433252..0e1f0467c7 100644
--- a/include/configs/crownbay.h
+++ b/include/configs/crownbay.h
@@ -17,8 +17,6 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_MISC_INIT
-#define CONFIG_NR_DRAM_BANKS 1
-
#define CONFIG_X86_SERIAL
#define CONFIG_SMSC_LPC47M
diff --git a/include/configs/galileo.h b/include/configs/galileo.h
index f780b8fa51..fd89bf30ef 100644
--- a/include/configs/galileo.h
+++ b/include/configs/galileo.h
@@ -15,8 +15,7 @@
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
#define CONFIG_BOARD_EARLY_INIT_F
-
-#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_ARCH_MISC_INIT
#define CONFIG_X86_SERIAL
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 2a1915d872..547765d137 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -15,8 +15,7 @@
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
#define CONFIG_BOARD_EARLY_INIT_F
-
-#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_X86_SERIAL
#define CONFIG_SMSC_LPC47M
@@ -56,9 +55,6 @@
#define CONFIG_X86_OPTION_ROM_FILE vga.bin
#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000
-#ifndef CONFIG_SYS_COREBOOT
-#define CONFIG_VIDEO_VESA
-#endif
#define VIDEO_IO_OFFSET 0
#define CONFIG_X86EMU_RAW_IO
#define CONFIG_VGA_AS_SINGLE_DEVICE
diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h
new file mode 100644
index 0000000000..78c296f5ad
--- /dev/null
+++ b/include/configs/qemu-x86.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN (1 << 20)
+#define CONFIG_ARCH_MISC_INIT
+
+#define CONFIG_X86_SERIAL
+
+#define CONFIG_PCI_MEM_BUS 0xc0000000
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x10000000
+
+#define CONFIG_PCI_PREF_BUS 0xd0000000
+#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS
+#define CONFIG_PCI_PREF_SIZE 0x10000000
+
+#define CONFIG_PCI_IO_BUS 0x2000
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0xe000
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
+#define CONFIG_PCI_PNP
+#define CONFIG_E1000
+
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga\0" \
+ "stdout=serial,vga\0" \
+ "stderr=serial,vga\0"
+
+/*
+ * ATA/SATA support for QEMU x86 targets
+ * - Only legacy IDE controller is supported for QEMU '-M pc' target
+ * - AHCI controller is supported for QEMU '-M q35' target
+ *
+ * Default configuraion is to support the QEMU default x86 target
+ * Undefine CONFIG_CMD_IDE to support q35 target
+ */
+#define CONFIG_CMD_IDE
+#ifdef CONFIG_CMD_IDE
+#define CONFIG_SYS_IDE_MAXBUS 2
+#define CONFIG_SYS_IDE_MAXDEVICE 4
+#define CONFIG_SYS_ATA_BASE_ADDR 0
+#define CONFIG_SYS_ATA_DATA_OFFSET 0
+#define CONFIG_SYS_ATA_REG_OFFSET 0
+#define CONFIG_SYS_ATA_ALT_OFFSET 0
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0
+#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
+#define CONFIG_ATAPI
+
+#undef CONFIG_SCSI_AHCI
+#undef CONFIG_CMD_SCSI
+#else
+#define CONFIG_SCSI_DEV_LIST \
+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_AHCI}
+#endif
+
+/* GPIO is not supported */
+#undef CONFIG_INTEL_ICH6_GPIO
+#undef CONFIG_CMD_GPIO
+
+/* SPI is not supported */
+#undef CONFIG_ICH_SPI
+#undef CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_IS_NOWHERE
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h
index b6a76fe075..e0e7fca9f8 100644
--- a/include/configs/x86-chromebook.h
+++ b/include/configs/x86-chromebook.h
@@ -14,7 +14,6 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MISC_INIT_R
-#define CONFIG_NR_DRAM_BANKS 8
#define CONFIG_X86_MRC_ADDR 0xfffa0000
#define CONFIG_CACHE_MRC_SIZE_KB 512
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index bf4758e3b3..1917d87ac5 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -21,6 +21,7 @@
#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_LAST_STAGE_INIT
+#define CONFIG_NR_DRAM_BANKS 8
#define CONFIG_LMB
#define CONFIG_OF_LIBFDT
@@ -36,6 +37,7 @@
#define CONFIG_SCSI_AHCI
#ifdef CONFIG_SCSI_AHCI
#define CONFIG_LIBATA
+#define CONFIG_LBA48
#define CONFIG_SYS_64BIT_LBA
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
@@ -75,10 +77,6 @@
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SUPPORT_VFAT
-/************************************************************
- * ATAPI support (experimental)
- ************************************************************/
-#define CONFIG_ATAPI
/************************************************************
* DISK Partition support
@@ -246,6 +244,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_STD_DEVICES_SETTINGS \
+ "pciconfighost=1\0" \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
"othbootargs=acpi=off\0" \