diff options
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/MPC8536DS.h | 51 | ||||
| -rw-r--r-- | include/configs/MPC8548CDS.h | 44 | ||||
| -rw-r--r-- | include/configs/MPC8641HPCN.h | 128 | ||||
| -rw-r--r-- | include/configs/P1022DS.h | 3 | ||||
| -rw-r--r-- | include/configs/p1_p2_rdb_pc.h | 5 |
5 files changed, 150 insertions, 81 deletions
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 3efe9373fd..4b8cba24b2 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -77,6 +77,7 @@ #define CONFIG_MPC8536DS 1 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ +#define CONFIG_SPI_FLASH 1 /* Has SPI Flash */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ @@ -458,6 +459,19 @@ #define CONFIG_SYS_EEPROM_BUS_NUM 1 /* + * eSPI - Enhanced SPI + */ +#define CONFIG_HARD_SPI +#define CONFIG_FSL_ESPI + +#if defined(CONFIG_SPI_FLASH) +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 +#endif + +/* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ @@ -630,10 +644,24 @@ #if defined(CONFIG_SYS_RAMBOOT) #if defined(CONFIG_RAMBOOT_NAND) - #define CONFIG_ENV_IS_IN_NAND 1 - #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE - #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) +#elif defined(CONFIG_RAMBOOT_SPIFLASH) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0xF0000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_RAMBOOT_SDCARD) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#else #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) #define CONFIG_ENV_SIZE 0x2000 @@ -680,6 +708,21 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_CMD_MMC #define CONFIG_GENERIC_MMC +#endif + +/* + * USB + */ +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_STORAGE +#endif + +#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 63e23c276e..ab887c1b9c 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -86,6 +86,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD +#define CONFIG_DDR_ECC #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef @@ -162,6 +163,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_HWCONFIG /* enable hwconfig */ /* * SDRAM on the Local Bus @@ -276,7 +278,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 2 @@ -381,8 +383,9 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_EEPRO100 #undef CONFIG_TULIP +#define CONFIG_E1000 /* Define e1000 pci Ethernet card */ -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ @@ -423,8 +426,12 @@ extern unsigned long get_clock_freq(void); * Environment */ #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) -#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ +#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 +#define CONFIG_ENV_ADDR 0xfff80000 +#else +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#endif +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */ #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -524,20 +531,21 @@ extern unsigned long get_clock_freq(void); #define CONFIG_BAUDRATE 115200 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ - "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ - "consoledev=ttyS1\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ - "fdtfile=mpc8548cds.dtb\0" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ecc=off\0" \ + "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\ + "consoledev=ttyS1\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=mpc8548cds.dtb\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 2bd67c3e11..93b360a2ba 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -99,9 +99,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0. */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f00000000ULL +#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f #else -#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0 +#define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000 #endif /* @@ -114,14 +114,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* Physical addresses */ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf -#define CONFIG_SYS_CCSRBAR_PHYS (CONFIG_SYS_CCSRBAR_PHYS_LOW \ - | ((u64)CONFIG_SYS_CCSRBAR_PHYS_HIGH << 32)) -#else -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW -#endif +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH +#define CONFIG_SYS_CCSRBAR_PHYS \ + PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ + CONFIG_SYS_CCSRBAR_PHYS_HIGH) #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */ @@ -181,8 +177,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */ -#define CONFIG_SYS_FLASH_BASE_PHYS (CONFIG_SYS_FLASH_BASE \ - | CONFIG_SYS_PHYS_ADDR_HIGH) +#define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_FLASH_BASE_PHYS \ + PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ + CONFIG_SYS_PHYS_ADDR_HIGH) #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} @@ -204,12 +202,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * required for the smallest BAT mapping, so there's a 64k hole. */ #define CONFIG_SYS_LBC_BASE 0xffde0000 -#define CONFIG_SYS_LBC_BASE_PHYS (CONFIG_SYS_LBC_BASE \ - | CONFIG_SYS_PHYS_ADDR_HIGH) +#define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000) -#define PIXIS_BASE_PHYS (CONFIG_SYS_LBC_BASE_PHYS + 0x00010000) +#define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000) +#define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \ + CONFIG_SYS_PHYS_ADDR_HIGH) #define PIXIS_SIZE 0x00008000 /* 32k */ #define PIXIS_ID 0x0 /* Board ID at offset 0 */ #define PIXIS_VER 0x1 /* Board version at offset 1 */ @@ -315,10 +314,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_SRIO1_MEM_PHYS 0x0000000c00000000ULL +#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c #else -#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE +#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE +#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000 #endif +#define CONFIG_SYS_SRIO1_MEM_PHYS \ + PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ + CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ /* @@ -330,16 +334,23 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x0000000c00000000ULL +#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c #else #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_VIRT +#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT +#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000 #endif +#define CONFIG_SYS_PCIE1_MEM_PHYS \ + PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ + CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCIE1_IO_PHYS (CONFIG_SYS_PCIE1_IO_VIRT \ - | CONFIG_SYS_PHYS_ADDR_HIGH) +#define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT +#define CONFIG_SYS_PCIE1_IO_PHYS \ + PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ + CONFIG_SYS_PHYS_ADDR_HIGH) #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ #ifdef CONFIG_PHYS_64BIT @@ -355,12 +366,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \ + CONFIG_SYS_PCIE1_MEM_SIZE) +#define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \ + + CONFIG_SYS_PCIE1_MEM_SIZE) +#define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \ + CONFIG_SYS_PCIE1_MEM_SIZE) #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \ + CONFIG_SYS_PCIE1_IO_SIZE) +#define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \ + + CONFIG_SYS_PCIE1_IO_SIZE) #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \ + CONFIG_SYS_PCIE1_IO_SIZE) #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE @@ -455,21 +471,22 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif /* CONFIG_TSEC_ENET */ -/* Contort an addr into the format needed for BATs */ -#ifdef CONFIG_PHYS_64BIT -#define BAT_PHYS_ADDR(x) ((unsigned long) \ - ((x & 0x00000000ffffffffULL) | \ - ((x & 0x0000000e00000000ULL) >> 24) | \ - ((x & 0x0000000100000000ULL) >> 30))) -#else -#define BAT_PHYS_ADDR(x) (x) -#endif - -/* Put high physical address bits into the BAT format */ +#ifdef CONFIG_PHYS_64BIT #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8) #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2) +/* Put physical address into the BAT format */ +#define BAT_PHYS_ADDR(low, high) \ + (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high)) +/* Convert high/low pairs to actual 64-bit value */ +#define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32)) +#else +/* 32-bit systems just ignore the "high" bits */ +#define BAT_PHYS_ADDR(low, high) (low) +#define PAIRED_PHYS_TO_PHYS(low, high) (low) +#endif + /* * BAT0 DDR */ @@ -479,12 +496,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * BAT1 LBC (PIXIS/CF) */ -#define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \ +#define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ + CONFIG_SYS_PHYS_ADDR_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT | \ BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \ | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \ +#define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ + CONFIG_SYS_PHYS_ADDR_HIGH) \ | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U @@ -494,45 +513,40 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * BAT2 Rapidio Memory */ #ifdef CONFIG_PCI -#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \ +#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ + CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \ | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \ +#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ + CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U #else /* CONFIG_RIO */ -#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS) \ +#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ + CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT | \ BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \ | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS) \ +#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ + CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT) - -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_PHYS | BATL_PP_RW \ - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U #endif /* * BAT3 CCSR Space - * This BAT is used early; don't use any macros with ULL - use HIGH/LOW pairs - * instead. The assembler chokes on ULL. */ -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \ - | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ - | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ +#define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ + CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \ | BATU_VP) -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \ - | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ - | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ +#define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ + CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U @@ -550,12 +564,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * BAT4 PCIE1_IO and PCIE2_IO */ -#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \ +#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ + CONFIG_SYS_PHYS_ADDR_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \ | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \ +#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ + CONFIG_SYS_PHYS_ADDR_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U @@ -570,12 +586,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * BAT6 FLASH */ -#define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ +#define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ + CONFIG_SYS_PHYS_ADDR_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ | BATU_VP) -#define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ +#define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ + CONFIG_SYS_PHYS_ADDR_HIGH) \ | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index d892b6701b..9620370874 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -43,8 +43,9 @@ #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#ifdef CONFIG_PHYS_64BIT #define CONFIG_ENABLE_36BIT_PHYS + +#ifdef CONFIG_PHYS_64BIT #define CONFIG_ADDR_MAP #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ #endif diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index b9b89cfa5d..b3d981f3e4 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -204,9 +204,8 @@ #define CONFIG_BTB #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ -#ifdef CONFIG_PHYS_64BIT + #define CONFIG_ENABLE_36BIT_PHYS -#endif #ifdef CONFIG_PHYS_64BIT #define CONFIG_ADDR_MAP 1 @@ -232,7 +231,7 @@ #define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS 0x52 -#define CONFIG_FSL_DDR_INTERACTIVE +#undef CONFIG_FSL_DDR_INTERACTIVE #ifdef CONFIG_P1020MBG #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G |