diff options
Diffstat (limited to 'include/mpc83xx.h')
| -rw-r--r-- | include/mpc83xx.h | 153 |
1 files changed, 153 insertions, 0 deletions
diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 7a19740302..b295d6d71b 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -74,6 +74,7 @@ #define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20) #define SPR_8308 0x8100 +#define SPR_8309 0x8110 #define SPR_831X_FAMILY 0x80B #define SPR_8311 0x80B2 #define SPR_8313 0x80B0 @@ -389,6 +390,86 @@ #define SICRH_TSOBI1_V2P5 (1 << 1) #define SICRH_TSOBI2_V3P3 (0 << 0) #define SICRH_TSOBI2_V2P5 (1 << 0) + +#elif defined(CONFIG_MPC8309) +/* SICR_1 */ +#define SICR_1_UART1_UART1S (0 << (30-2)) +#define SICR_1_UART1_UART1RTS (1 << (30-2)) +#define SICR_1_I2C_I2C (0 << (30-4)) +#define SICR_1_I2C_CKSTOP (1 << (30-4)) +#define SICR_1_IRQ_A_IRQ (0 << (30-6)) +#define SICR_1_IRQ_A_MCP (1 << (30-6)) +#define SICR_1_IRQ_B_IRQ (0 << (30-8)) +#define SICR_1_IRQ_B_CKSTOP (1 << (30-8)) +#define SICR_1_GPIO_A_GPIO (0 << (30-10)) +#define SICR_1_GPIO_A_SD (2 << (30-10)) +#define SICR_1_GPIO_A_DDR (3 << (30-10)) +#define SICR_1_GPIO_B_GPIO (0 << (30-12)) +#define SICR_1_GPIO_B_SD (2 << (30-12)) +#define SICR_1_GPIO_B_QE (3 << (30-12)) +#define SICR_1_GPIO_C_GPIO (0 << (30-14)) +#define SICR_1_GPIO_C_CAN (1 << (30-14)) +#define SICR_1_GPIO_C_DDR (2 << (30-14)) +#define SICR_1_GPIO_C_LCS (3 << (30-14)) +#define SICR_1_GPIO_D_GPIO (0 << (30-16)) +#define SICR_1_GPIO_D_CAN (1 << (30-16)) +#define SICR_1_GPIO_D_DDR (2 << (30-16)) +#define SICR_1_GPIO_D_LCS (3 << (30-16)) +#define SICR_1_GPIO_E_GPIO (0 << (30-18)) +#define SICR_1_GPIO_E_CAN (1 << (30-18)) +#define SICR_1_GPIO_E_DDR (2 << (30-18)) +#define SICR_1_GPIO_E_LCS (3 << (30-18)) +#define SICR_1_GPIO_F_GPIO (0 << (30-20)) +#define SICR_1_GPIO_F_CAN (1 << (30-20)) +#define SICR_1_GPIO_F_CK (2 << (30-20)) +#define SICR_1_USB_A_USBDR (0 << (30-22)) +#define SICR_1_USB_A_UART2S (1 << (30-22)) +#define SICR_1_USB_B_USBDR (0 << (30-24)) +#define SICR_1_USB_B_UART2S (1 << (30-24)) +#define SICR_1_USB_B_UART2RTS (2 << (30-24)) +#define SICR_1_USB_C_USBDR (0 << (30-26)) +#define SICR_1_USB_C_QE_EXT (3 << (30-26)) +#define SICR_1_FEC1_FEC1 (0 << (30-28)) +#define SICR_1_FEC1_GTM (1 << (30-28)) +#define SICR_1_FEC1_GPIO (2 << (30-28)) +#define SICR_1_FEC2_FEC2 (0 << (30-30)) +#define SICR_1_FEC2_GTM (1 << (30-30)) +#define SICR_1_FEC2_GPIO (2 << (30-30)) +/* SICR_2 */ +#define SICR_2_FEC3_FEC3 (0 << (30-0)) +#define SICR_2_FEC3_TMR (1 << (30-0)) +#define SICR_2_FEC3_GPIO (2 << (30-0)) +#define SICR_2_HDLC1_A_HDLC1 (0 << (30-2)) +#define SICR_2_HDLC1_A_GPIO (1 << (30-2)) +#define SICR_2_HDLC1_A_TDM1 (2 << (30-2)) +#define SICR_2_ELBC_A_LA (0 << (30-4)) +#define SICR_2_ELBC_B_LCLK (0 << (30-6)) +#define SICR_2_HDLC2_A_HDLC2 (0 << (30-8)) +#define SICR_2_HDLC2_A_GPIO (0 << (30-8)) +#define SICR_2_HDLC2_A_TDM2 (0 << (30-8)) +/* bits 10-11 unused */ +#define SICR_2_USB_D_USBDR (0 << (30-12)) +#define SICR_2_USB_D_GPIO (2 << (30-12)) +#define SICR_2_USB_D_QE_BRG (3 << (30-12)) +#define SICR_2_PCI_PCI (0 << (30-14)) +#define SICR_2_PCI_CPCI_HS (2 << (30-14)) +#define SICR_2_HDLC1_B_HDLC1 (0 << (30-16)) +#define SICR_2_HDLC1_B_GPIO (1 << (30-16)) +#define SICR_2_HDLC1_B_QE_BRG (2 << (30-16)) +#define SICR_2_HDLC1_B_TDM1 (3 << (30-16)) +#define SICR_2_HDLC1_C_HDLC1 (0 << (30-18)) +#define SICR_2_HDLC1_C_GPIO (1 << (30-18)) +#define SICR_2_HDLC1_C_TDM1 (2 << (30-18)) +#define SICR_2_HDLC2_B_HDLC2 (0 << (30-20)) +#define SICR_2_HDLC2_B_GPIO (1 << (30-20)) +#define SICR_2_HDLC2_B_QE_BRG (2 << (30-20)) +#define SICR_2_HDLC2_B_TDM2 (3 << (30-20)) +#define SICR_2_HDLC2_C_HDLC2 (0 << (30-22)) +#define SICR_2_HDLC2_C_GPIO (1 << (30-22)) +#define SICR_2_HDLC2_C_TDM2 (2 << (30-22)) +#define SICR_2_HDLC2_C_QE_BRG (3 << (30-22)) +#define SICR_2_QUIESCE_B (0 << (30-24)) + #endif /* @@ -580,6 +661,63 @@ #define HRCWL_SVCOD_DIV_8 0x10000000 #define HRCWL_SVCOD_DIV_2 0x20000000 #define HRCWL_SVCOD_DIV_1 0x30000000 +#elif defined(CONFIG_MPC8309) + +#define HRCWL_CEVCOD 0x000000C0 +#define HRCWL_CEVCOD_SHIFT 6 +/* + * According to Errata MPC8309RMAD, Rev. 0.2, 9/2012 + * these are different than with 8360, 832x + */ +#define HRCWL_CE_PLL_VCO_DIV_2 0x00000000 +#define HRCWL_CE_PLL_VCO_DIV_4 0x00000040 +#define HRCWL_CE_PLL_VCO_DIV_8 0x00000080 + +#define HRCWL_CEPDF 0x00000020 +#define HRCWL_CEPDF_SHIFT 5 +#define HRCWL_CE_PLL_DIV_1X1 0x00000000 +#define HRCWL_CE_PLL_DIV_2X1 0x00000020 + +#define HRCWL_CEPMF 0x0000001F +#define HRCWL_CEPMF_SHIFT 0 +#define HRCWL_CE_TO_PLL_1X16_ 0x00000000 +#define HRCWL_CE_TO_PLL_1X2 0x00000002 +#define HRCWL_CE_TO_PLL_1X3 0x00000003 +#define HRCWL_CE_TO_PLL_1X4 0x00000004 +#define HRCWL_CE_TO_PLL_1X5 0x00000005 +#define HRCWL_CE_TO_PLL_1X6 0x00000006 +#define HRCWL_CE_TO_PLL_1X7 0x00000007 +#define HRCWL_CE_TO_PLL_1X8 0x00000008 +#define HRCWL_CE_TO_PLL_1X9 0x00000009 +#define HRCWL_CE_TO_PLL_1X10 0x0000000A +#define HRCWL_CE_TO_PLL_1X11 0x0000000B +#define HRCWL_CE_TO_PLL_1X12 0x0000000C +#define HRCWL_CE_TO_PLL_1X13 0x0000000D +#define HRCWL_CE_TO_PLL_1X14 0x0000000E +#define HRCWL_CE_TO_PLL_1X15 0x0000000F +#define HRCWL_CE_TO_PLL_1X16 0x00000010 +#define HRCWL_CE_TO_PLL_1X17 0x00000011 +#define HRCWL_CE_TO_PLL_1X18 0x00000012 +#define HRCWL_CE_TO_PLL_1X19 0x00000013 +#define HRCWL_CE_TO_PLL_1X20 0x00000014 +#define HRCWL_CE_TO_PLL_1X21 0x00000015 +#define HRCWL_CE_TO_PLL_1X22 0x00000016 +#define HRCWL_CE_TO_PLL_1X23 0x00000017 +#define HRCWL_CE_TO_PLL_1X24 0x00000018 +#define HRCWL_CE_TO_PLL_1X25 0x00000019 +#define HRCWL_CE_TO_PLL_1X26 0x0000001A +#define HRCWL_CE_TO_PLL_1X27 0x0000001B +#define HRCWL_CE_TO_PLL_1X28 0x0000001C +#define HRCWL_CE_TO_PLL_1X29 0x0000001D +#define HRCWL_CE_TO_PLL_1X30 0x0000001E +#define HRCWL_CE_TO_PLL_1X31 0x0000001F + +#define HRCWL_SVCOD 0x30000000 +#define HRCWL_SVCOD_SHIFT 28 +#define HRCWL_SVCOD_DIV_2 0x00000000 +#define HRCWL_SVCOD_DIV_4 0x10000000 +#define HRCWL_SVCOD_DIV_8 0x20000000 +#define HRCWL_SVCOD_DIV_1 0x30000000 #endif /* @@ -940,6 +1078,21 @@ #define SCCR_SATACM_1 0x00000055 #define SCCR_SATACM_2 0x000000aa #define SCCR_SATACM_3 0x000000ff +#elif defined(CONFIG_MPC8309) +/* SCCR bits - MPC8309 specific */ +#define SCCR_SDHCCM 0x0c000000 +#define SCCR_SDHCCM_SHIFT 26 +#define SCCR_SDHCCM_0 0x00000000 +#define SCCR_SDHCCM_1 0x04000000 +#define SCCR_SDHCCM_2 0x08000000 +#define SCCR_SDHCCM_3 0x0c000000 + +#define SCCR_USBDRCM 0x00c00000 +#define SCCR_USBDRCM_SHIFT 22 +#define SCCR_USBDRCM_0 0x00000000 +#define SCCR_USBDRCM_1 0x00400000 +#define SCCR_USBDRCM_2 0x00800000 +#define SCCR_USBDRCM_3 0x00c00000 #endif #define SCCR_PCIEXP1CM 0x00300000 |