diff options
Diffstat (limited to 'include')
58 files changed, 1278 insertions, 99 deletions
diff --git a/include/bootstage.h b/include/bootstage.h index 87bf906b26..df13ab2f63 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -159,6 +159,9 @@ enum bootstage_id { /* Next 10 IDs used by BOOTSTAGE_SUB_... */ BOOTSTAGE_ID_FIT_RD_START = 120, /* Ramdisk stages */ + /* Next 10 IDs used by BOOTSTAGE_SUB_... */ + BOOTSTAGE_ID_FIT_SETUP_START = 130, /* x86 setup stages */ + BOOTSTAGE_ID_IDE_FIT_READ = 140, BOOTSTAGE_ID_IDE_FIT_READ_OK, diff --git a/include/compiler.h b/include/compiler.h index 14519163a3..21036022d7 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -48,6 +48,10 @@ # include <machine/endian.h> typedef unsigned long ulong; #endif +#ifdef __FreeBSD__ +# include <sys/endian.h> /* htole32 and friends */ +#endif + #include <time.h> typedef uint8_t __u8; diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h index 76818f673f..7d8daa2b8e 100644 --- a/include/config_fallbacks.h +++ b/include/config_fallbacks.h @@ -79,10 +79,6 @@ #define CONFIG_SYS_PROMPT "=> " #endif -#ifndef CONFIG_SYS_HZ -#define CONFIG_SYS_HZ 1000 -#endif - #ifndef CONFIG_FIT_SIGNATURE #define CONFIG_IMAGE_FORMAT_LEGACY #endif diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 9063c57b40..dc1a9bc1ef 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -82,6 +82,7 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS #define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCI /* Enable PCI/PCIE */ #define CONFIG_PCIE1 /* PCIE controler 1 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ @@ -759,6 +760,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_NET #endif +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + /* * USB */ @@ -913,4 +920,8 @@ unsigned long get_board_ddr_clk(void); #include <asm/fsl_secure_boot.h> +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 56a3e94868..bc5af526c5 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -55,6 +55,7 @@ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_TSEC_ENET @@ -382,6 +383,12 @@ extern unsigned long get_sdram_size(void); #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #endif +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + #define CONFIG_USB_EHCI #ifdef CONFIG_USB_EHCI diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index aeded6d85b..989363c0fb 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -78,6 +78,7 @@ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ #define CONFIG_PCI /* Enable PCI/PCIE */ @@ -598,6 +599,12 @@ combinations. this should be removed later #define CONFIG_DOS_PARTITION #endif +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + /* * Miscellaneous configurable options */ @@ -704,4 +711,8 @@ combinations. this should be removed later #include <asm/fsl_secure_boot.h> +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 715616d544..5d11278f03 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -86,6 +86,7 @@ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ #define CONFIG_PCI /* Enable PCI/PCIE */ @@ -506,6 +507,12 @@ #define CONFIG_CMD_SETEXPR #define CONFIG_CMD_REGINFO +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + /* * Miscellaneous configurable options */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index a373990e5d..d378dbd1a1 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -53,7 +53,7 @@ #ifdef CONFIG_SECURE_BOOT #define CONFIG_RAMBOOT_SPIFLASH #define CONFIG_SYS_TEXT_BASE 0x11000000 -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #else #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT #define CONFIG_SPL_DRIVERS_MISC_SUPPORT @@ -170,6 +170,7 @@ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ #define CONFIG_PCI /* Enable PCI/PCIE */ @@ -832,6 +833,12 @@ extern unsigned long get_sdram_size(void); #define CONFIG_DOS_PARTITION #endif +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + /* * Miscellaneous configurable options */ @@ -956,4 +963,8 @@ extern unsigned long get_sdram_size(void); #include <asm/fsl_secure_boot.h> +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 16f7525def..2e11aaa13c 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -49,6 +49,7 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCI /* Enable PCI/PCIE */ #define CONFIG_PCIE1 /* PCIE controler 1 */ #define CONFIG_PCIE2 /* PCIE controler 2 */ @@ -647,6 +648,12 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_DOS_PARTITION #endif +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + /* * Miscellaneous configurable options */ @@ -743,4 +750,8 @@ unsigned long get_board_sys_clk(unsigned long dummy); #include <asm/fsl_secure_boot.h> +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index a781ba327a..1d0664ddf6 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -58,6 +58,7 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS #define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCI /* Enable PCI/PCIE */ #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCIE1 /* PCIE controler 1 */ @@ -716,6 +717,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_NET #endif +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + /* * Miscellaneous configurable options */ @@ -818,6 +825,7 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_SECURE_BOOT #include <asm/fsl_secure_boot.h> +#define CONFIG_CMD_BLOB #endif #endif /* __CONFIG_H */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 5e2c100d93..2bb86e40ca 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -113,6 +113,7 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS #define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCI /* Enable PCI/PCIE */ #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCIE1 /* PCIE controler 1 */ @@ -731,6 +732,12 @@ #define CONFIG_CMD_NET #endif +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + /* * Miscellaneous configurable options */ @@ -865,6 +872,7 @@ #ifdef CONFIG_SECURE_BOOT #include <asm/fsl_secure_boot.h> +#define CONFIG_CMD_BLOB #endif #endif /* __CONFIG_H */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 395472be2b..27333589af 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -44,6 +44,7 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS #define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_ENV_OVERWRITE @@ -777,6 +778,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_NET #endif +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + /* * Miscellaneous configurable options */ @@ -909,6 +916,7 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_SECURE_BOOT #include <asm/fsl_secure_boot.h> +#define CONFIG_CMD_BLOB #undef CONFIG_CMD_USB #endif diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index e5936c7817..400d979643 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -37,6 +37,7 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS #define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_ENV_OVERWRITE @@ -736,6 +737,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_NET #endif +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + /* * Miscellaneous configurable options */ @@ -868,6 +875,7 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_SECURE_BOOT #include <asm/fsl_secure_boot.h> +#define CONFIG_CMD_BLOB #undef CONFIG_CMD_USB #endif diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index ca9724720d..1e0f5ece09 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -15,6 +15,7 @@ #define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE4 +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ @@ -506,6 +507,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #endif +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + /* * USB */ @@ -625,4 +632,8 @@ unsigned long get_board_ddr_clk(void); #include <asm/fsl_secure_boot.h> +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 183255d283..13f4bd3c53 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -47,6 +47,7 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS #define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCI /* Enable PCI/PCIE */ #define CONFIG_PCIE1 /* PCIE controler 1 */ #define CONFIG_PCIE2 /* PCIE controler 2 */ @@ -668,6 +669,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DOS_PARTITION #endif +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #define __USB_PHY_TYPE utmi @@ -751,6 +758,7 @@ unsigned long get_board_ddr_clk(void); * which is anyways not used in Secure Environment. */ #undef CONFIG_CMD_USB +#define CONFIG_CMD_BLOB #endif #endif /* __CONFIG_H */ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 7cf241e31d..f7277eb1d1 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -19,7 +19,17 @@ #define CONFIG_MX6 #define CONFIG_SYS_LITTLE_ENDIAN #define CONFIG_MACH_TYPE 4273 -#define CONFIG_SYS_HZ 1000 + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_DM +#define CONFIG_CMD_DM + +#define CONFIG_DM_GPIO +#define CONFIG_CMD_GPIO + +#define CONFIG_DM_SERIAL +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#endif /* Display information on boot */ #define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index 936be14511..200b744e4f 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -25,6 +25,7 @@ #define CONFIG_ZBOOT_32 #define CONFIG_PHYSMEM #define CONFIG_SYS_EARLY_PCI_INIT +#define CONFIG_DISPLAY_BOARDINFO_LATE #define CONFIG_LMB #define CONFIG_OF_LIBFDT @@ -39,6 +40,7 @@ #define CONFIG_BOOTSTAGE_USER_COUNT 60 #define CONFIG_LZO +#define CONFIG_FIT #undef CONFIG_ZLIB #undef CONFIG_GZIP @@ -109,7 +111,8 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_COMMAND_HISTORY -#define CONFIG_AUTOCOMPLETE +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER #define CONFIG_SUPPORT_VFAT /************************************************************ @@ -192,6 +195,7 @@ #define CONFIG_CMD_EXT2 #define CONFIG_CMD_ZBOOT +#define CONFIG_CMD_ELF #define CONFIG_BOOTDELAY 2 #define CONFIG_BOOTARGS \ @@ -208,8 +212,7 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "boot > " -#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_CBSIZE 512 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + \ 16) @@ -218,7 +221,7 @@ #define CONFIG_SYS_MEMTEST_START 0x00100000 #define CONFIG_SYS_MEMTEST_END 0x01000000 -#define CONFIG_SYS_LOAD_ADDR 0x100000 +#define CONFIG_SYS_LOAD_ADDR 0x02000000 /*----------------------------------------------------------------------- * SDRAM Configuration @@ -283,6 +286,11 @@ */ #define CONFIG_PCI +#define CONFIG_CROS_EC +#define CONFIG_CROS_EC_LPC +#define CONFIG_CMD_CROS_EC +#define CONFIG_ARCH_EARLY_INIT_R + /*----------------------------------------------------------------------- * USB configuration */ @@ -297,6 +305,12 @@ #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX #define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_TFTP_TSIZE +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME #define CONFIG_CMD_USB diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 12b32967b4..72b7efa509 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -57,6 +57,7 @@ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_PCI /* Enable PCI/PCIE */ #define CONFIG_PCIE1 /* PCIE controler 1 */ #define CONFIG_PCIE2 /* PCIE controler 2 */ @@ -648,6 +649,12 @@ #define CONFIG_DOS_PARTITION #endif +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + /* * Miscellaneous configurable options */ @@ -745,4 +752,8 @@ #include <asm/fsl_secure_boot.h> +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h new file mode 100644 index 0000000000..cb03e33b6e --- /dev/null +++ b/include/configs/db-mv784mp-gp.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_DB_MV7846MP_GP_H +#define _CONFIG_DB_MV7846MP_GP_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_ARMADA_XP /* SOC Family Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO_LATE + +#define CONFIG_SYS_TEXT_BASE 0x04000000 +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#include <config_cmd_default.h> +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_I2C +#define CONFIG_CMD_PING +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_CMD_TFTPPUT +#define CONFIG_CMD_TIME + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MVTWSI +#define CONFIG_I2C_MVTWSI_BASE MVEBU_TWSI_BASE +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 + +/* SPI NOR flash default params, used by sf commands */ +#define CONFIG_SF_DEFAULT_SPEED 1000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 +#define CONFIG_SPI_FLASH_STMICRO + +/* Environment in SPI NOR flash */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ +#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ +#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ + +#define CONFIG_PHY_MARVELL /* there is a marvell phy */ +#define CONFIG_PHY_BASE_ADDR 0x10 +#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_QSGMII +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ +#define CONFIG_RESET_PHY_R + +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ +#define CONFIG_SYS_ALT_MEMTEST + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +#endif /* _CONFIG_DB_MV7846MP_GP_H */ diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h index 37bdcc0f33..47a8420f42 100644 --- a/include/configs/edb93xx.h +++ b/include/configs/edb93xx.h @@ -89,7 +89,6 @@ #define CONFIG_EP93XX 1 /* in a Cirrus Logic 93xx SoC */ #define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */ -#define CONFIG_SYS_HZ 1000 /* decr freq: 1 ms ticks */ #undef CONFIG_USE_IRQ /* Don't need IRQ/FIQ */ /* Monitor configuration */ diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index 371f32d840..6ba9bb7a1b 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -17,6 +17,13 @@ #include <linux/sizes.h> #define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DM +#define CONFIG_CMD_DM +#define CONFIG_DM_GPIO +#define CONFIG_DM_SERIAL +#define CONFIG_DM_SPI +#define CONFIG_DM_SPI_FLASH + #define CONFIG_ARCH_CPU_INIT #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h index 51926f721f..137d9b0d32 100644 --- a/include/configs/ks2_evm.h +++ b/include/configs/ks2_evm.h @@ -23,7 +23,6 @@ #define CONFIG_ARMV7 #define CONFIG_ARCH_CPU_INIT #define CONFIG_SYS_ARCH_TIMER -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_TEXT_BASE 0x0c001000 #define CONFIG_SPL_TARGET "u-boot-spi.gph" #define CONFIG_SYS_DCACHE_OFF diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index bb47813345..d1f6ea7e7b 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -69,6 +69,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_HAS_SERDES +#define CONFIG_FSL_CAAM /* Enable CAAM */ /* * IFC Definitions */ @@ -359,7 +360,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_MEMTEST_END 0x9fffffff #define CONFIG_SYS_LOAD_ADDR 0x82000000 -#define CONFIG_SYS_HZ 1000 /* * Stack sizes @@ -388,4 +388,14 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_OF_BOARD_SETUP #define CONFIG_CMD_BOOTZ +#define CONFIG_MISC_INIT_R + +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB +#endif + #endif diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 45b2272ff5..3c73af8ac3 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -48,6 +48,8 @@ #define CONFIG_SYS_HAS_SERDES +#define CONFIG_FSL_CAAM /* Enable CAAM */ + /* * IFC Definitions */ @@ -259,7 +261,6 @@ #define CONFIG_SYS_MEMTEST_END 0x9fffffff #define CONFIG_SYS_LOAD_ADDR 0x82000000 -#define CONFIG_SYS_HZ 1000 /* * Stack sizes @@ -288,4 +289,14 @@ #define CONFIG_OF_BOARD_SETUP #define CONFIG_CMD_BOOTZ +#define CONFIG_MISC_INIT_R + +/* Hash command with SHA acceleration supported in hardware */ +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB +#endif + #endif diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index a72e1f3567..6fe032c9ff 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -253,8 +253,6 @@ #define CONFIG_NR_DRAM_BANKS 3 -#define CONFIG_SYS_HZ 1000 - #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h new file mode 100644 index 0000000000..72217bdb57 --- /dev/null +++ b/include/configs/maxbcm.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_DB_MV7846MP_GP_H +#define _CONFIG_DB_MV7846MP_GP_H + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_ARMADA_XP /* SOC Family Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO_LATE + +#define CONFIG_SYS_TEXT_BASE 0x04000000 +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ +#include <config_cmd_default.h> +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_I2C +#define CONFIG_CMD_PING +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_CMD_TFTPPUT +#define CONFIG_CMD_TIME + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MVTWSI +#define CONFIG_I2C_MVTWSI_BASE MVEBU_TWSI_BASE +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 + +/* SPI NOR flash default params, used by sf commands */ +#define CONFIG_SF_DEFAULT_SPEED 1000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 +#define CONFIG_SPI_FLASH_STMICRO + +/* Environment in SPI NOR flash */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ +#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ +#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ + +#define CONFIG_PHY_MARVELL /* there is a marvell phy */ +#define CONFIG_PHY_BASE_ADDR 0x0 +#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ +#define CONFIG_RESET_PHY_R + +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ +#define CONFIG_SYS_ALT_MEMTEST + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +#endif /* _CONFIG_DB_MV7846MP_GP_H */ diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index ab8ac60df2..91bd37d6bc 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -38,6 +38,7 @@ #define CONFIG_POWER_TPS65090_EC #define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */ +#define CONFIG_DM_CROS_EC #define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_EXYNOS diff --git a/include/configs/rpi_b.h b/include/configs/rpi_b.h index 2d69809480..d9475e950b 100644 --- a/include/configs/rpi_b.h +++ b/include/configs/rpi_b.h @@ -31,6 +31,11 @@ */ #define CONFIG_MACH_TYPE MACH_TYPE_BCM2708 +/* Enable driver model */ +#define CONFIG_DM +#define CONFIG_CMD_DM +#define CONFIG_DM_GPIO + /* Memory layout */ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE 0x00000000 diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 0c6e9c7878..3633a355bd 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -276,6 +276,8 @@ #define CONFIG_SYS_I2C_SOFT_SPEED 50000 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F #define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_INIT_BOARD + #define CONFIG_SYS_MAX_I2C_BUS 7 #define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_S3C_UDC_OTG @@ -286,4 +288,10 @@ #define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DM +#define CONFIG_CMD_DM +#define CONFIG_DM_GPIO +#define CONFIG_DM_SERIAL + #endif /* __CONFIG_H */ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 27f3d0af47..4b30d148c3 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -187,17 +187,7 @@ * SPI Settings */ #define CONFIG_SOFT_SPI -#define CONFIG_SOFT_SPI_MODE SPI_MODE_3 -#define CONFIG_SOFT_SPI_GPIO_SCLK EXYNOS4_GPIO_Y31 -#define CONFIG_SOFT_SPI_GPIO_MOSI EXYNOS4_GPIO_Y33 -#define CONFIG_SOFT_SPI_GPIO_MISO EXYNOS4_GPIO_Y30 -#define CONFIG_SOFT_SPI_GPIO_CS EXYNOS4_GPIO_Y43 - -#define SPI_DELAY udelay(1) -#undef SPI_INIT -#define SPI_SCL(bit) universal_spi_scl(bit) -#define SPI_SDA(bit) universal_spi_sda(bit) -#define SPI_READ universal_spi_read() + #ifndef __ASSEMBLY__ void universal_spi_scl(int bit); void universal_spi_sda(int bit); diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h index b5064ab37c..2dee315f91 100644 --- a/include/configs/sacsng.h +++ b/include/configs/sacsng.h @@ -259,7 +259,6 @@ #define I2C_MOSI 0x00004000 /* PD 17: Master Out, Slave In */ #define I2C_MISO 0x00008000 /* PD 16: Master In, Slave Out */ -#undef SPI_INIT /* no port initialization needed */ #define SPI_READ ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0) #define SPI_SDA(bit) do { \ if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \ diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 69726432a3..ee4b24473c 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -32,6 +32,7 @@ #define CONFIG_DM_GPIO #define CONFIG_DM_TEST #define CONFIG_DM_SERIAL +#define CONFIG_DM_CROS_EC #define CONFIG_SYS_STDIO_DEREGISTER @@ -97,8 +98,8 @@ #define CONFIG_CMD_SF_TEST #define CONFIG_CMD_SPI #define CONFIG_SPI_FLASH -#define CONFIG_OF_SPI -#define CONFIG_OF_SPI_FLASH +#define CONFIG_DM_SPI +#define CONFIG_DM_SPI_FLASH #define CONFIG_SPI_FLASH_ATMEL #define CONFIG_SPI_FLASH_EON #define CONFIG_SPI_FLASH_GIGADEVICE @@ -172,6 +173,7 @@ #define CONFIG_CONSOLE_MUX #define CONFIG_SYS_CONSOLE_IS_IN_ENV #define LCD_BPP LCD_COLOR16 +#define CONFIG_LCD_BMP_RLE8 #define CONFIG_CROS_EC_KEYB #define CONFIG_KEYBOARD diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index 22835ffd64..982d0dcea3 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -223,4 +223,10 @@ #define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DM +#define CONFIG_CMD_DM +#define CONFIG_DM_GPIO +#define CONFIG_DM_SERIAL + #endif /* __CONFIG_H */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 1d947d7d9e..0c117bc5e7 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -105,8 +105,6 @@ /* standalone support */ #define CONFIG_STANDALONE_LOAD_ADDR 0x42000000 -#define CONFIG_SYS_HZ 1000 - /* baudrate */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 9abf2683c1..c3ad8beb90 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -59,7 +59,7 @@ BOARD_EXTRA_ENV_SETTINGS #if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI) -#define CONFIG_FDT_SPI +#define CONFIG_TEGRA_SPI #endif /* overrides for SPL build here */ diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 723ef72ef4..5d2b12a11d 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -24,6 +24,8 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_DM_SERIAL #endif +#define CONFIG_DM_SPI +#define CONFIG_DM_SPI_FLASH #define CONFIG_SYS_TIMER_RATE 1000000 #define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE @@ -154,10 +156,6 @@ #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_GPIO_SUPPORT -#ifdef CONFIG_SPL_BUILD -# define CONFIG_USE_PRIVATE_LIBGCC -#endif - #define CONFIG_SYS_GENERIC_BOARD /* Misc utility code */ diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 2705d2c55f..d97a9613ae 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -450,7 +450,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 #define CONFIG_CMDLINE_EDITING #define CONFIG_STACKSIZE (128u * SZ_1K) diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index 41a7c99edc..fe331bc082 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -99,7 +99,6 @@ #define CONFIG_VIDEO_BMP_GZIP #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) -#undef SPI_INIT #define SPI_DELAY udelay(10) #define SPI_SDA(val) zipitz2_spi_sda(val) diff --git a/include/cros_ec.h b/include/cros_ec.h index 1e4d8db96b..9e13146ecb 100644 --- a/include/cros_ec.h +++ b/include/cros_ec.h @@ -14,6 +14,7 @@ #include <fdtdec.h> #include <cros_ec_message.h> +#ifndef CONFIG_DM_CROS_EC /* Which interface is the device on? */ enum cros_ec_interface_t { CROS_EC_IF_NONE, @@ -22,9 +23,13 @@ enum cros_ec_interface_t { CROS_EC_IF_LPC, /* Intel Low Pin Count interface */ CROS_EC_IF_SANDBOX, }; +#endif /* Our configuration information */ struct cros_ec_dev { +#ifdef CONFIG_DM_CROS_EC + struct udevice *dev; /* Transport device */ +#else enum cros_ec_interface_t interface; struct spi_slave *spi; /* Our SPI slave, if using SPI */ int node; /* Our node */ @@ -33,6 +38,7 @@ struct cros_ec_dev { unsigned int addr; /* Device address (for I2C) */ unsigned int bus_num; /* Bus number (for I2C) */ unsigned int max_frequency; /* Maximum interface frequency */ +#endif struct fdt_gpio_state ec_int; /* GPIO used as EC interrupt line */ int protocol_version; /* Protocol version to use */ int optimise_flash_write; /* Don't write erased flash blocks */ @@ -233,6 +239,22 @@ int cros_ec_flash_update_rw(struct cros_ec_dev *dev, */ struct cros_ec_dev *board_get_cros_ec_dev(void); +#ifdef CONFIG_DM_CROS_EC + +struct dm_cros_ec_ops { + int (*check_version)(struct udevice *dev); + int (*command)(struct udevice *dev, uint8_t cmd, int cmd_version, + const uint8_t *dout, int dout_len, + uint8_t **dinp, int din_len); + int (*packet)(struct udevice *dev, int out_bytes, int in_bytes); +}; + +#define dm_cros_ec_get_ops(dev) \ + ((struct dm_cros_ec_ops *)(dev)->driver->ops) + +int cros_ec_register(struct udevice *dev); + +#else /* !CONFIG_DM_CROS_EC */ /* Internal interfaces */ int cros_ec_i2c_init(struct cros_ec_dev *dev, const void *blob); @@ -336,6 +358,7 @@ int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, int cros_ec_spi_packet(struct cros_ec_dev *dev, int out_bytes, int in_bytes); int cros_ec_sandbox_packet(struct cros_ec_dev *dev, int out_bytes, int in_bytes); +#endif /** * Dump a block of data for a command. @@ -489,9 +512,11 @@ int cros_ec_get_error(void); * Returns information from the FDT about the Chrome EC flash * * @param blob FDT blob to use + * @param node Node offset to read from * @param config Structure to use to return information */ -int cros_ec_decode_ec_flash(const void *blob, struct fdt_cros_ec *config); +int cros_ec_decode_ec_flash(const void *blob, int node, + struct fdt_cros_ec *config); /** * Check the current keyboard state, in case recovery mode is requested. diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h index 7005d03d08..44cb7ef93b 100644 --- a/include/dm/device-internal.h +++ b/include/dm/device-internal.h @@ -66,6 +66,19 @@ int device_bind_by_name(struct udevice *parent, bool pre_reloc_only, int device_probe(struct udevice *dev); /** + * device_probe() - Probe a child device, activating it + * + * Activate a device so that it is ready for use. All its parents are probed + * first. The child is provided with parent data if parent_priv is not NULL. + * + * @dev: Pointer to device to probe + * @parent_priv: Pointer to parent data. If non-NULL then this is provided to + * the child. + * @return 0 if OK, -ve on error + */ +int device_probe_child(struct udevice *dev, void *parent_priv); + +/** * device_remove() - Remove a device, de-activating it * * De-activate a device so that it is no longer ready for use. All its diff --git a/include/dm/device.h b/include/dm/device.h index c8a4072bcf..9ce95a834e 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -57,7 +57,8 @@ struct driver_info; * @sibling_node: Next device in list of all devices * @flags: Flags for this device DM_FLAG_... * @req_seq: Requested sequence number for this device (-1 = any) - * @seq: Allocated sequence number for this device (-1 = none) + * @seq: Allocated sequence number for this device (-1 = none). This is set up + * when the device is probed and will be unique within the device's uclass. */ struct udevice { struct driver *driver; @@ -96,6 +97,12 @@ struct udevice_id { ulong data; }; +#ifdef CONFIG_OF_CONTROL +#define of_match_ptr(_ptr) (_ptr) +#else +#define of_match_ptr(_ptr) NULL +#endif /* CONFIG_OF_CONTROL */ + /** * struct driver - A driver for a feature or peripheral * @@ -133,6 +140,10 @@ struct udevice_id { * @per_child_auto_alloc_size: Each device can hold private data owned by * its parent. If required this will be automatically allocated if this * value is non-zero. + * TODO(sjg@chromium.org): I'm considering dropping this, and just having + * device_probe_child() pass it in. So far the use case for allocating it + * is SPI, but I found that unsatisfactory. Since it is here I will leave it + * until things are clearer. * @ops: Driver-specific operations. This is typically a list of function * pointers defined by the driver, to implement driver functions required by * the uclass. @@ -274,4 +285,22 @@ int device_find_child_by_of_offset(struct udevice *parent, int of_offset, int device_get_child_by_of_offset(struct udevice *parent, int seq, struct udevice **devp); +/** + * device_find_first_child() - Find the first child of a device + * + * @parent: Parent device to search + * @devp: Returns first child device, or NULL if none + * @return 0 + */ +int device_find_first_child(struct udevice *parent, struct udevice **devp); + +/** + * device_find_first_child() - Find the first child of a device + * + * @devp: Pointer to previous child device on entry. Returns pointer to next + * child device, or NULL if none + * @return 0 + */ +int device_find_next_child(struct udevice **devp); + #endif diff --git a/include/dm/lists.h b/include/dm/lists.h index 2356895246..704e33e37f 100644 --- a/include/dm/lists.h +++ b/include/dm/lists.h @@ -38,7 +38,7 @@ struct uclass_driver *lists_uclass_lookup(enum uclass_id id); * This searches the U_BOOT_DEVICE() structures and creates new devices for * each one. The devices will have @parent as their parent. * - * @parent: parent driver (root) + * @parent: parent device (root) * @early_only: If true, bind only drivers with the DM_INIT_F flag. If false * bind all drivers. */ @@ -50,7 +50,7 @@ int lists_bind_drivers(struct udevice *parent, bool pre_reloc_only); * This creates a new device bound to the given device tree node, with * @parent as its parent. * - * @parent: parent driver (root) + * @parent: parent device (root) * @blob: device tree blob * @offset: offset of this device tree node * @devp: if non-NULL, returns a pointer to the bound device diff --git a/include/dm/platdata.h b/include/dm/platdata.h index 2bc8b147ed..fbc8a6b3ad 100644 --- a/include/dm/platdata.h +++ b/include/dm/platdata.h @@ -11,10 +11,12 @@ #ifndef _DM_PLATDATA_H #define _DM_PLATDATA_H +#include <linker_lists.h> + /** * struct driver_info - Information required to instantiate a device * - * @name: Device name + * @name: Driver name * @platdata: Driver-specific platform data */ struct driver_info { @@ -25,4 +27,8 @@ struct driver_info { #define U_BOOT_DEVICE(__name) \ ll_entry_declare(struct driver_info, __name, driver_info) +/* Declare a list of devices. The argument is a driver_info[] array */ +#define U_BOOT_DEVICES(__name) \ + ll_entry_declare_list(struct driver_info, __name, driver_info) + #endif diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 7f0e37b7b7..a8944c97d0 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -18,10 +18,16 @@ enum uclass_id { UCLASS_TEST, UCLASS_TEST_FDT, UCLASS_TEST_BUS, + UCLASS_SPI_EMUL, /* sandbox SPI device emulator */ + UCLASS_SIMPLE_BUS, /* U-Boot uclasses start here */ UCLASS_GPIO, /* Bank of general-purpose I/O pins */ UCLASS_SERIAL, /* Serial UART */ + UCLASS_SPI, /* SPI bus */ + UCLASS_SPI_GENERIC, /* Generic SPI flash target */ + UCLASS_SPI_FLASH, /* SPI flash */ + UCLASS_CROS_EC, /* Chrome OS EC */ UCLASS_COUNT, UCLASS_INVALID = -1, diff --git a/include/dm/uclass.h b/include/dm/uclass.h index 8d09ecff7b..f6ec6d7e9f 100644 --- a/include/dm/uclass.h +++ b/include/dm/uclass.h @@ -11,6 +11,7 @@ #define _DM_UCLASS_H #include <dm/uclass-id.h> +#include <linker_lists.h> #include <linux/list.h> /** diff --git a/include/dm/util.h b/include/dm/util.h index 8be64a921d..6ac3a38ef0 100644 --- a/include/dm/util.h +++ b/include/dm/util.h @@ -5,6 +5,7 @@ */ #ifndef __DM_UTIL_H +#define __DM_UTIL_H void dm_warn(const char *fmt, ...); diff --git a/include/fdtdec.h b/include/fdtdec.h index 2590d3071f..4ae77be9ba 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -40,6 +40,27 @@ struct fdt_memory { fdt_addr_t end; }; +/* + * Information about a resource. start is the first address of the resource + * and end is the last address (inclusive). The length of the resource will + * be equal to: end - start + 1. + */ +struct fdt_resource { + fdt_addr_t start; + fdt_addr_t end; +}; + +/** + * Compute the size of a resource. + * + * @param res the resource to operate on + * @return the size of the resource + */ +static inline fdt_size_t fdt_resource_size(const struct fdt_resource *res) +{ + return res->end - res->start + 1; +} + /** * Compat types that we know about and for which we might have drivers. * Each is named COMPAT_<dir>_<filename> where <dir> is the directory @@ -96,6 +117,7 @@ enum fdt_compat_id { COMPAT_NXP_PTN3460, /* NXP PTN3460 DP/LVDS bridge */ COMPAT_SAMSUNG_EXYNOS_SYSMMU, /* Exynos sysmmu */ COMPAT_PARADE_PS8625, /* Parade PS8622 EDP->LVDS bridge */ + COMPAT_INTEL_LPC, /* Intel Low Pin Count I/F */ COMPAT_COUNT, }; @@ -597,4 +619,46 @@ struct fmap_entry { */ int fdtdec_read_fmap_entry(const void *blob, int node, const char *name, struct fmap_entry *entry); + +/** + * Obtain an indexed resource from a device property. + * + * @param fdt FDT blob + * @param node node to examine + * @param property name of the property to parse + * @param index index of the resource to retrieve + * @param res returns the resource + * @return 0 if ok, negative on error + */ +int fdt_get_resource(const void *fdt, int node, const char *property, + unsigned int index, struct fdt_resource *res); + +/** + * Obtain a named resource from a device property. + * + * Look up the index of the name in a list of strings and return the resource + * at that index. + * + * @param fdt FDT blob + * @param node node to examine + * @param property name of the property to parse + * @param prop_names name of the property containing the list of names + * @param name the name of the entry to look up + * @param res returns the resource + */ +int fdt_get_named_resource(const void *fdt, int node, const char *property, + const char *prop_names, const char *name, + struct fdt_resource *res); + +/** + * Look at the reg property of a device node that represents a PCI device + * and parse the bus, device and function number from it. + * + * @param fdt FDT blob + * @param node node to examine + * @param bdf returns bus, device, function triplet + * @return 0 if ok, negative on error + */ +int fdtdec_pci_get_bdf(const void *fdt, int node, int *bdf); + #endif diff --git a/include/fsl_sec.h b/include/fsl_sec.h new file mode 100644 index 0000000000..aa850a3bf1 --- /dev/null +++ b/include/fsl_sec.h @@ -0,0 +1,181 @@ +/* + * Common internal memory map for some Freescale SoCs + * + * Copyright 2014 Freescale Semiconductor, Inc. + * + */ + +#ifndef __FSL_SEC_H +#define __FSL_SEC_H + +#include <common.h> +#include <asm/io.h> + +#ifdef CONFIG_SYS_FSL_SEC_LE +#define sec_in32(a) in_le32(a) +#define sec_out32(a, v) out_le32(a, v) +#define sec_in16(a) in_le16(a) +#define sec_clrbits32 clrbits_le32 +#define sec_setbits32 setbits_le32 +#elif defined(CONFIG_SYS_FSL_SEC_BE) +#define sec_in32(a) in_be32(a) +#define sec_out32(a, v) out_be32(a, v) +#define sec_in16(a) in_be16(a) +#define sec_clrbits32 clrbits_be32 +#define sec_setbits32 setbits_be32 +#else +#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined +#endif + +/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */ +#if CONFIG_SYS_FSL_SEC_COMPAT >= 4 +/* RNG4 TRNG test registers */ +struct rng4tst { +#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */ + u32 rtmctl; /* misc. control register */ + u32 rtscmisc; /* statistical check misc. register */ + u32 rtpkrrng; /* poker range register */ +#define RTSDCTL_ENT_DLY_MIN 1200 +#define RTSDCTL_ENT_DLY_MAX 12800 + union { + u32 rtpkrmax; /* PRGM=1: poker max. limit register */ + u32 rtpkrsq; /* PRGM=0: poker square calc. result register */ + }; +#define RTSDCTL_ENT_DLY_SHIFT 16 +#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT) + u32 rtsdctl; /* seed control register */ + union { + u32 rtsblim; /* PRGM=1: sparse bit limit register */ + u32 rttotsam; /* PRGM=0: total samples register */ + }; + u32 rtfreqmin; /* frequency count min. limit register */ + union { + u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */ + u32 rtfreqcnt; /* PRGM=0: freq. count register */ + }; + u32 rsvd1[40]; +#define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001 + u32 rdsta; /*RNG DRNG Status Register*/ + u32 rsvd2[15]; +}; + +typedef struct ccsr_sec { + u32 res0; + u32 mcfgr; /* Master CFG Register */ + u8 res1[0x4]; + u32 scfgr; + struct { + u32 ms; /* Job Ring LIODN Register, MS */ + u32 ls; /* Job Ring LIODN Register, LS */ + } jrliodnr[4]; + u8 res2[0x2c]; + u32 jrstartr; /* Job Ring Start Register */ + struct { + u32 ms; /* RTIC LIODN Register, MS */ + u32 ls; /* RTIC LIODN Register, LS */ + } rticliodnr[4]; + u8 res3[0x1c]; + u32 decorr; /* DECO Request Register */ + struct { + u32 ms; /* DECO LIODN Register, MS */ + u32 ls; /* DECO LIODN Register, LS */ + } decoliodnr[8]; + u8 res4[0x40]; + u32 dar; /* DECO Avail Register */ + u32 drr; /* DECO Reset Register */ + u8 res5[0x4d8]; + struct rng4tst rng; /* RNG Registers */ + u8 res11[0x8a0]; + u32 crnr_ms; /* CHA Revision Number Register, MS */ + u32 crnr_ls; /* CHA Revision Number Register, LS */ + u32 ctpr_ms; /* Compile Time Parameters Register, MS */ + u32 ctpr_ls; /* Compile Time Parameters Register, LS */ + u8 res6[0x10]; + u32 far_ms; /* Fault Address Register, MS */ + u32 far_ls; /* Fault Address Register, LS */ + u32 falr; /* Fault Address LIODN Register */ + u32 fadr; /* Fault Address Detail Register */ + u8 res7[0x4]; + u32 csta; /* CAAM Status Register */ + u8 res8[0x8]; + u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/ + u32 ccbvid; /* CHA Cluster Block Version ID Register */ + u32 chavid_ms; /* CHA Version ID Register, MS */ + u32 chavid_ls; /* CHA Version ID Register, LS */ + u32 chanum_ms; /* CHA Number Register, MS */ + u32 chanum_ls; /* CHA Number Register, LS */ + u32 secvid_ms; /* SEC Version ID Register, MS */ + u32 secvid_ls; /* SEC Version ID Register, LS */ + u8 res9[0x6020]; + u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */ + u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */ + u8 res10[0x8fd8]; +} ccsr_sec_t; + +#define SEC_CTPR_MS_AXI_LIODN 0x08000000 +#define SEC_CTPR_MS_QI 0x02000000 +#define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001 +#define SEC_CTPR_MS_VIRT_EN_POR 0x00000002 +#define SEC_RVID_MA 0x0f000000 +#define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000 +#define SEC_CHANUM_MS_JRNUM_SHIFT 28 +#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000 +#define SEC_CHANUM_MS_DECONUM_SHIFT 24 +#define SEC_SECVID_MS_IPID_MASK 0xffff0000 +#define SEC_SECVID_MS_IPID_SHIFT 16 +#define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00 +#define SEC_SECVID_MS_MAJ_REV_SHIFT 8 +#define SEC_CCBVID_ERA_MASK 0xff000000 +#define SEC_CCBVID_ERA_SHIFT 24 +#define SEC_SCFGR_RDBENABLE 0x00000400 +#define SEC_SCFGR_VIRT_EN 0x00008000 +#define SEC_CHAVID_LS_RNG_SHIFT 16 +#define SEC_CHAVID_RNG_LS_MASK 0x000f0000 + +#define CONFIG_JRSTARTR_JR0 0x00000001 + +struct jr_regs { +#ifdef CONFIG_SYS_FSL_SEC_LE + u32 irba_l; + u32 irba_h; +#else + u32 irba_h; + u32 irba_l; +#endif + u32 rsvd1; + u32 irs; + u32 rsvd2; + u32 irsa; + u32 rsvd3; + u32 irja; +#ifdef CONFIG_SYS_FSL_SEC_LE + u32 orba_l; + u32 orba_h; +#else + u32 orba_h; + u32 orba_l; +#endif + u32 rsvd4; + u32 ors; + u32 rsvd5; + u32 orjr; + u32 rsvd6; + u32 orsf; + u32 rsvd7; + u32 jrsta; + u32 rsvd8; + u32 jrint; + u32 jrcfg0; + u32 jrcfg1; + u32 rsvd9; + u32 irri; + u32 rsvd10; + u32 orwi; + u32 rsvd11; + u32 jrcr; +}; + +int sec_init(void); +#endif + +#endif /* __FSL_SEC_H */ diff --git a/include/image.h b/include/image.h index 4347532520..a13a30289f 100644 --- a/include/image.h +++ b/include/image.h @@ -233,6 +233,7 @@ struct lmb; #define IH_TYPE_GPIMAGE 17 /* TI Keystone GPHeader Image */ #define IH_TYPE_ATMELIMAGE 18 /* ATMEL ROM bootable Image */ #define IH_TYPE_SOCFPGAIMAGE 19 /* Altera SOCFPGA Preloader */ +#define IH_TYPE_X86_SETUP 20 /* x86 setup.bin Image */ /* * Compression Types @@ -273,6 +274,7 @@ typedef struct image_info { ulong image_start, image_len; /* start of image within blob, len of image */ ulong load; /* load addr for the image */ uint8_t comp, type, os; /* compression, type of image, os type */ + uint8_t arch; /* CPU architecture */ } image_info_t; /* @@ -303,6 +305,10 @@ typedef struct bootm_headers { void *fit_hdr_fdt; /* FDT blob FIT image header */ const char *fit_uname_fdt; /* FDT blob subimage node unit name */ int fit_noffset_fdt;/* FDT blob subimage node offset */ + + void *fit_hdr_setup; /* x86 setup FIT image header */ + const char *fit_uname_setup; /* x86 setup subimage node name */ + int fit_noffset_setup;/* x86 setup subimage node offset */ #endif #ifndef USE_HOSTCC @@ -417,6 +423,9 @@ enum fit_load_op { FIT_LOAD_REQUIRED, /* Must be provided */ }; +int boot_get_setup(bootm_headers_t *images, uint8_t arch, ulong *setup_start, + ulong *setup_len); + #ifndef USE_HOSTCC /* Image format types, returned by _get_format() routine */ #define IMAGE_FORMAT_INVALID 0x00 @@ -438,6 +447,9 @@ int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images, uint8_t arch, ulong *rd_start, ulong *rd_end); #endif +int boot_get_setup_fit(bootm_headers_t *images, uint8_t arch, + ulong *setup_start, ulong *setup_len); + /** * fit_image_load() - load an image from a FIT * @@ -721,6 +733,7 @@ int bootz_setup(ulong image, ulong *start, ulong *end); #define FIT_RAMDISK_PROP "ramdisk" #define FIT_FDT_PROP "fdt" #define FIT_DEFAULT_PROP "default" +#define FIT_SETUP_PROP "setup" #define FIT_MAX_HASH_LEN HASH_MAX_DIGEST_SIZE diff --git a/include/libfdt.h b/include/libfdt.h index a1ef1e15df..f3cbb637be 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -163,6 +163,31 @@ int fdt_first_subnode(const void *fdt, int offset); */ int fdt_next_subnode(const void *fdt, int offset); +/** + * fdt_for_each_subnode - iterate over all subnodes of a parent + * + * This is actually a wrapper around a for loop and would be used like so: + * + * fdt_for_each_subnode(fdt, node, parent) { + * ... + * use node + * ... + * } + * + * Note that this is implemented as a macro and node is used as iterator in + * the loop. It should therefore be a locally allocated variable. The parent + * variable on the other hand is never modified, so it can be constant or + * even a literal. + * + * @fdt: FDT blob (const void *) + * @node: child node (int) + * @parent: parent node (int) + */ +#define fdt_for_each_subnode(fdt, node, parent) \ + for (node = fdt_first_subnode(fdt, parent); \ + node >= 0; \ + node = fdt_next_subnode(fdt, node)) + /**********************************************************************/ /* General functions */ /**********************************************************************/ @@ -857,6 +882,53 @@ int fdt_node_offset_by_compatible(const void *fdt, int startoffset, */ int fdt_stringlist_contains(const char *strlist, int listlen, const char *str); +/** + * fdt_count_strings - count the number of strings in a string list + * @fdt: pointer to the device tree blob + * @node: offset of the node + * @property: name of the property containing the string list + * @return: the number of strings in the given property + */ +int fdt_count_strings(const void *fdt, int node, const char *property); + +/** + * fdt_find_string - find a string in a string list and return its index + * @fdt: pointer to the device tree blob + * @node: offset of the node + * @property: name of the property containing the string list + * @string: string to look up in the string list + * @return: the index of the string or negative on error + */ +int fdt_find_string(const void *fdt, int node, const char *property, + const char *string); + +/** + * fdt_get_string_index() - obtain the string at a given index in a string list + * @fdt: pointer to the device tree blob + * @node: offset of the node + * @property: name of the property containing the string list + * @index: index of the string to return + * @output: return location for the string + * @return: 0 if the string was found or a negative error code otherwise + */ +int fdt_get_string_index(const void *fdt, int node, const char *property, + int index, const char **output); + +/** + * fdt_get_string() - obtain the string at a given index in a string list + * @fdt: pointer to the device tree blob + * @node: offset of the node + * @property: name of the property containing the string list + * @output: return location for the string + * @return: 0 if the string was found or a negative error code otherwise + * + * This is a shortcut for: + * + * fdt_get_string_index(fdt, node, property, 0, output). + */ +int fdt_get_string(const void *fdt, int node, const char *property, + const char **output); + /**********************************************************************/ /* Read-only functions (addressing related) */ /**********************************************************************/ diff --git a/include/linker_lists.h b/include/linker_lists.h index 507d61ba9a..d37fba44dc 100644 --- a/include/linker_lists.h +++ b/include/linker_lists.h @@ -11,6 +11,8 @@ #ifndef __LINKER_LISTS_H__ #define __LINKER_LISTS_H__ +#include <linux/compiler.h> + /* * There is no use in including this from ASM files, but that happens * anyway, e.g. PPC kgdb.S includes command.h which incluse us. @@ -141,6 +143,27 @@ section(".u_boot_list_2_"#_list"_2_"#_name))) /** + * ll_entry_declare_list() - Declare a list of link-generated array entries + * @_type: Data type of each entry + * @_name: Name of the entry + * @_list: name of the list. Should contain only characters allowed + * in a C variable name! + * + * This is like ll_entry_declare() but creates multiple entries. It should + * be assigned to an array. + * + * ll_entry_declare_list(struct my_sub_cmd, my_sub_cmd, cmd_sub, cmd.sub) = { + * { .x = 3, .y = 4 }, + * { .x = 8, .y = 2 }, + * { .x = 1, .y = 7 } + * }; + */ +#define ll_entry_declare_list(_type, _name, _list) \ + _type _u_boot_list_2_##_list##_2_##_name[] __aligned(4) \ + __attribute__((unused, \ + section(".u_boot_list_2_"#_list"_2_"#_name))) + +/** * We need a 0-byte-size type for iterator symbols, and the compiler * does not allow defining objects of C type 'void'. Using an empty * struct is allowed by the compiler, but causes gcc versions 4.4 and diff --git a/include/linux/mbus.h b/include/linux/mbus.h new file mode 100644 index 0000000000..717cbeab37 --- /dev/null +++ b/include/linux/mbus.h @@ -0,0 +1,73 @@ +/* + * Marvell MBUS common definitions. + * + * Copyright (C) 2008 Marvell Semiconductor + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __LINUX_MBUS_H +#define __LINUX_MBUS_H + +struct resource; + +struct mbus_dram_target_info { + /* + * The 4-bit MBUS target ID of the DRAM controller. + */ + u8 mbus_dram_target_id; + + /* + * The base address, size, and MBUS attribute ID for each + * of the possible DRAM chip selects. Peripherals are + * required to support at least 4 decode windows. + */ + int num_cs; + struct mbus_dram_window { + u8 cs_index; + u8 mbus_attr; + u32 base; + u32 size; + } cs[4]; +}; + +struct mvebu_mbus_state { + void __iomem *mbuswins_base; + void __iomem *sdramwins_base; + struct dentry *debugfs_root; + struct dentry *debugfs_sdram; + struct dentry *debugfs_devs; + const struct mvebu_mbus_soc_data *soc; + int hw_io_coherency; +}; + +/* Flags for PCI/PCIe address decoding regions */ +#define MVEBU_MBUS_PCI_IO 0x1 +#define MVEBU_MBUS_PCI_MEM 0x2 +#define MVEBU_MBUS_PCI_WA 0x3 + +/* + * Magic value that explicits that we don't need a remapping-capable + * address decoding window. + */ +#define MVEBU_MBUS_NO_REMAP (0xffffffff) + +/* Maximum size of a mbus window name */ +#define MVEBU_MBUS_MAX_WINNAME_SZ 32 + +const struct mbus_dram_target_info *mvebu_mbus_dram_info(void); +void mvebu_mbus_get_pcie_mem_aperture(struct resource *res); +void mvebu_mbus_get_pcie_io_aperture(struct resource *res); +int mvebu_mbus_add_window_remap_by_id(unsigned int target, + unsigned int attribute, + phys_addr_t base, size_t size, + phys_addr_t remap); +int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute, + phys_addr_t base, size_t size); +int mvebu_mbus_del_window(phys_addr_t base, size_t size); +int mbus_dt_setup_win(struct mvebu_mbus_state *mbus, + u32 base, u32 size, u8 target, u8 attr); + +#endif /* __LINUX_MBUS_H */ diff --git a/include/netdev.h b/include/netdev.h index a887bfb5f7..34651ab377 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -65,6 +65,7 @@ int mpc512x_fec_initialize(bd_t *bis); int mpc5xxx_fec_initialize(bd_t *bis); int mpc82xx_scc_enet_initialize(bd_t *bis); int mvgbe_initialize(bd_t *bis); +int mvneta_initialize(bd_t *bis, int base_addr, int devnum, int phy_addr); int natsemi_initialize(bd_t *bis); int ne2k_register(void); int npe_initialize(bd_t *bis); diff --git a/include/phy.h b/include/phy.h index 2fcc328d5b..b495077697 100644 --- a/include/phy.h +++ b/include/phy.h @@ -32,7 +32,9 @@ #define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \ SUPPORTED_10000baseT_Full) +#ifndef PHY_ANEG_TIMEOUT #define PHY_ANEG_TIMEOUT 4000 +#endif typedef enum { diff --git a/include/serial_mxc.h b/include/serial_mxc.h new file mode 100644 index 0000000000..7d3ace2f9e --- /dev/null +++ b/include/serial_mxc.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2014 Google, Inc + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __serial_mxc_h +#define __serial_mxc_h + +/* Information about a serial port */ +struct mxc_serial_platdata { + struct mxc_uart *reg; /* address of registers in physical memory */ +}; + +#endif diff --git a/include/serial_pl01x.h b/include/serial_pl01x.h new file mode 100644 index 0000000000..5e068f390b --- /dev/null +++ b/include/serial_pl01x.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2014 Google, Inc + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __serial_pl01x_h +#define __serial_pl01x_h + +enum pl01x_type { + TYPE_PL010, + TYPE_PL011, +}; + +/* + *Information about a serial port + * + * @base: Register base address + * @type: Port type + * @clock: Input clock rate, used for calculating the baud rate divisor + */ +struct pl01x_serial_platdata { + unsigned long base; + enum pl01x_type type; + unsigned int clock; +}; + +#endif diff --git a/include/spi.h b/include/spi.h index b673be270c..aa0a48ea62 100644 --- a/include/spi.h +++ b/include/spi.h @@ -54,12 +54,31 @@ #define SPI_DEFAULT_WORDLEN 8 +#ifdef CONFIG_DM_SPI +struct dm_spi_bus { + uint max_hz; +}; + +#endif /* CONFIG_DM_SPI */ + /** * struct spi_slave - Representation of a SPI slave * - * Drivers are expected to extend this with controller-specific data. + * For driver model this is the per-child data used by the SPI bus. It can + * be accessed using dev_get_parentdata() on the slave device. Each SPI + * driver should define this child data in its U_BOOT_DRIVER() definition: + * + * .per_child_auto_alloc_size = sizeof(struct spi_slave), * - * @bus: ID of the bus that the slave is attached to. + * If not using driver model, drivers are expected to extend this with + * controller-specific data. + * + * @dev: SPI slave device + * @max_hz: Maximum speed for this slave + * @mode: SPI mode to use for this slave (see SPI mode flags) + * @bus: ID of the bus that the slave is attached to. For + * driver model this is the sequence number of the SPI + * bus (bus->seq) so does not need to be stored * @cs: ID of the chip select connected to the slave. * @op_mode_rx: SPI RX operation mode. * @op_mode_tx: SPI TX operation mode. @@ -71,7 +90,13 @@ * @flags: Indication of SPI flags. */ struct spi_slave { +#ifdef CONFIG_DM_SPI + struct udevice *dev; /* struct spi_slave is dev->parentdata */ + uint max_hz; + uint mode; +#else unsigned int bus; +#endif unsigned int cs; u8 op_mode_rx; u8 op_mode_tx; @@ -228,8 +253,9 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, * Returns: 1 if bus:cs identifies a valid chip on this board, 0 * otherwise. */ -int spi_cs_is_valid(unsigned int bus, unsigned int cs); +int spi_cs_is_valid(unsigned int bus, unsigned int cs); +#ifndef CONFIG_DM_SPI /** * Activate a SPI chipselect. * This function is provided by the board code when using a driver @@ -255,6 +281,7 @@ void spi_cs_deactivate(struct spi_slave *slave); * @hz: The transfer speed */ void spi_set_speed(struct spi_slave *slave, uint hz); +#endif /** * Write 8 bits, then read 8 bits. @@ -305,4 +332,270 @@ struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node, struct spi_slave *spi_base_setup_slave_fdt(const void *blob, int busnum, int node); +#ifdef CONFIG_DM_SPI + +/** + * struct spi_cs_info - Information about a bus chip select + * + * @dev: Connected device, or NULL if none + */ +struct spi_cs_info { + struct udevice *dev; +}; + +/** + * struct struct dm_spi_ops - Driver model SPI operations + * + * The uclass interface is implemented by all SPI devices which use + * driver model. + */ +struct dm_spi_ops { + /** + * Claim the bus and prepare it for communication. + * + * The device provided is the slave device. It's parent controller + * will be used to provide the communication. + * + * This must be called before doing any transfers with a SPI slave. It + * will enable and initialize any SPI hardware as necessary, and make + * sure that the SCK line is in the correct idle state. It is not + * allowed to claim the same bus for several slaves without releasing + * the bus in between. + * + * @bus: The SPI slave + * + * Returns: 0 if the bus was claimed successfully, or a negative value + * if it wasn't. + */ + int (*claim_bus)(struct udevice *bus); + + /** + * Release the SPI bus + * + * This must be called once for every call to spi_claim_bus() after + * all transfers have finished. It may disable any SPI hardware as + * appropriate. + * + * @bus: The SPI slave + */ + int (*release_bus)(struct udevice *bus); + + /** + * Set the word length for SPI transactions + * + * Set the word length (number of bits per word) for SPI transactions. + * + * @bus: The SPI slave + * @wordlen: The number of bits in a word + * + * Returns: 0 on success, -ve on failure. + */ + int (*set_wordlen)(struct udevice *bus, unsigned int wordlen); + + /** + * SPI transfer + * + * This writes "bitlen" bits out the SPI MOSI port and simultaneously + * clocks "bitlen" bits in the SPI MISO port. That's just the way SPI + * works. + * + * The source of the outgoing bits is the "dout" parameter and the + * destination of the input bits is the "din" parameter. Note that + * "dout" and "din" can point to the same memory location, in which + * case the input data overwrites the output data (since both are + * buffered by temporary variables, this is OK). + * + * spi_xfer() interface: + * @dev: The slave device to communicate with + * @bitlen: How many bits to write and read. + * @dout: Pointer to a string of bits to send out. The bits are + * held in a byte array and are sent MSB first. + * @din: Pointer to a string of bits that will be filled in. + * @flags: A bitwise combination of SPI_XFER_* flags. + * + * Returns: 0 on success, not -1 on failure + */ + int (*xfer)(struct udevice *dev, unsigned int bitlen, const void *dout, + void *din, unsigned long flags); + + /** + * Set transfer speed. + * This sets a new speed to be applied for next spi_xfer(). + * @bus: The SPI bus + * @hz: The transfer speed + * @return 0 if OK, -ve on error + */ + int (*set_speed)(struct udevice *bus, uint hz); + + /** + * Set the SPI mode/flags + * + * It is unclear if we want to set speed and mode together instead + * of separately. + * + * @bus: The SPI bus + * @mode: Requested SPI mode (SPI_... flags) + * @return 0 if OK, -ve on error + */ + int (*set_mode)(struct udevice *bus, uint mode); + + /** + * Get information on a chip select + * + * This is only called when the SPI uclass does not know about a + * chip select, i.e. it has no attached device. It gives the driver + * a chance to allow activity on that chip select even so. + * + * @bus: The SPI bus + * @cs: The chip select (0..n-1) + * @info: Returns information about the chip select, if valid. + * On entry info->dev is NULL + * @return 0 if OK (and @info is set up), -ENODEV if the chip select + * is invalid, other -ve value on error + */ + int (*cs_info)(struct udevice *bus, uint cs, struct spi_cs_info *info); +}; + +struct dm_spi_emul_ops { + /** + * SPI transfer + * + * This writes "bitlen" bits out the SPI MOSI port and simultaneously + * clocks "bitlen" bits in the SPI MISO port. That's just the way SPI + * works. Here the device is a slave. + * + * The source of the outgoing bits is the "dout" parameter and the + * destination of the input bits is the "din" parameter. Note that + * "dout" and "din" can point to the same memory location, in which + * case the input data overwrites the output data (since both are + * buffered by temporary variables, this is OK). + * + * spi_xfer() interface: + * @slave: The SPI slave which will be sending/receiving the data. + * @bitlen: How many bits to write and read. + * @dout: Pointer to a string of bits sent to the device. The + * bits are held in a byte array and are sent MSB first. + * @din: Pointer to a string of bits that will be sent back to + * the master. + * @flags: A bitwise combination of SPI_XFER_* flags. + * + * Returns: 0 on success, not -1 on failure + */ + int (*xfer)(struct udevice *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags); +}; + +/** + * spi_find_bus_and_cs() - Find bus and slave devices by number + * + * Given a bus number and chip select, this finds the corresponding bus + * device and slave device. Neither device is activated by this function, + * although they may have been activated previously. + * + * @busnum: SPI bus number + * @cs: Chip select to look for + * @busp: Returns bus device + * @devp: Return slave device + * @return 0 if found, -ENODEV on error + */ +int spi_find_bus_and_cs(int busnum, int cs, struct udevice **busp, + struct udevice **devp); + +/** + * spi_get_bus_and_cs() - Find and activate bus and slave devices by number + * + * Given a bus number and chip select, this finds the corresponding bus + * device and slave device. + * + * If no such slave exists, and drv_name is not NULL, then a new slave device + * is automatically bound on this chip select. + * + * Ths new slave device is probed ready for use with the given speed and mode. + * + * @busnum: SPI bus number + * @cs: Chip select to look for + * @speed: SPI speed to use for this slave + * @mode: SPI mode to use for this slave + * @drv_name: Name of driver to attach to this chip select + * @dev_name: Name of the new device thus created + * @busp: Returns bus device + * @devp: Return slave device + * @return 0 if found, -ve on error + */ +int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, + const char *drv_name, const char *dev_name, + struct udevice **busp, struct spi_slave **devp); + +/** + * spi_chip_select() - Get the chip select for a slave + * + * @return the chip select this slave is attached to + */ +int spi_chip_select(struct udevice *slave); + +/** + * spi_bind_device() - bind a device to a bus's chip select + * + * This binds a new device to an given chip select (which must be unused). + * + * @bus: SPI bus to search + * @cs: Chip select to attach to + * @drv_name: Name of driver to attach to this chip select + * @dev_name: Name of the new device thus created + * @devp: Returns the newly bound device + */ +int spi_bind_device(struct udevice *bus, int cs, const char *drv_name, + const char *dev_name, struct udevice **devp); + +/** + * spi_ofdata_to_platdata() - decode standard SPI platform data + * + * This decodes the speed and mode from a device tree node and puts it into + * the spi_slave structure. + * + * @blob: Device tree blob + * @node: Node offset to read from + * @spi: Place to put the decoded information + */ +int spi_ofdata_to_platdata(const void *blob, int node, struct spi_slave *spi); + +/** + * spi_cs_info() - Check information on a chip select + * + * This checks a particular chip select on a bus to see if it has a device + * attached, or is even valid. + * + * @bus: The SPI bus + * @cs: The chip select (0..n-1) + * @info: Returns information about the chip select, if valid + * @return 0 if OK (and @info is set up), -ENODEV if the chip select + * is invalid, other -ve value on error + */ +int spi_cs_info(struct udevice *bus, uint cs, struct spi_cs_info *info); + +struct sandbox_state; + +/** + * sandbox_spi_get_emul() - get an emulator for a SPI slave + * + * This provides a way to attach an emulated SPI device to a particular SPI + * slave, so that xfer() operations on the slave will be handled by the + * emulator. If a emulator already exists on that chip select it is returned. + * Otherwise one is created. + * + * @state: Sandbox state + * @bus: SPI bus requesting the emulator + * @slave: SPI slave device requesting the emulator + * @emuip: Returns pointer to emulator + * @return 0 if OK, -ve on error + */ +int sandbox_spi_get_emul(struct sandbox_state *state, + struct udevice *bus, struct udevice *slave, + struct udevice **emulp); + +/* Access the serial operations for a device */ +#define spi_get_ops(dev) ((struct dm_spi_ops *)(dev)->driver->ops) +#define spi_emul_get_ops(dev) ((struct dm_spi_emul_ops *)(dev)->driver->ops) +#endif /* CONFIG_DM_SPI */ + #endif /* _SPI_H_ */ diff --git a/include/spi_flash.h b/include/spi_flash.h index 408a5b401c..5913b39e26 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -15,9 +15,8 @@ #ifndef _SPI_FLASH_H_ #define _SPI_FLASH_H_ -#include <spi.h> +#include <dm.h> /* Because we dereference struct udevice here */ #include <linux/types.h> -#include <linux/compiler.h> #ifndef CONFIG_SF_DEFAULT_SPEED # define CONFIG_SF_DEFAULT_SPEED 1000000 @@ -32,64 +31,19 @@ # define CONFIG_SF_DEFAULT_BUS 0 #endif -/* sf param flags */ -#define SECT_4K 1 << 1 -#define SECT_32K 1 << 2 -#define E_FSR 1 << 3 -#define WR_QPP 1 << 4 - -/* Enum list - Full read commands */ -enum spi_read_cmds { - ARRAY_SLOW = 1 << 0, - DUAL_OUTPUT_FAST = 1 << 1, - DUAL_IO_FAST = 1 << 2, - QUAD_OUTPUT_FAST = 1 << 3, - QUAD_IO_FAST = 1 << 4, -}; -#define RD_EXTN ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST -#define RD_FULL RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST - -/* Dual SPI flash memories */ -enum spi_dual_flash { - SF_SINGLE_FLASH = 0, - SF_DUAL_STACKED_FLASH = 1 << 0, - SF_DUAL_PARALLEL_FLASH = 1 << 1, -}; - -/** - * struct spi_flash_params - SPI/QSPI flash device params structure - * - * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO]) - * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id]) - * @ext_jedec: Device ext_jedec ID - * @sector_size: Sector size of this device - * @nr_sectors: No.of sectors on this device - * @e_rd_cmd: Enum list for read commands - * @flags: Important param, for flash specific behaviour - */ -struct spi_flash_params { - const char *name; - u32 jedec; - u16 ext_jedec; - u32 sector_size; - u32 nr_sectors; - u8 e_rd_cmd; - u16 flags; -}; - -extern const struct spi_flash_params spi_flash_params_table[]; +struct spi_slave; /** * struct spi_flash - SPI flash structure * * @spi: SPI slave * @name: Name of SPI flash - * @dual_flash: Indicates dual flash memories - dual stacked, parallel + * @dual_flash: Indicates dual flash memories - dual stacked, parallel * @shift: Flash shift useful in dual parallel * @size: Total flash size * @page_size: Write (page) size * @sector_size: Sector size - * @erase_size: Erase size + * @erase_size: Erase size * @bank_read_cmd: Bank read cmd * @bank_write_cmd: Bank write cmd * @bank_curr: Current flash bank @@ -97,8 +51,8 @@ extern const struct spi_flash_params spi_flash_params_table[]; * @erase_cmd: Erase cmd 4K, 32K, 64K * @read_cmd: Read cmd - Array Fast, Extn read and quad read. * @write_cmd: Write cmd - page and quad program. - * @dummy_byte: Dummy cycles for read operation. - * @memory_map: Address of read-only SPI flash access + * @dummy_byte: Dummy cycles for read operation. + * @memory_map: Address of read-only SPI flash access * @read: Flash read ops: Read len bytes at offset into buf * Supported cmds: Fast Array Read * @write: Flash write ops: Write len bytes from buf into offset @@ -108,7 +62,12 @@ extern const struct spi_flash_params spi_flash_params_table[]; * return 0 - Success, 1 - Failure */ struct spi_flash { +#ifdef CONFIG_DM_SPI_FLASH + struct spi_slave *spi; + struct udevice *dev; +#else struct spi_slave *spi; +#endif const char *name; u8 dual_flash; u8 shift; @@ -129,12 +88,75 @@ struct spi_flash { u8 dummy_byte; void *memory_map; +#ifndef CONFIG_DM_SPI_FLASH + /* + * These are not strictly needed for driver model, but keep them here + * whilt the transition is in progress. + * + * Normally each driver would provide its own operations, but for + * SPI flash most chips use the same algorithms. One approach is + * to create a 'common' SPI flash device which knows how to talk + * to most devices, and then allow other drivers to be used instead + * if requird, perhaps with a way of scanning through the list to + * find the driver that matches the device. + */ int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf); int (*write)(struct spi_flash *flash, u32 offset, size_t len, const void *buf); int (*erase)(struct spi_flash *flash, u32 offset, size_t len); +#endif }; +struct dm_spi_flash_ops { + int (*read)(struct udevice *dev, u32 offset, size_t len, void *buf); + int (*write)(struct udevice *dev, u32 offset, size_t len, + const void *buf); + int (*erase)(struct udevice *dev, u32 offset, size_t len); +}; + +/* Access the serial operations for a device */ +#define sf_get_ops(dev) ((struct dm_spi_flash_ops *)(dev)->driver->ops) + +#ifdef CONFIG_DM_SPI_FLASH +int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode, + struct udevice **devp); + +/* Compatibility function - this is the old U-Boot API */ +struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode); + +/* Compatibility function - this is the old U-Boot API */ +void spi_flash_free(struct spi_flash *flash); + +int spi_flash_remove(struct udevice *flash); + +static inline int spi_flash_read(struct spi_flash *flash, u32 offset, + size_t len, void *buf) +{ + return sf_get_ops(flash->dev)->read(flash->dev, offset, len, buf); +} + +static inline int spi_flash_write(struct spi_flash *flash, u32 offset, + size_t len, const void *buf) +{ + return sf_get_ops(flash->dev)->write(flash->dev, offset, len, buf); +} + +static inline int spi_flash_erase(struct spi_flash *flash, u32 offset, + size_t len) +{ + return sf_get_ops(flash->dev)->erase(flash->dev, offset, len); +} + +struct sandbox_state; + +int sandbox_sf_bind_emul(struct sandbox_state *state, int busnum, int cs, + struct udevice *bus, int of_offset, const char *spec); + +void sandbox_sf_unbind_emul(struct sandbox_state *state, int busnum, int cs); + +#else struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int spi_mode); @@ -169,6 +191,7 @@ static inline int spi_flash_erase(struct spi_flash *flash, u32 offset, { return flash->erase(flash, offset, len); } +#endif void spi_boot(void) __noreturn; void spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst); |