diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-arm/arch-imx/imx-regs.h | 177 | ||||
| -rw-r--r-- | include/asm-i386/types.h | 6 | ||||
| -rw-r--r-- | include/asm-microblaze/types.h | 6 | ||||
| -rw-r--r-- | include/asm-nios/types.h | 6 | ||||
| -rw-r--r-- | include/asm-nios2/types.h | 6 | ||||
| -rw-r--r-- | include/asm-ppc/global_data.h | 1 | ||||
| -rw-r--r-- | include/asm-ppc/immap_512x.h | 61 | ||||
| -rw-r--r-- | include/configs/ads5121.h | 30 | ||||
| -rw-r--r-- | include/mpc512x.h | 84 |
9 files changed, 298 insertions, 79 deletions
diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h index 318de22a49..ec94ba913f 100644 --- a/include/asm-arm/arch-imx/imx-regs.h +++ b/include/asm-arm/arch-imx/imx-regs.h @@ -6,11 +6,11 @@ * */ +#define IO_ADDRESS(x) ((x) | IMX_IO_BASE) + # ifndef __ASSEMBLY__ -# define __REG(x) (*((volatile u32 *)(x))) -# define __REG2(x,y) \ - ( __builtin_constant_p(y) ? (__REG((x) + (y))) \ - : (*(volatile u32 *)((u32)&__REG(x) + (y))) ) +# define __REG(x) (*((volatile u32 *)IO_ADDRESS(x))) +# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) # else # define __REG(x) (x) # define __REG2(x,y) ((x)+(y)) @@ -87,14 +87,20 @@ /* PLL registers */ #define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */ +#define CSCR_SPLL_RESTART (1<<22) +#define CSCR_MPLL_RESTART (1<<21) +#define CSCR_SYSTEM_SEL (1<<16) +#define CSCR_BCLK_DIV (0xf<<10) +#define CSCR_MPU_PRESC (1<<15) +#define CSCR_SPEN (1<<1) +#define CSCR_MPEN (1<<0) + #define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */ #define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */ #define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */ #define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ #define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */ -#define CSCR_MPLL_RESTART (1<<21) - /* * GPIO Module and I/O Multiplexer * x = 0..3 for reg_A, reg_B, reg_C, reg_D @@ -117,9 +123,12 @@ #define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8) #define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8) +#define GPIO_PORT_MAX 3 + #define GPIO_PIN_MASK 0x1f #define GPIO_PORT_MASK (0x3 << 5) +#define GPIO_PORT_SHIFT 5 #define GPIO_PORTA (0<<5) #define GPIO_PORTB (1<<5) #define GPIO_PORTC (2<<5) @@ -132,24 +141,37 @@ #define GPIO_PF (0<<9) #define GPIO_AF (1<<9) +#define GPIO_OCR_SHIFT 10 #define GPIO_OCR_MASK (3<<10) #define GPIO_AIN (0<<10) #define GPIO_BIN (1<<10) #define GPIO_CIN (2<<10) -#define GPIO_GPIO (3<<10) +#define GPIO_DR (3<<10) + +#define GPIO_AOUT_SHIFT 12 +#define GPIO_AOUT_MASK (3<<12) +#define GPIO_AOUT (0<<12) +#define GPIO_AOUT_ISR (1<<12) +#define GPIO_AOUT_0 (2<<12) +#define GPIO_AOUT_1 (3<<12) -#define GPIO_AOUT (1<<12) -#define GPIO_BOUT (1<<13) +#define GPIO_BOUT_SHIFT 14 +#define GPIO_BOUT_MASK (3<<14) +#define GPIO_BOUT (0<<14) +#define GPIO_BOUT_ISR (1<<14) +#define GPIO_BOUT_0 (2<<14) +#define GPIO_BOUT_1 (3<<14) + +#define GPIO_GIUS (1<<16) /* assignements for GPIO alternate/primary functions */ /* FIXME: This list is not completed. The correct directions are * missing on some (many) pins */ -#define PA0_PF_A24 ( GPIO_PORTA | GPIO_PF | 0 ) -#define PA0_AIN_SPI2_CLK ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 ) +#define PA0_AIN_SPI2_CLK ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0 ) #define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 ) -#define PA1_AOUT_SPI2_RXD ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 ) +#define PA1_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1 ) #define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 ) #define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 ) #define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 ) @@ -167,7 +189,7 @@ #define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 ) #define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 ) #define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 ) -#define PA17_AIN_SPI2_SS ( GPIO_PORTA | GPIO_AIN | 17 ) +#define PA17_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17 ) #define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 ) #define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 ) #define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 ) @@ -196,11 +218,11 @@ #define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 ) #define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 ) #define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 ) -#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 11 ) +#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | 11 ) #define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 ) -#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | GPIO_OUT | 12 ) +#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | 12 ) #define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 ) -#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_OUT | GPIO_PUEN | 13 ) +#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13 ) #define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 ) #define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 ) #define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 ) @@ -235,19 +257,27 @@ #define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 ) #define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 ) #define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 ) +#define PC24_BIN_UART3_RI ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24 ) +#define PC25_BIN_UART3_DSR ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25 ) +#define PC26_AOUT_UART3_DTR ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26 ) +#define PC27_BIN_UART3_DCD ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27 ) +#define PC28_BIN_UART3_CTS ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28 ) +#define PC29_AOUT_UART3_RTS ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29 ) +#define PC30_BIN_UART3_TX ( GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30 ) +#define PC31_AOUT_UART3_RX ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31) #define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 ) #define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 ) -#define PD7_AF_UART2_DTR ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 ) -#define PD7_AIN_SPI2_SCLK ( GPIO_PORTD | GPIO_AIN | 7 ) +#define PD7_AF_UART2_DTR ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7 ) +#define PD7_AIN_SPI2_SCLK ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7 ) #define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 ) #define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 ) -#define PD8_AIN_SPI2_SS ( GPIO_PORTD | GPIO_AIN | 8 ) +#define PD8_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8 ) #define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 ) #define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 ) -#define PD9_AOUT_SPI2_RXD ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 ) +#define PD9_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9 ) #define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 ) #define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 ) -#define PD10_AIN_SPI2_TXD ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 ) +#define PD10_AIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10 ) #define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 ) #define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 ) #define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 ) @@ -269,7 +299,31 @@ #define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 ) #define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 ) #define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 ) -#define PD31_BIN_SPI2_TXD ( GPIO_PORTD | GPIO_BIN | 31 ) +#define PD31_BIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31 ) + +/* + * PWM controller + */ +#define PWMC __REG(IMX_PWM_BASE + 0x00) /* PWM Control Register */ +#define PWMS __REG(IMX_PWM_BASE + 0x04) /* PWM Sample Register */ +#define PWMP __REG(IMX_PWM_BASE + 0x08) /* PWM Period Register */ +#define PWMCNT __REG(IMX_PWM_BASE + 0x0C) /* PWM Counter Register */ + +#define PWMC_HCTR (0x01<<18) /* Halfword FIFO Data Swapping */ +#define PWMC_BCTR (0x01<<17) /* Byte FIFO Data Swapping */ +#define PWMC_SWR (0x01<<16) /* Software Reset */ +#define PWMC_CLKSRC (0x01<<15) /* Clock Source */ +#define PWMC_PRESCALER(x) (((x-1) & 0x7F) << 8) /* PRESCALER */ +#define PWMC_IRQ (0x01<< 7) /* Interrupt Request */ +#define PWMC_IRQEN (0x01<< 6) /* Interrupt Request Enable */ +#define PWMC_FIFOAV (0x01<< 5) /* FIFO Available */ +#define PWMC_EN (0x01<< 4) /* Enables/Disables the PWM */ +#define PWMC_REPEAT(x) (((x) & 0x03) << 2) /* Sample Repeats */ +#define PWMC_CLKSEL(x) (((x) & 0x03) << 0) /* Clock Selection */ + +#define PWMS_SAMPLE(x) ((x) & 0xFFFF) /* Contains a two-sample word */ +#define PWMP_PERIOD(x) ((x) & 0xFFFF) /* Represents the PWM's period */ +#define PWMC_COUNTER(x) ((x) & 0xFFFF) /* Represents the current count value */ /* * DMA Controller @@ -291,7 +345,7 @@ #define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */ #define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */ #define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */ -#define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */ +#define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */ #define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */ #define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */ #define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */ @@ -401,8 +455,11 @@ #define POS_POS(x) ((x) & 1f) #define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28) -#define LSCR1_GRAY1(x) (((x) & 0xf) << 4) -#define LSCR1_GRAY2(x) ((x) & 0xf) +#define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26) +#define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16) +#define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8) +#define LSCR1_GRAY2(x) (((x) & 0xf) << 4) +#define LSCR1_GRAY1(x) (((x) & 0xf)) #define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C) #define PWMR_CLS(x) (((x) & 0x1ff) << 16) @@ -478,9 +535,9 @@ #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ #define UCR1_DOZE (1<<1) /* Doze */ #define UCR1_UARTEN (1<<0) /* UART enabled */ -#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ -#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ -#define UCR2_CTSC (1<<13) /* CTS pin control */ +#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ +#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ +#define UCR2_CTSC (1<<13) /* CTS pin control */ #define UCR2_CTS (1<<12) /* Clear to send */ #define UCR2_ESCEN (1<<11) /* Escape enable */ #define UCR2_PREN (1<<8) /* Parity enable */ @@ -490,8 +547,8 @@ #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ #define UCR2_TXEN (1<<2) /* Transmitter enabled */ #define UCR2_RXEN (1<<1) /* Receiver enabled */ -#define UCR2_SRST (1<<0) /* SW reset */ -#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ +#define UCR2_SRST (1<<0) /* SW reset */ +#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ #define UCR3_PARERREN (1<<12) /* Parity enable */ #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ #define UCR3_DSR (1<<10) /* Data set ready */ @@ -501,51 +558,51 @@ #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ -#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ -#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ -#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ -#define UCR3_BPEN (1<<0) /* Preset registers enable */ +#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ +#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ +#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ +#define UCR3_BPEN (1<<0) /* Preset registers enable */ #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ -#define UCR4_INVR (1<<9) /* Inverted infrared reception */ -#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ -#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ -#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ -#define UCR4_IRSC (1<<5) /* IR special case */ -#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ -#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ -#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ -#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ +#define UCR4_INVR (1<<9) /* Inverted infrared reception */ +#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ +#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ +#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ +#define UCR4_IRSC (1<<5) /* IR special case */ +#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ +#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ +#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ +#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ -#define USR1_RTSS (1<<14) /* RTS pin status */ -#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ -#define USR1_RTSD (1<<12) /* RTS delta */ -#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ +#define USR1_RTSS (1<<14) /* RTS pin status */ +#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ +#define USR1_RTSD (1<<12) /* RTS delta */ +#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ -#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ +#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ -#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ -#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ -#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ -#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ -#define USR2_IDLE (1<<12) /* Idle condition */ -#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ -#define USR2_WAKE (1<<7) /* Wake */ -#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ -#define USR2_TXDC (1<<3) /* Transmitter complete */ -#define USR2_BRCD (1<<2) /* Break condition */ +#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ +#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ +#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ +#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ +#define USR2_IDLE (1<<12) /* Idle condition */ +#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ +#define USR2_WAKE (1<<7) /* Wake */ +#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ +#define USR2_TXDC (1<<3) /* Transmitter complete */ +#define USR2_BRCD (1<<2) /* Break condition */ #define USR2_ORE (1<<1) /* Overrun error */ #define USR2_RDR (1<<0) /* Recv data ready */ #define UTS_FRCPERR (1<<13) /* Force parity error */ #define UTS_LOOP (1<<12) /* Loop tx and rx */ #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ -#define UTS_TXFULL (1<<4) /* TxFIFO full */ -#define UTS_RXFULL (1<<3) /* RxFIFO full */ +#define UTS_TXFULL (1<<4) /* TxFIFO full */ +#define UTS_RXFULL (1<<3) /* RxFIFO full */ #define UTS_SOFTRST (1<<0) /* Software reset */ /* General purpose timers registers */ diff --git a/include/asm-i386/types.h b/include/asm-i386/types.h index 69f8a5a7c6..bdbde4172a 100644 --- a/include/asm-i386/types.h +++ b/include/asm-i386/types.h @@ -17,9 +17,9 @@ typedef unsigned short __u16; typedef __signed__ int __s32; typedef unsigned int __u32; -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -typedef __signed__ long long __s64; -typedef unsigned long long __u64; +#if defined(__GNUC__) +__extension__ typedef __signed__ long long __s64; +__extension__ typedef unsigned long long __u64; #endif /* diff --git a/include/asm-microblaze/types.h b/include/asm-microblaze/types.h index 8c4bef2870..3895dc4365 100644 --- a/include/asm-microblaze/types.h +++ b/include/asm-microblaze/types.h @@ -25,9 +25,9 @@ typedef unsigned short __u16; typedef __signed__ int __s32; typedef unsigned int __u32; -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -typedef __signed__ long long __s64; -typedef unsigned long long __u64; +#if defined(__GNUC__) +__extension__ typedef __signed__ long long __s64; +__extension__ typedef unsigned long long __u64; #endif /* diff --git a/include/asm-nios/types.h b/include/asm-nios/types.h index 43fd8f6d2b..24c98a89e4 100644 --- a/include/asm-nios/types.h +++ b/include/asm-nios/types.h @@ -25,9 +25,9 @@ typedef unsigned short __u16; typedef __signed__ int __s32; typedef unsigned int __u32; -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -typedef __signed__ long long __s64; -typedef unsigned long long __u64; +#if defined(__GNUC__) +__extension__ typedef __signed__ long long __s64; +__extension__ typedef unsigned long long __u64; #endif /* diff --git a/include/asm-nios2/types.h b/include/asm-nios2/types.h index 39e2641787..f13d8bd4b4 100644 --- a/include/asm-nios2/types.h +++ b/include/asm-nios2/types.h @@ -25,9 +25,9 @@ typedef unsigned short __u16; typedef __signed__ int __s32; typedef unsigned int __u32; -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -typedef __signed__ long long __s64; -typedef unsigned long long __u64; +#if defined(__GNUC__) +__extension__ typedef __signed__ long long __s64; +__extension__ typedef unsigned long long __u64; #endif /* diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index f9a3d928b2..205f7ed74b 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -103,6 +103,7 @@ typedef struct global_data { #if defined(CONFIG_MPC512X) u32 ips_clk; u32 csb_clk; + u32 pci_clk; #endif /* CONFIG_MPC512X */ #if defined(CONFIG_MPC8220) unsigned long bExtUart; diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h index 23d10d4eb4..cd9094519b 100644 --- a/include/asm-ppc/immap_512x.h +++ b/include/asm-ppc/immap_512x.h @@ -29,7 +29,7 @@ typedef struct law512x { u32 bar; /* Base Addr Register */ u32 ar; /* Attributes Register */ -} law521x_t; +} law512x_t; /* * System configuration registers @@ -47,9 +47,9 @@ typedef struct sysconf512x { u32 lpcs6aw; /* LP CS6 Access Window */ u32 lpcs7aw; /* LP CS7 Access Window */ u8 res1[0x1c]; - law521x_t pcilaw[3]; /* PCI Local Access Window 0-2 Registers */ + law512x_t pcilaw[3]; /* PCI Local Access Window 0-2 Registers */ u8 res2[0x28]; - law521x_t ddrlaw; /* DDR Local Access Window */ + law512x_t ddrlaw; /* DDR Local Access Window */ u8 res3[0x18]; u32 mbxbar; /* MBX Base Address */ u32 srambar; /* SRAM Base Address */ @@ -241,21 +241,70 @@ typedef struct dma512x { * PCI Software Configuration Registers */ typedef struct pciconf512x { - u8 fixme[0x80]; + u32 config_address; + u32 config_data; + u32 int_ack; + u8 res[116]; } pciconf512x_t; /* + * PCI Outbound Translation Register + */ +typedef struct pci_outbound_window { + u32 potar; + u8 res0[4]; + u32 pobar; + u8 res1[4]; + u32 pocmr; + u8 res2[4]; +} pot512x_t; + +/* * Sequencer */ typedef struct ios512x { - u8 fixme[0x100]; + pot512x_t pot[6]; + u8 res0[0x60]; + u32 pmcr; + u8 res1[4]; + u32 dtcr; + u8 res2[4]; } ios512x_t; /* * PCI Controller */ typedef struct pcictrl512x { - u8 fixme[0x100]; + u32 esr; + u32 ecdr; + u32 eer; + u32 eatcr; + u32 eacr; + u32 eeacr; + u32 edlcr; + u32 edhcr; + u32 gcr; + u32 ecr; + u32 gsr; + u8 res0[12]; + u32 pitar2; + u8 res1[4]; + u32 pibar2; + u32 piebar2; + u32 piwar2; + u8 res2[4]; + u32 pitar1; + u8 res3[4]; + u32 pibar1; + u32 piebar1; + u32 piwar1; + u8 res4[4]; + u32 pitar0; + u8 res5[4]; + u32 pibar0; + u8 res6[4]; + u32 piwar0; + u8 res7[132]; } pcictrl512x_t; diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index 09c3140360..65dc97ebdd 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -34,6 +34,9 @@ * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB) * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) * 0x8200_0000 - 0x8200_001F CPLD (32 B) + * 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB) + * 0xA000_0000 - 0xAFFF_FFFF PCI memory space (256 MB) + * 0xB000_0000 - 0xBFFF_FFFF PCI memory mapped I/O space (256 MB) * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB) */ @@ -43,7 +46,7 @@ #define CONFIG_E300 1 /* E300 Family */ #define CONFIG_MPC512X 1 /* MPC512X family */ -#undef CONFIG_PCI +/* CONFIG_PCI is defined at config time */ #define CFG_MPC512X_CLKIN 66000000 /* in Hz */ @@ -217,6 +220,31 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* + * PCI + */ +#ifdef CONFIG_PCI + +/* + * General PCI + */ +#define CFG_PCI_MEM_BASE 0xA0000000 +#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE +#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI_MMIO_BASE (CFG_PCI_MEM_BASE + CFG_PCI_MEM_SIZE) +#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE +#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI_IO_BASE 0x00000000 +#define CFG_PCI_IO_PHYS 0x84000000 +#define CFG_PCI_IO_SIZE 0x01000000 /* 16M */ + + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +#endif + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */ diff --git a/include/mpc512x.h b/include/mpc512x.h index b51cf78e6c..b4cc2b9e96 100644 --- a/include/mpc512x.h +++ b/include/mpc512x.h @@ -46,6 +46,7 @@ #define LPCS6AW 0x003C #define LPCA7AW 0x0040 #define SRAMBAR 0x00C4 +#define LAWBAR_BAR 0xFFFFF000 /* Base address mask */ #define LPC_OFFSET 0x10000 @@ -189,6 +190,10 @@ #define SCFR1_IPS_DIV_MASK 0x03800000 #define SCFR1_IPS_DIV_SHIFT 23 +#define SCFR1_PCI_DIV 0x6 +#define SCFR1_PCI_DIV_MASK 0x00700000 +#define SCFR1_PCI_DIV_SHIFT 20 + /* SCFR2 System Clock Frequency Register 2 */ #define SCFR2_SYS_DIV 0xFC000000 @@ -404,4 +409,83 @@ #define I2C_IF 0x02 #define I2C_RXAK 0x01 +/* POTAR - PCI Outbound Translation Address Register + */ +#define POTAR_TA_MASK 0x000fffff + +/* POBAR - PCI Outbound Base Address Register + */ +#define POBAR_BA_MASK 0x000fffff + +/* POCMR - PCI Outbound Comparision Mask Register + */ +#define POCMR_EN 0x80000000 +#define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */ +#define POCMR_PRE 0x20000000 /* prefetch enable */ +#define POCMR_SBS 0x00100000 /* special byte swap enable */ +#define POCMR_CM_MASK 0x000fffff +#define POCMR_CM_4G 0x00000000 +#define POCMR_CM_2G 0x00080000 +#define POCMR_CM_1G 0x000C0000 +#define POCMR_CM_512M 0x000E0000 +#define POCMR_CM_256M 0x000F0000 +#define POCMR_CM_128M 0x000F8000 +#define POCMR_CM_64M 0x000FC000 +#define POCMR_CM_32M 0x000FE000 +#define POCMR_CM_16M 0x000FF000 +#define POCMR_CM_8M 0x000FF800 +#define POCMR_CM_4M 0x000FFC00 +#define POCMR_CM_2M 0x000FFE00 +#define POCMR_CM_1M 0x000FFF00 +#define POCMR_CM_512K 0x000FFF80 +#define POCMR_CM_256K 0x000FFFC0 +#define POCMR_CM_128K 0x000FFFE0 +#define POCMR_CM_64K 0x000FFFF0 +#define POCMR_CM_32K 0x000FFFF8 +#define POCMR_CM_16K 0x000FFFFC +#define POCMR_CM_8K 0x000FFFFE +#define POCMR_CM_4K 0x000FFFFF + +/* PITAR - PCI Inbound Translation Address Register + */ +#define PITAR_TA_MASK 0x000fffff + +/* PIBAR - PCI Inbound Base/Extended Address Register + */ +#define PIBAR_MASK 0xffffffff +#define PIEBAR_EBA_MASK 0x000fffff + +/* PIWAR - PCI Inbound Windows Attributes Register + */ +#define PIWAR_EN 0x80000000 +#define PIWAR_SBS 0x40000000 +#define PIWAR_PF 0x20000000 +#define PIWAR_RTT_MASK 0x000f0000 +#define PIWAR_RTT_NO_SNOOP 0x00040000 +#define PIWAR_RTT_SNOOP 0x00050000 +#define PIWAR_WTT_MASK 0x0000f000 +#define PIWAR_WTT_NO_SNOOP 0x00004000 +#define PIWAR_WTT_SNOOP 0x00005000 +#define PIWAR_IWS_MASK 0x0000003F +#define PIWAR_IWS_4K 0x0000000B +#define PIWAR_IWS_8K 0x0000000C +#define PIWAR_IWS_16K 0x0000000D +#define PIWAR_IWS_32K 0x0000000E +#define PIWAR_IWS_64K 0x0000000F +#define PIWAR_IWS_128K 0x00000010 +#define PIWAR_IWS_256K 0x00000011 +#define PIWAR_IWS_512K 0x00000012 +#define PIWAR_IWS_1M 0x00000013 +#define PIWAR_IWS_2M 0x00000014 +#define PIWAR_IWS_4M 0x00000015 +#define PIWAR_IWS_8M 0x00000016 +#define PIWAR_IWS_16M 0x00000017 +#define PIWAR_IWS_32M 0x00000018 +#define PIWAR_IWS_64M 0x00000019 +#define PIWAR_IWS_128M 0x0000001A +#define PIWAR_IWS_256M 0x0000001B +#define PIWAR_IWS_512M 0x0000001C +#define PIWAR_IWS_1G 0x0000001D +#define PIWAR_IWS_2G 0x0000001E + #endif /* __MPC512X_H__ */ |