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-rw-r--r--include/configs/apalis-imx8.h1
-rw-r--r--include/configs/imx8mq_phanbell.h216
-rw-r--r--include/configs/malta.h1
-rw-r--r--include/configs/mx6sxsabreauto.h6
-rw-r--r--include/configs/mx6sxsabresd.h11
-rw-r--r--include/configs/mx6ul_14x14_evk.h6
-rw-r--r--include/configs/mx6ullevk.h6
-rw-r--r--include/configs/mx7dsabresd.h8
-rw-r--r--include/configs/pcm052.h7
-rw-r--r--include/configs/vf610twr.h8
-rw-r--r--include/dt-bindings/clock/rk3328-cru.h212
-rw-r--r--include/dt-bindings/pinctrl/pins-imxrt1020.h2
-rw-r--r--include/dt-bindings/power/rk3328-power.h19
-rw-r--r--include/imx_sip.h5
-rw-r--r--include/micrel.h11
-rw-r--r--include/netdev.h1
16 files changed, 358 insertions, 162 deletions
diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h
index bea035c3e2..4003715733 100644
--- a/include/configs/apalis-imx8.h
+++ b/include/configs/apalis-imx8.h
@@ -24,6 +24,7 @@
/* Networking */
#define FEC_QUIRK_ENET_MAC
+#define FEC_ENET_ENABLE_TXC_DELAY
#define CONFIG_TFTP_TSIZE
diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h
new file mode 100644
index 0000000000..4fa48c0578
--- /dev/null
+++ b/include/configs/imx8mq_phanbell.h
@@ -0,0 +1,216 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef __IMX8M_PHANBELL_H
+#define __IMX8M_PHANBELL_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_SPL_MAX_SIZE (172 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+
+#ifdef CONFIG_SPL_BUILD
+/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK 0x187FF0
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_BSS_START_ADDR 0x00180000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
+#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
+
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CONFIG_MALLOC_F_ADDR 0x182000
+/* For RAW image gives a error info not panic */
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#undef CONFIG_DM_MMC
+#undef CONFIG_DM_PMIC
+#undef CONFIG_DM_PMIC_PFUZE100
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#endif
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMPORTENV
+#undef CONFIG_CMD_IMLS
+
+#undef CONFIG_CMD_CRC32
+
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_MII
+#define CONFIG_ETHPRIME "FEC"
+
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_MXC_PHYADDR 0
+#define FEC_QUIRK_ENET_MAC
+
+#define CONFIG_PHY_GIGE
+#define IMX_FEC_BASE 0x30BE0000
+
+#define CONFIG_PHYLIB
+#endif
+
+#define CONFIG_MFG_ENV_SETTINGS \
+ "initrd_addr=0x43800000\0" \
+ "initrd_high=0xffffffff\0" \
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_MFG_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=Image\0" \
+ "console=ttymxc0,115200\0" \
+ "fdt_addr=0x43000000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "boot_fdt=try\0" \
+ "fdt_file=imx8mq-phanbell.dtb\0" \
+ "initrd_addr=0x43800000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
+ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "booti ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "else " \
+ "echo wait for boot; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${loadaddr} ${image}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "booti ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "else " \
+ "booti; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else booti ${loadaddr} - ${fdt_addr}; fi"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR 0x40480000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
+#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM 0x40000000
+#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */
+
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
+ (PHYS_SDRAM_SIZE >> 1))
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_IMX_BOOTAUX
+
+#define CONFIG_CMD_MMC
+
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_CMD_FUSE
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+#define CONFIG_OF_SYSTEM_SETUP
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_DM_PMIC
+#endif
+
+#endif
diff --git a/include/configs/malta.h b/include/configs/malta.h
index bb8a44433e..d41b80c7dc 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -16,7 +16,6 @@
#define CONFIG_PCI_GT64120
#define CONFIG_PCI_MSC01
#define CONFIG_PCNET
-#define CONFIG_PCNET_79C973
#define PCNET_HAS_PROM
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h
index 984cf611f4..dc5e818443 100644
--- a/include/configs/mx6sxsabreauto.h
+++ b/include/configs/mx6sxsabreauto.h
@@ -143,12 +143,6 @@
#define CONFIG_IMX_THERMAL
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SYS_FSL_QSPI_AHB
-#define FSL_QSPI_FLASH_SIZE SZ_32M
-#define FSL_QSPI_FLASH_NUM 2
-#endif
-
#define CONFIG_SYS_FSL_USDHC_NUM 2
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC3*/
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 86007a2d36..3bff496bad 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -173,17 +173,6 @@
#define CONFIG_IMX_THERMAL
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SYS_FSL_QSPI_LE
-#define CONFIG_SYS_FSL_QSPI_AHB
-#ifdef CONFIG_MX6SX_SABRESD_REVA
-#define FSL_QSPI_FLASH_SIZE SZ_16M
-#else
-#define FSL_QSPI_FLASH_SIZE SZ_32M
-#endif
-#define FSL_QSPI_FLASH_NUM 2
-#endif
-
#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_MXS
diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
index a30d2c0879..1bdd577940 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -157,12 +157,6 @@
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SYS_FSL_QSPI_AHB
-#define FSL_QSPI_FLASH_NUM 1
-#define FSL_QSPI_FLASH_SIZE SZ_32M
-#endif
-
/* USB Configs */
#ifdef CONFIG_CMD_USB
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h
index af335bcfff..3d42d26aa4 100644
--- a/include/configs/mx6ullevk.h
+++ b/include/configs/mx6ullevk.h
@@ -160,12 +160,6 @@
#define CONFIG_SOFT_SPI
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SYS_FSL_QSPI_AHB
-#define FSL_QSPI_FLASH_NUM 1
-#define FSL_QSPI_FLASH_SIZE SZ_32M
-#endif
-
#ifdef CONFIG_CMD_NET
#define CONFIG_FEC_ENET_DEV 1
#if (CONFIG_FEC_ENET_DEV == 0)
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index e7d35ed648..fa59748776 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -154,12 +154,4 @@
#define CONFIG_VIDEO_BMP_LOGO
#endif
-#ifdef CONFIG_FSL_QSPI
-#define CONFIG_SYS_FSL_QSPI_AHB
-#define FSL_QSPI_FLASH_NUM 1
-#define FSL_QSPI_FLASH_SIZE SZ_64M
-#define QSPI0_BASE_ADDR QSPI1_IPS_BASE_ADDR
-#define QSPI0_AMBA_BASE QSPI0_ARB_BASE_ADDR
-#endif
-
#endif /* __CONFIG_H */
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index 72f8d08a66..d4d6ad2143 100644
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h
@@ -26,13 +26,6 @@
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-/* QSPI Configs*/
-#ifdef CONFIG_FSL_QSPI
-#define FSL_QSPI_FLASH_SIZE (SZ_16M)
-#define FSL_QSPI_FLASH_NUM 2
-#define CONFIG_SYS_FSL_QSPI_LE
-#endif
-
#define CONFIG_LOADADDR 0x82000000
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index 3ab3231943..d52a5a7e83 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -43,14 +43,6 @@
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_FEC_MXC_PHYADDR 0
-/* QSPI Configs*/
-
-#ifdef CONFIG_FSL_QSPI
-#define FSL_QSPI_FLASH_SIZE (1 << 24)
-#define FSL_QSPI_FLASH_NUM 2
-#define CONFIG_SYS_FSL_QSPI_LE
-#endif
-
/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h
index cde61ed883..555b4ff660 100644
--- a/include/dt-bindings/clock/rk3328-cru.h
+++ b/include/dt-bindings/clock/rk3328-cru.h
@@ -1,6 +1,7 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
+ * Author: Elaine <zhangqing@rock-chips.com>
*/
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
@@ -90,119 +91,118 @@
#define SCLK_MAC2IO_EXT 102
/* dclk gates */
-#define DCLK_LCDC 180
-#define DCLK_HDMIPHY 181
-#define HDMIPHY 182
-#define USB480M 183
-#define DCLK_LCDC_SRC 184
+#define DCLK_LCDC 120
+#define DCLK_HDMIPHY 121
+#define HDMIPHY 122
+#define USB480M 123
+#define DCLK_LCDC_SRC 124
/* aclk gates */
-#define ACLK_AXISRAM 190
-#define ACLK_VOP_PRE 191
-#define ACLK_USB3OTG 192
-#define ACLK_RGA_PRE 193
-#define ACLK_DMAC 194
-#define ACLK_GPU 195
-#define ACLK_BUS_PRE 196
-#define ACLK_PERI_PRE 197
-#define ACLK_RKVDEC_PRE 198
-#define ACLK_RKVDEC 199
-#define ACLK_RKVENC 200
-#define ACLK_VPU_PRE 201
-#define ACLK_VIO_PRE 202
-#define ACLK_VPU 203
-#define ACLK_VIO 204
-#define ACLK_VOP 205
-#define ACLK_GMAC 206
-#define ACLK_H265 207
-#define ACLK_H264 208
-#define ACLK_MAC2PHY 209
-#define ACLK_MAC2IO 210
-#define ACLK_DCF 211
-#define ACLK_TSP 212
-#define ACLK_PERI 213
-#define ACLK_RGA 214
-#define ACLK_IEP 215
-#define ACLK_CIF 216
-#define ACLK_HDCP 217
+#define ACLK_AXISRAM 130
+#define ACLK_VOP_PRE 131
+#define ACLK_USB3OTG 132
+#define ACLK_RGA_PRE 133
+#define ACLK_DMAC 134
+#define ACLK_GPU 135
+#define ACLK_BUS_PRE 136
+#define ACLK_PERI_PRE 137
+#define ACLK_RKVDEC_PRE 138
+#define ACLK_RKVDEC 139
+#define ACLK_RKVENC 140
+#define ACLK_VPU_PRE 141
+#define ACLK_VIO_PRE 142
+#define ACLK_VPU 143
+#define ACLK_VIO 144
+#define ACLK_VOP 145
+#define ACLK_GMAC 146
+#define ACLK_H265 147
+#define ACLK_H264 148
+#define ACLK_MAC2PHY 149
+#define ACLK_MAC2IO 150
+#define ACLK_DCF 151
+#define ACLK_TSP 152
+#define ACLK_PERI 153
+#define ACLK_RGA 154
+#define ACLK_IEP 155
+#define ACLK_CIF 156
+#define ACLK_HDCP 157
/* pclk gates */
-#define PCLK_GPIO0 300
-#define PCLK_GPIO1 301
-#define PCLK_GPIO2 302
-#define PCLK_GPIO3 303
-#define PCLK_GRF 304
-#define PCLK_I2C0 305
-#define PCLK_I2C1 306
-#define PCLK_I2C2 307
-#define PCLK_I2C3 308
-#define PCLK_SPI 309
-#define PCLK_UART0 310
-#define PCLK_UART1 311
-#define PCLK_UART2 312
-#define PCLK_TSADC 313
-#define PCLK_PWM 314
-#define PCLK_TIMER 315
-#define PCLK_BUS_PRE 316
-#define PCLK_PERI_PRE 317
-#define PCLK_HDMI_CTRL 318
-#define PCLK_HDMI_PHY 319
-#define PCLK_GMAC 320
-#define PCLK_H265 321
-#define PCLK_MAC2PHY 322
-#define PCLK_MAC2IO 323
-#define PCLK_USB3PHY_OTG 324
-#define PCLK_USB3PHY_PIPE 325
-#define PCLK_USB3_GRF 326
-#define PCLK_USB2_GRF 327
-#define PCLK_HDMIPHY 328
-#define PCLK_DDR 329
-#define PCLK_PERI 330
-#define PCLK_HDMI 331
-#define PCLK_HDCP 332
-#define PCLK_DCF 333
-#define PCLK_SARADC 334
+#define PCLK_GPIO0 200
+#define PCLK_GPIO1 201
+#define PCLK_GPIO2 202
+#define PCLK_GPIO3 203
+#define PCLK_GRF 204
+#define PCLK_I2C0 205
+#define PCLK_I2C1 206
+#define PCLK_I2C2 207
+#define PCLK_I2C3 208
+#define PCLK_SPI 209
+#define PCLK_UART0 210
+#define PCLK_UART1 211
+#define PCLK_UART2 212
+#define PCLK_TSADC 213
+#define PCLK_PWM 214
+#define PCLK_TIMER 215
+#define PCLK_BUS_PRE 216
+#define PCLK_PERI_PRE 217
+#define PCLK_HDMI_CTRL 218
+#define PCLK_HDMI_PHY 219
+#define PCLK_GMAC 220
+#define PCLK_H265 221
+#define PCLK_MAC2PHY 222
+#define PCLK_MAC2IO 223
+#define PCLK_USB3PHY_OTG 224
+#define PCLK_USB3PHY_PIPE 225
+#define PCLK_USB3_GRF 226
+#define PCLK_USB2_GRF 227
+#define PCLK_HDMIPHY 228
+#define PCLK_DDR 229
+#define PCLK_PERI 230
+#define PCLK_HDMI 231
+#define PCLK_HDCP 232
+#define PCLK_DCF 233
+#define PCLK_SARADC 234
+#define PCLK_ACODECPHY 235
+#define PCLK_WDT 236
/* hclk gates */
-#define HCLK_PERI 408
-#define HCLK_TSP 409
-#define HCLK_GMAC 410
-#define HCLK_I2S0_8CH 411
-#define HCLK_I2S1_8CH 413
-#define HCLK_I2S2_2CH 413
-#define HCLK_SPDIF_8CH 414
-#define HCLK_VOP 415
-#define HCLK_NANDC 416
-#define HCLK_SDMMC 417
-#define HCLK_SDIO 418
-#define HCLK_EMMC 419
-#define HCLK_SDMMC_EXT 420
-#define HCLK_RKVDEC_PRE 421
-#define HCLK_RKVDEC 422
-#define HCLK_RKVENC 423
-#define HCLK_VPU_PRE 424
-#define HCLK_VIO_PRE 425
-#define HCLK_VPU 426
-#define HCLK_VIO 427
-#define HCLK_BUS_PRE 428
-#define HCLK_PERI_PRE 429
-#define HCLK_H264 430
-#define HCLK_CIF 431
-#define HCLK_OTG_PMU 432
-#define HCLK_OTG 433
-#define HCLK_HOST0 434
-#define HCLK_HOST0_ARB 435
-#define HCLK_CRYPTO_MST 436
-#define HCLK_CRYPTO_SLV 437
-#define HCLK_PDM 438
-#define HCLK_IEP 439
-#define HCLK_RGA 440
-#define HCLK_HDCP 441
+#define HCLK_PERI 308
+#define HCLK_TSP 309
+#define HCLK_GMAC 310
+#define HCLK_I2S0_8CH 311
+#define HCLK_I2S1_8CH 312
+#define HCLK_I2S2_2CH 313
+#define HCLK_SPDIF_8CH 314
+#define HCLK_VOP 315
+#define HCLK_NANDC 316
+#define HCLK_SDMMC 317
+#define HCLK_SDIO 318
+#define HCLK_EMMC 319
+#define HCLK_SDMMC_EXT 320
+#define HCLK_RKVDEC_PRE 321
+#define HCLK_RKVDEC 322
+#define HCLK_RKVENC 323
+#define HCLK_VPU_PRE 324
+#define HCLK_VIO_PRE 325
+#define HCLK_VPU 326
+#define HCLK_BUS_PRE 328
+#define HCLK_PERI_PRE 329
+#define HCLK_H264 330
+#define HCLK_CIF 331
+#define HCLK_OTG_PMU 332
+#define HCLK_OTG 333
+#define HCLK_HOST0 334
+#define HCLK_HOST0_ARB 335
+#define HCLK_CRYPTO_MST 336
+#define HCLK_CRYPTO_SLV 337
+#define HCLK_PDM 338
+#define HCLK_IEP 339
+#define HCLK_RGA 340
+#define HCLK_HDCP 341
#define CLK_NR_CLKS (HCLK_HDCP + 1)
-#define CLKGRF_NR_CLKS (SCLK_MAC2PHY + 1)
-
/* soft-reset indices */
#define SRST_CORE0_PO 0
#define SRST_CORE1_PO 1
diff --git a/include/dt-bindings/pinctrl/pins-imxrt1020.h b/include/dt-bindings/pinctrl/pins-imxrt1020.h
index c6bacb7378..b3a833bde2 100644
--- a/include/dt-bindings/pinctrl/pins-imxrt1020.h
+++ b/include/dt-bindings/pinctrl/pins-imxrt1020.h
@@ -7,8 +7,6 @@
#ifndef _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H
#define _DT_BINDINGS_PINCTRL_IMXRT1020_PINFUNC_H
-/* TODO: continue from LPI2C4_SDA_SELECT_INPUT */
-
#define IMX_PAD_SION 0x40000000
/*
diff --git a/include/dt-bindings/power/rk3328-power.h b/include/dt-bindings/power/rk3328-power.h
new file mode 100644
index 0000000000..02e3d7fc1c
--- /dev/null
+++ b/include/dt-bindings/power/rk3328-power.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_BINDINGS_POWER_RK3328_POWER_H__
+#define __DT_BINDINGS_POWER_RK3328_POWER_H__
+
+/**
+ * RK3328 idle id Summary.
+ */
+#define RK3328_PD_CORE 0
+#define RK3328_PD_GPU 1
+#define RK3328_PD_BUS 2
+#define RK3328_PD_MSCH 3
+#define RK3328_PD_PERI 4
+#define RK3328_PD_VIDEO 5
+#define RK3328_PD_HEVC 6
+#define RK3328_PD_SYS 7
+#define RK3328_PD_VPU 8
+#define RK3328_PD_VIO 9
+
+#endif
diff --git a/include/imx_sip.h b/include/imx_sip.h
index 139ff61b8a..26dbe0421a 100644
--- a/include/imx_sip.h
+++ b/include/imx_sip.h
@@ -7,7 +7,10 @@
#define _IMX_SIP_H_
#define IMX_SIP_GPC 0xC2000000
-#define IMX_SIP_GPC_PM_DOMAIN 0x03
+#define IMX_SIP_GPC_PM_DOMAIN 0x03
+
+#define IMX_SIP_BUILDINFO 0xC2000003
+#define IMX_SIP_BUILDINFO_GET_COMMITHASH 0x00
#define IMX_SIP_SRC 0xC2000005
#define IMX_SIP_SRC_M4_START 0x00
diff --git a/include/micrel.h b/include/micrel.h
index 3e6b5312d8..a2593c5b10 100644
--- a/include/micrel.h
+++ b/include/micrel.h
@@ -23,6 +23,16 @@
#define MII_KSZ9031_FLP_BURST_TX_LO 0x3
#define MII_KSZ9031_FLP_BURST_TX_HI 0x4
+#define MII_KSZ9x31_SILICON_REV_MASK 0xfffff0
+
+#define MII_KSZ9131_RXTXDLL_BYPASS BIT(12)
+#define MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL 0x4c
+#define MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL 0x4d
+
+#define PHY_ID_KSZ9031 0x00221620
+#define PHY_ID_KSZ9131 0x00221640
+
+
/* Registers */
#define MMD_ACCESS_CONTROL 0xd
#define MMD_ACCESS_REG_DATA 0xe
@@ -35,5 +45,6 @@ int ksz9031_phy_extended_write(struct phy_device *phydev, int devaddr,
int regnum, u16 mode, u16 val);
int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
int regnum, u16 mode);
+int ksz9xx1_phy_get_id(struct phy_device *phydev);
#endif
diff --git a/include/netdev.h b/include/netdev.h
index 68a3fceab6..f2d21c45d0 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -125,6 +125,7 @@ int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
/*
* Allow FEC to fine-tune MII configuration on boards which require this.
*/
+struct eth_device;
int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int));
#endif
generated by cgit (git 2.34.1) at 2025-01-11 16:31:09 +0000