diff options
Diffstat (limited to 'include')
52 files changed, 869 insertions, 1199 deletions
diff --git a/include/common.h b/include/common.h index 4ad17eafb9..6d52924225 100644 --- a/include/common.h +++ b/include/common.h @@ -270,7 +270,8 @@ int cpu_init(void); phys_size_t initdram (int); int display_options (void); void print_size(unsigned long long, const char *); -int print_buffer (ulong addr, void* data, uint width, uint count, uint linelen); +int print_buffer(ulong addr, const void *data, uint width, uint count, + uint linelen); /* common/main.c */ void main_loop (void); @@ -357,7 +358,19 @@ int getenv_yesno(const char *var); int saveenv (void); int setenv (const char *, const char *); int setenv_ulong(const char *varname, ulong value); -int setenv_addr(const char *varname, const void *addr); +int setenv_hex(const char *varname, ulong value); +/** + * setenv_addr - Set an environment variable to an address in hex + * + * @varname: Environmet variable to set + * @addr: Value to set it to + * @return 0 if ok, 1 on error + */ +static inline int setenv_addr(const char *varname, const void *addr) +{ + return setenv_hex(varname, (ulong)addr); +} + #ifdef CONFIG_ARM # include <asm/mach-types.h> # include <asm/setup.h> @@ -869,6 +882,18 @@ int cpu_disable(int nr); int cpu_release(int nr, int argc, char * const argv[]); #endif +/* Define a null map_sysmem() if the architecture doesn't use it */ +# ifndef CONFIG_ARCH_MAP_SYSMEM +static inline void *map_sysmem(phys_addr_t paddr, unsigned long len) +{ + return (void *)(uintptr_t)paddr; +} + +static inline void unmap_sysmem(const void *vaddr) +{ +} +# endif + #endif /* __ASSEMBLY__ */ #ifdef CONFIG_PPC diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index 2a82e19c78..0930781d83 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -76,6 +76,7 @@ #define CONFIG_CMD_RARP /* rarpboot support */ #define CONFIG_CMD_READ /* Read data from partition */ #define CONFIG_CMD_RUN /* run command in env variable */ +#define CONFIG_CMD_SANDBOX /* sb command to access sandbox features */ #define CONFIG_CMD_SAVEENV /* saveenv */ #define CONFIG_CMD_SAVES /* save S record dump */ #define CONFIG_CMD_SCSI /* SCSI Support */ diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 33ee2c49d5..709c1f3373 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -35,6 +35,7 @@ #define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM #define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG @@ -49,6 +50,7 @@ #define CONFIG_BOOTDELAY 1 #define CONFIG_ENV_VARS_UBOOT_CONFIG #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ "fdtaddr=0x80F80000\0" \ @@ -61,12 +63,38 @@ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 ro\0" \ "mmcrootfstype=ext4 rootwait\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \ + "nandrootfstype=ubifs rootwait=1\0" \ + "nandsrcaddr=0x280000\0" \ + "nandimgsize=0x500000\0" \ + "rootpath=/export/rootfs\0" \ + "nfsopts=nolock\0" \ + "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ + "::off\0" \ "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ "ramrootfstype=ext2\0" \ "mmcargs=setenv bootargs console=${console} " \ "${optargs} " \ "root=${mmcroot} " \ "rootfstype=${mmcrootfstype}\0" \ + "nandargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "spiroot=/dev/mtdblock4 rw\0" \ + "spirootfstype=jffs2\0" \ + "spisrcaddr=0xe0000\0" \ + "spiimgsize=0x362000\0" \ + "spibusno=0\0" \ + "spiargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${spiroot} " \ + "rootfstype=${spirootfstype}\0" \ + "netargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=/dev/nfs " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ + "ip=dhcp\0" \ "bootenv=uEnv.txt\0" \ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ "importbootenv=echo Importing environment from mmc ...; " \ @@ -81,6 +109,21 @@ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} ${nandsrcaddr} ${nandimgsize}; " \ + "bootm ${loadaddr}\0" \ + "spiboot=echo Booting from spi ...; " \ + "run spiargs; " \ + "sf probe ${spibusno}:0; " \ + "sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \ + "bootm ${loadaddr}\0" \ + "netboot=echo Booting from network ...; " \ + "setenv autoload no; " \ + "dhcp; " \ + "tftp ${loadaddr} ${bootfile}; " \ + "run netargs; " \ + "bootm ${loadaddr}\0" \ "ramboot=echo Booting from ramdisk ...; " \ "run ramargs; " \ "bootm ${loadaddr}\0" \ @@ -92,6 +135,8 @@ "if test $board_name = A335X_SK; then " \ "setenv fdtfile am335x-evmsk.dtb; fi\0" \ +#endif + #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "echo SD/MMC found on device ${mmcdev};" \ @@ -106,6 +151,8 @@ "if run loaduimage; then " \ "run mmcboot;" \ "fi;" \ + "else " \ + "run nandboot;" \ "fi;" \ /* Clock Defines */ @@ -237,8 +284,8 @@ #define CONFIG_SPL_SPI_LOAD #define CONFIG_SPL_SPI_BUS 0 #define CONFIG_SPL_SPI_CS 0 -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 -#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x80000 +#define CONFIG_SPL_MUSB_NEW_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" #define CONFIG_SPL_BOARD_INIT @@ -312,8 +359,38 @@ #ifdef CONFIG_MUSB_GADGET #define CONFIG_USB_ETHER #define CONFIG_USB_ETH_RNDIS +#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00" #endif /* CONFIG_MUSB_GADGET */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT) +/* disable host part of MUSB in SPL */ +#undef CONFIG_MUSB_HOST +/* + * Disable CPSW SPL support so we fit within the 101KiB limit. + */ +#undef CONFIG_SPL_ETH_SUPPORT +#endif + +/* + * Default to using SPI for environment, etc. We have multiple copies + * of SPL as the ROM will check these locations. + * 0x0 - 0x20000 : First copy of SPL + * 0x20000 - 0x40000 : Second copy of SPL + * 0x40000 - 0x60000 : Third copy of SPL + * 0x60000 - 0x80000 : Fourth copy of SPL + * 0x80000 - 0xDF000 : U-Boot + * 0xDF000 - 0xE0000 : U-Boot Environment + * 0xE0000 - 0x442000 : Linux Kernel + * 0x442000 - 0x800000 : Userland + */ +#if defined(CONFIG_SPI_BOOT) +# undef CONFIG_ENV_IS_NOWHERE +# define CONFIG_ENV_IS_IN_SPI_FLASH +# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +# define CONFIG_ENV_OFFSET (892 << 10) /* 892 KiB in */ +# define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ +#endif /* SPI support */ + /* Unsupported features */ #undef CONFIG_USE_IRQ @@ -346,10 +423,12 @@ /* CS0 */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#if !defined(CONFIG_SPI_BOOT) #undef CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ #endif +#endif #endif /* ! __CONFIG_AM335X_EVM_H */ diff --git a/include/configs/apx4devkit.h b/include/configs/apx4devkit.h index 73c66af06d..ab4efa4b03 100644 --- a/include/configs/apx4devkit.h +++ b/include/configs/apx4devkit.h @@ -222,7 +222,7 @@ "root=ubi0:rootfs rootfstype=ubifs ${mtdparts} rw\0" \ "bootcmd_nand=" \ "run bootargs_nand && ubi part root 2048 && " \ - "ubifsmount rootfs && ubifsload 41000000 boot/uImage && " \ + "ubifsmount ubi:rootfs && ubifsload 41000000 boot/uImage && " \ "bootm 41000000\0" \ "bootargs_mmc=" \ "setenv bootargs ${kernelargs} " \ diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h new file mode 100644 index 0000000000..02149fa94d --- /dev/null +++ b/include/configs/bf609-ezkit.h @@ -0,0 +1,162 @@ +/* + * U-boot - Configuration file for BF609 EZ-Kit board + */ + +#ifndef __CONFIG_BF609_EZKIT_H__ +#define __CONFIG_BF609_EZKIT_H__ + +#include <asm/config-pre.h> + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf609-0.0 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA + + +/* For ez-board version 1.0, else undef this */ +#define CONFIG_BFIN_BOARD_VERSION_1_0 + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SYSCLK_DIV + * SCLK0 = SCLK / SCLK0_DIV + * SCLK1 = SCLK / SCLK1_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ (25000000) +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF (0) + +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-127 (where 0 means 128) */ +#define CONFIG_VCO_MULT (20) + +/* CCLK_DIV controls the core clock divider */ +/* Values can range from 0-31 (where 0 means 32) */ +#define CONFIG_CCLK_DIV (1) +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 0-31 (where 0 means 32) */ +#define CONFIG_SCLK_DIV (4) +/* Values can range from 0-7 (where 0 means 8) */ +#define CONFIG_SCLK0_DIV (1) +#define CONFIG_SCLK1_DIV (1) +/* DCLK_DIV controls the DDR clock divider */ +/* Values can range from 0-31 (where 0 means 32) */ +#define CONFIG_DCLK_DIV (2) +/* OCLK_DIV controls the output clock divider */ +/* Values can range from 0-127 (where 0 means 128) */ +#define CONFIG_OCLK_DIV (16) + +/* + * Memory Settings + */ +#define CONFIG_MEM_SIZE 128 + +#define CONFIG_SMC_GCTL_VAL 0x00000010 +#define CONFIG_SMC_B0CTL_VAL 0x01007011 +#define CONFIG_SMC_B0TIM_VAL 0x08170977 +#define CONFIG_SMC_B0ETIM_VAL 0x00092231 + +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) + +#define CONFIG_HW_WATCHDOG +/* + * Network Settings + */ +#define ADI_CMDS_NETWORK +#define CONFIG_NETCONSOLE +#define CONFIG_NET_MULTI +#define CONFIG_HOSTNAME "bf609-ezkit" +#define CONFIG_DESIGNWARE_ETH +#define CONFIG_DW_PORTS 1 +#define CONFIG_DW_AUTONEG +#define CONFIG_DW_ALTDESCRIPTOR +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_MII + +/* i2c Settings */ +#define CONFIG_BFIN_TWI_I2C +#define CONFIG_HARD_I2C + +/* + * Flash Settings + */ +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_JFFS2 +#define CONFIG_SYS_FLASH_CFI_WIDTH 2 +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_BASE 0xb0000000 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 131 +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS + +/* + * SPI Settings + */ +#define CONFIG_BFIN_SPI6XX +#define CONFIG_ENV_SPI_MAX_HZ 25000000 +#define CONFIG_SF_DEFAULT_SPEED 25000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_ALL + +/* + * Env Storage Settings + */ +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x10000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR +#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x60000 +#define CONFIG_ENV_SIZE 0x20000 +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_OFFSET 0x8000 +#define CONFIG_ENV_SIZE 0x8000 +#define CONFIG_ENV_SECT_SIZE 0x8000 +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR +#endif + +#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0xB0100000\0" + +/* + * SDH Settings + */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_BFIN_SDH + +/* + * Misc Settings + */ +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_UART_CONSOLE 0 + +#define CONFIG_CMD_MEMORY + +#define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 20*1024*1024 + 4) +#define CONFIG_BFIN_SOFT_SWITCH + +#if 0 +#define CONFIG_UART_MEM 1024 +#undef CONFIG_UART_CONSOLE +#undef CONFIG_JTAG_CONSOLE +#undef CONFIG_UART_CONSOLE_IS_JTAG +#endif + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include <configs/bfin_adi_common.h> +#endif diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index ccdec0d564..d3ae3a71cd 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -10,7 +10,7 @@ */ #ifndef _CONFIG_CMD_DEFAULT_H # include <config_cmd_default.h> -# if ADI_CMDS_NETWORK +# ifdef ADI_CMDS_NETWORK # define CONFIG_CMD_DHCP # define CONFIG_BOOTP_SUBNETMASK # define CONFIG_BOOTP_GATEWAY @@ -58,7 +58,7 @@ # endif # ifdef CONFIG_RTC_BFIN # define CONFIG_CMD_DATE -# if ADI_CMDS_NETWORK +# ifdef ADI_CMDS_NETWORK # define CONFIG_CMD_SNTP # endif # endif @@ -193,10 +193,12 @@ "nand erase 0 0x40000;" \ "nand write $(loadaddr) 0 0x40000" # else -# define UBOOT_ENV_UPDATE \ +# ifndef UBOOT_ENV_UPDATE +# define UBOOT_ENV_UPDATE \ "protect off 0x20000000 +$(filesize);" \ "erase 0x20000000 +$(filesize);" \ "cp.b $(loadaddr) 0x20000000 $(filesize)" +# endif # endif # ifdef CONFIG_NETCONSOLE # define NETCONSOLE_ENV \ diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h index a7a698c0ca..56528ddaaf 100644 --- a/include/configs/cam_enc_4xx.h +++ b/include/configs/cam_enc_4xx.h @@ -451,7 +451,7 @@ "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage \0" \ "kernel_addr_r=80600000\0" \ "load_kernel=tftp ${kernel_addr_r} ${bootfile}\0" \ - "ubi_load_kernel=ubi part ubi 2048;ubifsmount ${img_volume};" \ + "ubi_load_kernel=ubi part ubi 2048;ubifsmount ubi:${img_volume};" \ "ubifsload ${kernel_addr_r} boot/uImage\0" \ "fit_addr_r=" __stringify(CONFIG_BOARD_IMG_ADDR_R) "\0" \ "img_addr_r=" __stringify(CONFIG_BOARD_IMG_ADDR_R) "\0" \ diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 943b65841c..8d79ffd48a 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -331,9 +331,18 @@ #define STATUS_LED_BOOT STATUS_LED_BIT #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ +#define CONFIG_SPLASHIMAGE_GUARD + /* GPIO banks */ #ifdef CONFIG_STATUS_LED #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ #endif +/* Display Configuration */ +#define CONFIG_OMAP3_GPIO_2 +#define CONFIG_VIDEO_OMAP3 +#define LCD_BPP LCD_COLOR16 + +#define CONFIG_LCD + #endif /* __CONFIG_H */ diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index c7f36ff148..49f05decc0 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -42,6 +42,12 @@ #define CONFIG_ZBOOT_32 #define CONFIG_PHYSMEM +#define CONFIG_LMB +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE +#define CONFIG_DEFAULT_DEVICE_TREE link + /*----------------------------------------------------------------------- * Watchdog Configuration */ diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index d926f74026..788227d79d 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -354,7 +354,6 @@ /* SPL OS boot options */ #define CONFIG_SPL_OS_BOOT -#define CONFIG_SPL_OS_BOOT_KEY 26 #define CONFIG_CMD_SPL #define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */ diff --git a/include/configs/dockstar.h b/include/configs/dockstar.h index 249f93bf13..63d5e35e92 100644 --- a/include/configs/dockstar.h +++ b/include/configs/dockstar.h @@ -85,7 +85,7 @@ #define CONFIG_BOOTCOMMAND \ "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ "ubi part root; " \ - "ubifsmount root; " \ + "ubifsmount ubi:root; " \ "ubifsload 0x800000 ${kernel}; " \ "ubifsload 0x1100000 ${initrd}; " \ "bootm 0x800000 0x1100000" diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h new file mode 100644 index 0000000000..10a493995f --- /dev/null +++ b/include/configs/dra7xx_evm.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2013 + * Texas Instruments Incorporated. + * Lokesh Vutla <lokeshvutla@ti.com> + * + * Configuration settings for the TI DRA7XX board. + * See omap5_common.h for omap5 common settings. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_DRA7XX_EVM_H +#define __CONFIG_DRA7XX_EVM_H + +#include <configs/omap5_common.h> + +#define CONFIG_DRA7XX /* in a TI DRA7XX core */ +#define CONFIG_SYS_PROMPT "DRA752 EVM # " + +#endif /* __CONFIG_DRA7XX_EVM_H */ diff --git a/include/configs/ea20.h b/include/configs/ea20.h index d3eb5969dc..90fc7c58d2 100644 --- a/include/configs/ea20.h +++ b/include/configs/ea20.h @@ -42,6 +42,7 @@ #define CONFIG_MACH_DAVINCI_DA850_EVM #define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ +#define CONFIG_SOC_DA850 /* TI DA850 SoC */ #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) #define CONFIG_SYS_OSCIN_FREQ 24000000 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE @@ -293,12 +294,12 @@ "bootm ${kernel_addr_r}\0" \ "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \ "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \ - "nand_nand=ubi part nand0,${as};ubifsmount rootfs;" \ + "nand_nand=ubi part nand0,${as};ubifsmount ubi:rootfs;" \ "ubifsload ${kernel_addr_r} /boot/uImage;" \ "ubifsumount; run nandargs addip addtty " \ "addmtd addmisc addmem;clrlogo;" \ "bootm ${kernel_addr_r}\0" \ - "nand_nandrw=ubi part nand0,${as};ubifsmount rootfs;" \ + "nand_nandrw=ubi part nand0,${as};ubifsmount ubi:rootfs;" \ "ubifsload ${kernel_addr_r} /boot/uImage;" \ "ubifsumount; run nandrwargs addip addtty " \ "addmtd addmisc addmem;clrlogo;" \ @@ -309,7 +310,7 @@ "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \ "load_magic=if sf probe 0;then sf " \ "read c0000000 0x10000 0x60000;fi\0" \ - "load_nand=ubi part nand0,${as};ubifsmount rootfs;" \ + "load_nand=ubi part nand0,${as};ubifsmount ubi:rootfs;" \ "if ubifsload c0000014 /boot/u-boot.bin;" \ "then mw c0000008 ${filesize};else echo Error reading" \ " u-boot from nand!;fi\0" \ diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h index f646ae5776..d3c664cd18 100644 --- a/include/configs/ib62x0.h +++ b/include/configs/ib62x0.h @@ -88,7 +88,7 @@ #define CONFIG_BOOTCOMMAND \ "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ "ubi part root; " \ - "ubifsmount root; " \ + "ubifsmount ubi:root; " \ "ubifsload 0x800000 ${kernel}; " \ "ubifsload 0x1100000 ${initrd}; " \ "bootm 0x800000 0x1100000" diff --git a/include/configs/iconnect.h b/include/configs/iconnect.h index ba57849a60..c882bfa606 100644 --- a/include/configs/iconnect.h +++ b/include/configs/iconnect.h @@ -87,7 +87,7 @@ #define CONFIG_BOOTCOMMAND \ "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ "ubi part rootfs; " \ - "ubifsmount rootfs; " \ + "ubifsmount ubi:rootfs; " \ "ubifsload 0x800000 ${kernel}; " \ "bootm 0x800000" diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index 0e7f9247c8..559e3759de 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -36,6 +36,7 @@ #include <asm/arch/cpu.h> #include <asm/arch/omap3.h> +#include <asm/mach-types.h> /* * Display CPU and Board information @@ -86,7 +87,10 @@ #define CONFIG_DOS_PARTITION 1 /* define to enable boot progress via leds */ +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \ + (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) #define CONFIG_SHOW_BOOT_PROGRESS +#endif /* USB */ #define CONFIG_MUSB_UDC 1 @@ -118,7 +122,8 @@ #ifdef CONFIG_BOOT_NAND #define CONFIG_CMD_NAND #endif -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \ + (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032) #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ #endif #define CONFIG_CMD_DHCP diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index f64748e349..796f33080d 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -148,6 +148,14 @@ "ubi part " CONFIG_KM_UBI_PARTITION_NAME_APP "; fi\0" #endif /* CONFIG_KM_UBI_PARTITION_NAME_APP */ +#ifdef CONFIG_NAND_ECC_BCH +#define CONFIG_KM_UIMAGE_NAME "ecc_bch_uImage\0" +#define CONFIG_KM_ECC_MODE " eccmode=bch" +#else +#define CONFIG_KM_UIMAGE_NAME "uImage\0" +#define CONFIG_KM_ECC_MODE +#endif + /* * boottargets * - set 'subbootcmds' @@ -184,6 +192,7 @@ ":${hostname}:${netdev}:off3" \ " console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}" \ " mem=${kernelmem} init=${init}" \ + CONFIG_KM_ECC_MODE \ " phram.phram=phvar,${varaddr}," __stringify(CONFIG_KM_PHRAM)\ " " CONFIG_KM_UBI_LINUX_MTD " " \ CONFIG_KM_DEF_BOOT_ARGS_CPU \ @@ -210,9 +219,10 @@ */ #define CONFIG_KM_DEF_ENV_FLASH_BOOT \ "cramfsaddr=" __stringify(CONFIG_KM_CRAMFS_ADDR) "\0" \ - "cramfsloadkernel=cramfsload ${load_addr_r} uImage\0" \ + "cramfsloadkernel=cramfsload ${load_addr_r} ${uimage}\0" \ "ubicopy=ubi read "__stringify(CONFIG_KM_CRAMFS_ADDR) \ " bootfs${boot_bank}\0" \ + "uimage=" CONFIG_KM_UIMAGE_NAME \ CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI /* diff --git a/include/configs/km/km8309-common.h b/include/configs/km/km8309-common.h index b36e892cbe..7f9cffa3b7 100644 --- a/include/configs/km/km8309-common.h +++ b/include/configs/km/km8309-common.h @@ -22,7 +22,7 @@ #define CONFIG_MPC830x 1 /* MPC830x family */ #define CONFIG_MPC8309 1 /* MPC8309 CPU specific */ -#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" +#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" #define CONFIG_CMD_DIAG 1 /* include common defines/options for all 83xx Keymile boards */ @@ -33,8 +33,6 @@ /* at end of uboot partition, before env */ #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xF00B0000 -#define CONFIG_MISC_INIT_R - /* * System IO Config */ diff --git a/include/configs/km/km8321-common.h b/include/configs/km/km8321-common.h index 8ad6fc3a33..abb908162a 100644 --- a/include/configs/km/km8321-common.h +++ b/include/configs/km/km8321-common.h @@ -38,8 +38,6 @@ /* include common defines/options for all 83xx Keymile boards */ #include "km83xx-common.h" -#define CONFIG_MISC_INIT_R - /* * System IO Config */ diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h index a9823d6ef9..eb0e5b6f32 100644 --- a/include/configs/km/km83xx-common.h +++ b/include/configs/km/km83xx-common.h @@ -165,19 +165,15 @@ #define CONFIG_UEC_ETH #define CONFIG_ETHPRIME "UEC0" +#if !defined(CONFIG_MPC8309) #define CONFIG_UEC_ETH1 /* GETH1 */ #define UEC_VERBOSE_DEBUG 1 +#endif #ifdef CONFIG_UEC_ETH1 -#if defined(CONFIG_MPC8309) -#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 -#else #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#endif #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 0 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII @@ -316,7 +312,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_KM_DEF_ENV \ CONFIG_KM_DEF_ARCH \ - "dtt_bus=pca9547:70:a\0" \ "EEprom_ivm=pca9547:70:9\0" \ "newenv=" \ "prot off 0xF00C0000 +0x40000 && " \ diff --git a/include/configs/km8360.h b/include/configs/km8360.h index 7631ab6a65..5b191bcdcd 100644 --- a/include/configs/km8360.h +++ b/include/configs/km8360.h @@ -25,6 +25,8 @@ #define CONFIG_KM_BOARD_NAME "kmcoge5ne" #define CONFIG_KM_DEF_NETDEV "netdev=eth1\0" #define CONFIG_CMD_NAND +#define CONFIG_NAND_ECC_BCH +#define CONFIG_BCH #define CONFIG_NAND_KMETER1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 diff --git a/include/configs/ns9750dev.h b/include/configs/ns9750dev.h deleted file mode 100644 index 3f49c6f0b1..0000000000 --- a/include/configs/ns9750dev.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (C) 2004 by FS Forth-Systeme GmbH. - * All rights reserved. - * Markus Pietrek <mpietrek@fsforth.de> - * - * Configuation settings for the NetSilicon NS9750 DevBoard - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ -#define CONFIG_NS9750 1 /* in an NetSilicon NS9750 SoC */ -#define CONFIG_NS9750DEV 1 /* on an NetSilicon NS9750 DevBoard */ - -/* input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 324403200 /* Don't use PLL. SW11-4 off */ - -#define CPU_CLK_FREQ (CONFIG_SYS_CLK_FREQ/2) -#define AHB_CLK_FREQ (CONFIG_SYS_CLK_FREQ/4) -#define BBUS_CLK_FREQ (CONFIG_SYS_CLK_FREQ/8) - -/*@TODO #define CONFIG_STATUS_LED*/ -#define CONFIG_USE_IRQ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ -#define CONFIG_NS9750_UART 1 /* use on-chip UART */ - -/* - * select serial console configuration - */ -#define CONFIG_CONS_INDEX 1 /* Port B */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 38400 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ - -#define CONFIG_CMD_BDI -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_PING - - -#define CONFIG_BOOTDELAY 3 -/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */ - -#define CONFIG_ETHADDR 00:04:f3:ff:ff:fb /*@TODO unset */ -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.42.30 -#define CONFIG_SERVERIP 192.168.42.1 - -/*#define CONFIG_BOOTFILE "elinos-lart" */ -/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -/* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "NS9750DEV # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00780000 /* 7,5 MB in DRAM */ /* @TODO */ - -#define CONFIG_SYS_LOAD_ADDR 0x00600000 /* default load address */ /* @TODO */ - -#define CONFIG_SYS_HZ (CPU_CLK_FREQ/64) - -#define NS9750_ETH_PHY_ADDRESS (0x0000) - -/*----------------------------------------------------------------------- - * Stack sizes - */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -/* TODO */ -#define CONFIG_NR_DRAM_BANKS 2 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB */ -#define PHYS_SDRAM_2 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_2_SIZE 0x00800000 /* 8 MB */ - -#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */ - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -/* @TODO*/ -#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */ -#if 0 -#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ -#endif - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#ifdef CONFIG_AMD_LV800 -#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ -#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */ -#endif -#ifdef CONFIG_AMD_LV400 -#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ -#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */ -#endif - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -/* @TODO */ -/*#define CONFIG_ENV_IS_IN_FLASH 1*/ -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ - -#ifdef CONFIG_STATUS_LED - -extern void __led_init(led_id_t mask, int state); -extern void __led_toggle(led_id_t mask); -extern void __led_set(led_id_t mask, int state); - -#endif /* CONFIG_STATUS_LED */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 59255c4e26..48ce4c05f5 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -53,7 +53,8 @@ #define CONFIG_MISC_INIT_R -#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index 07de56567d..376a3d031e 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -90,9 +90,9 @@ /* * select serial console configuration */ -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SERIAL3 3 /* UART3 */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 +#define CONFIG_SERIAL1 1 /* UART1 */ #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ @@ -102,6 +102,10 @@ #define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 +/* silent console by default */ +#define CONFIG_SYS_DEVICE_NULLDEV 1 +#define CONFIG_SILENT_CONSOLE 1 + /* USB */ #define CONFIG_MUSB_UDC 1 #define CONFIG_USB_OMAP3 1 @@ -152,19 +156,23 @@ /* Environment information */ #undef CONFIG_ENV_OVERWRITE /* disallow overwriting serial# and ethaddr */ -#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTDELAY 0 +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_STOP_STR "S" #define CONFIG_EXTRA_ENV_SETTINGS \ + "silent=true\0" \ "loadaddr=0x82000000\0" \ "usbtty=cdc_acm\0" \ - "console=ttyO2,115200n8\0" \ + "console=ttyO0,115200n8\0" \ "mpurate=600\0" \ "vram=12M\0" \ "dvimode=1024x768-24@60\0" \ "defaultdisplay=dvi\0" \ - "fpgafilename=mvbluelynx_x.rbf\0" \ - "loadfpga=if fatload mmc ${mmcdev} ${loadaddr} ${fpgafilename}; then " \ - "fpga load 0 ${loadaddr} ${filesize}; " \ + "loadfpga=if ext2load mmc ${mmcdev}:2 ${loadaddr} "\ + "/lib/firmware/mvblx/${fpgafilename}; then " \ + "fpga load 0 ${loadaddr} ${filesize}; " \ "fi;\0" \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 rw\0" \ @@ -177,6 +185,7 @@ "omapdss.def_disp=${defaultdisplay} " \ "root=${mmcroot} " \ "rootfstype=${mmcrootfstype} " \ + "mvfw.fpgavers=${fpgavers} " \ "${cmdline_suffix}\0" \ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ "importbootenv=echo Importing environment from mmc ...; " \ diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index ee888418c5..b77ce25880 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -180,7 +180,8 @@ "ext2load mmc1 0 ${loadaddr} autoboot.scr; then " \ "source ${loadaddr}; " \ "fi; " \ - "ubi part boot && ubifsmount boot && ubifsload ${loadaddr} uImage && bootm ${loadaddr}" + "ubi part boot && ubifsmount ubi:boot && " \ + "ubifsload ${loadaddr} uImage && bootm ${loadaddr}" #define CONFIG_AUTO_COMPLETE 1 /* diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index 180cb24f38..6ae6a0f435 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -52,7 +52,7 @@ #define CONFIG_MISC_INIT_R #define CONFIG_OF_LIBFDT 1 - +#define CONFIG_CMD_BOOTZ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h new file mode 100644 index 0000000000..af97564011 --- /dev/null +++ b/include/configs/omap5_common.h @@ -0,0 +1,262 @@ +/* + * (C) Copyright 2013 + * Texas Instruments Incorporated. + * Sricharan R <r.sricharan@ti.com> + * + * Derived from OMAP4 done by: + * Aneesh V <aneesh@ti.com> + * + * TI OMAP5 AND DRA7XX common configuration settings + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_OMAP5_COMMON_H +#define __CONFIG_OMAP5_COMMON_H + +/* + * High Level Configuration Options + */ +#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_OMAP54XX /* which is a 54XX */ +#define CONFIG_OMAP_GPIO + +/* Get CPU defs */ +#include <asm/arch/cpu.h> +#include <asm/arch/omap.h> + +/* Display CPU and Board Info */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Clock Defines */ +#define V_OSCK 19200000 /* Clock output from T2 */ +#define V_SCLK V_OSCK + +#define CONFIG_MISC_INIT_R + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* + * Size of malloc() pool + * Total Size Environment - 128k + * Malloc - add 256k + */ +#define CONFIG_ENV_SIZE (128 << 10) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10)) +/* Vector Base */ +#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE + +/* + * Hardware drivers + */ + +/* + * serial port - NS16550 compatible + */ +#define V_NS16550_CLK 48000000 + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 UART3_BASE + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} +/* I2C */ +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_DRIVER_OMAP34XX_I2C +#define CONFIG_I2C_MULTI_BUS + + +/* MMC */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_DOS_PARTITION + +/* MMC ENV related defines */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ +#define CONFIG_ENV_OFFSET 0xE0000 +#define CONFIG_CMD_SAVEENV + +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +/* Flash */ +#define CONFIG_SYS_NO_FLASH + +/* Cache */ +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_SYS_CACHELINE_SHIFT 6 + +/* commands to include */ +#include <config_cmd_default.h> + +/* Enabled commands */ +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_SAVEENV + +/* Disabled commands */ +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMLS /* List all found images */ + +/* + * Environment setup + */ + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyO2,115200n8\0" \ + "usbtty=cdc_acm\0" \ + "vram=16M\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "vram=${vram} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc${mmcdev} ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "fi; " \ + "fi; " \ + "fi" + +#define CONFIG_AUTO_COMPLETE 1 + +/* + * Miscellaneous configurable options + */ + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_CBSIZE 256 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +/* + * memtest setup + */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20)) + +/* Default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x80000000 + +/* Use General purpose timer 1 */ +#define CONFIG_SYS_TIMERBASE GPT2_BASE +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/* + * SDRAM Memory Map + * Even though we use two CS all the memory + * is mapped to one contiguous block + */ +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS + +/* Defines for SDRAM init */ +#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION +#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS +#endif + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x40300350 +#define CONFIG_SPL_MAX_SIZE 0x19000 /* 100K */ +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SPL_DISPLAY_PRINT + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 80E7FFC0--0x80E80000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80E80000 + +/* + * BSS and malloc area 64MB into memory to allow enough + * space for the kernel at the beginning of memory + */ +#define CONFIG_SPL_BSS_START_ADDR 0x84000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x84100000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ +#define CONFIG_SPL_GPIO_SUPPORT + +#endif /* __CONFIG_OMAP5_COMMON_H */ diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_evm.h index 623da777fa..22a8e13f48 100644 --- a/include/configs/omap5_evm.h +++ b/include/configs/omap5_evm.h @@ -1,12 +1,10 @@ /* - * (C) Copyright 2010 + * (C) Copyright 2013 * Texas Instruments Incorporated. * Sricharan R <r.sricharan@ti.com> * - * Derived from OMAP4 done by: - * Aneesh V <aneesh@ti.com> - * * Configuration settings for the TI EVM5430 board. + * See omap5_common.h for omap5 common settings. * * See file CREDITS for list of people who contributed to this * project. @@ -27,242 +25,16 @@ * MA 02111-1307 USA */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */ -#define CONFIG_OMAP /* in a TI OMAP core */ -#define CONFIG_OMAP54XX /* which is a 54XX */ -#define CONFIG_OMAP5430 /* which is in a 5430 */ -#define CONFIG_5430EVM /* working with EVM */ -#define CONFIG_OMAP_GPIO - -/* Get CPU defs */ -#include <asm/arch/cpu.h> -#include <asm/arch/omap.h> - -/* Display CPU and Board Info */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -/* Clock Defines */ -#define V_OSCK 19200000 /* Clock output from T2 */ -#define V_SCLK V_OSCK - -#define CONFIG_MISC_INIT_R - -#define CONFIG_OF_LIBFDT - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* - * Size of malloc() pool - * Total Size Environment - 128k - * Malloc - add 256k - */ -#define CONFIG_ENV_SIZE (128 << 10) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10)) -/* Vector Base */ -#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE - -/* - * Hardware drivers - */ - -/* - * serial port - NS16550 compatible - */ -#define V_NS16550_CLK 48000000 - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 UART3_BASE +#ifndef __CONFIG_OMAP5_EVM_H +#define __CONFIG_OMAP5_EVM_H -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} -/* I2C */ -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C -#define CONFIG_I2C_MULTI_BUS +#include <configs/omap5_common.h> /* TWL6035 */ #ifndef CONFIG_SPL_BUILD #define CONFIG_TWL6035_POWER #endif -/* MMC */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_OMAP_HSMMC -#define CONFIG_DOS_PARTITION - -/* MMC ENV related defines */ -#define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ -#define CONFIG_ENV_OFFSET 0xE0000 -#define CONFIG_CMD_SAVEENV - -#define CONFIG_SYS_CONSOLE_IS_IN_ENV - -/* Flash */ -#define CONFIG_SYS_NO_FLASH - -/* Cache */ -#define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_SYS_CACHELINE_SHIFT 6 - -/* commands to include */ -#include <config_cmd_default.h> - -/* Enabled commands */ -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ -#define CONFIG_CMD_SAVEENV - -/* Disabled commands */ -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ -#undef CONFIG_CMD_IMLS /* List all found images */ - -/* - * Environment setup - */ - -#define CONFIG_BOOTDELAY 3 - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ - "console=ttyO2,115200n8\0" \ - "usbtty=cdc_acm\0" \ - "vram=16M\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext3 rootwait\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "vram=${vram} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ - "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - "mmcboot=echo Booting from mmc${mmcdev} ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "fi; " \ - "fi; " \ - "fi" - -#define CONFIG_AUTO_COMPLETE 1 - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT "OMAP5430 EVM # " -#define CONFIG_SYS_CBSIZE 256 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -/* - * memtest setup - */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20)) - -/* Default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x80000000 - -/* Use General purpose timer 1 */ -#define CONFIG_SYS_TIMERBASE GPT2_BASE -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 - -/* - * SDRAM Memory Map - * Even though we use two CS all the memory - * is mapped to one contiguous block - */ -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS - -/* Defines for SDRAM init */ -#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION -#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS -#endif - -/* Defines for SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_TEXT_BASE 0x40300350 -#define CONFIG_SPL_MAX_SIZE 0x19000 /* 100K */ -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SPL_DISPLAY_PRINT - -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" - -/* - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 80E7FFC0--0x80E80000 should not be used for any - * other needs. - */ -#define CONFIG_SYS_TEXT_BASE 0x80E80000 - -/* - * BSS and malloc area 64MB into memory to allow enough - * space for the kernel at the beginning of memory - */ -#define CONFIG_SPL_BSS_START_ADDR 0x84000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x84100000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ -#endif /* __CONFIG_H */ +#endif /* __CONFIG_OMAP5_EVM_H */ diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 9c431bf27a..406da43aa1 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -32,6 +32,13 @@ #define CONFIG_OF_LIBFDT #define CONFIG_LMB +#define CONFIG_FS_FAT +#define CONFIG_FS_EXT4 +#define CONFIG_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE + #define CONFIG_SYS_VSNPRINTF #define CONFIG_CMD_GPIO @@ -63,8 +70,8 @@ #define CONFIG_SYS_HZ 1000 /* Memory things - we don't really want a memory test */ -#define CONFIG_SYS_LOAD_ADDR 0x10000000 -#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_LOAD_ADDR 0x00000000 +#define CONFIG_SYS_MEMTEST_START 0x00100000 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1000) #define CONFIG_PHYS_64BIT @@ -85,6 +92,13 @@ #undef CONFIG_CMD_NET #undef CONFIG_CMD_NFS +#define CONFIG_CMD_HASH +#define CONFIG_HASH_VERIFY +#define CONFIG_SHA1 +#define CONFIG_SHA256 + +#define CONFIG_CMD_SANDBOX + #define CONFIG_BOOTARGS "" #define CONFIG_EXTRA_ENV_SETTINGS "stdin=serial\0" \ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index c50832c1e0..bbf9da545b 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -110,4 +110,41 @@ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U +/* + * QE UEC ethernet configuration + */ +#if defined(CONFIG_KMVECT1) +#define CONFIG_MV88E6352_SWITCH +#define CONFIG_KM_MVEXTSW_ADDR 0x10 + +/* ethernet port connected to simple switch 88e6122 (UEC0) */ +#define CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 + +#define CONFIG_FIXED_PHY 0xFFFFFFFF +#define CONFIG_SYS_FIXED_PHY_ADDR 0x1E /* unused address */ +#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \ + {devnum, speed, duplex} +#define CONFIG_SYS_FIXED_PHY_PORTS \ + CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL) + +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII +#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 + +/* ethernet port connected to piggy (UEC2) */ +#define CONFIG_HAS_ETH1 +#define CONFIG_UEC_ETH2 +#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */ +#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12 +#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC2_PHY_ADDR 0 +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII +#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 +#endif /* CONFIG_KMVECT1 */ + #endif /* __CONFIG_H */ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 1a665ac3ac..ebd7a257f3 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -193,7 +193,7 @@ "bootm ${loadaddr}\0" \ "loaduimage_ubi=mtd default; " \ "ubi part fs; " \ - "ubifsmount root; " \ + "ubifsmount ubi:root; " \ "ubifsload ${loadaddr} /boot/uImage\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 90d2e61147..6caf23a478 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -11,7 +11,7 @@ * (C) Copyright 2008 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * - * (C) Copyright 2010-2012 + * (C) Copyright 2010-2013 * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com * @@ -27,16 +27,20 @@ /* * High Level Configuration Options */ -#ifdef CONFIG_KMSUPX5 +#if defined(CONFIG_KMSUPX5) #define CONFIG_KM_BOARD_NAME "kmsupx5" #define CONFIG_HOSTNAME kmsupx5 -#elif defined CONFIG_TUGE1 +#elif defined(CONFIG_TUGE1) #define CONFIG_KM_BOARD_NAME "tuge1" #define CONFIG_HOSTNAME tuge1 -#else -#define CONFIG_TUXXX /* TUXX1 board (tuxa1/tuda1) specific */ +#elif defined(CONFIG_TUXX1) /* TUXX1 board (tuxa1/tuda1) specific */ #define CONFIG_KM_BOARD_NAME "tuxx1" #define CONFIG_HOSTNAME tuxx1 +#elif defined(CONFIG_KMOPTI2) +#define CONFIG_KM_BOARD_NAME "kmopti2" +#define CONFIG_HOSTNAME kmopti2 +#else +#error ("Board not supported") #endif #define CONFIG_SYS_TEXT_BASE 0xF0000000 @@ -46,18 +50,18 @@ #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ -#ifndef CONFIG_KM_DISABLE_APP2 +#if defined(CONFIG_TUXX1) || defined(CONFIG_KMOPTI2) #define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ #define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ #endif /* * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device on TUDA1 TUXA1 TUGE1 KMSUPX4 - * ---- --- ------- ------ ----- --------------------------------------- - * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF - * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused + * Device on + * Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2 + * ---- --- ------- ------ ----- --------------------------------------- + * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE + * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit) * */ @@ -81,7 +85,7 @@ OR_GPCM_TRLX_SET | \ OR_GPCM_EHTR_CLEAR | \ OR_GPCM_EAD) -#ifndef CONFIG_KM_DISABLE_APP2 +#if defined(CONFIG_TUXX1) /* * Configuration for C3 on the local bus */ @@ -107,6 +111,22 @@ MxMR_WLFx_2X) #endif +#if defined(CONFIG_KMOPTI2) +/* + * Configuration for C3 on the local bus + */ +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ + BR_PS_16 | \ + BR_MS_GPCM | \ + BR_V) +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ + OR_GPCM_SCY_4 | \ + OR_GPCM_TRLX_CLEAR | \ + OR_GPCM_EHTR_CLEAR) +#endif + /* * MMU Setup */ @@ -125,7 +145,7 @@ BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#ifdef CONFIG_KM_DISABLE_APP2 +#if defined(CONFIG_TUGE1) || defined(CONFIG_KMSUPX5) #define CONFIG_SYS_IBAT6L (0) #define CONFIG_SYS_IBAT6U (0) #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L diff --git a/include/configs/twister.h b/include/configs/twister.h index a8524816a8..4205a11bca 100644 --- a/include/configs/twister.h +++ b/include/configs/twister.h @@ -58,7 +58,6 @@ #define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\ 0x600000) #define CONFIG_SPL_OS_BOOT -#define CONFIG_SPL_OS_BOOT_KEY 55 #define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100) #define CONFIG_SPL_BOARD_INIT diff --git a/include/configs/x600.h b/include/configs/x600.h index 3082aaa1e6..bb495a1c90 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -262,7 +262,7 @@ "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \ " addcon addmisc addmtd;" \ "bootm ${kernel_addr} - ${dtb_addr}\0" \ - "ubifs_mount=ubi part ubi${boot_part};ubifsmount rootfs\0" \ + "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \ "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \ "ubifsload ${dtb_addr} ${dtb_fs};\0" \ "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \ diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 18fd76f47e..2989e723e0 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -58,6 +58,11 @@ #define CONFIG_ZYNQ_GEM #define CONFIG_ZYNQ_GEM_BASEADDR0 0xE000B000 +#if defined(CONFIG_ZYNQ_DCC) +# define CONFIG_ARM_DCC +# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */ +#endif + #define CONFIG_BOOTP_SERVERIP #define CONFIG_BOOTP_BOOTPATH #define CONFIG_BOOTP_GATEWAY diff --git a/include/env_callback.h b/include/env_callback.h index c583120c1c..62428d1e0c 100644 --- a/include/env_callback.h +++ b/include/env_callback.h @@ -41,6 +41,12 @@ #define SILENT_CALLBACK #endif +#ifdef CONFIG_SPLASHIMAGE_GUARD +#define SPLASHIMAGE_CALLBACK "splashimage:splashimage," +#else +#define SPLASHIMAGE_CALLBACK +#endif + /* * This list of callback bindings is static, but may be overridden by defining * a new association in the ".callbacks" environment variable. @@ -51,6 +57,7 @@ "bootfile:bootfile," \ "loadaddr:loadaddr," \ SILENT_CALLBACK \ + SPLASHIMAGE_CALLBACK \ "stdin:console,stdout:console,stderr:console," \ CONFIG_ENV_CALLBACK_LIST_STATIC diff --git a/include/exports.h b/include/exports.h index 6cf31aa5e7..41d5085e16 100644 --- a/include/exports.h +++ b/include/exports.h @@ -24,6 +24,7 @@ int setenv (const char *varname, const char *varvalue); long simple_strtol(const char *cp,char **endp,unsigned int base); int strcmp(const char * cs,const char * ct); unsigned long ustrtoul(const char *cp, char **endp, unsigned int base); +unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base); #if defined(CONFIG_CMD_I2C) int i2c_write (uchar, uint, int , uchar* , int); int i2c_read (uchar, uint, int , uchar* , int); diff --git a/include/ext4fs.h b/include/ext4fs.h index 3b59d15aab..025a2e89c2 100644 --- a/include/ext4fs.h +++ b/include/ext4fs.h @@ -138,4 +138,7 @@ void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot); int ext4fs_devread(int sector, int byte_offset, int byte_len, char *buf); void ext4fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info); long int read_allocated_block(struct ext2_inode *inode, int fileblock); +int ext4fs_probe(block_dev_desc_t *fs_dev_desc, + disk_partition_t *fs_partition); +int ext4_read_file(const char *filename, void *buf, int offset, int len); #endif diff --git a/include/fat.h b/include/fat.h index b28c3fd668..9701323748 100644 --- a/include/fat.h +++ b/include/fat.h @@ -213,4 +213,6 @@ int fat_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info); int fat_register_device(block_dev_desc_t *dev_desc, int part_no); int file_fat_write(const char *filename, void *buffer, unsigned long maxsize); +int fat_read_file(const char *filename, void *buf, int offset, int len); +void fat_close(void); #endif /* _FAT_H_ */ diff --git a/include/fs.h b/include/fs.h index 4f30a385a0..b6d69e5ced 100644 --- a/include/fs.h +++ b/include/fs.h @@ -21,6 +21,7 @@ #define FS_TYPE_ANY 0 #define FS_TYPE_FAT 1 #define FS_TYPE_EXT 2 +#define FS_TYPE_SANDBOX 3 /* * Tell the fs layer which block device an partition to use for future diff --git a/include/hash.h b/include/hash.h index 34ba558bd0..2dbbd9b7d5 100644 --- a/include/hash.h +++ b/include/hash.h @@ -22,7 +22,7 @@ #ifndef _HASH_H #define _HASH_H -#ifdef CONFIG_SHA1SUM_VERIFY +#if defined(CONFIG_SHA1SUM_VERIFY) || defined(CONFIG_CRC32_VERIFY) #define CONFIG_HASH_VERIFY #endif @@ -51,19 +51,24 @@ struct hash_algo { */ #define HASH_MAX_DIGEST_SIZE 32 +enum { + HASH_FLAG_VERIFY = 1 << 0, /* Enable verify mode */ + HASH_FLAG_ENV = 1 << 1, /* Allow env vars */ +}; + /** * hash_command: Process a hash command for a particular algorithm * * This common function is used to implement specific hash commands. * - * @algo_name: Hash algorithm being used - * @verify: Non-zero to enable verify mode + * @algo_name: Hash algorithm being used (lower case!) + * @flags: Flags value (HASH_FLAG_...) * @cmdtp: Pointer to command table entry * @flag: Some flags normally 0 (see CMD_FLAG_.. above) * @argc: Number of arguments (arg 0 must be the command text) * @argv: Arguments */ -int hash_command(const char *algo_name, int verify, cmd_tbl_t *cmdtp, int flag, +int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); #endif diff --git a/include/lcd.h b/include/lcd.h index c24164a9de..4ac4ddd1e0 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -47,6 +47,7 @@ extern struct vidinfo panel_info; extern void lcd_ctrl_init (void *lcdbase); extern void lcd_enable (void); +extern int board_splash_screen_prepare(void); /* setcolreg used in 8bpp/16bpp; initcolregs used in monochrome */ extern void lcd_setcolreg (ushort regno, diff --git a/include/malloc.h b/include/malloc.h index 84ecf79344..6295929ea3 100644 --- a/include/malloc.h +++ b/include/malloc.h @@ -937,7 +937,6 @@ extern ulong mem_malloc_end; extern ulong mem_malloc_brk; void mem_malloc_init(ulong start, ulong size); -void malloc_bin_reloc(void); #ifdef __cplusplus }; /* end of extern "C" */ diff --git a/include/mmc.h b/include/mmc.h index a13e2bdcf1..de6d497d53 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -259,6 +259,7 @@ struct mmc { void (*set_ios)(struct mmc *mmc); int (*init)(struct mmc *mmc); int (*getcd)(struct mmc *mmc); + int (*getwp)(struct mmc *mmc); uint b_max; }; @@ -274,6 +275,7 @@ int get_mmc_num(void); int board_mmc_getcd(struct mmc *mmc); int mmc_switch_part(int dev_num, unsigned int part_num); int mmc_getcd(struct mmc *mmc); +int mmc_getwp(struct mmc *mmc); void spl_mmc_load(void) __noreturn; #ifdef CONFIG_GENERIC_MMC diff --git a/include/ns9750_bbus.h b/include/ns9750_bbus.h deleted file mode 100644 index 9485338f73..0000000000 --- a/include/ns9750_bbus.h +++ /dev/null @@ -1,125 +0,0 @@ -/*********************************************************************** - * - * Copyright (C) 2004 by FS Forth-Systeme GmbH. - * All rights reserved. - * - * $Id: ns9750_bbus.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $ - * @Author: Markus Pietrek - * @Descr: Definitions for BBus usage - * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 10 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * - ***********************************************************************/ - -#ifndef FS_NS9750_BBUS_H -#define FS_NS9750_BBUS_H - -#define NS9750_BBUS_MODULE_BASE (0x90600000) - -#define get_bbus_reg_addr(c) \ - ((volatile unsigned int *)(NS9750_BBUS_MODULE_BASE+(unsigned int) (c))) - -/* We have support for 50 GPIO pins */ - -#define get_gpio_cfg_reg_addr(pin) \ - get_bbus_reg_addr( NS9750_BBUS_GPIO_CFG_BASE + (((pin) >> 3) * 4) ) - -/* To Read/Modify/Write a pin configuration register, use it like - set_gpio_cfg_reg_val( 12, NS9750_GPIO_CFG_FUNC_GPIO|NS9750_GPIO_CFG_OUTPUT ); - They should be wrapped by cli()/sti() */ -#define set_gpio_cfg_reg_val(pin,cfg) \ - *get_gpio_cfg_reg_addr(pin)=(*get_gpio_cfg_reg_addr((pin)) & \ - ~NS9750_GPIO_CFG_MASK((pin))) |\ - NS9750_GPIO_CFG_VAL((pin),(cfg)); - -#define NS9750_GPIO_CFG_MASK(pin) (NS9750_GPIO_CFG_VAL(pin, \ - NS9750_GPIO_CFG_MA)) -#define NS9750_GPIO_CFG_VAL(pin,cfg) ((cfg) << (((pin) % 8) * 4)) - -#define NS9750_GPIO_CFG_MA (0x0F) -#define NS9750_GPIO_CFG_INPUT (0x00) -#define NS9750_GPIO_CFG_OUTPUT (0x08) -#define NS9750_GPIO_CFG_FUNC_GPIO (0x03) -#define NS9750_GPIO_CFG_FUNC_2 (0x02) -#define NS9750_GPIO_CFG_FUNC_1 (0x01) -#define NS9750_GPIO_CFG_FUNC_0 (0x00) - -/* the register addresses */ - -#define NS9750_BBUS_MASTER_RESET (0x00) -#define NS9750_BBUS_GPIO_CFG_BASE (0x10) -#define NS9750_BBUS_GPIO_CTRL_BASE (0x30) -#define NS9750_BBUS_GPIO_STAT_BASE (0x40) -#define NS9750_BBUS_MONITOR (0x50) -#define NS9750_BBUS_DMA_INT_STAT (0x60) -#define NS9750_BBUS_DMA_INT_ENABLE (0x64) -#define NS9750_BBUS_USB_CFG (0x70) -#define NS9750_BBUS_ENDIAN_CFG (0x80) -#define NS9750_BBUS_ARM_WAKE_UP (0x90) - -/* register bit fields */ - -#define NS9750_BBUS_MASTER_RESET_UTIL (0x00000100) -#define NS9750_BBUS_MASTER_RESET_I2C (0x00000080) -#define NS9750_BBUS_MASTER_RESET_1284 (0x00000040) -#define NS9750_BBUS_MASTER_RESET_SER4 (0x00000020) -#define NS9750_BBUS_MASTER_RESET_SER3 (0x00000010) -#define NS9750_BBUS_MASTER_RESET_SER2 (0x00000008) -#define NS9750_BBUS_MASTER_RESET_SER1 (0x00000004) -#define NS9750_BBUS_MASTER_RESET_USB (0x00000002) -#define NS9750_BBUS_MASTER_RESET_DMA (0x00000001) - -/* BS9750_BBUS_DMA_INT_BINT* are valid for *DMA_INT_STAT and *DMA_INT_ENABLE */ - -#define NS9750_BBUS_DMA_INT_BINT16 (0x00010000) -#define NS9750_BBUS_DMA_INT_BINT15 (0x00008000) -#define NS9750_BBUS_DMA_INT_BINT14 (0x00004000) -#define NS9750_BBUS_DMA_INT_BINT13 (0x00002000) -#define NS9750_BBUS_DMA_INT_BINT12 (0x00001000) -#define NS9750_BBUS_DMA_INT_BINT11 (0x00000800) -#define NS9750_BBUS_DMA_INT_BINT10 (0x00000400) -#define NS9750_BBUS_DMA_INT_BINT9 (0x00000200) -#define NS9750_BBUS_DMA_INT_BINT8 (0x00000100) -#define NS9750_BBUS_DMA_INT_BINT7 (0x00000080) -#define NS9750_BBUS_DMA_INT_BINT6 (0x00000040) -#define NS9750_BBUS_DMA_INT_BINT5 (0x00000020) -#define NS9750_BBUS_DMA_INT_BINT4 (0x00000010) -#define NS9750_BBUS_DMA_INT_BINT3 (0x00000008) -#define NS9750_BBUS_DMA_INT_BINT2 (0x00000004) -#define NS9750_BBUS_DMA_INT_BINT1 (0x00000002) -#define NS9750_BBUS_DMA_INT_BINT0 (0x00000001) - -#define NS9750_BBUS_USB_CFG_OUTEN (0x00000008) -#define NS9750_BBUS_USB_CFG_SPEED (0x00000004) -#define NS9750_BBUS_USB_CFG_CFG_MA (0x00000003) -#define NS9750_BBUS_USB_CFG_CFG_HOST_SOFT (0x00000003) -#define NS9750_BBUS_USB_CFG_CFG_DEVICE (0x00000002) -#define NS9750_BBUS_USB_CFG_CFG_HOST (0x00000001) -#define NS9750_BBUS_USB_CFG_CFG_DIS (0x00000000) - -#define NS9750_BBUS_ENDIAN_CFG_AHBM (0x00001000) -#define NS9750_BBUS_ENDIAN_CFG_I2C (0x00000080) -#define NS9750_BBUS_ENDIAN_CFG_IEEE1284 (0x00000040) -#define NS9750_BBUS_ENDIAN_CFG_SER4 (0x00000020) -#define NS9750_BBUS_ENDIAN_CFG_SER3 (0x00000010) -#define NS9750_BBUS_ENDIAN_CFG_SER2 (0x00000008) -#define NS9750_BBUS_ENDIAN_CFG_SER1 (0x00000004) -#define NS9750_BBUS_ENDIAN_CFG_USB (0x00000002) -#define NS9750_BBUS_ENDIAN_CFG_DMA (0x00000001) - -#endif /* FS_NS9750_BBUS_H */ diff --git a/include/ns9750_mem.h b/include/ns9750_mem.h deleted file mode 100644 index 666e4127c8..0000000000 --- a/include/ns9750_mem.h +++ /dev/null @@ -1,172 +0,0 @@ -/*********************************************************************** - * - * Copyright (C) 2004 by FS Forth-Systeme GmbH. - * All rights reserved. - * - * $Id: ns9750_mem.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $ - * @Author: Markus Pietrek - * @Descr: Definitions for Memory Control Module - * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 5 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - ***********************************************************************/ - -#ifndef FS_NS9750_MEM_H -#define FS_NS9750_SYS_H - -#define NS9750_MEM_MODULE_BASE (0xA0700000) - -#define get_mem_reg_addr(c) \ - ((volatile unsigned int *)(NS9750_MEM_MODULE_BASE+(unsigned int) (c))) - -/* the register addresses */ - -#define NS9750_MEM_CTRL (0x0000) -#define NS9750_MEM_STATUS (0x0004) -#define NS9750_MEM_CFG (0x0008) -#define NS9750_MEM_DYN_CTRL (0x0020) -#define NS9750_MEM_DYN_REFRESH (0x0024) -#define NS9750_MEM_DYN_READ_CFG (0x0028) -#define NS9750_MEM_DYN_TRP (0x0030) -#define NS9750_MEM_DYN_TRAS (0x0034) -#define NS9750_MEM_DYN_TSREX (0x0038) -#define NS9750_MEM_DYN_TAPR (0x003C) -#define NS9750_MEM_DYN_TDAL (0x0040) -#define NS9750_MEM_DYN_TWR (0x0044) -#define NS9750_MEM_DYN_TRC (0x0048) -#define NS9750_MEM_DYN_TRFC (0x004C) -#define NS9750_MEM_DYN_TXSR (0x0050) -#define NS9750_MEM_DYN_TRRD (0x0054) -#define NS9750_MEM_DYN_TMRD (0x0058) -#define NS9750_MEM_STAT_EXT_WAIT (0x0080) -#define NS9750_MEM_DYN_CFG_BASE (0x0100) -#define NS9750_MEM_DYN_RAS_CAS_BASE (0x0104) -#define NS9750_MEM_STAT_CFG_BASE (0x0200) -#define NS9750_MEM_STAT_WAIT_WEN_BASE (0x0204) -#define NS9750_MEM_STAT_WAIT_OEN_BASE (0x0208) -#define NS9750_MEM_STAT_WAIT_RD_BASE (0x020C) -#define NS9750_MEM_STAT_WAIT_PAGE_BASE (0x0210) -#define NS9750_MEM_STAT_WAIR_WR_BASE (0x0214) -#define NS9750_MEM_STAT_WAIT_TURN_BASE (0x0218) - -/* the vectored register addresses */ - -#define NS9750_MEM_DYN_CFG(c) (NS9750_MEM_DYN_CFG_BASE + (c)*0x20) -#define NS9750_MEM_DYN_RAS_CAS(c) (NS9750_MEM_DYN_RAS_CAS_BASE + (c)*0x20) -#define NS9750_MEM_STAT_CFG(c) (NS9750_MEM_STAT_CFG_BASE + (c)*0x20) -#define NS9750_MEM_STAT_WAIT_WEN(c) (NS9750_MEM_STAT_WAIT_WEN_BASE+(c)*0x20) -#define NS9750_MEM_STAT_WAIT_OEN(c) (NS9750_MEM_STAT_WAIT_OEN_BASE+(c)*0x20) -#define NS9750_MEM_STAT_RD(c) (NS9750_MEM_STAT_WAIT_RD_BASE+(c)*0x20) -#define NS9750_MEM_STAT_PAGE(c) (NS9750_MEM_STAT_WAIT_PAGE_BASE+(c)*0x20) -#define NS9750_MEM_STAT_WR(c) (NS9750_MEM_STAT_WAIT_WR_BASE+(c)*0x20) -#define NS9750_MEM_STAT_TURN(c) (NS9750_MEM_STAT_WAIT_TURN_BASE+(c)*0x20) - -/* register bit fields */ - -#define NS9750_MEM_CTRL_L (0x00000004) -#define NS9750_MEM_CTRL_M (0x00000002) -#define NS9750_MEM_CTRL_E (0x00000001) - -#define NS9750_MEM_STAT_SA (0x00000004) -#define NS9750_MEM_STAT_S (0x00000002) -#define NS9750_MEM_STAT_B (0x00000001) - -#define NS9750_MEM_CFG_CLK (0x00000010) -#define NS9750_MEM_CFG_N (0x00000001) - -#define NS9750_MEM_DYN_CTRL_NRP (0x00004000) -#define NS9750_MEM_DYN_CTRL_DP (0x00002000) -#define NS9750_MEM_DYN_CTRL_I_MA (0x00000180) -#define NS9750_MEM_DYN_CTRL_I_NORMAL (0x00000000) -#define NS9750_MEM_DYN_CTRL_I_MODE (0x00000080) -#define NS9750_MEM_DYN_CTRL_I_PALL (0x00000100) -#define NS9750_MEM_DYN_CTRL_I_NOP (0x00000180) -#define NS9750_MEM_DYN_CTRL_SR (0x00000002) -#define NS9750_MEM_DYN_CTRL_CE (0x00000001) - - -#define NS9750_MEM_DYN_REFRESH_MA (0x000007FF) - -#define NS9750_MEM_DYN_READ_CFG_MA (0x00000003) -#define NS9750_MEM_DYN_READ_CFG_DELAY0 (0x00000001) -#define NS9750_MEM_DYN_READ_CFG_DELAY1 (0x00000002) -#define NS9750_MEM_DYN_READ_CFG_DELAY2 (0x00000003) - -#define NS9750_MEM_DYN_TRP_MA (0x0000000F) - -#define NS9750_MEM_DYN_TRAS_MA (0x0000000F) - -#define NS9750_MEM_DYN_TSREX_MA (0x0000000F) - -#define NS9750_MEM_DYN_TAPR_MA (0x0000000F) - -#define NS9750_MEM_DYN_TDAL_MA (0x0000000F) - -#define NS9750_MEM_DYN_TWR_MA (0x0000000F) - -#define NS9750_MEM_DYN_TRC_MA (0x0000001F) - -#define NS9750_MEM_DYN_TRFC_MA (0x0000001F) - -#define NS9750_MEM_DYN_TXSR_MA (0x0000001F) - -#define NS9750_MEM_DYN_TRRD_MA (0x0000000F) - -#define NS9750_MEM_DYN_TMRD_MA (0x0000000F) - -#define NS9750_MEM_STAT_EXTW_WAIT_MA (0x0000003F) - -#define NS9750_MEM_DYN_CFG_P (0x00100000) -#define NS9750_MEM_DYN_CFG_BDMC (0x00080000) -#define NS9750_MEM_DYN_CFG_AM (0x00004000) -#define NS9750_MEM_DYN_CFG_AM_MA (0x00001F80) -#define NS9750_MEM_DYN_CFG_MD (0x00000018) - -#define NS9750_MEM_DYN_RAS_CAS_CAS_MA (0x00000300) -#define NS9750_MEM_DYN_RAS_CAS_CAS_1 (0x00000100) -#define NS9750_MEM_DYN_RAS_CAS_CAS_2 (0x00000200) -#define NS9750_MEM_DYN_RAS_CAS_CAS_3 (0x00000300) -#define NS9750_MEM_DYN_RAS_CAS_RAS_MA (0x00000003) -#define NS9750_MEM_DYN_RAS_CAS_RAS_1 (0x00000001) -#define NS9750_MEM_DYN_RAS_CAS_RAS_2 (0x00000002) -#define NS9750_MEM_DYN_RAS_CAS_RAS_3 (0x00000003) - -#define NS9750_MEM_STAT_CFG_PSMC (0x00100000) -#define NS9750_MEM_STAT_CFG_BSMC (0x00080000) -#define NS9750_MEM_STAT_CFG_EW (0x00000100) -#define NS9750_MEM_STAT_CFG_PB (0x00000080) -#define NS9750_MEM_STAT_CFG_PC (0x00000040) -#define NS9750_MEM_STAT_CFG_PM (0x00000008) -#define NS9750_MEM_STAT_CFG_MW_MA (0x00000003) -#define NS9750_MEM_STAT_CFG_MW_8 (0x00000000) -#define NS9750_MEM_STAT_CFG_MW_16 (0x00000001) -#define NS9750_MEM_STAT_CFG_MW_32 (0x00000002) - -#define NS9750_MEM_STAT_WAIT_WEN_MA (0x0000000F) - -#define NS9750_MEM_STAT_WAIT_OEN_MA (0x0000000F) - -#define NS9750_MEM_STAT_WAIT_RD_MA (0x0000001F) - -#define NS9750_MEM_STAT_WAIT_PAGE_MA (0x0000001F) - -#define NS9750_MEM_STAT_WAIT_WR_MA (0x0000001F) - -#define NS9750_MEM_STAT_WAIT_TURN_MA (0x0000000F) - - -#endif /* FS_NS9750_MEM_H */ diff --git a/include/ns9750_ser.h b/include/ns9750_ser.h deleted file mode 100644 index b5c297e436..0000000000 --- a/include/ns9750_ser.h +++ /dev/null @@ -1,202 +0,0 @@ -/*********************************************************************** - * - * Copyright (C) 2004 by FS Forth-Systeme GmbH. - * All rights reserved. - * - * $Id: ns9750_ser.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $ - * @Author: Markus Pietrek - * @References: [1] NS9750 Hardware Reference, December 2003 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - ***********************************************************************/ - -#ifndef FS_NS9750_SER_H -#define FS_NS9750_SER_H - -#define NS9750_SER_MODULE_BASE (0x90200000) - -#define get_ser_reg_addr(c) \ - ((volatile unsigned int *)(NS9750_SER_MODULE_BASE+(unsigned int) (c))) - -#define get_ser_reg_addr_channel(reg,chan) \ - get_ser_reg_addr((reg)+(((chan)<2)?0:0x00100000)+(((chan)&1)?0x40:0)) - -/* the register addresses */ - -#define NS9750_SER_CTRL_A (0x00) -#define NS9750_SER_CTRL_B (0x04) -#define NS9750_SER_STAT_A (0x08) -#define NS9750_SER_BITRATE (0x0C) -#define NS9750_SER_FIFO (0x10) -#define NS9750_SER_RX_BUF_TIMER (0x14) -#define NS9750_SER_RX_CHAR_TIMER (0x18) -#define NS9750_SER_RX_MATCH (0x1C) -#define NS9750_SER_RX_MATCH_MASK (0x20) -#define NS9750_SER_FLOW_CTRL (0x34) -#define NS9750_SER_FLOW_CTRL_FORCE (0x38) - -/* register bit fields */ - -/* control A register */ - -#define NS9750_SER_CTRL_A_CE (0x80000000) -#define NS9750_SER_CTRL_A_BRK (0x40000000) -#define NS9750_SER_CTRL_A_STICKP (0x20000000) -#define NS9750_SER_CTRL_A_EPS (0x10000000) -#define NS9750_SER_CTRL_A_PE (0x08000000) -#define NS9750_SER_CTRL_A_STOP (0x04000000) -#define NS9750_SER_CTRL_A_WLS_MA (0x03000000) -#define NS9750_SER_CTRL_A_WLS_5 (0x00000000) -#define NS9750_SER_CTRL_A_WLS_6 (0x01000000) -#define NS9750_SER_CTRL_A_WLS_7 (0x02000000) -#define NS9750_SER_CTRL_A_WLS_8 (0x03000000) -#define NS9750_SER_CTRL_A_CTSTX (0x00800000) -#define NS9750_SER_CTRL_A_RTSRX (0x00400000) -#define NS9750_SER_CTRL_A_RL (0x00200000) -#define NS9750_SER_CTRL_A_LL (0x00100000) -#define NS9750_SER_CTRL_A_RES (0x000CF000) -#define NS9750_SER_CTRL_A_DTR (0x00020000) -#define NS9750_SER_CTRL_A_RTS (0x00010000) -#define NS9750_SER_CTRL_A_RIE_MA (0x00000E00) -#define NS9750_SER_CTRL_A_ERXDMA (0x00000100) -#define NS9750_SER_CTRL_A_RIC_MA (0x000000E0) -#define NS9750_SER_CTRL_A_TIC_MA (0x0000001E) -#define NS9750_SER_CTRL_A_ETXDMA (0x00000001) - -/* control B register */ - -#define NS9750_SER_CTRL_B_RDM1 (0x80000000) -#define NS9750_SER_CTRL_B_RDM2 (0x40000000) -#define NS9750_SER_CTRL_B_RDM3 (0x20000000) -#define NS9750_SER_CTRL_B_RDM4 (0x10000000) -#define NS9750_SER_CTRL_B_RBGT (0x08000000) -#define NS9750_SER_CTRL_B_RCGT (0x04000000) -#define NS9750_SER_CTRL_B_MODE_MA (0x00300000) -#define NS9750_SER_CTRL_B_MODE_UART (0x00000000) -#define NS9750_SER_CTRL_B_MODE_HDLC (0x00100000) -#define NS9750_SER_CTRL_B_MODE_SPI_M (0x00200000) -#define NS9750_SER_CTRL_B_MODE_SPI_S (0x00300000) -#define NS9750_SER_CTRL_B_BITORDR (0x00080000) -#define NS9750_SER_CTRL_B_RES (0x0007703F) -#define NS9750_SER_CTRL_B_RTSTX (0x00008000) -#define NS9750_SER_CTRL_B_ENDEC_MA (0x00000FC0) - -/* status A register */ - -#define NS9750_SER_STAT_A_MATCH1 (0x80000000) -#define NS9750_SER_STAT_A_MATCH2 (0x40000000) -#define NS9750_SER_STAT_A_MATCH3 (0x20000000) -#define NS9750_SER_STAT_A_MATCH4 (0x10000000) -#define NS9750_SER_STAT_A_BGAP (0x08000000) -#define NS9750_SER_STAT_A_CGAP (0x04000000) -#define NS9750_SER_STAT_A_RXFDB_MA (0x00300000) -#define NS9750_SER_STAT_A_RXFDB_FULL (0x00000000) -#define NS9750_SER_STAT_A_RXFDB_1 (0x00100000) -#define NS9750_SER_STAT_A_RXFDB_2 (0x00200000) -#define NS9750_SER_STAT_A_RXFDB_3 (0x00300000) -#define NS9750_SER_STAT_A_DCD (0x00080000) -#define NS9750_SER_STAT_A_RI (0x00040000) -#define NS9750_SER_STAT_A_DSR (0x00020000) -#define NS9750_SER_STAT_A_CTS (0x00010000) -#define NS9750_SER_STAT_A_RBRK (0x00008000) -#define NS9750_SER_STAT_A_RFE (0x00004000) -#define NS9750_SER_STAT_A_RPE (0x00002000) -#define NS9750_SER_STAT_A_ROVER (0x00001000) -#define NS9750_SER_STAT_A_RRDY (0x00000800) -#define NS9750_SER_STAT_A_RHALF (0x00000400) -#define NS9750_SER_STAT_A_RBC (0x00000200) -#define NS9750_SER_STAT_A_RFULL (0x00000100) -#define NS9750_SER_STAT_A_DCDI (0x00000080) -#define NS9750_SER_STAT_A_RII (0x00000040) -#define NS9750_SER_STAT_A_DSRI (0x00000020) -#define NS9750_SER_STAT_A_CTSI (0x00000010) -#define NS9750_SER_STAT_A_TRDY (0x00000008) -#define NS9750_SER_STAT_A_THALF (0x00000004) -#define NS9750_SER_STAT_A_TBC (0x00000002) -#define NS9750_SER_STAT_A_TEMPTY (0x00000001) - -#define NS9750_SER_STAT_A_RX_COND_ERR ( NS9750_SER_STAT_A_RFE | \ - NS9750_SER_STAT_A_ROVER | \ - NS9750_SER_STAT_A_RPE ) -#define NS9750_SER_STAT_A_RX_COND_ALL ( NS9750_SER_STAT_A_RX_COND_ERR | \ - NS9750_SER_STAT_A_RBRK | \ - NS9750_SER_STAT_A_RRDY | \ - NS9750_SER_STAT_A_RHALF | \ - NS9750_SER_STAT_A_RBC | \ - NS9750_SER_STAT_A_DCDI | \ - NS9750_SER_STAT_A_RII | \ - NS9750_SER_STAT_A_DSRI | \ - NS9750_SER_STAT_A_CTSI ) -#define NS9750_SER_STAT_A_TX_COND_ALL ( NS9750_SER_STAT_A_TRDY | \ - NS9750_SER_STAT_A_THALF | \ - NS9750_SER_STAT_A_TBC | \ - NS9750_SER_STAT_A_TEMPTY ) -/* bit rate register */ - -#define NS9750_SER_BITRATE_EBIT (0x80000000) -#define NS9750_SER_BITRATE_TMODE (0x40000000) -#define NS9750_SER_BITRATE_RXSRC (0x20000000) -#define NS9750_SER_BITRATE_TXSRC (0x10000000) -#define NS9750_SER_BITRATE_RXEXT (0x08000000) -#define NS9750_SER_BITRATE_TXEXT (0x04000000) -#define NS9750_SER_BITRATE_CLKMUX_MA (0x03000000) -#define NS9750_SER_BITRATE_CLKMUX_XTAL (0x00000000) -#define NS9750_SER_BITRATE_CLKMUX_BCLK (0x01000000) -#define NS9750_SER_BITRATE_CLKMUX_OUT1 (0x02000000) -#define NS9750_SER_BITRATE_CLKMUX_OUT2 (0x03000000) -#define NS9750_SER_BITRATE_TXCINV (0x00800000) -#define NS9750_SER_BITRATE_RXCINV (0x00400000) -#define NS9750_SER_BITRATE_TCDR_MA (0x00180000) -#define NS9750_SER_BITRATE_TCDR_1 (0x00000000) -#define NS9750_SER_BITRATE_TCDR_8 (0x00080000) -#define NS9750_SER_BITRATE_TCDR_16 (0x00100000) -#define NS9750_SER_BITRATE_TCDR_32 (0x00180000) -#define NS9750_SER_BITRATE_RCDR_MA (0x00070000) -#define NS9750_SER_BITRATE_RCDR_1 (0x00000000) -#define NS9750_SER_BITRATE_RCDR_8 (0x00020000) -#define NS9750_SER_BITRATE_RCDR_16 (0x00040000) -#define NS9750_SER_BITRATE_RCDR_32 (0x00060000) -#define NS9750_SER_BITRATE_TICS (0x00010000) -#define NS9750_SER_BITRATE_RICS (0x00008000) -#define NS9750_SER_BITRATE_N_MA (0x00007FFF) - -/* receive buffer gap timer */ - -#define NS9750_SER_RX_BUF_TIMER_TRUN (0x80000000) /* UART and SPI */ -#define NS9750_SER_RX_BUF_TIMER_BT_MA (0x0000FFFF) /* UART and SPI */ -#define NS9750_SER_RX_BUF_TIMER_MAXLEN_MA (0x0000FFFF) /* HDLC only */ - -/* receive character gap timer */ - -#define NS9750_SER_RX_CHAR_TIMER_TRUN (0x80000000) -#define NS9750_SER_RX_CHAR_TIMER_CT_MA (0x000FFFFF) - -/* receive match */ - -#define NS9750_SER_RX_MATCH_RDMB1_MA (0xFF000000) -#define NS9750_SER_RX_MATCH_RDMB2_MA (0x00FF0000) -#define NS9750_SER_RX_MATCH_RDMB3_MA (0x0000FF00) -#define NS9750_SER_RX_MATCH_RDMB4_MA (0x000000FF) - -/* receive match mask */ - -#define NS9750_SER_RX_MATCH_MASK_RDMB1_MA (0xFF000000) -#define NS9750_SER_RX_MATCH_MASK_RDMB2_MA (0x00FF0000) -#define NS9750_SER_RX_MATCH_MASK_RDMB3_MA (0x0000FF00) -#define NS9750_SER_RX_MATCH_MASK_RDMB4_MA (0x000000FF) - -#endif /* FS_NS9750_SER_H */ diff --git a/include/ns9750_sys.h b/include/ns9750_sys.h deleted file mode 100644 index f1dc2b2382..0000000000 --- a/include/ns9750_sys.h +++ /dev/null @@ -1,215 +0,0 @@ -/*********************************************************************** - * - * Copyright (C) 2004 by FS Forth-Systeme GmbH. - * All rights reserved. - * - * $Id: ns9750_sys.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $ - * @Author: Markus Pietrek - * @Descr: Definitions for SYS Control Module - * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 4 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - ***********************************************************************/ - -#ifndef FS_NS9750_SYS_H -#define FS_NS9750_SYS_H - -#define NS9750_SYS_MODULE_BASE (0xA0900000) - -#define get_sys_reg_addr(c) \ - ((volatile unsigned int *)(NS9750_SYS_MODULE_BASE+(unsigned int) (c))) - -/* the register addresses */ - -#define NS9750_SYS_AHB_GEN (0x0000) -#define NS9750_SYS_BRC_BASE (0x0004) -#define NS9750_SYS_AHB_TIMEOUT (0x0014) -#define NS9750_SYS_AHB_ERROR1 (0x0018) -#define NS9750_SYS_AHB_ERROR2 (0x001C) -#define NS9750_SYS_AHB_MON (0x0020) -#define NS9750_SYS_TIMER_COUNT_BASE (0x0044) -#define NS9750_SYS_TIMER_READ_BASE (0x0084) -#define NS9750_SYS_INT_VEC_ADR_BASE (0x00C4) -#define NS9750_SYS_INT_CFG_BASE (0x0144) -#define NS9750_SYS_ISRADDR (0x0164) -#define NS9750_SYS_INT_STAT_ACTIVE (0x0168) -#define NS9750_SYS_INT_STAT_RAW (0x016C) -#define NS9750_SYS_TIMER_INT_STAT (0x0170) -#define NS9750_SYS_SW_WDOG_CFG (0x0174) -#define NS9750_SYS_SW_WDOG_TIMER (0x0178) -#define NS9750_SYS_CLOCK (0x017C) -#define NS9750_SYS_RESET (0x0180) -#define NS9750_SYS_MISC (0x0184) -#define NS9750_SYS_PLL (0x0188) -#define NS9750_SYS_ACT_INT_STAT (0x018C) -#define NS9750_SYS_TIMER_CTRL_BASE (0x0190) -#define NS9750_SYS_CS_DYN_BASE_BASE (0x01D0) -#define NS9750_SYS_CS_DYN_MASK_BASE (0x01D4) -#define NS9750_SYS_CS_STATIC_BASE_BASE (0x01F0) -#define NS9750_SYS_CS_STATIC_MASK_BASE (0x01F4) -#define NS9750_SYS_GEN_ID (0x0210) -#define NS9750_SYS_EXT_INT_CTRL_BASE (0x0214) - -/* the vectored register addresses */ - -#define NS9750_SYS_TIMER_COUNT(c) (NS9750_SYS_TIMER_COUNT_BASE + (c)) -#define NS9750_SYS_TIMER_READ(c) (NS9750_SYS_TIMER_READ_BASE + (c)) -#define NS9750_SYS_INT_VEC_ADR(c) (NS9750_SYS_INT_VEC_ADR_BASE + (c)) -#define NS9750_SYS_TIMER_CTRL(c) (NS9750_SYS_TIMER_CTRL_BASE + (c)) -/* CS_DYN start with 4 */ -#define NS9750_SYS_CS_DYN_BASE(c) (NS9750_SYS_CS_DYN_BASE_BASE + ((c)-4)*2) -#define NS9750_SYS_CS_DYN_MASK(c) (NS9750_SYS_CS_DYN_MASK_BASE + ((c)-4)*2) -/* CS_STATIC start with 0 */ -#define NS9750_SYS_CS_STATIC_BASE(c) (NS9750_SYS_CS_STATIC_BASE_BASE + (c)*2) -#define NS9750_SYS_CS_STATIC_MASK(c) (NS9750_SYS_CS_STATIC_MASK_BASE + (c)*2) -#define NS9750_SYS_EXT_INT_CTRL(c) (NS9750_SYS_EXT_INT_CTRL + (c)) - -/* register bit fields */ - -#define NS9750_SYS_AHB_GEN_EXMAM (0x00000001) - -/* need to be n*8bit to BRC channel */ -#define NS9750_SYS_BRC_CEB (0x00000080) -#define NS9750_SYS_BRC_BRF_MA (0x00000030) -#define NS9750_SYS_BRC_BRF_100 (0x00000000) -#define NS9750_SYS_BRC_BRF_75 (0x00000010) -#define NS9750_SYS_BRC_BRF_50 (0x00000020) -#define NS9750_SYS_BRC_BRF_25 (0x00000030) - -#define NS9750_SYS_AHB_TIMEOUT_BAT_MA (0xFFFF0000) -#define NS9750_SYS_AHB_TIMEOUT_BMT_MA (0x0000FFFF) - -#define NS9750_SYS_AHB_ERROR2_ABL (0x00040000) -#define NS9750_SYS_AHB_ERROR2_AER (0x00020000) -#define NS9750_SYS_AHB_ERROR2_ABM (0x00010000) -#define NS9750_SYS_AHB_ERROR2_ABA (0x00008000) -#define NS9750_SYS_AHB_ERROR2_HWRT (0x00004000) -#define NS9750_SYS_AHB_ERROR2_HMID_MA (0x00003C00) -#define NS9750_SYS_AHB_ERROR2_HTPC_MA (0x000003C0) -#define NS9750_SYS_AHB_ERROR2_HSZ_MA (0x00000038) -#define NS9750_SYS_AHB_ERROR2_RR_MA (0x00000007) - -#define NS9750_SYS_AHB_MON_EIC (0x00800000) -#define NS9750_SYS_AHB_MON_MBII (0x00400000) -#define NS9750_SYS_AHB_MON_MBL_MA (0x003FFFC0) -#define NS9750_SYS_AHB_MON_MBLDC (0x00000020) -#define NS9750_SYS_AHB_MON_SERDC (0x00000010) -#define NS9750_SYS_AHB_MON_BMTC_MA (0x0000000C) -#define NS9750_SYS_AHB_MON_BMTC_RECORD (0x00000000) -#define NS9750_SYS_AHB_MON_BMTC_GEN_IRQ (0x00000004) -#define NS9750_SYS_AHB_MON_BMTC_GEN_RES (0x00000008) -#define NS9750_SYS_AHB_MON_BATC_MA (0x00000003) -#define NS9750_SYS_AHB_MON_BATC_RECORD (0x00000000) -#define NS9750_SYS_AHB_MON_BATC_GEN_IRQ (0x00000001) -#define NS9750_SYS_AHB_MON_BATC_GEN_RES (0x00000002) - -/* need to be n*8bit to Int Level */ - -#define NS9750_SYS_INT_CFG_IE (0x00000080) -#define NS9750_SYS_INT_CFG_IT (0x00000020) -#define NS9750_SYS_INT_CFG_IAD_MA (0x0000001F) - -#define NS9750_SYS_TIMER_INT_STAT_MA (0x0000FFFF) - -#define NS9750_SYS_SW_WDOG_CFG_SWWE (0x00000080) -#define NS9750_SYS_SW_WDOG_CFG_SWWI (0x00000020) -#define NS9750_SYS_SW_WDOG_CFG_SWWIC (0x00000010) -#define NS9750_SYS_SW_WDOG_CFG_SWTCS_MA (0x00000007) -#define NS9750_SYS_SW_WDOG_CFG_SWTCS_2 (0x00000000) -#define NS9750_SYS_SW_WDOG_CFG_SWTCS_4 (0x00000001) -#define NS9750_SYS_SW_WDOG_CFG_SWTCS_8 (0x00000002) -#define NS9750_SYS_SW_WDOG_CFG_SWTCS_16 (0x00000003) -#define NS9750_SYS_SW_WDOG_CFG_SWTCS_32 (0x00000004) -#define NS9750_SYS_SW_WDOG_CFG_SWTCS_64 (0x00000005) - -#define NS9750_SYS_CLOCK_LPCS_MA (0x00000380) -#define NS9750_SYS_CLOCK_LPCS_1 (0x00000000) -#define NS9750_SYS_CLOCK_LPCS_2 (0x00000080) -#define NS9750_SYS_CLOCK_LPCS_4 (0x00000100) -#define NS9750_SYS_CLOCK_LPCS_8 (0x00000180) -#define NS9750_SYS_CLOCK_LPCS_EXT (0x00000200) -#define NS9750_SYS_CLOCK_BBC (0x00000040) -#define NS9750_SYS_CLOCK_LCC (0x00000020) -#define NS9750_SYS_CLOCK_MCC (0x00000010) -#define NS9750_SYS_CLOCK_PARBC (0x00000008) -#define NS9750_SYS_CLOCK_PC (0x00000004) -#define NS9750_SYS_CLOCK_MACC (0x00000001) - -#define NS9750_SYS_RESET_SR (0x80000000) -#define NS9750_SYS_RESET_I2CW (0x00100000) -#define NS9750_SYS_RESET_CSE (0x00080000) -#define NS9750_SYS_RESET_SMWE (0x00040000) -#define NS9750_SYS_RESET_EWE (0x00020000) -#define NS9750_SYS_RESET_PI3WE (0x00010000) -#define NS9750_SYS_RESET_BBT (0x00000040) -#define NS9750_SYS_RESET_LCDC (0x00000020) -#define NS9750_SYS_RESET_MEMC (0x00000010) -#define NS9750_SYS_RESET_PCIAR (0x00000008) -#define NS9750_SYS_RESET_PCIM (0x00000004) -#define NS9750_SYS_RESET_MACM (0x00000001) - -#define NS9750_SYS_MISC_REV_MA (0xFF000000) -#define NS9750_SYS_MISC_PCIA (0x00002000) -#define NS9750_SYS_MISC_VDIS (0x00001000) -#define NS9750_SYS_MISC_BMM (0x00000800) -#define NS9750_SYS_MISC_CS1DB (0x00000400) -#define NS9750_SYS_MISC_CS1DW_MA (0x00000300) -#define NS9750_SYS_MISC_MCCM (0x00000080) -#define NS9750_SYS_MISC_PMSS (0x00000040) -#define NS9750_SYS_MISC_CS1P (0x00000020) -#define NS9750_SYS_MISC_ENDM (0x00000008) -#define NS9750_SYS_MISC_MBAR (0x00000004) -#define NS9750_SYS_MISC_IRAM0 (0x00000001) - -#define NS9750_SYS_PLL_PLLBS (0x02000000) -#define NS9750_SYS_PLL_PLLFS_MA (0x01800000) -#define NS9750_SYS_PLL_PLLIS_MA (0x00600000) -#define NS9750_SYS_PLL_PLLND_MA (0x001F0000) -#define NS9750_SYS_PLL_PLLSW (0x00008000) -#define NS9750_SYS_PLL_PLLBSSW (0x00000200) -#define NS9750_SYS_PLL_FSEL_MA (0x00000180) -#define NS9750_SYS_PLL_CPCC_MA (0x00000060) -#define NS9750_SYS_PLL_NDSW_MA (0x0000001F) - -#define NS9750_SYS_ACT_INT_STAT_MA (0x0000FFFF) - -#define NS9750_SYS_TIMER_CTRL_TEN (0x00008000) -#define NS9750_SYS_TIMER_CTRL_INTC (0x00000200) -#define NS9750_SYS_TIMER_CTRL_TLCS_MA (0x000001C0) -#define NS9750_SYS_TIMER_CTRL_TLCS_1 (0x00000000) -#define NS9750_SYS_TIMER_CTRL_TLCS_2 (0x00000040) -#define NS9750_SYS_TIMER_CTRL_TLCS_4 (0x00000080) -#define NS9750_SYS_TIMER_CTRL_TLCS_8 (0x000000C0) -#define NS9750_SYS_TIMER_CTRL_TLCS_16 (0x00000100) -#define NS9750_SYS_TIMER_CTRL_TLCS_32 (0x00000140) -#define NS9750_SYS_TIMER_CTRL_TLCS_64 (0x00000180) -#define NS9750_SYS_TIMER_CTRL_TLCS_EXT (0x000001C0) -#define NS9750_SYS_TIMER_CTRL_TM_MA (0x00000030) -#define NS9750_SYS_TIMER_CTRL_TM_INT (0x00000000) -#define NS9750_SYS_TIMER_CTRL_TM_LOW (0x00000010) -#define NS9750_SYS_TIMER_CTRL_TM_HIGH (0x00000020) -#define NS9750_SYS_TIMER_CTRL_INTS (0x00000008) -#define NS9750_SYS_TIMER_CTRL_UDS (0x00000004) -#define NS9750_SYS_TIMER_CTRL_TSZ (0x00000002) -#define NS9750_SYS_TIMER_CTRL_REN (0x00000001) - -#define NS9750_SYS_EXT_INT_CTRL_STS (0x00000008) -#define NS9750_SYS_EXT_INT_CTRL_CLR (0x00000004) -#define NS9750_SYS_EXT_INT_CTRL_PLTY (0x00000002) -#define NS9750_SYS_EXT_INT_CTRL_LVEDG (0x00000001) - -#endif /* FS_NS9750_SYS_H */ diff --git a/include/os.h b/include/os.h index 699682a408..038aba9e4f 100644 --- a/include/os.h +++ b/include/os.h @@ -40,6 +40,16 @@ struct sandbox_state; ssize_t os_read(int fd, void *buf, size_t count); /** + * Access to the OS read() system call with non-blocking access + * + * \param fd File descriptor as returned by os_open() + * \param buf Buffer to place data + * \param count Number of bytes to read + * \return number of bytes read, or -1 on error + */ +ssize_t os_read_no_block(int fd, void *buf, size_t count); + +/** * Access to the OS write() system call * * \param fd File descriptor as returned by os_open() @@ -136,4 +146,52 @@ u64 os_get_nsec(void); */ int os_parse_args(struct sandbox_state *state, int argc, char *argv[]); +/* + * Types of directory entry that we support. See also os_dirent_typename in + * the C file. + */ +enum os_dirent_t { + OS_FILET_REG, /* Regular file */ + OS_FILET_LNK, /* Symbolic link */ + OS_FILET_DIR, /* Directory */ + OS_FILET_UNKNOWN, /* Something else */ + + OS_FILET_COUNT, +}; + +/** A directory entry node, containing information about a single dirent */ +struct os_dirent_node { + struct os_dirent_node *next; /* Pointer to next node, or NULL */ + ulong size; /* Size of file in bytes */ + enum os_dirent_t type; /* Type of entry */ + char name[0]; /* Name of entry */ +}; + +/** + * Get a directionry listing + * + * This allocates and returns a linked list containing the directory listing. + * + * @param dirname Directory to examine + * @param headp Returns pointer to head of linked list, or NULL if none + * @return 0 if ok, -ve on error + */ +int os_dirent_ls(const char *dirname, struct os_dirent_node **headp); + +/** + * Get the name of a directory entry type + * + * @param type Type to cehck + * @return string containing the name of that type, or "???" if none/invalid + */ +const char *os_dirent_get_typename(enum os_dirent_t type); + +/** + * Get the size of a file + * + * @param fname Filename to check + * @return size of file, or -1 if an error ocurred + */ +ssize_t os_get_filesize(const char *fname); + #endif diff --git a/include/sandboxfs.h b/include/sandboxfs.h new file mode 100644 index 0000000000..f5213ac107 --- /dev/null +++ b/include/sandboxfs.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2012, Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __SANDBOX_FS__ +#define __SANDBOX_FS__ + +int sandbox_fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info); + +long sandbox_fs_read_at(const char *filename, unsigned long pos, + void *buffer, unsigned long maxsize); + +void sandbox_fs_close(void); +int sandbox_fs_ls(const char *dirname); +int fs_read_sandbox(const char *filename, void *buf, int offset, int len); + +#endif diff --git a/include/spl.h b/include/spl.h index b02f36fa94..b40be8039c 100644 --- a/include/spl.h +++ b/include/spl.h @@ -59,6 +59,9 @@ void spl_display_print(void); /* NAND SPL functions */ void spl_nand_load_image(void); +/* OneNAND SPL functions */ +void spl_onenand_load_image(void); + /* NOR SPL functions */ void spl_nor_load_image(void); diff --git a/include/u-boot/crc.h b/include/u-boot/crc.h index 07badbfc5a..08e509edb4 100644 --- a/include/u-boot/crc.h +++ b/include/u-boot/crc.h @@ -30,4 +30,15 @@ uint32_t crc32 (uint32_t, const unsigned char *, uint); uint32_t crc32_wd (uint32_t, const unsigned char *, uint, uint); uint32_t crc32_no_comp (uint32_t, const unsigned char *, uint); +/** + * crc32_wd_buf - Perform CRC32 on a buffer and return result in buffer + * + * @input: Input buffer + * @ilen: Input buffer length + * @output: Place to put checksum result (4 bytes) + * @chunk_sz: Trigger watchdog after processing this many bytes + */ +void crc32_wd_buf(const unsigned char *input, uint ilen, + unsigned char *output, uint chunk_sz); + #endif /* _UBOOT_CRC_H */ |