diff options
Diffstat (limited to 'include')
128 files changed, 1135 insertions, 19884 deletions
diff --git a/include/api.h b/include/api.h new file mode 100644 index 0000000000..85817f3400 --- /dev/null +++ b/include/api.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2017 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __API_H +#define __API_H + +void api_init(void); + +#endif diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index e6f905110e..fb90be9d3e 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -110,6 +110,10 @@ typedef struct global_data { ulong video_top; /* Top of video frame buffer area */ ulong video_bottom; /* Bottom of video frame buffer area */ #endif +#ifdef CONFIG_BOOTSTAGE + struct bootstage_data *bootstage; /* Bootstage information */ + struct bootstage_data *new_bootstage; /* Relocated bootstage info */ +#endif } gd_t; #endif diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index 9f3351d602..95930ad20e 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -41,11 +41,10 @@ typedef struct bd_info { unsigned long bi_dsp_freq; /* dsp core frequency */ unsigned long bi_ddr_freq; /* ddr frequency */ #endif -#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) \ - || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) +#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) unsigned long bi_immr_base; /* base of IMMR register */ #endif -#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K) +#if defined(CONFIG_M68K) unsigned long bi_mbar_base; /* base of internal registers */ #endif #if defined(CONFIG_MPC83xx) @@ -63,10 +62,7 @@ typedef struct bd_info { unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */ unsigned long bi_vco; /* VCO Out from PLL, in MHz */ #endif -#if defined(CONFIG_MPC512X) - unsigned long bi_ipsfreq; /* IPS Bus Freq, in MHz */ -#endif /* CONFIG_MPC512X */ -#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K) +#if defined(CONFIG_M68K) unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ #endif diff --git a/include/blk.h b/include/blk.h index a128ee4841..ef29a07ee2 100644 --- a/include/blk.h +++ b/include/blk.h @@ -377,6 +377,13 @@ int blk_find_max_devnum(enum if_type if_type); */ int blk_select_hwpart(struct udevice *dev, int hwpart); +/** + * blk_get_from_parent() - obtain a block device by looking up its parent + * + * All devices with + */ +int blk_get_from_parent(struct udevice *parent, struct udevice **devp); + #else #include <errno.h> /* diff --git a/include/bootstage.h b/include/bootstage.h index a589be6316..c5d93f57fd 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -2,6 +2,7 @@ * This file implements recording of each stage of the boot process. It is * intended to implement timing of each stage, reporting this information * to the user and passing it to the OS for logging / further analysis. + * Note that it requires timer_get_boot_us() to be defined by the board * * Copyright (c) 2011 The Chromium OS Authors. * @@ -176,6 +177,7 @@ enum bootstage_id { */ BOOTSTAGE_ID_AWAKE, BOOTSTAGE_ID_START_SPL, + BOOTSTAGE_ID_END_SPL, BOOTSTAGE_ID_START_UBOOT_F, BOOTSTAGE_ID_START_UBOOT_R, BOOTSTAGE_ID_USB_START, @@ -198,7 +200,11 @@ enum bootstage_id { BOOTSTAGE_ID_ACCUM_SCSI, BOOTSTAGE_ID_ACCUM_SPI, BOOTSTAGE_ID_ACCUM_DECOMP, + BOOTSTAGE_ID_ACCUM_OF_LIVE, BOOTSTAGE_ID_FPGA_INIT, + BOOTSTATE_ID_ACCUM_DM_SPL, + BOOTSTATE_ID_ACCUM_DM_F, + BOOTSTATE_ID_ACCUM_DM_R, /* a few spare for the user, from here */ BOOTSTAGE_ID_USER, @@ -209,14 +215,14 @@ enum bootstage_id { /* * Return the time since boot in microseconds, This is needed for bootstage * and should be defined in CPU- or board-specific code. If undefined then - * millisecond resolution will be used (the standard get_timer()). + * you will get a link error. */ ulong timer_get_boot_us(void); #if defined(USE_HOSTCC) #define show_boot_progress(val) do {} while (0) #else -/* +/** * Board code can implement show_boot_progress() if needed. * * @param val Progress state (enum bootstage_id), or -id if an error @@ -225,8 +231,14 @@ ulong timer_get_boot_us(void); void show_boot_progress(int val); #endif -#if defined(CONFIG_BOOTSTAGE) && !defined(CONFIG_SPL_BUILD) && \ - !defined(USE_HOSTCC) +#if !defined(USE_HOSTCC) +#if CONFIG_IS_ENABLED(BOOTSTAGE) +#define ENABLE_BOOTSTAGE +#endif +#endif + +#ifdef ENABLE_BOOTSTAGE + /* This is the full bootstage implementation */ /** @@ -234,7 +246,7 @@ void show_boot_progress(int val); * * Call this after relocation has happened and after malloc has been initted. * We need to copy any pointers in bootstage records that were added pre- - * relocation, since memory can be overritten later. + * relocation, since memory can be overwritten later. * @return Always returns 0, to indicate success */ int bootstage_relocate(void); @@ -250,7 +262,7 @@ int bootstage_relocate(void); ulong bootstage_add_record(enum bootstage_id id, const char *name, int flags, ulong mark); -/* +/** * Mark a time stamp for the current boot stage. */ ulong bootstage_mark(enum bootstage_id id); @@ -309,7 +321,7 @@ void bootstage_report(void); */ int bootstage_fdt_add_report(void); -/* +/** * Stash bootstage data into memory * * @param base Base address of memory buffer @@ -326,9 +338,26 @@ int bootstage_stash(void *base, int size); * * @param base Base address of memory buffer * @param size Size of memory buffer (-1 if unknown) - * @return 0 if unstashed ok, -1 if bootstage info not found, or out of space + * @return 0 if unstashed ok, -ENOENT if bootstage info not found, -ENOSPC if + * there is not space for read the stacked data, or other error if + * something else went wrong + */ +int bootstage_unstash(const void *base, int size); + +/** + * bootstage_get_size() - Get the size of the bootstage data + * + * @return size of boostage data in bytes */ -int bootstage_unstash(void *base, int size); +int bootstage_get_size(void); + +/** + * bootstage_init() - Prepare bootstage for use + * + * @first: true if this is the first time bootstage is set up. This causes it + * to add a 'reset' record with a time of 0. + */ +int bootstage_init(bool first); #else static inline ulong bootstage_add_record(enum bootstage_id id, @@ -386,11 +415,22 @@ static inline int bootstage_stash(void *base, int size) return 0; /* Pretend to succeed */ } -static inline int bootstage_unstash(void *base, int size) +static inline int bootstage_unstash(const void *base, int size) { return 0; /* Pretend to succeed */ } -#endif /* CONFIG_BOOTSTAGE */ + +static inline int bootstage_get_size(void) +{ + return 0; +} + +static inline int bootstage_init(bool first) +{ + return 0; +} + +#endif /* ENABLE_BOOTSTAGE */ /* Helper macro for adding a bootstage to a line of code */ #define BOOTSTAGE_MARKER() \ diff --git a/include/common.h b/include/common.h index 45f190a600..638c45b954 100644 --- a/include/common.h +++ b/include/common.h @@ -30,61 +30,6 @@ typedef volatile unsigned char vu_char; #include <asm/ptrace.h> #include <stdarg.h> #include <linux/kernel.h> -#if defined(CONFIG_PCI) && defined(CONFIG_4xx) -#include <pci.h> -#endif -#if defined(CONFIG_8xx) -#include <asm/8xx_immap.h> -#if defined(CONFIG_MPC859) || defined(CONFIG_MPC859T) || \ - defined(CONFIG_MPC866) || \ - defined(CONFIG_MPC866P) -# define CONFIG_MPC866_FAMILY 1 -#elif defined(CONFIG_MPC885) -# define CONFIG_MPC885_FAMILY 1 -#endif -#if defined(CONFIG_MPC860) \ - || defined(CONFIG_MPC860T) \ - || defined(CONFIG_MPC866_FAMILY) \ - || defined(CONFIG_MPC885_FAMILY) -# define CONFIG_MPC86x 1 -#endif -#elif defined(CONFIG_5xx) -#include <asm/5xx_immap.h> -#elif defined(CONFIG_MPC5xxx) -#include <mpc5xxx.h> -#elif defined(CONFIG_MPC512X) -#include <asm/immap_512x.h> -#elif defined(CONFIG_MPC8260) -#if defined(CONFIG_MPC8247) \ - || defined(CONFIG_MPC8272) -#define CONFIG_MPC8272_FAMILY 1 -#endif -#include <asm/immap_8260.h> -#endif -#ifdef CONFIG_MPC86xx -#include <mpc86xx.h> -#include <asm/immap_86xx.h> -#endif -#ifdef CONFIG_MPC85xx -#include <mpc85xx.h> -#include <asm/immap_85xx.h> -#endif -#ifdef CONFIG_MPC83xx -#include <mpc83xx.h> -#include <asm/immap_83xx.h> -#endif -#ifdef CONFIG_4xx -#include <asm/ppc4xx.h> -#endif -#ifdef CONFIG_SOC_DA8XX -#include <asm/arch/hardware.h> -#endif -#ifdef CONFIG_FSL_LSCH3 -#include <asm/arch/immap_lsch3.h> -#endif -#ifdef CONFIG_FSL_LSCH2 -#include <asm/arch/immap_lsch2.h> -#endif #include <part.h> #include <flash.h> @@ -166,28 +111,6 @@ typedef void (interrupt_handler_t)(void *); #include <asm/u-boot.h> /* boot information for Linux kernel */ #include <asm/global_data.h> /* global data used for startup functions */ -/* - * enable common handling for all TQM8xxL/M boards: - * - CONFIG_TQM8xxM will be defined for all TQM8xxM boards - * - CONFIG_TQM8xxL will be defined for all TQM8xxL _and_ TQM8xxM boards - * and for the TQM885D board - */ -#if defined(CONFIG_TQM823M) || defined(CONFIG_TQM850M) || \ - defined(CONFIG_TQM855M) || defined(CONFIG_TQM860M) || \ - defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M) -# ifndef CONFIG_TQM8xxM -# define CONFIG_TQM8xxM -# endif -#endif -#if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L) || \ - defined(CONFIG_TQM855L) || defined(CONFIG_TQM860L) || \ - defined(CONFIG_TQM862L) || defined(CONFIG_TQM8xxM) || \ - defined(CONFIG_TQM885D) -# ifndef CONFIG_TQM8xxL -# define CONFIG_TQM8xxL -# endif -#endif - #if defined(CONFIG_ENV_IS_EMBEDDED) #define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN #elif ( ((CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) < CONFIG_SYS_MONITOR_BASE) || \ @@ -428,29 +351,6 @@ static inline int setenv_addr(const char *varname, const void *addr) return setenv_hex(varname, (ulong)addr); } -#ifdef CONFIG_ARM -# include <asm/mach-types.h> -# include <asm/setup.h> -# include <asm/u-boot-arm.h> /* ARM version to be fixed! */ -#endif /* CONFIG_ARM */ -#ifdef CONFIG_X86 /* x86 version to be fixed! */ -# include <asm/u-boot-x86.h> -#endif /* CONFIG_X86 */ -#ifdef CONFIG_SANDBOX -# include <asm/u-boot-sandbox.h> /* TODO(sjg) what needs to be fixed? */ -#endif -#ifdef CONFIG_NDS32 -# include <asm/mach-types.h> -# include <asm/setup.h> -# include <asm/u-boot-nds32.h> -#endif /* CONFIG_NDS32 */ -#ifdef CONFIG_MIPS -# include <asm/u-boot-mips.h> -#endif /* CONFIG_MIPS */ -#ifdef CONFIG_ARC -# include <asm/u-boot-arc.h> -#endif /* CONFIG_ARC */ - #ifdef CONFIG_AUTO_COMPLETE int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf); #endif @@ -459,25 +359,6 @@ int get_env_id (void); void pci_init (void); void pci_init_board(void); -#if defined(CONFIG_PCI) && defined(CONFIG_4xx) - int pci_pre_init (struct pci_controller *); - int is_pci_host (struct pci_controller *); -#endif - -#if defined(CONFIG_PCI) && (defined(CONFIG_440) || defined(CONFIG_405EX)) -# if defined(CONFIG_SYS_PCI_TARGET_INIT) - void pci_target_init (struct pci_controller *); -# endif -# if defined(CONFIG_SYS_PCI_MASTER_INIT) - void pci_master_init (struct pci_controller *); -# endif -#if defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_405EX) - void pcie_setup_hoses(int busno); -#endif -#endif - int misc_init_f (void); int misc_init_r (void); @@ -487,9 +368,6 @@ void jumptable_init(void); /* common/kallsysm.c */ const char *symbol_lookup(unsigned long addr, unsigned long *caddr); -/* api/api.c */ -void api_init (void); - /* common/memsize.c */ long get_ram_size (long *, long); phys_size_t get_effective_memsize(void); @@ -545,21 +423,6 @@ int testdram(void); #endif /* CONFIG_SYS_DRAM_TEST */ /* $(CPU)/start.S */ -#if defined(CONFIG_5xx) || \ - defined(CONFIG_8xx) -uint get_immr (uint); -#endif -#if defined(CONFIG_MPC5xxx) -uint get_svr (void); -#endif -uint get_pvr (void); -uint get_svr (void); -uint rd_ic_cst (void); -void wr_ic_cst (uint); -void wr_ic_adr (uint); -uint rd_dc_cst (void); -void wr_dc_cst (uint); -void wr_dc_adr (uint); int icache_status (void); void icache_enable (void); void icache_disable(void); @@ -574,40 +437,6 @@ void relocate_code(ulong, gd_t *, ulong) __attribute__ ((noreturn)); #endif ulong get_endaddr (void); void trap_init (ulong); -#if defined (CONFIG_4xx) || \ - defined (CONFIG_MPC5xxx) || \ - defined (CONFIG_MPC85xx) || \ - defined (CONFIG_MPC86xx) || \ - defined (CONFIG_MPC83xx) -unsigned char in8(unsigned int); -void out8(unsigned int, unsigned char); -unsigned short in16(unsigned int); -unsigned short in16r(unsigned int); -void out16(unsigned int, unsigned short value); -void out16r(unsigned int, unsigned short value); -unsigned long in32(unsigned int); -unsigned long in32r(unsigned int); -void out32(unsigned int, unsigned long value); -void out32r(unsigned int, unsigned long value); -void ppcDcbf(unsigned long value); -void ppcDcbi(unsigned long value); -void ppcSync(void); -void ppcDcbz(unsigned long value); -#endif -#if defined (CONFIG_MICROBLAZE) -unsigned short in16(unsigned int); -void out16(unsigned int, unsigned short value); -#endif - -#if defined (CONFIG_MPC83xx) -void ppcDWload(unsigned int *addr, unsigned int *ret); -void ppcDWstore(unsigned int *addr, unsigned int *value); -void disable_addr_trans(void); -void enable_addr_trans(void); -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -void ddr_enable_ecc(unsigned int dram_size); -#endif -#endif /* $(CPU)/cpu.c */ static inline int cpumask_next(int cpu, unsigned int mask) @@ -668,76 +497,9 @@ int serial_stub_tstc(struct stdio_dev *sdev); /* $(CPU)/speed.c */ int get_clocks (void); -#if defined(CONFIG_MPC5xxx) -int prt_mpc5xxx_clks (void); -#endif -#ifdef CONFIG_4xx -ulong get_OPB_freq (void); -ulong get_PCI_freq (void); -#endif -#if defined(CONFIG_S3C24X0) || \ - defined(CONFIG_LH7A40X) || \ - defined(CONFIG_EP93XX) -ulong get_FCLK (void); -ulong get_HCLK (void); -ulong get_PCLK (void); -ulong get_UCLK (void); -#endif -#if defined(CONFIG_LH7A40X) -ulong get_PLLCLK (void); -#endif -#if defined(CONFIG_IMX) -ulong get_systemPLLCLK(void); -ulong get_FCLK(void); -ulong get_HCLK(void); -ulong get_BCLK(void); -ulong get_PERCLK1(void); -ulong get_PERCLK2(void); -ulong get_PERCLK3(void); -#endif ulong get_bus_freq (ulong); int get_serial_clock(void); -#if defined(CONFIG_MPC85xx) -typedef MPC85xx_SYS_INFO sys_info_t; -void get_sys_info ( sys_info_t * ); -void ft_fixup_cpu(void *, u64); -void ft_fixup_num_cores(void *); -#endif -#if defined(CONFIG_MPC86xx) -typedef MPC86xx_SYS_INFO sys_info_t; -void get_sys_info ( sys_info_t * ); -static inline ulong get_ddr_freq(ulong dummy) -{ - return get_bus_freq(dummy); -} -#else -ulong get_ddr_freq(ulong); -#endif - -#if defined(CONFIG_4xx) -# if defined(CONFIG_440) -# if defined(CONFIG_440SPE) - unsigned long determine_sysper(void); - unsigned long determine_pci_clock_per(void); -# endif -# endif -typedef PPC4xx_SYS_INFO sys_info_t; -int ppc440spe_revB(void); -void get_sys_info ( sys_info_t * ); -#endif - -/* $(CPU)/cpu_init.c */ -#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) -void cpu_init_f (volatile immap_t *immr); -#endif -#if defined(CONFIG_4xx) || defined(CONFIG_MCF52x2) || defined(CONFIG_MPC86xx) -void cpu_init_f (void); -#endif -#ifdef CONFIG_MPC85xx -ulong cpu_init_f(void); -#endif - int cpu_init_r (void); /* $(CPU)/interrupts.c */ @@ -963,14 +725,6 @@ int cpu_release(int nr, int argc, char * const argv[]); #endif /* __ASSEMBLY__ */ -#ifdef CONFIG_PPC -/* - * Has to be included outside of the #ifndef __ASSEMBLY__ section. - * Otherwise might lead to compilation errors in assembler files. - */ -#include <asm/cache.h> -#endif - /* Put only stuff here that the assembler can digest */ /* Declare an unsigned long constant digestable both by C and an assembler. */ diff --git a/include/commproc.h b/include/commproc.h deleted file mode 100644 index 9d4cb109ad..0000000000 --- a/include/commproc.h +++ /dev/null @@ -1,849 +0,0 @@ -/* - * MPC8xx Communication Processor Module. - * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) - * - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This file contains structures and information for the communication - * processor channels. Some CPM control and status is available - * throught the MPC8xx internal memory map. See immap.h for details. - * This file only contains what I need for the moment, not the total - * CPM capabilities. I (or someone else) will add definitions as they - * are needed. -- Dan - * - */ -#ifndef __CPM_8XX__ -#define __CPM_8XX__ - -#include <asm/8xx_immap.h> - -/* CPM Command register. -*/ -#define CPM_CR_RST ((ushort)0x8000) -#define CPM_CR_OPCODE ((ushort)0x0f00) -#define CPM_CR_CHAN ((ushort)0x00f0) -#define CPM_CR_FLG ((ushort)0x0001) - -/* Some commands (there are more...later) -*/ -#define CPM_CR_INIT_TRX ((ushort)0x0000) -#define CPM_CR_INIT_RX ((ushort)0x0001) -#define CPM_CR_INIT_TX ((ushort)0x0002) -#define CPM_CR_HUNT_MODE ((ushort)0x0003) -#define CPM_CR_STOP_TX ((ushort)0x0004) -#define CPM_CR_RESTART_TX ((ushort)0x0006) -#define CPM_CR_SET_GADDR ((ushort)0x0008) - -/* Channel numbers. -*/ -#define CPM_CR_CH_SCC1 ((ushort)0x0000) -#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */ -#define CPM_CR_CH_SCC2 ((ushort)0x0004) -#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI/IDMA2/Timers */ -#define CPM_CR_CH_SCC3 ((ushort)0x0008) -#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */ -#define CPM_CR_CH_SCC4 ((ushort)0x000c) -#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */ - -#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) - -/* - * DPRAM defines and allocation functions - */ -#define CPM_SERIAL_BASE 0x0800 -#define CPM_I2C_BASE 0x0820 -#define CPM_SPI_BASE 0x0840 -#define CPM_FEC_BASE 0x0860 -#define CPM_SERIAL2_BASE 0x08E0 -#define CPM_SCC_BASE 0x0900 -#define CPM_POST_BASE 0x0980 -#define CPM_WLKBD_BASE 0x0a00 - -#ifndef CONFIG_SYS_CPM_POST_WORD_ADDR -#define CPM_POST_WORD_ADDR 0x07FC -#else -#define CPM_POST_WORD_ADDR CONFIG_SYS_CPM_POST_WORD_ADDR -#endif - -#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR -#define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong)) -#else -#define CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_BOOTCOUNT_ADDR -#endif - -#define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */ - -/* Export the base address of the communication processor registers - * and dual port ram. - */ -extern cpm8xx_t *cpmp; /* Pointer to comm processor */ - -/* Buffer descriptors used by many of the CPM protocols. -*/ -typedef struct cpm_buf_desc { - ushort cbd_sc; /* Status and Control */ - ushort cbd_datlen; /* Data length in buffer */ - uint cbd_bufaddr; /* Buffer address in host memory */ -} cbd_t; - -#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ -#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ -#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ -#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ -#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ -#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ -#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ -#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ -#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ -#define BD_SC_BR ((ushort)0x0020) /* Break received */ -#define BD_SC_FR ((ushort)0x0010) /* Framing error */ -#define BD_SC_PR ((ushort)0x0008) /* Parity error */ -#define BD_SC_OV ((ushort)0x0002) /* Overrun */ -#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */ - -/* Parameter RAM offsets. -*/ -#define PROFF_SCC1 ((uint)0x0000) -#define PROFF_IIC ((uint)0x0080) -#define PROFF_REVNUM ((uint)0x00b0) -#define PROFF_SCC2 ((uint)0x0100) -#define PROFF_SPI ((uint)0x0180) -#define PROFF_SCC3 ((uint)0x0200) -#define PROFF_SMC1 ((uint)0x0280) -#define PROFF_SCC4 ((uint)0x0300) -#define PROFF_SMC2 ((uint)0x0380) - -/* Define enough so I can at least use the serial port as a UART. - */ -typedef struct smc_uart { - ushort smc_rbase; /* Rx Buffer descriptor base address */ - ushort smc_tbase; /* Tx Buffer descriptor base address */ - u_char smc_rfcr; /* Rx function code */ - u_char smc_tfcr; /* Tx function code */ - ushort smc_mrblr; /* Max receive buffer length */ - uint smc_rstate; /* Internal */ - uint smc_idp; /* Internal */ - ushort smc_rbptr; /* Internal */ - ushort smc_ibc; /* Internal */ - uint smc_rxtmp; /* Internal */ - uint smc_tstate; /* Internal */ - uint smc_tdp; /* Internal */ - ushort smc_tbptr; /* Internal */ - ushort smc_tbc; /* Internal */ - uint smc_txtmp; /* Internal */ - ushort smc_maxidl; /* Maximum idle characters */ - ushort smc_tmpidl; /* Temporary idle counter */ - ushort smc_brklen; /* Last received break length */ - ushort smc_brkec; /* rcv'd break condition counter */ - ushort smc_brkcr; /* xmt break count register */ - ushort smc_rmask; /* Temporary bit mask */ - u_char res1[8]; - ushort smc_rpbase; /* Relocation pointer */ -} smc_uart_t; - -/* Function code bits. -*/ -#define SMC_EB ((u_char)0x10) /* Set big endian byte order */ - -/* SMC uart mode register. -*/ -#define SMCMR_REN ((ushort)0x0001) -#define SMCMR_TEN ((ushort)0x0002) -#define SMCMR_DM ((ushort)0x000c) -#define SMCMR_SM_GCI ((ushort)0x0000) -#define SMCMR_SM_UART ((ushort)0x0020) -#define SMCMR_SM_TRANS ((ushort)0x0030) -#define SMCMR_SM_MASK ((ushort)0x0030) -#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ -#define SMCMR_REVD SMCMR_PM_EVEN -#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ -#define SMCMR_BS SMCMR_PEN -#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ -#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ -#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) - -/* SMC2 as Centronics parallel printer. It is half duplex, in that - * it can only receive or transmit. The parameter ram values for - * each direction are either unique or properly overlap, so we can - * include them in one structure. - */ -typedef struct smc_centronics { - ushort scent_rbase; - ushort scent_tbase; - u_char scent_cfcr; - u_char scent_smask; - ushort scent_mrblr; - uint scent_rstate; - uint scent_r_ptr; - ushort scent_rbptr; - ushort scent_r_cnt; - uint scent_rtemp; - uint scent_tstate; - uint scent_t_ptr; - ushort scent_tbptr; - ushort scent_t_cnt; - uint scent_ttemp; - ushort scent_max_sl; - ushort scent_sl_cnt; - ushort scent_character1; - ushort scent_character2; - ushort scent_character3; - ushort scent_character4; - ushort scent_character5; - ushort scent_character6; - ushort scent_character7; - ushort scent_character8; - ushort scent_rccm; - ushort scent_rccr; -} smc_cent_t; - -/* Centronics Status Mask Register. -*/ -#define SMC_CENT_F ((u_char)0x08) -#define SMC_CENT_PE ((u_char)0x04) -#define SMC_CENT_S ((u_char)0x02) - -/* SMC Event and Mask register. -*/ -#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ -#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ -#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ -#define SMCM_BSY ((unsigned char)0x04) -#define SMCM_TX ((unsigned char)0x02) -#define SMCM_RX ((unsigned char)0x01) - -/* Baud rate generators. -*/ -#define CPM_BRG_RST ((uint)0x00020000) -#define CPM_BRG_EN ((uint)0x00010000) -#define CPM_BRG_EXTC_INT ((uint)0x00000000) -#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000) -#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000) -#define CPM_BRG_ATB ((uint)0x00002000) -#define CPM_BRG_CD_MASK ((uint)0x00001ffe) -#define CPM_BRG_DIV16 ((uint)0x00000001) - -/* SI Clock Route Register -*/ -#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000) -#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000) -#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800) -#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100) -#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000) -#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000) -#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000) -#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000) - -/* SCCs. -*/ -#define SCC_GSMRH_IRP ((uint)0x00040000) -#define SCC_GSMRH_GDE ((uint)0x00010000) -#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) -#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) -#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) -#define SCC_GSMRH_REVD ((uint)0x00002000) -#define SCC_GSMRH_TRX ((uint)0x00001000) -#define SCC_GSMRH_TTX ((uint)0x00000800) -#define SCC_GSMRH_CDP ((uint)0x00000400) -#define SCC_GSMRH_CTSP ((uint)0x00000200) -#define SCC_GSMRH_CDS ((uint)0x00000100) -#define SCC_GSMRH_CTSS ((uint)0x00000080) -#define SCC_GSMRH_TFL ((uint)0x00000040) -#define SCC_GSMRH_RFW ((uint)0x00000020) -#define SCC_GSMRH_TXSY ((uint)0x00000010) -#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) -#define SCC_GSMRH_SYNL8 ((uint)0x00000008) -#define SCC_GSMRH_SYNL4 ((uint)0x00000004) -#define SCC_GSMRH_RTSM ((uint)0x00000002) -#define SCC_GSMRH_RSYN ((uint)0x00000001) - -#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ -#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) -#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) -#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) -#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) -#define SCC_GSMRL_TCI ((uint)0x10000000) -#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) -#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) -#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) -#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) -#define SCC_GSMRL_RINV ((uint)0x02000000) -#define SCC_GSMRL_TINV ((uint)0x01000000) -#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) -#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) -#define SCC_GSMRL_TPL_48 ((uint)0x00800000) -#define SCC_GSMRL_TPL_32 ((uint)0x00600000) -#define SCC_GSMRL_TPL_16 ((uint)0x00400000) -#define SCC_GSMRL_TPL_8 ((uint)0x00200000) -#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) -#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) -#define SCC_GSMRL_TPP_01 ((uint)0x00100000) -#define SCC_GSMRL_TPP_10 ((uint)0x00080000) -#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) -#define SCC_GSMRL_TEND ((uint)0x00040000) -#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) -#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) -#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) -#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) -#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) -#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) -#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) -#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) -#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) -#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) -#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) -#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) -#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) -#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) -#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) -#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) -#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) -#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) -#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ -#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) -#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) -#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) -#define SCC_GSMRL_ENR ((uint)0x00000020) -#define SCC_GSMRL_ENT ((uint)0x00000010) -#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) -#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) -#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) -#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) -#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) -#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) -#define SCC_GSMRL_MODE_UART ((uint)0x00000004) -#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) -#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) -#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) - -#define SCC_TODR_TOD ((ushort)0x8000) - -/* SCC Event and Mask register. -*/ -#define SCCM_TXE ((unsigned char)0x10) -#define SCCM_BSY ((unsigned char)0x04) -#define SCCM_TX ((unsigned char)0x02) -#define SCCM_RX ((unsigned char)0x01) - -typedef struct scc_param { - ushort scc_rbase; /* Rx Buffer descriptor base address */ - ushort scc_tbase; /* Tx Buffer descriptor base address */ - u_char scc_rfcr; /* Rx function code */ - u_char scc_tfcr; /* Tx function code */ - ushort scc_mrblr; /* Max receive buffer length */ - uint scc_rstate; /* Internal */ - uint scc_idp; /* Internal */ - ushort scc_rbptr; /* Internal */ - ushort scc_ibc; /* Internal */ - uint scc_rxtmp; /* Internal */ - uint scc_tstate; /* Internal */ - uint scc_tdp; /* Internal */ - ushort scc_tbptr; /* Internal */ - ushort scc_tbc; /* Internal */ - uint scc_txtmp; /* Internal */ - uint scc_rcrc; /* Internal */ - uint scc_tcrc; /* Internal */ -} sccp_t; - -/* Function code bits. -*/ -#define SCC_EB ((u_char)0x10) /* Set big endian byte order */ - -/* CPM Ethernet through SCCx. - */ -typedef struct scc_enet { - sccp_t sen_genscc; - uint sen_cpres; /* Preset CRC */ - uint sen_cmask; /* Constant mask for CRC */ - uint sen_crcec; /* CRC Error counter */ - uint sen_alec; /* alignment error counter */ - uint sen_disfc; /* discard frame counter */ - ushort sen_pads; /* Tx short frame pad character */ - ushort sen_retlim; /* Retry limit threshold */ - ushort sen_retcnt; /* Retry limit counter */ - ushort sen_maxflr; /* maximum frame length register */ - ushort sen_minflr; /* minimum frame length register */ - ushort sen_maxd1; /* maximum DMA1 length */ - ushort sen_maxd2; /* maximum DMA2 length */ - ushort sen_maxd; /* Rx max DMA */ - ushort sen_dmacnt; /* Rx DMA counter */ - ushort sen_maxb; /* Max BD byte count */ - ushort sen_gaddr1; /* Group address filter */ - ushort sen_gaddr2; - ushort sen_gaddr3; - ushort sen_gaddr4; - uint sen_tbuf0data0; /* Save area 0 - current frame */ - uint sen_tbuf0data1; /* Save area 1 - current frame */ - uint sen_tbuf0rba; /* Internal */ - uint sen_tbuf0crc; /* Internal */ - ushort sen_tbuf0bcnt; /* Internal */ - ushort sen_paddrh; /* physical address (MSB) */ - ushort sen_paddrm; - ushort sen_paddrl; /* physical address (LSB) */ - ushort sen_pper; /* persistence */ - ushort sen_rfbdptr; /* Rx first BD pointer */ - ushort sen_tfbdptr; /* Tx first BD pointer */ - ushort sen_tlbdptr; /* Tx last BD pointer */ - uint sen_tbuf1data0; /* Save area 0 - current frame */ - uint sen_tbuf1data1; /* Save area 1 - current frame */ - uint sen_tbuf1rba; /* Internal */ - uint sen_tbuf1crc; /* Internal */ - ushort sen_tbuf1bcnt; /* Internal */ - ushort sen_txlen; /* Tx Frame length counter */ - ushort sen_iaddr1; /* Individual address filter */ - ushort sen_iaddr2; - ushort sen_iaddr3; - ushort sen_iaddr4; - ushort sen_boffcnt; /* Backoff counter */ - - /* NOTE: Some versions of the manual have the following items - * incorrectly documented. Below is the proper order. - */ - ushort sen_taddrh; /* temp address (MSB) */ - ushort sen_taddrm; - ushort sen_taddrl; /* temp address (LSB) */ -} scc_enet_t; - -/********************************************************************** - * - * Board specific configuration settings. - * - * Please note that we use the presence of a #define SCC_ENET and/or - * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers. - **********************************************************************/ - -/*** BSEIP **********************************************************/ - -#ifdef CONFIG_BSEIP -/* This ENET stuff is for the MPC823 with ethernet on SCC2. - * This is unique to the BSE ip-Engine board. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) -#define PA_ENET_TXD ((ushort)0x0008) -#define PA_ENET_TCLK ((ushort)0x0100) -#define PA_ENET_RCLK ((ushort)0x0200) -#define PB_ENET_TENA ((uint)0x00002000) -#define PC_ENET_CLSN ((ushort)0x0040) -#define PC_ENET_RENA ((ushort)0x0080) - -/* BSE uses port B and C bits for PHY control also. -*/ -#define PB_BSE_POWERUP ((uint)0x00000004) -#define PB_BSE_FDXDIS ((uint)0x00008000) -#define PC_BSE_LOOPBACK ((ushort)0x0800) - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002c00) -#endif /* CONFIG_BSEIP */ - -/*** KM8XX *********************************************************/ - -/* The KM8XX Service Module uses SCC3 for Ethernet */ - -#ifdef CONFIG_KM8XX -#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */ -#define CPM_CR_ENET CPM_CR_CH_SCC3 -#define SCC_ENET 2 -#define PA_ENET_RXD ((ushort)0x0010) /* PA 11 */ -#define PA_ENET_TXD ((ushort)0x0020) /* PA 10 */ -#define PA_ENET_RCLK ((ushort)0x1000) /* PA 3 CLK 5 */ -#define PA_ENET_TCLK ((ushort)0x2000) /* PA 2 CLK 6 */ - -#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */ - -#define PC_ENET_RENA ((ushort)0x0200) /* PC 6 */ -#define PC_ENET_CLSN ((ushort)0x0100) /* PC 7 */ - -/* Control bits in the SICR to route TCLK (CLK6) and RCLK (CLK5) to - * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero. - */ -#define SICR_ENET_MASK ((uint)0x00FF0000) -#define SICR_ENET_CLKRT ((uint)0x00250000) -#endif /* CONFIG_KM8XX */ - -/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/ - -#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \ - defined(CONFIG_TQM823L) || \ - defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \ - defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D) - -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC2 use. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ - -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002600) - -# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */ -#define FEC_ENET -# endif /* CONFIG_FEC_ENET */ - -#endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */ - -/*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/ - -#if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \ - defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \ - defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \ - defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M) - -# ifdef CONFIG_SCC1_ENET /* use SCC for 10Mbps Ethernet */ - -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - */ -#define PROFF_ENET PROFF_SCC1 -#define CPM_CR_ENET CPM_CR_CH_SCC1 -#define SCC_ENET 0 -#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ -#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ -#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ -#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ -#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x00000026) - -# endif /* CONFIG_SCC1_ENET */ - -# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */ - -#define FEC_ENET - -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ - -#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ - -# endif /* CONFIG_FEC_ENET */ -#endif /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */ - -/*********************************************************************/ - -/* SCC Event register as used by Ethernet. -*/ -#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ -#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ -#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ -#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ -#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ -#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ - -/* SCC Mode Register (PSMR) as used by Ethernet. -*/ -#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ -#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ -#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ -#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ -#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ -#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ -#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ -#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ -#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ -#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ -#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ -#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ -#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ - -/* Buffer descriptor control/status used by Ethernet receive. -*/ -#define BD_ENET_RX_EMPTY ((ushort)0x8000) -#define BD_ENET_RX_WRAP ((ushort)0x2000) -#define BD_ENET_RX_INTR ((ushort)0x1000) -#define BD_ENET_RX_LAST ((ushort)0x0800) -#define BD_ENET_RX_FIRST ((ushort)0x0400) -#define BD_ENET_RX_MISS ((ushort)0x0100) -#define BD_ENET_RX_LG ((ushort)0x0020) -#define BD_ENET_RX_NO ((ushort)0x0010) -#define BD_ENET_RX_SH ((ushort)0x0008) -#define BD_ENET_RX_CR ((ushort)0x0004) -#define BD_ENET_RX_OV ((ushort)0x0002) -#define BD_ENET_RX_CL ((ushort)0x0001) -#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ - -/* Buffer descriptor control/status used by Ethernet transmit. -*/ -#define BD_ENET_TX_READY ((ushort)0x8000) -#define BD_ENET_TX_PAD ((ushort)0x4000) -#define BD_ENET_TX_WRAP ((ushort)0x2000) -#define BD_ENET_TX_INTR ((ushort)0x1000) -#define BD_ENET_TX_LAST ((ushort)0x0800) -#define BD_ENET_TX_TC ((ushort)0x0400) -#define BD_ENET_TX_DEF ((ushort)0x0200) -#define BD_ENET_TX_HB ((ushort)0x0100) -#define BD_ENET_TX_LC ((ushort)0x0080) -#define BD_ENET_TX_RL ((ushort)0x0040) -#define BD_ENET_TX_RCMASK ((ushort)0x003c) -#define BD_ENET_TX_UN ((ushort)0x0002) -#define BD_ENET_TX_CSL ((ushort)0x0001) -#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ - -/* SCC as UART -*/ -typedef struct scc_uart { - sccp_t scc_genscc; - uint scc_res1; /* Reserved */ - uint scc_res2; /* Reserved */ - ushort scc_maxidl; /* Maximum idle chars */ - ushort scc_idlc; /* temp idle counter */ - ushort scc_brkcr; /* Break count register */ - ushort scc_parec; /* receive parity error counter */ - ushort scc_frmec; /* receive framing error counter */ - ushort scc_nosec; /* receive noise counter */ - ushort scc_brkec; /* receive break condition counter */ - ushort scc_brkln; /* last received break length */ - ushort scc_uaddr1; /* UART address character 1 */ - ushort scc_uaddr2; /* UART address character 2 */ - ushort scc_rtemp; /* Temp storage */ - ushort scc_toseq; /* Transmit out of sequence char */ - ushort scc_char1; /* control character 1 */ - ushort scc_char2; /* control character 2 */ - ushort scc_char3; /* control character 3 */ - ushort scc_char4; /* control character 4 */ - ushort scc_char5; /* control character 5 */ - ushort scc_char6; /* control character 6 */ - ushort scc_char7; /* control character 7 */ - ushort scc_char8; /* control character 8 */ - ushort scc_rccm; /* receive control character mask */ - ushort scc_rccr; /* receive control character register */ - ushort scc_rlbc; /* receive last break character */ -} scc_uart_t; - -/* SCC Event and Mask registers when it is used as a UART. -*/ -#define UART_SCCM_GLR ((ushort)0x1000) -#define UART_SCCM_GLT ((ushort)0x0800) -#define UART_SCCM_AB ((ushort)0x0200) -#define UART_SCCM_IDL ((ushort)0x0100) -#define UART_SCCM_GRA ((ushort)0x0080) -#define UART_SCCM_BRKE ((ushort)0x0040) -#define UART_SCCM_BRKS ((ushort)0x0020) -#define UART_SCCM_CCR ((ushort)0x0008) -#define UART_SCCM_BSY ((ushort)0x0004) -#define UART_SCCM_TX ((ushort)0x0002) -#define UART_SCCM_RX ((ushort)0x0001) - -/* The SCC PSMR when used as a UART. -*/ -#define SCU_PSMR_FLC ((ushort)0x8000) -#define SCU_PSMR_SL ((ushort)0x4000) -#define SCU_PSMR_CL ((ushort)0x3000) -#define SCU_PSMR_UM ((ushort)0x0c00) -#define SCU_PSMR_FRZ ((ushort)0x0200) -#define SCU_PSMR_RZS ((ushort)0x0100) -#define SCU_PSMR_SYN ((ushort)0x0080) -#define SCU_PSMR_DRT ((ushort)0x0040) -#define SCU_PSMR_PEN ((ushort)0x0010) -#define SCU_PSMR_RPM ((ushort)0x000c) -#define SCU_PSMR_REVP ((ushort)0x0008) -#define SCU_PSMR_TPM ((ushort)0x0003) -#define SCU_PSMR_TEVP ((ushort)0x0003) - -/* CPM Transparent mode SCC. - */ -typedef struct scc_trans { - sccp_t st_genscc; - uint st_cpres; /* Preset CRC */ - uint st_cmask; /* Constant mask for CRC */ -} scc_trans_t; - -#define BD_SCC_TX_LAST ((ushort)0x0800) - -/* IIC parameter RAM. -*/ -typedef struct iic { - ushort iic_rbase; /* Rx Buffer descriptor base address */ - ushort iic_tbase; /* Tx Buffer descriptor base address */ - u_char iic_rfcr; /* Rx function code */ - u_char iic_tfcr; /* Tx function code */ - ushort iic_mrblr; /* Max receive buffer length */ - uint iic_rstate; /* Internal */ - uint iic_rdp; /* Internal */ - ushort iic_rbptr; /* Internal */ - ushort iic_rbc; /* Internal */ - uint iic_rxtmp; /* Internal */ - uint iic_tstate; /* Internal */ - uint iic_tdp; /* Internal */ - ushort iic_tbptr; /* Internal */ - ushort iic_tbc; /* Internal */ - uint iic_txtmp; /* Internal */ - uint iic_res; /* reserved */ - ushort iic_rpbase; /* Relocation pointer */ - ushort iic_res2; /* reserved */ -} iic_t; - -/* SPI parameter RAM. -*/ -typedef struct spi { - ushort spi_rbase; /* Rx Buffer descriptor base address */ - ushort spi_tbase; /* Tx Buffer descriptor base address */ - u_char spi_rfcr; /* Rx function code */ - u_char spi_tfcr; /* Tx function code */ - ushort spi_mrblr; /* Max receive buffer length */ - uint spi_rstate; /* Internal */ - uint spi_rdp; /* Internal */ - ushort spi_rbptr; /* Internal */ - ushort spi_rbc; /* Internal */ - uint spi_rxtmp; /* Internal */ - uint spi_tstate; /* Internal */ - uint spi_tdp; /* Internal */ - ushort spi_tbptr; /* Internal */ - ushort spi_tbc; /* Internal */ - uint spi_txtmp; /* Internal */ - uint spi_res; - ushort spi_rpbase; /* Relocation pointer */ - ushort spi_res2; -} spi_t; - -/* SPI Mode register. -*/ -#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ -#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ -#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ -#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ -#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ -#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ -#define SPMODE_EN ((ushort)0x0100) /* Enable */ -#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ -#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ - -#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) -#define SPMODE_PM(x) ((x) &0xF) - -/* HDLC parameter RAM. -*/ - -typedef struct hdlc_pram_s { - /* - * SCC parameter RAM - */ - ushort rbase; /* Rx Buffer descriptor base address */ - ushort tbase; /* Tx Buffer descriptor base address */ - uchar rfcr; /* Rx function code */ - uchar tfcr; /* Tx function code */ - ushort mrblr; /* Rx buffer length */ - ulong rstate; /* Rx internal state */ - ulong rptr; /* Rx internal data pointer */ - ushort rbptr; /* rb BD Pointer */ - ushort rcount; /* Rx internal byte count */ - ulong rtemp; /* Rx temp */ - ulong tstate; /* Tx internal state */ - ulong tptr; /* Tx internal data pointer */ - ushort tbptr; /* Tx BD pointer */ - ushort tcount; /* Tx byte count */ - ulong ttemp; /* Tx temp */ - ulong rcrc; /* temp receive CRC */ - ulong tcrc; /* temp transmit CRC */ - /* - * HDLC specific parameter RAM - */ - uchar res[4]; /* reserved */ - ulong c_mask; /* CRC constant */ - ulong c_pres; /* CRC preset */ - ushort disfc; /* discarded frame counter */ - ushort crcec; /* CRC error counter */ - ushort abtsc; /* abort sequence counter */ - ushort nmarc; /* nonmatching address rx cnt */ - ushort retrc; /* frame retransmission cnt */ - ushort mflr; /* maximum frame length reg */ - ushort max_cnt; /* maximum length counter */ - ushort rfthr; /* received frames threshold */ - ushort rfcnt; /* received frames count */ - ushort hmask; /* user defined frm addr mask */ - ushort haddr1; /* user defined frm address 1 */ - ushort haddr2; /* user defined frm address 2 */ - ushort haddr3; /* user defined frm address 3 */ - ushort haddr4; /* user defined frm address 4 */ - ushort tmp; /* temp */ - ushort tmp_mb; /* temp */ -} hdlc_pram_t; - -/* CPM interrupts. There are nearly 32 interrupts generated by CPM - * channels or devices. All of these are presented to the PPC core - * as a single interrupt. The CPM interrupt handler dispatches its - * own handlers, in a similar fashion to the PPC core handler. We - * use the table as defined in the manuals (i.e. no special high - * priority and SCC1 == SCCa, etc...). - */ -#define CPMVEC_NR 32 -#define CPMVEC_OFFSET 0x00010000 -#define CPMVEC_PIO_PC15 ((ushort)0x1f | CPMVEC_OFFSET) -#define CPMVEC_SCC1 ((ushort)0x1e | CPMVEC_OFFSET) -#define CPMVEC_SCC2 ((ushort)0x1d | CPMVEC_OFFSET) -#define CPMVEC_SCC3 ((ushort)0x1c | CPMVEC_OFFSET) -#define CPMVEC_SCC4 ((ushort)0x1b | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC14 ((ushort)0x1a | CPMVEC_OFFSET) -#define CPMVEC_TIMER1 ((ushort)0x19 | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC13 ((ushort)0x18 | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC12 ((ushort)0x17 | CPMVEC_OFFSET) -#define CPMVEC_SDMA_CB_ERR ((ushort)0x16 | CPMVEC_OFFSET) -#define CPMVEC_IDMA1 ((ushort)0x15 | CPMVEC_OFFSET) -#define CPMVEC_IDMA2 ((ushort)0x14 | CPMVEC_OFFSET) -#define CPMVEC_TIMER2 ((ushort)0x12 | CPMVEC_OFFSET) -#define CPMVEC_RISCTIMER ((ushort)0x11 | CPMVEC_OFFSET) -#define CPMVEC_I2C ((ushort)0x10 | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC11 ((ushort)0x0f | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC10 ((ushort)0x0e | CPMVEC_OFFSET) -#define CPMVEC_TIMER3 ((ushort)0x0c | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC9 ((ushort)0x0b | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC8 ((ushort)0x0a | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC7 ((ushort)0x09 | CPMVEC_OFFSET) -#define CPMVEC_TIMER4 ((ushort)0x07 | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC6 ((ushort)0x06 | CPMVEC_OFFSET) -#define CPMVEC_SPI ((ushort)0x05 | CPMVEC_OFFSET) -#define CPMVEC_SMC1 ((ushort)0x04 | CPMVEC_OFFSET) -#define CPMVEC_SMC2 ((ushort)0x03 | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC5 ((ushort)0x02 | CPMVEC_OFFSET) -#define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET) -#define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET) - -extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id); - -/* CPM interrupt configuration vector. -*/ -#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ -#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ -#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ -#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ -#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */ -#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ -#define CICR_IEN ((uint)0x00000080) /* Int. enable */ -#define CICR_SPS ((uint)0x00000001) /* SCC Spread */ -#endif /* __CPM_8XX__ */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index ab4b060906..c66b26ff82 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -139,7 +139,6 @@ * IDE/ATA stuff *----------------------------------------------------------------------- */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ #undef CONFIG_IDE_LED /* no led for ide supported */ #define CONFIG_IDE_RESET 1 /* reset for ide supported */ diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index b13809f88a..3a1d4d9388 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -306,7 +306,6 @@ #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ #undef CONFIG_IDE_LED /* no led for ide supported */ #define CONFIG_IDE_RESET /* reset for ide supported... */ #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 9b2f8364d5..3b62449ea5 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -326,13 +326,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * Environment */ #define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 #define CONFIG_ENV_ADDR 0xfff80000 #else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000) +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #endif #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 618d5377fc..3734055bd3 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -206,7 +206,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 @@ -337,9 +337,9 @@ extern unsigned long get_clock_freq(void); * Environment */ #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) -#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ #define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 4b932103a6..7ec36eb608 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -101,7 +101,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * DDR Setup */ -#undef CONFIG_FSL_DDR_INTERACTIVE +#define CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/PATI.h b/include/configs/PATI.h deleted file mode 100644 index 1f26ac4c2d..0000000000 --- a/include/configs/PATI.h +++ /dev/null @@ -1,245 +0,0 @@ -/* - * (C) Copyright 2003 - * Denis Peter d.peter@mpl.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * File: PATI.h - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -#define CONFIG_MPC555 1 /* This is an MPC555 CPU */ -#define CONFIG_PATI 1 /* ...On a PATI board */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -/* Serial Console Configuration */ -#define CONFIG_5xx_CONS_SCI1 -#undef CONFIG_5xx_CONS_SCI2 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_REGINFO - -#define CONFIG_BOOTCOMMAND "" /* autoboot command */ - -#define CONFIG_BOOTARGS "" /* */ - -#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ - -#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_PREBOOT - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00010000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 } - -/*********************************************************************** - * Last Stage Init - ***********************************************************************/ -#define CONFIG_LAST_STAGE_INIT - -/* - * Low Level Configuration Settings - */ - -/* - * Internal Memory Mapped (This is not the IMMR content) - */ -#define CONFIG_SYS_IMMR 0x01C00000 /* Physical start adress of internal memory map */ - -/* - * Definitions for initial stack pointer and data area - */ -#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IMMR + 0x03fa000) /* Physical start adress of inital stack */ -/* - * Start addresses for the final memory configuration - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ -#define CONFIG_SYS_FLASH_BASE 0xffC00000 /* External flash */ -#define PCI_BASE 0x03000000 /* PCI Base (CS2) */ -#define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */ -#define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */ - -#define CONFIG_SYS_MONITOR_BASE 0xFFF00000 -/* CONFIG_SYS_FLASH_BASE */ /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file. */ - /* This adress is given to the linker with -Ttext to */ - /* locate the text section at this adress. */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#define CONFIG_SYS_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - *----------------------------------------------------------------------- - * - */ - -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER - -#define CONFIG_FLASH_SHOW_PROGRESS 45 - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 128 - -#define CONFIG_ENV_IS_IN_EEPROM -#ifdef CONFIG_ENV_IS_IN_EEPROM -#define CONFIG_ENV_OFFSET 0 -#define CONFIG_ENV_SIZE 2048 -#endif - -#undef CONFIG_ENV_IS_IN_FLASH -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 0x00002000 /* Set whole sector as env */ -#define CONFIG_ENV_OFFSET ((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE) /* Environment starts at this adress */ -#endif - -#define CONFIG_SPI 1 -#define CONFIG_SYS_SPI_CS_USED 0x09 /* CS0 and CS3 are used */ -#define CONFIG_SYS_SPI_CS_BASE 0x08 /* CS3 is active low */ -#define CONFIG_SYS_SPI_CS_ACT 0x00 /* CS3 is active low */ -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * SW Watchdog freeze - */ -#undef CONFIG_WATCHDOG -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF00 -#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ - SCCR_COM01 | SCCR_DFNL000 | SCCR_DFNH000) - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration - *----------------------------------------------------------------------- - * Data show cycle - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */ - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register - *----------------------------------------------------------------------- - * Set all bits to 40 Mhz - * - */ -#define CONFIG_SYS_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ - -#define CONFIG_SYS_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) - -/*----------------------------------------------------------------------- - * UMCR - UIMB Module Configuration Register - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ - -/*----------------------------------------------------------------------- - * ICTRL - I-Bus Support Control Register - */ -#define CONFIG_SYS_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ - -/*----------------------------------------------------------------------- - * USIU - Memory Controller Register - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA) -#define CONFIG_SYS_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */ -/* SDRAM */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) -#define CONFIG_SYS_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */ -/* PCI */ -#define CONFIG_SYS_BR2_PRELIM (PCI_BASE | BR_V | BR_PS_32 | BR_SETA) -#define CONFIG_SYS_OR2_PRELIM (OR_ADDR_MK_FF) -/* config registers: */ -#define CONFIG_SYS_BR3_PRELIM (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) -#define CONFIG_SYS_OR3_PRELIM (0xffff0000) - -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* We don't realign the flash */ - -/*----------------------------------------------------------------------- - * DER - Timer Decrementer - *----------------------------------------------------------------------- - * Initialise to zero - */ -#define CONFIG_SYS_DER 0x00000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 393a02dd78..1f5b9f045f 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -246,7 +246,6 @@ #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ #undef CONFIG_IDE_LED /* no led for ide supported */ #define CONFIG_IDE_RESET /* reset for ide supported... */ #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 78ce91d089..b8f23d769c 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -150,7 +150,6 @@ /* * IDE/ATA stuff */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ #undef CONFIG_IDE_LED /* no led for ide supported */ #define CONFIG_IDE_RESET 1 /* reset for ide supported */ diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h deleted file mode 100644 index e1f04459c4..0000000000 --- a/include/configs/TQM5200.h +++ /dev/null @@ -1,626 +0,0 @@ -/* - * (C) Copyright 2003-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2006 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_TQM5200 1 /* ... on TQM5200 module */ -#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFC000000 boot low (standard configuration with room for - * max 64 MByte Flash ROM) - * 0xFFF00000 boot high (for a backup copy of U-Boot) - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFC000000 -#endif - -/* On a Cameron or on a FO300 board or ... */ -#if !defined(CONFIG_CAM5200) && !defined(CONFIG_CHARON) \ - && !defined(CONFIG_FO300) -#define CONFIG_STK52XX 1 /* ... on a STK52XX board */ -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#define CONFIG_BOOTCOUNT_LIMIT 1 - -#ifdef CONFIG_FO300 -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enable null device */ -#define CONFIG_USB_BIN_FIXUP 1 /* for a buggy USB device */ -#if 0 -#define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED 1 /* silent console on PSC1 when S1 */ - /* switch is closed */ -#endif - -#undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* silent console on PSC1 when S1 */ - /* switch is open */ -#endif /* CONFIG_FO300 */ - -#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX) -#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ -#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ -#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */ -#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */ -#define CONFIG_BOARD_EARLY_INIT_R -#endif /* CONFIG_STK52XX */ - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX) -/* #define CONFIG_PCI_SCAN_SHOW 1 */ - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_EEPRO100 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 -#endif /* CONFIG_STK52XX */ - -/* - * Video console - */ -#ifndef CONFIG_TQM5200S /* No graphics controller on TQM5200S */ -#define CONFIG_VIDEO_SM501 -#define CONFIG_VIDEO_SM501_32BPP -#define CONFIG_VIDEO_LOGO - -#ifndef CONFIG_FO300 -#else -#define CONFIG_VIDEO_BMP_LOGO -#endif - -#define CONFIG_SPLASH_SCREEN -#endif /* #ifndef CONFIG_TQM5200S */ - -/* Partitions */ - -/* USB */ -#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \ - defined(CONFIG_STK52XX) -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_OHCI_BE_CONTROLLER - -#undef CONFIG_SYS_USB_OHCI_BOARD_INIT -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 - -#endif - -#ifndef CONFIG_CAM5200 -/* POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_CPU) -#endif - -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_REGINFO - -#ifdef CONFIG_PCI -#define CONFIG_CMD_PCI -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 -#endif - -#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \ - defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX) -#endif - -#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \ - defined(CONFIG_STK52XX) - #define CONFIG_CFG_USB - #define CONFIG_CFG_FAT -#endif - -#define CONFIG_TIMESTAMP /* display image timestamps */ - -#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000) -# define CONFIG_SYS_LOWBOOT 1 /* Boot low */ -#endif - -/* - * Autobooting - */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#if defined(CONFIG_TQM5200_B) && !defined(CONFIG_SYS_LOWBOOT) -# define ENV_UPDT \ - "update=protect off FFF00000 +${filesize};" \ - "erase FFF00000 +${filesize};" \ - "cp.b 200000 FFF00000 ${filesize};" \ - "protect on FFF00000 +${filesize}\0" -#else /* default lowboot configuration */ -# define ENV_UPDT \ - "update=protect off FC000000 +${filesize};" \ - "erase FC000000 +${filesize};" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 +${filesize}\0" -#endif - -#if defined(CONFIG_TQM5200) -#define CUSTOM_ENV_SETTINGS \ - "hostname=tqm5200\0" \ - "bootfile=/tftpboot/tqm5200/uImage\0" \ - "fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \ - "u-boot=/tftpboot/tqm5200/u-boot.bin\0" -#elif defined(CONFIG_CAM5200) -#define CUSTOM_ENV_SETTINGS \ - "bootfile=cam5200/uImage\0" \ - "u-boot=cam5200/u-boot.bin\0" \ - "setup=tftp 200000 cam5200/setup.img; source 200000\0" -#endif - -#if defined(CONFIG_TQM5200_B) -#define ENV_FLASH_LAYOUT \ - "fdt_addr=FC100000\0" \ - "kernel_addr=FC140000\0" \ - "ramdisk_addr=FC600000\0" -#elif defined(CONFIG_CHARON) -#define ENV_FLASH_LAYOUT \ - "fdt_addr=FDFC0000\0" \ - "kernel_addr=FC0A0000\0" \ - "ramdisk_addr=FC200000\0" -#else /* !CONFIG_TQM5200_B */ -#define ENV_FLASH_LAYOUT \ - "fdt_addr=FC0A0000\0" \ - "kernel_addr=FC0C0000\0" \ - "ramdisk_addr=FC300000\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "console=ttyPSC0\0" \ - ENV_FLASH_LAYOUT \ - "kernel_addr_r=400000\0" \ - "fdt_addr_r=600000\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addcons=setenv bootargs ${bootargs} " \ - "console=${console},${baudrate}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "flash_self_old=sete console ttyS0; " \ - "run ramargs addip addcons addmtd; " \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_self=run ramargs addip addcons;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "flash_nfs_old=sete console ttyS0; run nfsargs addip addcons;" \ - "bootm ${kernel_addr}\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \ - "sete console ttyS0; run nfsargs addip addcons;bootm\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "tftp ${fdt_addr_r} ${fdt_file}; " \ - "run nfsargs addip addcons addmtd; " \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - CUSTOM_ENV_SETTINGS \ - "load=tftp 200000 ${u-boot}\0" \ - ENV_UPDT \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200) -/* - * PCI Bus clocking configuration - * - * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of - * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. - */ -#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ -#endif - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_BASE 0xFC000000 - -#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH) -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks - (= chip selects) */ -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned int /* main flash device with */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_ADDR0 0x555 -#define CONFIG_SYS_FLASH_ADDR1 0x2AA -#define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* NIOS flash is a 16bit device */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 -#else -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_FLASH_CFI_MTD /* with MTD support */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START } -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#endif - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - -#if defined (CONFIG_CAM5200) -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) -#elif defined(CONFIG_TQM5200_B) -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000) -#else -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) -#endif - -/* Dynamic MTD partition support */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define MTDIDS_DEFAULT "nor0=fc000000.flash" - -#if defined(CONFIG_STK52XX) -# if defined(CONFIG_TQM5200_B) -# if defined(CONFIG_SYS_LOWBOOT) -# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:1m(firmware)," \ - "256k(dtb)," \ - "2304k(kernel)," \ - "2560k(small-fs)," \ - "2m(initrd)," \ - "8m(misc)," \ - "16m(big-fs)" -# else /* highboot */ -# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:2560k(kernel),"\ - "3584k(small-fs)," \ - "2m(initrd)," \ - "8m(misc)," \ - "15m(big-fs)," \ - "1m(firmware)" -# endif /* CONFIG_SYS_LOWBOOT */ -# else /* !CONFIG_TQM5200_B */ -# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\ - "128k(dtb)," \ - "2304k(kernel)," \ - "2m(initrd)," \ - "4m(small-fs)," \ - "8m(misc)," \ - "15m(big-fs)" -# endif /* CONFIG_TQM5200_B */ -#elif defined (CONFIG_CAM5200) -# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:768k(firmware),"\ - "1792k(kernel)," \ - "5632k(rootfs)," \ - "24m(home)" -#elif defined (CONFIG_CHARON) -# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\ - "1408k(kernel)," \ - "2m(initrd)," \ - "4m(small-fs)," \ - "24320k(big-fs)," \ - "256k(dts)" -#elif defined (CONFIG_FO300) -# define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:640k(firmware),"\ - "1408k(kernel)," \ - "2m(initrd)," \ - "4m(small-fs)," \ - "8m(misc)," \ - "16m(big-fs)" -#else -# error "Unknown Carrier Board" -#endif /* CONFIG_STK52XX */ - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */ -#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200) -#define CONFIG_ENV_SECT_SIZE 0x40000 -#else -#define CONFIG_ENV_SECT_SIZE 0x20000 -#endif /* CONFIG_TQM5200_B */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE -#else -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE -#endif - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#if defined (CONFIG_CAM5200) -# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#elif defined(CONFIG_TQM5200_B) -# define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ -#else -# define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ -#endif - -#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -/* - * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb - */ -/* #define CONFIG_MPC5xxx_FEC_MII10 */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - * - * use CS1: Bit 0 (mask: 0x80000000): - * 1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1). - * use ALT CAN position: Bits 2-3 (mask: 0x30000000): - * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. - * SPI on PSC3 according to PSC3 setting. Use for CAM5200. - * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. - * Use for REV200 STK52XX boards and FO300 boards. Do not use - * with REV100 modules (because, there I2C1 is used as I2C bus). - * use ATA: Bits 6-7 (mask 0x03000000): - * 00 -> No ATA chip selects, csb_4/5 used as normal chip selects. - * Use for CAM5200 board. - * 01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards. - * use PSC6: Bits 9-11 (mask 0x00700000): - * 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as - * UART, CODEC or IrDA. - * GPIO on PSC6_3 is used in post_hotkeys_pressed() to - * enable extended POST tests. - * Use for MINI-FAP and TQM5200_IB boards. - * 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used. - * Extended POST test is not available. - * Use for STK52xx, FO300 and CAM5200 boards. - * WARNING: When the extended POST is enabled, these bits will - * be overridden by this code as GPIOs! - * use PCI_DIS: Bit 16 (mask 0x00008000): - * 1 -> disable PCI controller (on CAM5200 board). - * use USB: Bits 18-19 (mask 0x00003000): - * 10 -> two UARTs (on FO300 and CAM5200). - * use PSC3: Bits 20-23 (mask: 0x00000f00): - * 0000 -> All PSC3 pins are GPIOs. - * 1100 -> UART/SPI (on FO300 board). - * 0100 -> UART (on CAM5200 board). - * use PSC2: Bits 25:27 (mask: 0x00000030): - * 000 -> All PSC2 pins are GPIOs. - * 100 -> UART (on CAM5200 board). - * 001 -> CAN1/2 on PSC2 pins. - * Use for REV100 STK52xx boards - * 01x -> Use AC97 (on FO300 board). - * use PSC1: Bits 29-31 (mask: 0x00000007): - * 100 -> UART (on all boards). - */ -#if !defined(CONFIG_SYS_GPS_PORT_CONFIG) -#if defined (CONFIG_MINIFAP) -# define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004 -#elif defined (CONFIG_STK52XX) -# if defined (CONFIG_STK52XX_REV100) -# define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014 -# else /* STK52xx REV200 and above */ -# if defined (CONFIG_TQM5200_REV100) -# error TQM5200 REV100 not supported on STK52XX REV200 or above -# else/* TQM5200 REV200 and above */ -# define CONFIG_SYS_GPS_PORT_CONFIG 0x91500404 -# endif -# endif -#elif defined (CONFIG_FO300) -# define CONFIG_SYS_GPS_PORT_CONFIG 0x91502c24 -#elif defined (CONFIG_CAM5200) -# define CONFIG_SYS_GPS_PORT_CONFIG 0x8050A444 -#else /* TMQ5200 Inbetriebnahme-Board */ -# define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004 -#endif -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/* Enable an alternate, more extensive memory test */ -#define CONFIG_SYS_ALT_MEMTEST - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 -#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ -#else -#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ -#endif -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_LAST_STAGE_INIT - -/* - * SRAM - Do not map below 2 GB in address space, because this area is used - * for SDRAM autosizing. - */ -#define CONFIG_SYS_CS2_START 0xE5000000 -#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */ -#define CONFIG_SYS_CS2_CFG 0x0004D930 - -/* - * Grafic controller - Do not map below 2 GB in address space, because this - * area is used for SDRAM autosizing. - */ -#define SM501_FB_BASE 0xE0000000 -#define CONFIG_SYS_CS1_START (SM501_FB_BASE) -#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */ -#define CONFIG_SYS_CS1_CFG 0x8F48FF70 -#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000 - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ - -#if defined(CONFIG_CAM5200) -#define CONFIG_SYS_CS4_START 0xB0000000 -#define CONFIG_SYS_CS4_SIZE 0x00010000 -#define CONFIG_SYS_CS4_CFG 0x01019C10 - -#define CONFIG_SYS_CS5_START 0xD0000000 -#define CONFIG_SYS_CS5_SIZE 0x01208000 -#define CONFIG_SYS_CS5_CFG 0x1414BF10 -#endif - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -/* Support ATAPI devices */ -#define CONFIG_ATAPI 1 - -/*----------------------------------------------------------------------- - * Open firmware flat tree support - *----------------------------------------------------------------------- - */ -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h deleted file mode 100644 index 74636b9162..0000000000 --- a/include/configs/TQM823L.h +++ /dev/null @@ -1,435 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#ifdef CONFIG_LCD /* with LCD controller ? */ -#define CONFIG_MPC8XX_LCD -#define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */ -#define CONFIG_LCD_INFO 1 /* ... and some board info */ -#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM823L\0" \ - "bootfile=TQM823L/uImage\0" \ - "fdt_addr=40040000\0" \ - "kernel_addr=40060000\0" \ - "ramdisk_addr=40200000\0" \ - "u-boot=TQM823L/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ - "128k(dtb)," \ - "1664k(kernel)," \ - "2m(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h deleted file mode 100644 index 6b345c427c..0000000000 --- a/include/configs/TQM823M.h +++ /dev/null @@ -1,434 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#ifdef CONFIG_LCD /* with LCD controller ? */ -#define CONFIG_MPC8XX_LCD -/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM823M\0" \ - "bootfile=TQM823M/uImage\0" \ - "fdt_addr=40080000\0" \ - "kernel_addr=400A0000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM823M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h deleted file mode 100644 index b4ed561544..0000000000 --- a/include/configs/TQM850L.h +++ /dev/null @@ -1,428 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM850L\0" \ - "bootfile=TQM850L/uImage\0" \ - "fdt_addr=40040000\0" \ - "kernel_addr=40060000\0" \ - "ramdisk_addr=40200000\0" \ - "u-boot=TQM850L/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ - "128k(dtb)," \ - "1664k(kernel)," \ - "2m(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h deleted file mode 100644 index 1dc13295ff..0000000000 --- a/include/configs/TQM850M.h +++ /dev/null @@ -1,429 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ -#define CONFIG_TQM850M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM850M\0" \ - "bootfile=TQM850M/uImage\0" \ - "fdt_addr=40080000\0" \ - "kernel_addr=400A0000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM850M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h deleted file mode 100644 index b4c3a79387..0000000000 --- a/include/configs/TQM855L.h +++ /dev/null @@ -1,434 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ -#define CONFIG_TQM855L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM855L\0" \ - "bootfile=TQM855L/uImage\0" \ - "fdt_addr=40040000\0" \ - "kernel_addr=40060000\0" \ - "ramdisk_addr=40200000\0" \ - "u-boot=TQM855L/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ - "128k(dtb)," \ - "1664k(kernel)," \ - "2m(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC" - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h deleted file mode 100644 index 14b76a66bc..0000000000 --- a/include/configs/TQM855M.h +++ /dev/null @@ -1,464 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC855 1 /* This is a MPC855 CPU */ -#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM855M\0" \ - "bootfile=TQM855M/uImage\0" \ - "fdt_addr=40080000\0" \ - "kernel_addr=400A0000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM855M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ -#if 0 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC" - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h deleted file mode 100644 index f55fe56abb..0000000000 --- a/include/configs/TQM860L.h +++ /dev/null @@ -1,434 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_TQM860L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM860L\0" \ - "bootfile=TQM860L/uImage\0" \ - "fdt_addr=40040000\0" \ - "kernel_addr=40060000\0" \ - "ramdisk_addr=40200000\0" \ - "u-boot=TQM860L/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ - "128k(dtb)," \ - "1664k(kernel)," \ - "2m(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC" - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h deleted file mode 100644 index 52c4d68693..0000000000 --- a/include/configs/TQM860M.h +++ /dev/null @@ -1,438 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ -#define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM860M\0" \ - "bootfile=TQM860M/uImage\0" \ - "fdt_addr=400C0000\0" \ - "kernel_addr=40100000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM860M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 10 column SDRAM */ -#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC" - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h deleted file mode 100644 index 06981c9861..0000000000 --- a/include/configs/TQM862L.h +++ /dev/null @@ -1,438 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_MPC862 1 - -#define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM862L\0" \ - "bootfile=TQM862L/uImage\0" \ - "fdt_addr=40040000\0" \ - "kernel_addr=40060000\0" \ - "ramdisk_addr=40200000\0" \ - "u-boot=TQM862L/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ - "128k(dtb)," \ - "1664k(kernel)," \ - "2m(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - * 100 Mhz => 100.000.000 / Divider = 195 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC" - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h deleted file mode 100644 index 3f87d8aa11..0000000000 --- a/include/configs/TQM862M.h +++ /dev/null @@ -1,439 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 -#define CONFIG_MPC860T 1 -#define CONFIG_MPC862 1 - -#define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM862M\0" \ - "bootfile=TQM862M/uImage\0" \ - "fdt_addr=40080000\0" \ - "kernel_addr=400A0000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM862M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - * 100 Mhz => 100.000.000 / Divider = 195 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC" - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h deleted file mode 100644 index 975f4b76dc..0000000000 --- a/include/configs/TQM866M.h +++ /dev/null @@ -1,457 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC866 1 /* This is a MPC866 CPU */ -#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ -#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ -#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ -#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */ - /* (it will be used if there is no */ - /* 'cpuclk' variable with valid value) */ - -#undef CONFIG_SYS_MEASURE_CPUCLK /* Measure real cpu clock */ - /* (function measure_gclk() */ - /* will be called) */ -#ifdef CONFIG_SYS_MEASURE_CPUCLK -#define CONFIG_SYS_8XX_XIN 10000000 /* measure_gclk() needs this */ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM866M\0" \ - "bootfile=TQM866M/uImage\0" \ - "fdt_addr=400C0000\0" \ - "kernel_addr=40100000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM866M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE - -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */ - -#define CONFIG_TIMESTAMP /* but print image timestmps */ - -/* - * Command line configuration. - */ - -#define CONFIG_NETCONSOLE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: Default value of OR0 after reset - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ - OR_SCY_15_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - */ -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) - -/* - * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) - * - * CPUclock(MHz) * 31.2 - * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0 - * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 - * - * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us - * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us - * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us - * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us - * - * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will - * be met also in the default configuration, i.e. if environment variable - * 'cpuclk' is not set. - */ -#define CONFIG_SYS_MAMR_PTA 97 - -/* - * Memory Periodic Timer Prescaler Register (MPTPR) values. - */ -/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 -/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 10 column SDRAM */ -#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -#define CONFIG_SCC1_ENET -#define CONFIG_FEC_ENET -#define CONFIG_ETHPRIME "SCC" - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h deleted file mode 100644 index 184cb62e19..0000000000 --- a/include/configs/TQM885D.h +++ /dev/null @@ -1,451 +0,0 @@ -/* - * (C) Copyright 2000-2014 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2006 - * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC885 1 /* This is a MPC885 CPU */ -#define CONFIG_TQM885D 1 /* ...on a TQM88D module */ - -#define CONFIG_SYS_TEXT_BASE 0x40000000 - -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ -#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ -#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ -#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */ - /* (it will be used if there is no */ - /* 'cpuclk' variable with valid value) */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -#define CONFIG_BOOTCOUNT_LIMIT - - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM885D/uImage\0" \ - "fdt_addr=400C0000\0" \ - "kernel_addr=40100000\0" \ - "ramdisk_addr=40280000\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=protect off 40000000 +${filesize};" \ - "erase 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "protect on 40000000 +${filesize}\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -# define CONFIG_RTC_DS1337 1 -# define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */ - -#define CONFIG_TIMESTAMP /* but print image timestmps */ - -/* - * Command line configuration. - */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */ -#define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive - memory test.*/ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: Default value of OR0 after reset - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ - OR_SCY_6_CLK | OR_TRLX) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - */ -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) - -/* - * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) - * - * CPUclock(MHz) * 31.2 - * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0 - * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 - * - * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us - * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us - * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us - * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us - * - * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will - * be met also in the default configuration, i.e. if environment variable - * 'cpuclk' is not set. - */ -#define CONFIG_SYS_MAMR_PTA 128 - -/* - * Memory Periodic Timer Prescaler Register (MPTPR) values. - */ -/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 -/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 10 column SDRAM */ -#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - -/* - * Network configuration - */ -#define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */ -#define CONFIG_FEC_ENET /* enable ethernet on FEC */ -#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */ -#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */ - -#if defined(CONFIG_CMD_MII) -#define CONFIG_SYS_DISCOVER_PHY -#define CONFIG_MII_INIT 1 -#endif - -#define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before - switching to another netwok (if the - tried network is unreachable) */ - -#define CONFIG_ETHPRIME "SCC" - -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index b2feccfd39..8579290e81 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -311,7 +311,7 @@ #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ #define CONFIG_RTC_DS1337 -#define CONFIG_SYS_RTC_DS1337_NOOSC +#define CONFIG_RTC_DS1337_NOOSC #define CONFIG_SYS_I2C_RTC_ADDR 0x68 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h deleted file mode 100644 index 82b9ff471d..0000000000 --- a/include/configs/a3m071.h +++ /dev/null @@ -1,408 +0,0 @@ -/* - * Copyright 2012-2013 Stefan Roese <sr@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 -#define CONFIG_A3M071 /* A3M071 board */ - -#define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */ - -#define CONFIG_SPL_TARGET "u-boot-img.bin" - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ - -#define CONFIG_MISC_INIT_R -#define CONFIG_SYS_LOWBOOT /* Enable lowboot */ - -#ifdef CONFIG_A4M2K -#define CONFIG_HOSTNAME a4m2k -#else -#define CONFIG_HOSTNAME a3m071 -#endif - -#define CONFIG_BOOTCOUNT_LIMIT - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Command line configuration. - */ -#define CONFIG_CMD_REGINFO -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_BOOTP_SERVERIP -#define CONFIG_BOOTP_MAY_FAIL -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_SERVERIP -#define CONFIG_NET_RETRY_COUNT 3 -#define CONFIG_NETCONSOLE -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_MTD_PARTITIONS /* needed for UBI */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=fc000000.flash" -#define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:512k(u-boot)," \ - "128k(env1)," \ - "128k(env2)," \ - "128k(hwinfo)," \ - "1M(nvramsim)," \ - "128k(dtb)," \ - "5M(kernel)," \ - "128k(sysinfo)," \ - "7552k(root)," \ - "4M(app)," \ - "5376k(data)," \ - "8M(install)" - -#define CONFIG_LZO /* needed for UBI */ -#define CONFIG_RBTREE /* needed for UBI */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_UBIFS - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -/* define for 66MHz speed - undef for 33MHz PCI clock speed */ -#ifdef CONFIG_A4M2K -#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 -#else -#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 -#endif - -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" - -/* - * NOR flash configuration - */ -#define CONFIG_SYS_FLASH_BASE 0xfc000000 -#define CONFIG_SYS_FLASH_SIZE 0x02000000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000) - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 -#define CONFIG_SYS_FLASH_LOCK_TOUT 5 -#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_FLASH_VERIFY - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xf0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_MONITOR_LEN (512 << 10) -#define CONFIG_SYS_MALLOC_LEN (4 << 20) -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC -#define CONFIG_MPC5xxx_FEC_MII100 -#ifdef CONFIG_A4M2K -#define CONFIG_PHY_ADDR 0x01 -#else -#define CONFIG_PHY_ADDR 0x00 -#endif - -/* - * GPIO configuration - */ - -/* - * GPIO-config depends on failsave-level - * failsave 0 means just MPX-config, no digiboard, no fpga - * 1 means digiboard ok - * 2 means fpga ok - */ - -#ifdef CONFIG_A4M2K -#define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C805 -#else -/* for failsave-level 0 - full failsave */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C005 -/* for failsave-level 1 - only digiboard ok */ -#define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C065 -/* for failsave-level 2 - all ok */ -#define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C065 -#endif - -#define CONFIG_WDOG_GPIO_PIN GPIO_WKUP_7 -#if defined(CONFIG_A4M2K) && !defined(CONFIG_SPL_BUILD) -#define CONFIG_HW_WATCHDOG /* Use external HW-Watchdog */ -#endif - -/* - * Configuration matrix - * MSB LSB - * failsave 0 0x1005C005 00010000000001011100000000000101 ( full failsave ) - * failsave 1 0x1005C065 00010000000001011100000001100101 ( digib.-ver ok ) - * failsave 2 0x1005C065 00010000000001011100000001100101 ( all ok ) - * || ||| || | ||| | | | | - * || ||| || | ||| | | | | bit rev name - * ++-+++-++--+---+++-+---+---+---+- 0 31 CS1 - * +-+++-++--+---+++-+---+---+---+- 1 30 LPTZ - * ||| || | ||| | | | | 2 29 ALTs - * +++-++--+---+++-+---+---+---+- 3 28 ALTs - * ++-++--+---+++-+---+---+---+- 4 27 CS7 - * +-++--+---+++-+---+---+---+- 5 26 CS6 - * || | ||| | | | | 6 25 ATA - * ++--+---+++-+---+---+---+- 7 24 ATA - * +--+---+++-+---+---+---+- 8 23 IR_USB_CLK - * | ||| | | | | 9 22 IRDA - * | ||| | | | | 10 21 IRDA - * +---+++-+---+---+---+- 11 20 IRDA - * ||| | | | | 12 19 Ether - * ||| | | | | 13 18 Ether - * ||| | | | | 14 17 Ether - * +++-+---+---+---+- 15 16 Ether - * ++-+---+---+---+- 16 15 PCI_DIS - * +-+---+---+---+- 17 14 USB_SE - * | | | | 18 13 USB - * +---+---+---+- 19 12 USB - * | | | 20 11 PSC3 - * | | | 21 10 PSC3 - * | | | 22 9 PSC3 - * +---+---+- 23 8 PSC3 - * | | 24 7 - - * | | 25 6 PSC2 - * | | 26 5 PSC2 - * +---+- 27 4 PSC2 - * | 28 3 - - * | 29 2 PSC1 - * | 30 1 PSC1 - * +- 31 0 PSC1 - */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP - -#define CONFIG_CMDLINE_EDITING - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 -#else -#define CONFIG_SYS_CBSIZE 256 -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00100000 -#define CONFIG_SYS_MEMTEST_END 0x00f00000 - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI) -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#ifdef CONFIG_A4M2K -/* external MRAM */ -#define CONFIG_SYS_CS1_START 0xf1000000 -#define CONFIG_SYS_CS1_SIZE (512 << 10) /* 512KiB MRAM */ -#endif - -#define CONFIG_SYS_CS2_START 0xe0000000 -#define CONFIG_SYS_CS2_SIZE 0x00100000 - -/* FPGA slave io (512kiB / 1MiB) - see ticket #66 */ -#define CONFIG_SYS_CS3_START 0xE9000000 -#ifdef CONFIG_A4M2K -#define CONFIG_SYS_CS3_SIZE 0x00100000 -#else -#define CONFIG_SYS_CS3_SIZE 0x00080000 -#endif -/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */ -#define CONFIG_SYS_CS3_CFG 0x0032B900 - -#ifndef CONFIG_A4M2K -/* Diagnosis Interface - see ticket #63 */ -#define CONFIG_SYS_CS4_START 0xEA000000 -#define CONFIG_SYS_CS4_SIZE 0x00000001 -/* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0002B900 */ -#define CONFIG_SYS_CS4_CFG 0x0002B900 -#endif - -/* FPGA master io (64kiB / 1MiB) - see ticket #66 */ -#define CONFIG_SYS_CS5_START 0xE8000000 -#ifdef CONFIG_A4M2K -#define CONFIG_SYS_CS5_SIZE 0x00100000 -#else -#define CONFIG_SYS_CS5_SIZE 0x00010000 -#endif -/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */ -#define CONFIG_SYS_CS5_CFG 0x0032B900 - -#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for pci_clk = 66 MHz */ -#define CONFIG_SYS_BOOTCS_CFG 0x0006F900 -#define CONFIG_SYS_CS1_CFG 0x0008FD00 -#define CONFIG_SYS_CS2_CFG 0x0006F90C -#else /* for pci_clk = 33 MHz */ -#define CONFIG_SYS_BOOTCS_CFG 0x0002F900 -#define CONFIG_SYS_CS1_CFG 0x0001FB00 -#define CONFIG_SYS_CS2_CFG 0x0002F90C -#endif - -#define CONFIG_SYS_CS_BURST 0x00000000 -/* set DC for FPGA CS5 and CS3 to 0 - see ticket #66 */ -/* R 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 */ -/* 00 11 00 11 00 00 00 11 00 00 00 00 00 00 00 00 */ -#define CONFIG_SYS_CS_DEADCYCLE 0x33030000 - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/* - * Environment Configuration - */ - -#undef CONFIG_BOOTARGS - -#define CONFIG_SYS_AUTOLOAD "n" - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_mtd\" to boot from flash with mtd filesystem;" \ - "echo Type \"run net_nfs\" to boot from tftp with nfs filesystem;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_SYS_FDT_BASE 0xfc1e0000 -#define CONFIG_SYS_FDT_SIZE (16<<10) - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "verify=no\0" \ - "loadaddr=200000\0" \ - "kernel_addr=" __stringify(CONFIG_SYS_OS_BASE) "\0" \ - "kernel_addr_r=1000000\0" \ - "fdt_addr=" __stringify(CONFIG_SYS_FDT_BASE) "\0" \ - "fdt_addr_r=1800000\0" \ - "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ - "fdtfile=" __stringify(CONFIG_HOSTNAME) "/" \ - __stringify(CONFIG_HOSTNAME) ".dtb\0" \ - "rootpath=/opt/eldk-5.2.1/powerpc/" \ - "core-image-minimal-mtdutils-dropbear-generic\0" \ - "consoledev=ttyPSC0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "mtdargs=setenv bootargs root=/dev/mtdblock8 " \ - "rootfstype=squashfs,jffs2\0" \ - "addhost=setenv bootargs ${bootargs} " \ - "hostname=${hostname}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} " \ - "console=${consoledev},${baudrate}\0" \ - "flash_nfs=run nfsargs addip addtty addmtd addhost;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "flash_mtd=run mtdargs addip addtty addmtd addhost;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "flash_self=run ramargs addip addtty addmtd addhost;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${fdt_addr_r} ${fdtfile};" \ - "run nfsargs addip addtty addmtd addhost;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME) \ - "/u-boot-img.bin\0" \ - "update=protect off fc000000 fc07ffff;" \ - "era fc000000 fc07ffff;" \ - "cp.b ${loadaddr} fc000000 ${filesize}\0" \ - "upd=run load;run update\0" \ - "upd_fdt=tftp 1800000 a3m071/a3m071.dtb;" \ - "run mtdargs addip addtty addmtd addhost;" \ - "fdt addr 1800000;fdt boardsetup;fdt chosen;" \ - "erase fc1e0000 fc1fffff;cp.b 1800000 fc1e0000 20000" \ - "upd_kernel=tftp 1000000 a3m071/uImage-uncompressed;" \ - "erase fc200000 fc6fffff;" \ - "cp.b 1000000 fc200000 ${filesize}" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "mtdids=" MTDIDS_DEFAULT "\0" \ - "mtdparts=" MTDPARTS_DEFAULT "\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_mtd" - -/* - * SPL related defines - */ -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_TEXT_BASE 0xfc000000 - -/* Place BSS for SPL near end of SDRAM */ -#define CONFIG_SPL_BSS_START_ADDR ((128 - 1) << 20) -#define CONFIG_SPL_BSS_MAX_SIZE (64 << 10) - -/* Place patched DT blob (fdt) at this address */ -#define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000 - -/* Settings for real U-Boot to be loaded from NOR flash */ -#ifndef __ASSEMBLY__ -extern char __spl_flash_end[]; -#endif -#define CONFIG_SYS_UBOOT_BASE __spl_flash_end -#define CONFIG_SYS_SPL_MAX_LEN (32 << 10) -#define CONFIG_SYS_UBOOT_START 0x1000100 - -#endif /* __CONFIG_H */ diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h deleted file mode 100644 index 6a26269807..0000000000 --- a/include/configs/a4m072.h +++ /dev/null @@ -1,324 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2010 - * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ -#define CONFIG_A4M072 1 /* ... on A4M072 board */ -#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ - -#define CONFIG_SYS_TEXT_BASE 0xFE000000 - -#define CONFIG_MISC_INIT_R - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -/* define to enable silent console */ -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ - -#if defined(CONFIG_PCI) -#define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 -#endif - -#define CONFIG_SYS_XLB_PIPELINING 1 - -#undef CONFIG_EEPRO100 - -/* USB */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_OHCI_BE_CONTROLLER -#undef CONFIG_SYS_USB_OHCI_BOARD_INIT -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 -#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_PCI -#endif - -#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */ -#define CONFIG_SYS_LOWBOOT 1 -#define CONFIG_SYS_LOWBOOT32 1 -#endif - -/* - * Autobooting - */ - -#define CONFIG_SYS_AUTOLOAD "n" - -#undef CONFIG_BOOTARGS -#define CONFIG_PREBOOT "run try_update" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bk=run add_mtd ; run add_consolespec ; bootm 200000\0" \ - "cf1=diskboot 200000 0:1\0" \ - "bootcmd_cf1=run bcf1\0" \ - "bcf=setenv bootargs root=/dev/hda3\0" \ - "bootcmd_nfs=run bnfs\0" \ - "norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs "\ - "panic=1\0" \ - "bootcmd_nor=cp.b ${kernel_addr} 200000 100000;" \ - "run norargs addip; run bk\0" \ - "bnfs=nfs 200000 ${rootpath}/boot/uImage;" \ - "run nfsargs addip ; run bk\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "try_update=usb start;sleep 2;usb start;sleep 1;" \ - "fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;" \ - "source 2F0000\0" \ - "env_addr=FE060000\0" \ - "kernel_addr=FE100000\0" \ - "rootfs_addr=FE200000\0" \ - "add_mtd=setenv bootargs ${bootargs} mtdparts=" \ - "phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0" \ - "bcf1=run cf1; run bcf; run addip; run bk\0" \ - "add_consolespec=setenv bootargs ${bootargs} " \ - "console=/dev/null quiet\0" \ - "addip=if test -n ${ethaddr};" \ - "then if test -n ${ipaddr};" \ - "then setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:"\ - "${netmask}:${hostname}:${netdev}:off;" \ - "fi;" \ - "else;" \ - "setenv bootargs ${bootargs} no_ethaddr;" \ - "fi\0" \ - "hostname=CPUP0\0" \ - "netdev=eth0\0" \ - "bootcmd=run bootcmd_nor\0" \ - "" -/* - * IPB Bus clocking configuration. - */ -#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_SIZE 0x02000000 -#if !defined(CONFIG_SYS_LOWBOOT) -#error "CONFIG_SYS_LOWBOOT not defined?" -#else /* CONFIG_SYS_LOWBOOT */ -#if defined(CONFIG_SYS_LOWBOOT32) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) -#endif -#endif /* CONFIG_SYS_LOWBOOT */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS0_START} -#define CONFIG_SYS_FLASH_BANKS_SIZES {CONFIG_SYS_CS0_SIZE} - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -/* - * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb - */ -/* #define CONFIG_MPC5xxx_FEC_MII10 */ -#define CONFIG_PHY_ADDR 0x1f -#define CONFIG_PHY_TYPE 0x79c874 /* AMD Phy Controller */ - -/* - * GPIO configuration - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x18000004 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE -/* Flash at CSBoot, CS0 */ -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x0002DD00 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE -/* External SRAM at CS1 */ -#define CONFIG_SYS_CS1_START 0x62000000 -#define CONFIG_SYS_CS1_SIZE 0x00400000 -#define CONFIG_SYS_CS1_CFG 0x00009930 -#define CONFIG_SYS_SRAM_BASE CONFIG_SYS_CS1_START -#define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_CS1_SIZE -/* LED display at CS7 */ -#define CONFIG_SYS_CS7_START 0x6a000000 -#define CONFIG_SYS_CS7_SIZE (64*1024) -#define CONFIG_SYS_CS7_CFG 0x0000bf30 - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333003 - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 /* 0x4000 for SE mode */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#define CONFIG_ATAPI 1 - -/*----------------------------------------------------------------------- - * Open firmware flat tree support - *----------------------------------------------------------------------- - */ -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" - -/* Support for the 7-segment display */ -#define CONFIG_SYS_DISP_CHR_RAM CONFIG_SYS_CS7_START -#define CONFIG_SHOW_ACTIVITY /* used for display realization */ - -#define CONFIG_SHOW_BOOT_PROGRESS - -#endif /* __CONFIG_H */ diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h deleted file mode 100644 index 4eb8f39aaf..0000000000 --- a/include/configs/ac14xx.h +++ /dev/null @@ -1,516 +0,0 @@ -/* - * (C) Copyright 2009 Wolfgang Denk <wd@denx.de> - * (C) Copyright 2010 DAVE Srl <www.dave.eu> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * ifm AC14xx (MPC5121e based) board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_AC14XX 1 - -/* - * Memory map for the ifm AC14xx board: - * - * 0x0000_0000-0x0FFF_FFFF DDR RAM (256 MB) - * 0x3000_0000-0x3001_FFFF On Chip SRAM (128 KB) - * 0x8000_0000-0x803F_FFFF IMMR (4 MB) - * 0xE000_0000-0xEFFF_FFFF several LPB attached hardware (CSx) - * 0xFC00_0000-0xFFFF_FFFF NOR Boot FLASH (64 MB) - */ - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 Family */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_SYS_MPC512X_CLKIN 25000000 /* in Hz */ -#define SCFR1_IPS_DIV 2 -#define SCFR1_LPC_DIV 2 -#define SCFR1_NFC_DIV 2 -#define SCFR1_DIU_DIV 240 - -#define CONFIG_MISC_INIT_R - -#define CONFIG_SYS_IMMR 0x80000000 -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR + 0x2100) - -/* more aggressive 'mtest' over a wider address range */ -#define CONFIG_SYS_ALT_MEMTEST -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x0FE00000 - -/* - * DDR Setup - manually set all parameters as there's no SPD etc. - */ -#define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#define CONFIG_SYS_DDR_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 - -/* - * DDR Controller Configuration - * - * SYS_CFG: - * [31:31] MDDRC Soft Reset: Diabled - * [30:30] DRAM CKE pin: Enabled - * [29:29] DRAM CLK: Enabled - * [28:28] Command Mode: Enabled (For initialization only) - * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] - * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] - * [20:19] Read Test: DON'T USE - * [18:18] Self Refresh: Enabled - * [17:17] 16bit Mode: Disabled - * [16:13] Ready Delay: 2 - * [12:12] Half DQS Delay: Disabled - * [11:11] Quarter DQS Delay: Disabled - * [10:08] Write Delay: 2 - * [07:07] Early ODT: Disabled - * [06:06] On DIE Termination: Disabled - * [05:05] FIFO Overflow Clear: DON'T USE here - * [04:04] FIFO Underflow Clear: DON'T USE here - * [03:03] FIFO Overflow Pending: DON'T USE here - * [02:02] FIFO Underlfow Pending: DON'T USE here - * [01:01] FIFO Overlfow Enabled: Enabled - * [00:00] FIFO Underflow Enabled: Enabled - * TIME_CFG0 - * [31:16] DRAM Refresh Time: 0 CSB clocks - * [15:8] DRAM Command Time: 0 CSB clocks - * [07:00] DRAM Precharge Time: 0 CSB clocks - * TIME_CFG1 - * [31:26] DRAM tRFC: - * [25:21] DRAM tWR1: - * [20:17] DRAM tWRT1: - * [16:11] DRAM tDRR: - * [10:05] DRAM tRC: - * [04:00] DRAM tRAS: - * TIME_CFG2 - * [31:28] DRAM tRCD: - * [27:23] DRAM tFAW: - * [22:19] DRAM tRTW1: - * [18:15] DRAM tCCD: - * [14:10] DRAM tRTP: - * [09:05] DRAM tRP: - * [04:00] DRAM tRPA - */ - -/* - * NOTE: although this board uses DDR1 only, the common source brings defaults - * for DDR2 init sequences, that's why we have to keep those here as well - */ - -/* DDR1 -- 32bit, drive strength (pad configuration) 3 for control and data */ -#define CONFIG_SYS_IOCTRL_MUX_DDR ((0 << 6) | (3 << 3) | (3 << 0)) - -#define CONFIG_SYS_MDDRC_SYS_CFG (/* 0xEAA09100 */ 0 \ - | (1 << 31) /* RST_B */ \ - | (1 << 30) /* CKE */ \ - | (1 << 29) /* CLK_ON */ \ - | (0 << 28) /* CMD_MODE */ \ - | (5 << 25) /* DRAM_ROW_SELECT */ \ - | (5 << 21) /* DRAM_BANK_SELECT */ \ - | (0 << 18) /* SELF_REF_EN */ \ - | (0 << 17) /* 16BIT_MODE */ \ - | (4 << 13) /* RDLY */ \ - | (1 << 12) /* HALF_DQS_DLY */ \ - | (0 << 11) /* QUART_DQS_DLY */ \ - | (1 << 8) /* WDLY */ \ - | (0 << 7) /* EARLY_ODT */ \ - | (0 << 6) /* ON_DIE_TERMINATE */ \ - | (0 << 5) /* FIFO_OV_CLEAR */ \ - | (0 << 4) /* FIFO_UV_CLEAR */ \ - | (0 << 1) /* FIFO_OV_EN */ \ - | (0 << 0) /* FIFO_UV_EN */ \ - ) - -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x04E03124 -#define CONFIG_SYS_MDDRC_TIME_CFG1 0x30CA1147 -#define CONFIG_SYS_MDDRC_TIME_CFG2 0x32B10864 - -/* register address only, i.e. template without values */ -#define CONFIG_SYS_MICRON_BMODE 0x01000000 -#define CONFIG_SYS_MICRON_EMODE 0x01010000 -#define CONFIG_SYS_MICRON_EMODE2 0x01020000 -#define CONFIG_SYS_MICRON_EMODE3 0x01030000 -/* - * values for mode registers (without mode register address) - */ -/* CAS 2.5 (6), burst seq (0) and length 4 (2) */ -#define CONFIG_SYS_MICRON_BMODE_PARAM 0x00000062 -#define CONFIG_SYS_MICRON_BMODE_RSTDLL 0x00000100 -/* DLL enable, reduced drive strength */ -#define CONFIG_SYS_MICRON_EMODE_PARAM 0x00000002 - -#define CONFIG_SYS_DDRCMD_NOP 0x01380000 -#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 -#define CONFIG_SYS_MICRON_EMR ((1 << 24) | /* CMD_REQ */ \ - (0 << 22) | /* DRAM_CS */ \ - (0 << 21) | /* DRAM_RAS */ \ - (0 << 20) | /* DRAM_CAS */ \ - (0 << 19) | /* DRAM_WEB */ \ - (1 << 16) | /* DRAM_BS[2:0] */ \ - (0 << 15) | /* */ \ - (0 << 12) | /* A12->out */ \ - (0 << 11) | /* A11->RDQS */ \ - (0 << 10) | /* A10->DQS# */ \ - (0 << 7) | /* OCD program */ \ - (0 << 6) | /* Rtt1 */ \ - (0 << 3) | /* posted CAS# */ \ - (0 << 2) | /* Rtt0 */ \ - (1 << 1) | /* ODS */ \ - (0 << 0) /* DLL */ \ - ) -#define CONFIG_SYS_MICRON_EMR2 0x01020000 -#define CONFIG_SYS_MICRON_EMR3 0x01030000 -#define CONFIG_SYS_DDRCMD_RFSH 0x01080000 -#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_MICRON_EMR_OCD ((1 << 24) | /* CMD_REQ */ \ - (0 << 22) | /* DRAM_CS */ \ - (0 << 21) | /* DRAM_RAS */ \ - (0 << 20) | /* DRAM_CAS */ \ - (0 << 19) | /* DRAM_WEB */ \ - (1 << 16) | /* DRAM_BS[2:0] */ \ - (0 << 15) | /* */ \ - (0 << 12) | /* A12->out */ \ - (0 << 11) | /* A11->RDQS */ \ - (1 << 10) | /* A10->DQS# */ \ - (7 << 7) | /* OCD program */ \ - (0 << 6) | /* Rtt1 */ \ - (0 << 3) | /* posted CAS# */ \ - (1 << 2) | /* Rtt0 */ \ - (0 << 1) | /* ODS */ \ - (0 << 0) /* DLL */ \ - ) - -/* - * Backward compatible definitions, - * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c - */ -#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2) -#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3) -#define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR) -#define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD) - -/* DDR Priority Manager Configuration */ -#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 -#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 -#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 -#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC -#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA -#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 -#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 -#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 - -/* - * NOR FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_CFI /* use the CFI code */ -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ -#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size */ - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST { \ - CONFIG_SYS_FLASH_BASE + 0 * CONFIG_SYS_FLASH_SIZE, \ - } -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_PROTECTION - -/* - * SRAM support - */ -#define CONFIG_SYS_SRAM_BASE 0x30000000 -#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ - -/* - * CS related parameters - */ -/* CS0 Flash */ -#define CONFIG_SYS_CS0_CFG 0x00031110 -#define CONFIG_SYS_CS0_START 0xFC000000 -#define CONFIG_SYS_CS0_SIZE 0x04000000 -/* CS1 FRAM */ -#define CONFIG_SYS_CS1_CFG 0x00011000 -#define CONFIG_SYS_CS1_START 0xE0000000 -#define CONFIG_SYS_CS1_SIZE 0x00010000 -/* CS2 AS-i 1 */ -#define CONFIG_SYS_CS2_CFG 0x00009100 -#define CONFIG_SYS_CS2_START 0xE0100000 -#define CONFIG_SYS_CS2_SIZE 0x00080000 -/* CS3 netX */ -#define CONFIG_SYS_CS3_CFG 0x000A1140 -#define CONFIG_SYS_CS3_START 0xE0300000 -#define CONFIG_SYS_CS3_SIZE 0x00020000 -/* CS5 safety */ -#define CONFIG_SYS_CS5_CFG 0x0011F000 -#define CONFIG_SYS_CS5_START 0xE0400000 -#define CONFIG_SYS_CS5_SIZE 0x00010000 -/* CS6 AS-i 2 */ -#define CONFIG_SYS_CS6_CFG 0x00009100 -#define CONFIG_SYS_CS6_START 0xE0200000 -#define CONFIG_SYS_CS6_SIZE 0x00080000 - -/* Don't use alternative CS timing for any CS */ -#define CONFIG_SYS_CS_ALETIMING 0x00000000 -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x00000020 -#define CONFIG_SYS_CS_HOLDCYCLE 0x00000020 - -/* Use SRAM for initial stack */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) - -#ifdef CONFIG_FSL_DIU_FB -#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) -#else -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) -#endif - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */ -#define CONFIG_SYS_PSC3 -#if CONFIG_PSC_CONSOLE != 3 -#error CONFIG_PSC_CONSOLE must be 3 -#endif - -#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE -#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR -#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE -#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR - -/* - * Clocks in use - */ -#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ - CLOCK_SCCR1_LPC_EN | \ - CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ - CLOCK_SCCR1_PSC_EN(7) | \ - CLOCK_SCCR1_PSCFIFO_EN | \ - CLOCK_SCCR1_DDR_EN | \ - CLOCK_SCCR1_FEC_EN | \ - CLOCK_SCCR1_TPR_EN) - -#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ - CLOCK_SCCR2_SPDIF_EN | \ - CLOCK_SCCR2_DIU_EN | \ - CLOCK_SCCR2_I2C_EN) - -#define CONFIG_CMDLINE_EDITING 1 /* command line history */ - -/* - * IIM - IC Identification Module - */ -#undef CONFIG_FSL_IIM - -/* - * Ethernet configuration - */ -#define CONFIG_MPC512x_FEC 1 -#define CONFIG_PHY_ADDR 0x1F -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_FEC_AN_TIMEOUT 1 -#define CONFIG_HAS_ETH0 - -/* - * Environment - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -/* This has to be a multiple of the flash sector size */ -#define CONFIG_ENV_ADDR 0xFFF40000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_LOADS_ECHO 1 -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 - -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_PCI -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -#ifdef CONFIG_CMD_KGDB -# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 32 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* Cache Configuration */ -#define CONFIG_SYS_DCACHE_SIZE 32768 -#define CONFIG_SYS_CACHELINE_SIZE 32 -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of 32 */ -#endif - -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ICE) -#define CONFIG_SYS_HID2 HID2_HBE - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_TIMESTAMP - -/* default load addr for tftp and bootm */ -#define CONFIG_LOADADDR 400000 - - -/* the builtin environment and standard greeting */ -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#define CONFIG_EXTRA_ENV_SETTINGS_DEVEL \ - "muster_nr=-00\0" \ - "fromram=run ramargs addip addtty; " \ - "tftp ${fdt_addr_r} ac14xx/ac14xx.dtb${muster_nr}; " \ - "tftp ${kernel_addr_r} ac14xx/uImage${muster_nr}; " \ - "tftp ${ramdisk_addr_r} ac14xx/uFS${muster_nr}; " \ - "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \ - "fromnfs=run nfsargs addip addtty; " \ - "tftp ${fdt_addr_r} ac14xx/ac14xx.dtb${muster_nr}; " \ - "tftp ${kernel_addr_r} ac14xx/uImage${muster_nr}; " \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "fromflash=run nfsargs addip addtty; " \ - "bootm fc020000 - fc000000\0" \ - "mtdargsrec=setenv bootargs root=/dev/mtdblock1 ro\0" \ - "recovery=run mtdargsrec addip addtty; " \ - "bootm ffd20000 - ffee0000\0" \ - "production=run ramargs addip addtty; " \ - "bootm fc020000 fc400000 fc000000\0" \ - "mtdargs=setenv bootargs root=/dev/mtdblock1 ro\0" \ - "prodmtd=run mtdargs addip addtty; " \ - "bootm fc020000 - fc000000\0" \ - "" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "u-boot_addr_r=200000\0" \ - "kernel_addr_r=600000\0" \ - "fdt_addr_r=a00000\0" \ - "ramdisk_addr_r=b00000\0" \ - "u-boot_addr=FFF00000\0" \ - "kernel_addr=FC020000\0" \ - "fdt_addr=FC000000\0" \ - "ramdisk_addr=FC400000\0" \ - "verify=n\0" \ - "ramdiskfile=ac14xx/uRamdisk\0" \ - "u-boot=ac14xx/u-boot.bin\0" \ - "bootfile=ac14xx/uImage\0" \ - "fdtfile=ac14xx/ac14xx.dtb\0" \ - "netdev=eth0\0" \ - "consdev=ttyPSC0\0" \ - "hostname=ac14xx\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}${muster_nr}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} " \ - "console=${consdev},${baudrate}\0" \ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${fdt_addr_r} ${fdtfile};" \ - "run nfsargs addip addtty;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "net_self=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ - "tftp ${fdt_addr_r} ${fdtfile};" \ - "run ramargs addip addtty;" \ - "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ - "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ - "update=protect off ${u-boot_addr} +${filesize};" \ - "era ${u-boot_addr} +${filesize};" \ - "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ - CONFIG_EXTRA_ENV_SETTINGS_DEVEL \ - "upd=run load update\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run production" - -#define CONFIG_ARP_TIMEOUT 200UL - -#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1 - -#define OF_CPU "PowerPC,5121@0" -#define OF_SOC_COMPAT "fsl,mpc5121-immr" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc@80000000/serial@11300" - -#endif /* __CONFIG_H */ diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index b379e0839d..7a42d79647 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -13,6 +13,7 @@ #define __CONFIG_AM57XX_EVM_H #include <environment/ti/dfu.h> +#include <linux/sizes.h> #ifdef CONFIG_SPL_BUILD #define CONFIG_IODELAY_RECALIBRATION @@ -20,11 +21,14 @@ #define CONFIG_NR_DRAM_BANKS 2 -#define CONFIG_ENV_SIZE (64 << 10) -#define CONFIG_ENV_IS_IN_FAT -#define FAT_ENV_INTERFACE "mmc" -#define FAT_ENV_DEVICE_AND_PART "0:1" -#define FAT_ENV_FILE "uboot.env" +/* MMC ENV related defines */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 /* eMMC */ +#define CONFIG_SYS_MMC_ENV_PART 0 +#define CONFIG_ENV_SIZE SZ_128K +#define CONFIG_ENV_OFFSET 0x260000 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONSOLEDEV "ttyO2" #define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ @@ -46,7 +50,7 @@ "partitions_android=" \ "uuid_disk=${uuid_gpt_disk};" \ "name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \ - "name=bootloader,size=768K,uuid=${uuid_gpt_bootloader};" \ + "name=bootloader,size=1792K,uuid=${uuid_gpt_bootloader};" \ "name=environment,size=128K,uuid=${uuid_gpt_environment};" \ "name=misc,size=128K,uuid=${uuid_gpt_misc};" \ "name=reserved,size=256K,uuid=${uuid_gpt_reserved};" \ diff --git a/include/configs/aria.h b/include/configs/aria.h deleted file mode 100644 index 0a7ef9919e..0000000000 --- a/include/configs/aria.h +++ /dev/null @@ -1,591 +0,0 @@ -/* - * (C) Copyright 2009 Wolfgang Denk <wd@denx.de> - * (C) Copyright 2009, DAVE Srl <www.dave.eu> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Aria board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_ARIA 1 - -/* - * Memory map for the ARIA board: - * - * 0x0000_0000-0x0FFF_FFFF DDR RAM (256 MB) - * 0x3000_0000-0x3001_FFFF On Chip SRAM (128 KB) - * 0x3010_0000-0x3011_FFFF On Board SRAM (128 KB) - CS6 - * 0x3020_0000-0x3021_FFFF FPGA (128 KB) - CS2 - * 0x8000_0000-0x803F_FFFF IMMR (4 MB) - * 0x8400_0000-0x82FF_FFFF PCI I/O space (16 MB) - * 0xA000_0000-0xAFFF_FFFF PCI memory space (256 MB) - * 0xB000_0000-0xBFFF_FFFF PCI memory mapped I/O space (256 MB) - * 0xFC00_0000-0xFFFF_FFFF NOR Boot FLASH (64 MB) - */ - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -/* video */ - -/* CONFIG_PCI is defined at config time */ - -#define CONFIG_SYS_MPC512X_CLKIN 33000000 /* in Hz */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_SYS_IMMR 0x80000000 -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100) - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * DDR Setup - manually set all parameters as there's no SPD etc. - */ -#define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#define CONFIG_SYS_DDR_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 - -#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036 - -/* DDR Controller Configuration - * - * SYS_CFG: - * [31:31] MDDRC Soft Reset: Diabled - * [30:30] DRAM CKE pin: Enabled - * [29:29] DRAM CLK: Enabled - * [28:28] Command Mode: Enabled (For initialization only) - * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] - * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] - * [20:19] Read Test: DON'T USE - * [18:18] Self Refresh: Enabled - * [17:17] 16bit Mode: Disabled - * [16:13] Ready Delay: 2 - * [12:12] Half DQS Delay: Disabled - * [11:11] Quarter DQS Delay: Disabled - * [10:08] Write Delay: 2 - * [07:07] Early ODT: Disabled - * [06:06] On DIE Termination: Disabled - * [05:05] FIFO Overflow Clear: DON'T USE here - * [04:04] FIFO Underflow Clear: DON'T USE here - * [03:03] FIFO Overflow Pending: DON'T USE here - * [02:02] FIFO Underlfow Pending: DON'T USE here - * [01:01] FIFO Overlfow Enabled: Enabled - * [00:00] FIFO Underflow Enabled: Enabled - * TIME_CFG0 - * [31:16] DRAM Refresh Time: 0 CSB clocks - * [15:8] DRAM Command Time: 0 CSB clocks - * [07:00] DRAM Precharge Time: 0 CSB clocks - * TIME_CFG1 - * [31:26] DRAM tRFC: - * [25:21] DRAM tWR1: - * [20:17] DRAM tWRT1: - * [16:11] DRAM tDRR: - * [10:05] DRAM tRC: - * [04:00] DRAM tRAS: - * TIME_CFG2 - * [31:28] DRAM tRCD: - * [27:23] DRAM tFAW: - * [22:19] DRAM tRTW1: - * [18:15] DRAM tCCD: - * [14:10] DRAM tRTP: - * [09:05] DRAM tRP: - * [04:00] DRAM tRPA - */ -#define CONFIG_SYS_MDDRC_SYS_CFG ( (1 << 31) | /* RST_B */ \ - (1 << 30) | /* CKE */ \ - (1 << 29) | /* CLK_ON */ \ - (0 << 28) | /* CMD_MODE */ \ - (4 << 25) | /* DRAM_ROW_SELECT */ \ - (3 << 21) | /* DRAM_BANK_SELECT */ \ - (0 << 18) | /* SELF_REF_EN */ \ - (0 << 17) | /* 16BIT_MODE */ \ - (2 << 13) | /* RDLY */ \ - (0 << 12) | /* HALF_DQS_DLY */ \ - (1 << 11) | /* QUART_DQS_DLY */ \ - (2 << 8) | /* WDLY */ \ - (0 << 7) | /* EARLY_ODT */ \ - (1 << 6) | /* ON_DIE_TERMINATE */ \ - (0 << 5) | /* FIFO_OV_CLEAR */ \ - (0 << 4) | /* FIFO_UV_CLEAR */ \ - (0 << 1) | /* FIFO_OV_EN */ \ - (0 << 0) /* FIFO_UV_EN */ \ - ) - -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E -#define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189 -#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863 - -#define CONFIG_SYS_DDRCMD_NOP 0x01380000 -#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 -#define CONFIG_SYS_MICRON_EMR ( (1 << 24) | /* CMD_REQ */ \ - (0 << 22) | /* DRAM_CS */ \ - (0 << 21) | /* DRAM_RAS */ \ - (0 << 20) | /* DRAM_CAS */ \ - (0 << 19) | /* DRAM_WEB */ \ - (1 << 16) | /* DRAM_BS[2:0] */ \ - (0 << 15) | /* */ \ - (0 << 12) | /* A12->out */ \ - (0 << 11) | /* A11->RDQS */ \ - (0 << 10) | /* A10->DQS# */ \ - (0 << 7) | /* OCD program */ \ - (0 << 6) | /* Rtt1 */ \ - (0 << 3) | /* posted CAS# */ \ - (0 << 2) | /* Rtt0 */ \ - (1 << 1) | /* ODS */ \ - (0 << 0) /* DLL */ \ - ) -#define CONFIG_SYS_MICRON_EMR2 0x01020000 -#define CONFIG_SYS_MICRON_EMR3 0x01030000 -#define CONFIG_SYS_DDRCMD_RFSH 0x01080000 -#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_MICRON_EMR_OCD ( (1 << 24) | /* CMD_REQ */ \ - (0 << 22) | /* DRAM_CS */ \ - (0 << 21) | /* DRAM_RAS */ \ - (0 << 20) | /* DRAM_CAS */ \ - (0 << 19) | /* DRAM_WEB */ \ - (1 << 16) | /* DRAM_BS[2:0] */ \ - (0 << 15) | /* */ \ - (0 << 12) | /* A12->out */ \ - (0 << 11) | /* A11->RDQS */ \ - (1 << 10) | /* A10->DQS# */ \ - (7 << 7) | /* OCD program */ \ - (0 << 6) | /* Rtt1 */ \ - (0 << 3) | /* posted CAS# */ \ - (1 << 2) | /* Rtt0 */ \ - (0 << 1) | /* ODS (Output Drive Strength) */ \ - (0 << 0) /* DLL */ \ - ) - -/* - * Backward compatible definitions, - * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c - */ -#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2) -#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3) -#define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR) -#define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD) - -/* DDR Priority Manager Configuration */ -#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 -#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 -#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 -#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC -#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA -#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 -#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 -#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 - -/* - * NOR FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_CFI /* use the CFI code */ -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ -#define CONFIG_SYS_FLASH_BASE 0xF8000000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 0x08000000 /* max flash size */ - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max sectors */ - -#undef CONFIG_SYS_FLASH_CHECKSUM - -/* - * NAND FLASH support - * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only) - */ -#define CONFIG_CMD_NAND /* enable NAND support */ -#define CONFIG_JFFS2_NAND /* with JFFS2 on it */ -#define CONFIG_NAND_MPC5121_NFC -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -/* - * Configuration parameters for MPC5121 NAND driver - */ -#define CONFIG_FSL_NFC_WIDTH 1 -#define CONFIG_FSL_NFC_WRITE_SIZE 2048 -#define CONFIG_FSL_NFC_SPARE_SIZE 64 -#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE - -#define CONFIG_SYS_SRAM_BASE 0x30000000 -#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ - -/* Make two SRAM regions contiguous */ -#define CONFIG_SYS_ARIA_SRAM_BASE (CONFIG_SYS_SRAM_BASE + \ - CONFIG_SYS_SRAM_SIZE) -#define CONFIG_SYS_ARIA_SRAM_SIZE 0x00100000 /* reserve 1MB-window */ -#define CONFIG_SYS_CS6_START CONFIG_SYS_ARIA_SRAM_BASE -#define CONFIG_SYS_CS6_SIZE CONFIG_SYS_ARIA_SRAM_SIZE - -#define CONFIG_SYS_ARIA_FPGA_BASE (CONFIG_SYS_ARIA_SRAM_BASE + \ - CONFIG_SYS_ARIA_SRAM_SIZE) -#define CONFIG_SYS_ARIA_FPGA_SIZE 0x20000 /* 128 KB */ - -#define CONFIG_SYS_CS2_START CONFIG_SYS_ARIA_FPGA_BASE -#define CONFIG_SYS_CS2_SIZE CONFIG_SYS_ARIA_FPGA_SIZE - -#define CONFIG_SYS_CS0_CFG 0x05059150 -#define CONFIG_SYS_CS2_CFG ( (5 << 24) | \ - (5 << 16) | \ - (1 << 15) | \ - (0 << 14) | \ - (0 << 13) | \ - (1 << 12) | \ - (0 << 10) | \ - (3 << 8) | /* 32 bit */ \ - (0 << 7) | \ - (1 << 6) | \ - (1 << 4) | \ - (0 << 3) | \ - (0 << 2) | \ - (0 << 1) | \ - (0 << 0) \ - ) -#define CONFIG_SYS_CS6_CFG 0x05059150 - -/* Use alternative CS timing for CS0 and CS2 */ -#define CONFIG_SYS_CS_ALETIMING 0x00000005 - -/* Use SRAM for initial stack */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) - -#ifdef CONFIG_FSL_DIU_FB -#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) -#else -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) -#endif - -/* FPGA */ -#define CONFIG_ARIA_FPGA 1 - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */ -#define CONFIG_SYS_PSC3 -#if CONFIG_PSC_CONSOLE != 3 -#error CONFIG_PSC_CONSOLE must be 3 -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE -#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR -#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE -#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR - -#define CONFIG_CMDLINE_EDITING 1 /* command line history */ - -/* - * PCI - */ -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE - -#define CONFIG_SYS_PCI_MEM_BASE 0xA0000000 -#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + \ - CONFIG_SYS_PCI_MEM_SIZE) -#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE -#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI_IO_PHYS 0x84000000 -#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */ - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#endif - -/* - * IIM - IC Identification Module - */ -#undef CONFIG_FSL_IIM - -/* - * Ethernet configuration - */ -#define CONFIG_MPC512x_FEC 1 -#define CONFIG_PHY_ADDR 0x17 -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_FEC_AN_TIMEOUT 1 -#define CONFIG_HAS_ETH0 - -/* - * Environment - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -/* This has to be a multiple of the flash sector size */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_LOADS_ECHO 1 -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 - -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_PCI -#endif - -/* - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=f8000000.flash,nand0=mpc5121.nand" - -/* - * NOR flash layout: - * - * F8000000 - FEAFFFFF 107 MiB User Data - * FEB00000 - FFAFFFFF 16 MiB Root File System - * FFB00000 - FFFEFFFF 4 MiB Linux Kernel - * FFF00000 - FFFBFFFF 768 KiB U-Boot (up to 512 KiB) and 2 x * env - * FFFC0000 - FFFFFFFF 256 KiB Device Tree - * - * NAND flash layout: one big partition - */ -#define MTDPARTS_DEFAULT "mtdparts=f8000000.flash:107m(user)," \ - "16m(rootfs)," \ - "4m(kernel)," \ - "768k(u-boot)," \ - "256k(dtb);" \ - "mpc5121.nand:-(data)" - -/* - * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. - * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE - * is set to 0xFFFF, watchdog timeouts after about 64s. For details - * refer to chapter 36 of the MPC5121e Reference Manual. - */ -/* #define CONFIG_WATCHDOG */ /* enable watchdog */ -#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF - - /* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -#ifdef CONFIG_CMD_KGDB -# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 32 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) - -/* Cache Configuration */ -#define CONFIG_SYS_DCACHE_SIZE 32768 -#define CONFIG_SYS_CACHELINE_SIZE 32 -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of 32 */ -#endif - -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ICE) -#define CONFIG_SYS_HID2 HID2_HBE - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_TIMESTAMP - -#define CONFIG_HOSTNAME aria -#define CONFIG_BOOTFILE "aria/uImage" -#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx" - -#define CONFIG_LOADADDR 400000 /* default load addr */ - -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "u-boot_addr_r=200000\0" \ - "kernel_addr_r=600000\0" \ - "fdt_addr_r=880000\0" \ - "ramdisk_addr_r=900000\0" \ - "u-boot_addr=FFF00000\0" \ - "kernel_addr=FFB00000\0" \ - "fdt_addr=FFFC0000\0" \ - "ramdisk_addr=FEB00000\0" \ - "ramdiskfile=aria/uRamdisk\0" \ - "u-boot=aria/u-boot.bin\0" \ - "fdtfile=aria/aria.dtb\0" \ - "netdev=eth0\0" \ - "consdev=ttyPSC0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} " \ - "console=${consdev},${baudrate}\0" \ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${fdt_addr_r} ${fdtfile};" \ - "run nfsargs addip addtty;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "net_self=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ - "tftp ${fdt_addr_r} ${fdtfile};" \ - "run ramargs addip addtty;" \ - "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ - "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ - "update=protect off ${u-boot_addr} +${filesize};" \ - "era ${u-boot_addr} +${filesize};" \ - "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ - "upd=run load update\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1 - -#define OF_CPU "PowerPC,5121@0" -#define OF_SOC_COMPAT "fsl,mpc5121-immr" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc@80000000/serial@11300" - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for IDE not supported */ - -#define CONFIG_IDE_RESET /* reset for IDE supported */ -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_BASE_ADDR get_pata_base() - -/* Offset for data I/O RefMan MPC5121EE Table 28-10 */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers RefMan MPC5121EE Table 28-23 */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#define ATA_BASE_ADDR get_pata_base() - -/* - * Control register bit definitions - */ -#define FSL_ATA_CTRL_FIFO_RST_B 0x80000000 -#define FSL_ATA_CTRL_ATA_RST_B 0x40000000 -#define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000 -#define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000 -#define FSL_ATA_CTRL_DMA_PENDING 0x08000000 -#define FSL_ATA_CTRL_DMA_ULTRA 0x04000000 -#define FSL_ATA_CTRL_DMA_WRITE 0x02000000 -#define FSL_ATA_CTRL_IORDY_EN 0x01000000 - -/* Clocks in use */ -#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ - CLOCK_SCCR1_LPC_EN | \ - CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ - CLOCK_SCCR1_PSCFIFO_EN | \ - CLOCK_SCCR1_DDR_EN | \ - CLOCK_SCCR1_FEC_EN | \ - CLOCK_SCCR1_NFC_EN | \ - CLOCK_SCCR1_PATA_EN | \ - CLOCK_SCCR1_PCI_EN | \ - CLOCK_SCCR1_TPR_EN) - -#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ - CLOCK_SCCR2_SPDIF_EN | \ - CLOCK_SCCR2_DIU_EN | \ - CLOCK_SCCR2_I2C_EN) - -#endif /* __CONFIG_H */ diff --git a/include/configs/brxre1.h b/include/configs/brxre1.h index 5814d748d9..f7d736939b 100644 --- a/include/configs/brxre1.h +++ b/include/configs/brxre1.h @@ -16,14 +16,8 @@ #include <configs/bur_am335x_common.h> /* ------------------------------------------------------------------------- */ #define CONFIG_AM335X_LCD -#define CONFIG_LCD_NOSTDOUT #define LCD_BPP LCD_COLOR32 -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1366*767*4) -#define CONFIG_BMP_24BPP -#define CONFIG_BMP_32BPP - /* memory */ #define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) @@ -37,8 +31,6 @@ /* I2C IP block */ #define CONFIG_SYS_OMAP24_I2C_SPEED_PSOC 20000 -/* GPIO */ - /* MMC/SD IP block */ #define CONFIG_SUPPORT_EMMC_BOOT @@ -46,51 +38,36 @@ #define CONFIG_ENV_SIZE (64 << 10) #ifndef CONFIG_SPL_BUILD -#define CONFIG_EXTRA_ENV_SETTINGS \ + +/* Default environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ BUR_COMMON_ENV \ +"autoload=0\0" \ +"scradr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "bootaddr=0x80001100\0" \ "bootdev=cpsw(0,0)\0" \ "vx_romfsbase=0x800E0000\0" \ "vx_romfssize=0x20000\0" \ "vx_memtop=0x8FBEF000\0" \ "loadromfs=mmc read ${vx_romfsbase} 700 100\0" \ -"autoload=0\0" \ "loadaddr=0x80100000\0" \ -"logoaddr=0x82000000\0" \ -"defaultARlen=0x8000\0" \ -"loaddefaultAR=mmc read ${loadaddr} 800 ${defaultARlen}\0" \ -"defaultAR=run loadromfs; run loaddefaultAR; bootvx ${loadaddr}\0" \ -"logo0=fatload mmc 0:1 ${logoaddr} SYSTEM/ADDON/Bootlogo/Bootlogo.bmp.gz && " \ - "bmp display ${logoaddr} 0 0\0" \ -"logo1=fatload mmc 0:1 ${logoaddr} SYSTEM/BASE/Bootlogo/Bootlogo.bmp.gz && " \ - "bmp display ${logoaddr} 0 0\0" \ -"mmcboot=echo booting AR from eMMC-flash ...; "\ - "run logo0 || run logo1; " \ - "run loadromfs; " \ - "fatload mmc 0:1 ${loadaddr} arimg && bootvx ${loadaddr}; " \ - "run defaultAR;\0" \ -"netboot=echo booting AR from network ...; " \ - "run loadromfs; " \ - "tftp ${loadaddr} arimg && bootvx ${loadaddr}; " \ - "puts 'networkboot failed!';\0" \ -"netscript=echo running script from network (tftp) ...; " \ - "tftp 0x80000000 netscript.img && source; " \ - "puts 'netscript load failed!'\0" \ -"netupdate=tftp ${loadddr} MLO && mmc write ${loadaddr} 100 100; " \ - "tftp ${loadaddr} u-boot.img && mmc write ${loadaddr} 300 300\0" \ -"netupdatedefaultAR=echo updating defaultAR from network (tftp) ...; " \ - "if tftp 0x80100000 arimg.bin; " \ - "then mmc write 0x80100000 800 ${defaultARlen}; " \ - "else setcurs 1 8; puts 'defAR update failed (tftp)!'; fi;\0" \ -"netupdateROMFS=echo updating romfs from network (tftp) ...; " \ - "if tftp 0x80100000 romfs.bin; " \ - "then mmc write 0x80100000 700 100; " \ - "else setcurs 1 8; puts 'romfs update failed (tftp)!'; fi;\0" - +"startvx=run loadromfs; bootvx ${loadaddr}\0" \ +"b_break=0\0" \ +"b_tgts_std=mmc def net usb0\0" \ +"b_tgts_rcy=def net usb0\0" \ +"b_tgts_pme=net usb0 mmc\0" \ +"b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \ +" elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \ +" else setenv b_tgts ${b_tgts_std}; fi\0" \ +"b_mmc=load mmc 1 ${loadaddr} arimg && run startvx\0" \ +"b_def=mmc read ${loadaddr} 800 8000; run startvx\0" \ +"b_net=tftp ${scradr} netscript.img && source ${scradr}\0" \ +"b_usb0=usb start && load usb 0 ${scradr} usbscript.img && source ${scradr}\0" \ +"b_default=run b_deftgts; for target in ${b_tgts};"\ +" do run b_${target}; if test ${b_break} = 1; then; exit; fi; done\0" #endif /* !CONFIG_SPL_BUILD*/ -#define CONFIG_BOOTCOMMAND \ - "run usbscript;" +#define CONFIG_BOOTCOMMAND "mmc dev 1; run b_default" /* undefine command which we not need here */ #undef CONFIG_BOOTM_NETBSD @@ -113,7 +90,7 @@ BUR_COMMON_ENV \ #undef CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_DEV 1 #define CONFIG_SYS_MMC_ENV_PART 2 #define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 7907310084..8d0e0ea793 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -12,7 +12,6 @@ #ifndef __BUR_AM335X_COMMON_H__ #define __BUR_AM335X_COMMON_H__ /* ------------------------------------------------------------------------- */ -#define CONFIG_AM33XX #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ /* Timer information */ diff --git a/include/configs/calimain.h b/include/configs/calimain.h index 29d3bdacac..d43e3314a7 100644 --- a/include/configs/calimain.h +++ b/include/configs/calimain.h @@ -316,4 +316,6 @@ int calimain_get_osc_freq(void); #endif +#include <asm/arch/hardware.h> + #endif /* __CONFIG_H */ diff --git a/include/configs/canmb.h b/include/configs/canmb.h deleted file mode 100644 index b7c74b4264..0000000000 --- a/include/configs/canmb.h +++ /dev/null @@ -1,199 +0,0 @@ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ -#define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */ - -/* - * allowed and functional CONFIG_SYS_TEXT_BASE values: - * 0xfe000000 low boot at 0x00000100 (default board setting) - * 0x00100000 RAM load and test - */ -#define CONFIG_SYS_TEXT_BASE 0xFE000000 - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_BOARD_EARLY_INIT_R - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_REGINFO - -/* - * MUST be low boot - HIGHBOOT is not supported anymore - */ -#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */ -# define CONFIG_SYS_LOWBOOT 1 -# define CONFIG_SYS_LOWBOOT16 1 -#else -# error "CONFIG_SYS_TEXT_BASE must be 0xFE000000" -#endif - -/* - * Autobooting - */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=/tftpboot/canmb/uImage\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* - * IPB Bus clocking configuration. - */ -#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/* - * Flash configuration, expect one 16 Megabyte Bank at most - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_SIZE 0x02000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET (2*128*1024) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE (128*1024) - -/* - * Memory map - * - * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000 - */ -#define CONFIG_SYS_MBAR 0xf0000000 /* DO NOT CHANGE this */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x0 -/* - * GPIO configuration: - * PSC1,2,3 predefined as UART - * PCI disabled - * Ethernet 100 with MD - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x00058444 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ - -#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00047D01 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -#define CONFIG_SYS_RESET_ADDRESS 0x7f000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/charon.h b/include/configs/charon.h deleted file mode 100644 index 913b707a5f..0000000000 --- a/include/configs/charon.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2006 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * (C) Copyright 2010 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_CHARON_H -#define __CONFIG_CHARON_H - -#define CONFIG_CHARON -#define CONFIG_HOSTNAME charon - -#define CONFIG_SYS_GPS_PORT_CONFIG 0x81550414 - -/* include common defines/options for TQM52xx boards */ -#include "TQM5200.h" - -/* defines special on charon board */ -#undef CONFIG_RTC_MPC5200 - -#undef CUSTOM_ENV_SETTINGS -#define CUSTOM_ENV_SETTINGS \ - "bootfile=/tftpboot/charon/uImage\0" \ - "fdt_file=/tftpboot/charon/charon.dtb\0" \ - "u-boot=/tftpboot/charon/u-boot.bin\0" \ - "mtdparts=" MTDPARTS_DEFAULT "\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" - -/* additional features on charon board */ -#define CONFIG_RESET_PHY_R - -/* - * I2C configuration - */ -#define CONFIG_I2C_MULTI_BUS - -#define CONFIG_SYS_TFP410_ADDR 0x38 -#define CONFIG_SYS_TFP410_BUS 0 - -/* - * FPGA configuration - */ -#define CONFIG_SYS_CS3_START 0xE8000000 -#define CONFIG_SYS_CS3_SIZE 0x80000 /* 512 KByte */ - -/* - * CS3 Config Register Init: - * CS3 Enabled - * AddrBus: 8bits - * DataBus: 4bytes - * Multiplexed: Yes - * MuxBank: 00 - */ -#define CONFIG_SYS_CS3_CFG 0x00009310 - -#endif /* __CONFIG_CHARON_H */ diff --git a/include/configs/cl-som-am57x.h b/include/configs/cl-som-am57x.h index 96e5c9cdd5..a04f4cd23d 100644 --- a/include/configs/cl-som-am57x.h +++ b/include/configs/cl-som-am57x.h @@ -42,9 +42,9 @@ #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD -/* SD/MMC RAW boot */ -#undef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME -#undef CONFIG_SYS_MMCSD_FS_BOOT_PARTITION +/* SD/MMC RAW/FS boot */ +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 /* Environment */ #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB env size */ @@ -128,8 +128,10 @@ "bootkernel=bootz ${loadaddr} - ${fdtaddr}\0" \ "mmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \ "mmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \ + "emmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \ + "emmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \ "load_mmc=mmc dev ${mmcdev} && mmc rescan && " \ - "run mmcloadkernel run mmcloadfdt\0" \ + "run mmcloadkernel && run mmcloadfdt\0" \ "mmcroot=/dev/mmcblk1p2\0" \ "mmcrootfstype=ext4 rw rootwait\0" \ "mmcargs=setenv bootargs console=${console} root=${mmcroot} " \ @@ -165,7 +167,7 @@ "source ${loadaddr}\0" \ "sataboot=run load_sata && run sataargs && " \ "echo Booting from SATA ... && " \ - "run bootkernel\0" \ + "run bootkernel\0" #undef CONFIG_BOOTCOMMAND #define CONFIG_BOOTCOMMAND \ diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h deleted file mode 100644 index 3777a0d863..0000000000 --- a/include/configs/cm5200.h +++ /dev/null @@ -1,286 +0,0 @@ -/* - * (C) Copyright 2003-2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_CM5200 1 /* ... on CM5200 platform */ - -#define CONFIG_SYS_TEXT_BASE 0xfc000000 - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Supported commands - */ -#define CONFIG_CMD_REGINFO - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_ENV_OVERWRITE 1 /* allow overwriting of ethaddr */ -/* use misc_init_r() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */ -#define CONFIG_MISC_INIT_R 1 -#define CONFIG_MAC_OFFSET 0x35 /* MAC address offset in I2C EEPROM */ - -/* - * POST support - */ -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_CPU) -#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4) -/* List of I2C addresses to be verified by POST */ -#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_SLAVE, \ - CONFIG_SYS_I2C_IO, \ - CONFIG_SYS_I2C_EEPROM} - -/* display image timestamps */ -#define CONFIG_TIMESTAMP 1 - -/* - * Autobooting - */ -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \ - "echo" -#undef CONFIG_BOOTARGS - -/* - * Default environment settings - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "netmask=255.255.0.0\0" \ - "ipaddr=192.168.160.33\0" \ - "serverip=192.168.1.1\0" \ - "gatewayip=192.168.1.1\0" \ - "console=ttyPSC0\0" \ - "u-boot_addr=100000\0" \ - "kernel_addr=200000\0" \ - "kernel_addr_flash=fc0c0000\0" \ - "fdt_addr=400000\0" \ - "fdt_addr_flash=fc0a0000\0" \ - "ramdisk_addr=500000\0" \ - "rootpath=/opt/eldk-4.1/ppc_6xx\0" \ - "u-boot=/tftpboot/cm5200/u-boot.bin\0" \ - "bootfile_fdt=/tftpboot/cm5200/uImage\0" \ - "fdt_file=/tftpboot/cm5200/cm5200.dtb\0" \ - "load=tftp ${u-boot_addr} ${u-boot}\0" \ - "update=prot off fc000000 +${filesize}; " \ - "era fc000000 +${filesize}; " \ - "cp.b ${u-boot_addr} fc000000 ${filesize}; " \ - "prot on fc000000 +${filesize}\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "flashargs=setenv bootargs root=/dev/mtdblock5 rw\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addinit=setenv bootargs ${bootargs} init=/linuxrc\0" \ - "addcons=setenv bootargs ${bootargs} " \ - "console=${console},${baudrate}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off panic=1\0" \ - "flash_flash=run flashargs addinit addip addcons;" \ - "bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0" \ - "net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; " \ - "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip " \ - "addcons; bootm ${kernel_addr} - ${fdt_addr}\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_flash" - -/* - * Low level configuration - */ - -/* - * Clock configuration - */ -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* SYS_XTAL_IN = 33MHz */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK 1 /* IPB = 133MHz */ - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -#define CONFIG_SYS_LOWBOOT 1 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE -#else -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE -#endif - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_BOARD_TYPES 1 /* we use board_type */ - -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */ - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_BASE 0xfc000000 -/* we need these despite using CFI */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sectors on one chip */ -#define CONFIG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT 1 -#undef CONFIG_SYS_LOWBOOT -#endif - -/* - * Chip selects configuration - */ -/* Boot Chipselect */ -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00087D31 /* for pci_clk = 33 MHz */ -/* use board_early_init_r to enable flash write in CS_BOOT */ -#define CONFIG_BOARD_EARLY_INIT_R - -/* Flash memory addressing */ -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -/* No burst, dead cycle = 1 for CS0 (Flash) */ -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x00000001 - -/* - * SDRAM configuration - * settings for k4s561632E-xx75, assuming XLB = 132 MHz - */ -#define SDRAM_MODE 0x00CD0000 /* CASL 3, burst length 8 */ -#define SDRAM_CONTROL 0x514F0000 -#define SDRAM_CONFIG1 0xE2333900 -#define SDRAM_CONFIG2 0x8EE70000 - -/* - * MTD configuration - */ -#define CONFIG_CMD_MTDPARTS 1 -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=cm5200-0" -#define MTDPARTS_DEFAULT "mtdparts=cm5200-0:" \ - "384k(uboot),128k(env)," \ - "128k(redund_env),128k(dtb)," \ - "2m(kernel),27904k(rootfs)," \ - "-(config)" - -/* - * RTC configuration - */ -#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ - -/* - * USB configuration - */ -#define CONFIG_USB_OHCI 1 -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 -/* Partitions (for USB) */ - -/* - * Invoke our last_stage_init function - needed by fwupdate - */ -#define CONFIG_LAST_STAGE_INIT 1 - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) -/* Configuration of redundant environment */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/* - * Pin multiplexing configuration - */ - -/* - * CS1/GPIO_WKUP_6: GPIO (default) - * ALTs: CAN1 on I2C1, CAN2 on TIMER0/1 - * IRDA/PSC6: UART - * Ether: Ethernet 100Mbit with MD - * PCI_DIS: PCI controller disabled - * USB: USB - * PSC3: SPI with UART3 - * PSC2: UART - * PSC1: UART - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x10559C44 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_ALT_MEMTEST 1 -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x03f00000 /* 1 .. 63 MiB in SDRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_XLB_PIPELINING 1 /* enable transaction pipeling */ - -/* - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Flat Device Tree support - */ -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" - -#endif /* __CONFIG_H */ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 1e63098d5f..7b5ca0db0f 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -9,7 +9,6 @@ #ifndef __CONFIG_CM_T43_H #define __CONFIG_CM_T43_H -#define CONFIG_AM43XX #define CONFIG_CM_T43 #define CONFIG_ARCH_CPU_INIT #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */ @@ -21,7 +20,7 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 48000000 #define CONFIG_SYS_NS16550_COM1 0x44e09000 -#ifdef CONFIG_SPL_BUILD +#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL) #define CONFIG_SYS_NS16550_REG_SIZE (-4) #endif diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index f46f466196..b7199bb9e0 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -330,4 +330,7 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ GENERATED_GBL_DATA_SIZE) #endif /* CONFIG_DIRECT_NOR_BOOT */ + +#include <asm/arch/hardware.h> + #endif /* __CONFIG_H */ diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h deleted file mode 100644 index 6710507a8d..0000000000 --- a/include/configs/digsy_mtc.h +++ /dev/null @@ -1,410 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2005-2007 - * Modified for InterControl digsyMTC MPC5200 board by - * Frank Bodammer, GCD Hard- & Software GmbH, - * frank.bodammer@gcd-solutions.de - * - * (C) Copyright 2009 Semihalf - * Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFFF00000 boot high (standard configuration) - * 0xFE000000 boot low - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */ -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 - -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCI_BOOTDELAY 250 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_BZIP2 - -/* - * Video - */ - -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_MB862xx -#define CONFIG_VIDEO_MB862xx_ACCEL -#define CONFIG_VIDEO_CORALP -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_SPLASH_SCREEN -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ - -/* Coral-PA clock frequency, geo and other both 133MHz */ -#define CONFIG_SYS_MB862xx_CCF 0x00050000 -/* Video SDRAM parameters */ -#define CONFIG_SYS_MB862xx_MMR 0x11d7fa72 -#endif - -/* - * Command line configuration. - */ -#define CONFIG_CMD_PCI -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SAVES - -#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) -#define CONFIG_SYS_LOWBOOT 1 -#endif - -/* - * Autobooting - */ - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fw_image=digsyMPC.img\0" \ - "mtcb_start=mtc led diag orange; run mtcb_1\0" \ - "mtcb_clearled=for x in user1 user2 usbpwr usbbusy; " \ - "do mtc led $x; done\0" \ - "mtcb_1=if mtc key; then run mtcb_clearled mtcb_update; " \ - "else run mtcb_fw; fi\0" \ - "mtcb_fw=if bootm ff000000; then echo FIRMWARE OK!; " \ - "else echo BAD FIRMWARE CRC!; mtc led diag red; fi\0" \ - "mtcb_update=mtc led user1 orange;" \ - "while mtc key; do ; done; run mtcb_2;\0" \ - "mtcb_2=mtc led user1 green 2; usb reset; run mtcb_usb1;\0" \ - "mtcb_usb1=if fatload usb 0 400000 script.img; " \ - "then run mtcb_doscript; else run mtcb_usb2; fi\0" \ - "mtcb_usb2=if fatload usb 0 400000 $fw_image; " \ - "then run mtcb_dousb; else run mtcb_ide; fi\0" \ - "mtcb_doscript=run mtcb_usbleds; mtc led user2 orange 2; " \ - "run mtcb_wait_flickr mtcb_ds_1;\0" \ - "mtcb_ds_1=if imi 400000; then mtc led usbbusy; " \ - "source 400000; else run mtcb_error; fi\0" \ - "mtcb_dousb=run mtcb_usbleds mtcb_wait_flickr mtcb_du_1;\0" \ - "mtcb_du_1=if imi 400000; then run mtcb_du_2; " \ - "else run mtcb_error; fi\0" \ - "mtcb_du_2=run mtcb_clear mtcb_prog; mtc led usbbusy; " \ - "run mtcb_checkfw\0" \ - "mtcb_checkfw=if imi ff000000; then run mtcb_success; " \ - "else run mtcb_error; fi\0" \ - "mtcb_waitkey=mtc key; until test $? -eq 0; do mtc key; done\0" \ - "mtcb_wait_flickr=run mtcb_waitkey mtcb_uledflckr\0" \ - "mtcb_usbleds=mtc led usbpwr green; mtc led usbbusy orange 1;\0"\ - "mtcb_uledflckr=mtc led user1 orange 11\0" \ - "mtcb_error=mtc led user1 red\0" \ - "mtcb_clear=erase ff000000 ff0fffff\0" \ - "mtcb_prog=cp.b 400000 ff000000 ${filesize}\0" \ - "mtcb_success=mtc led user1 green\0" \ - "mtcb_ide=if fatload ide 0 400000 $fw_image;" \ - "then run mtcb_doide; else run mtcb_error; fi\0" \ - "mtcb_doide=mtc led user2 green 1;" \ - "run mtcb_wait_flickr mtcb_di_1;\0" \ - "mtcb_di_1=if imi 400000; then run mtcb_di_2;" \ - "else run mtcb_error; fi\0" \ - "mtcb_di_2=run mtcb_clear; run mtcb_prog mtcb_checkfw\0" \ - "ramdisk_num_sector=16\0" \ - "flash_base=ff000000\0" \ - "flashdisk_size=e00000\0" \ - "env_sector=fff60000\0" \ - "flashdisk_start=ff100000\0" \ - "load_cmd=tftp 400000 digsyMPC.img\0" \ - "clear_cmd=erase ff000000 ff0fffff\0" \ - "flash_cmd=cp.b 400000 ff000000 ${filesize}\0" \ - "update_cmd=run load_cmd; " \ - "iminfo 400000; " \ - "run clear_cmd flash_cmd; " \ - "iminfo ff000000\0" \ - "spi_driver=yes\0" \ - "spi_watchdog=no\0" \ - "ftps_start=yes\0" \ - "ftps_user1=admin\0" \ - "ftps_pass1=admin\0" \ - "ftps_base1=/\0" \ - "ftps_home1=/\0" \ - "plc_sio_srv=no\0" \ - "plc_sio_baud=57600\0" \ - "plc_sio_parity=no\0" \ - "plc_sio_stop=1\0" \ - "plc_sio_com=2\0" \ - "plc_eth_srv=yes\0" \ - "plc_eth_port=1200\0" \ - "plc_root=/ide/\0" \ - "diag_level=0\0" \ - "webvisu=no\0" \ - "plc_can1_routing=no\0" \ - "plc_can1_baudrate=250\0" \ - "plc_can2_routing=no\0" \ - "plc_can2_baudrate=250\0" \ - "plc_can3_routing=no\0" \ - "plc_can3_baudrate=250\0" \ - "plc_can4_routing=no\0" \ - "plc_can4_baudrate=250\0" \ - "netdev=eth0\0" \ - "console=ttyPSC0\0" \ - "kernel_addr_r=400000\0" \ - "fdt_addr_r=600000\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off panic=1\0" \ - "addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${fdt_addr_r} ${fdt_file};" \ - "run nfsargs addip addcons;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=protect off FFF00000 +${filesize};" \ - "erase FFF00000 +${filesize};" \ - "cp.b 200000 FFF00000 ${filesize};" \ - "protect on FFF00000 +${filesize}\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run mtcb_start" - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 - -#if defined(CONFIG_DIGSY_REV5) -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_BASE_CS1 0xFC000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ - CONFIG_SYS_FLASH_BASE_CS1} -#define CONFIG_SYS_UPDATE_FLASH_SIZE -#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE -#else -#define CONFIG_SYS_FLASH_BASE 0xFF000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#endif - -#define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_FLASH_16BIT -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_FLASH_SIZE 0x01000000 -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 - -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) - -#define CONFIG_BOARD_EARLY_INIT_R -#define CONFIG_MISC_INIT_R - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#if defined(CONFIG_LOWBOOT) -#define CONFIG_ENV_ADDR 0xFF060000 -#else /* CONFIG_LOWBOOT */ -#define CONFIG_ENV_ADDR 0xFFF60000 -#endif /* CONFIG_LOWBOOT */ -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#if !defined(CONFIG_SYS_LOWBOOT) -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 -#else -#define CONFIG_SYS_DEFAULT_MBAR 0xF0000000 -#endif - -/* - * Use SRAM until RAM will be available - */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_SYS_MALLOC_LEN (4096 << 10) -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -#if defined(CONFIG_DIGSY_REV5) -#define CONFIG_PHY_ADDR 0x01 -#else -#define CONFIG_PHY_ADDR 0x00 -#endif -#define CONFIG_PHY_RESET_DELAY 1000 - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - -/* - * GPIO configuration - * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1) - * Bit 0 (mask 0x80000000) : 0x1 - * SPI on Tmr2/3/4/5 pins - * Bit 2:3 (mask 0x30000000) : 0x2 - * ATA cs0/1 on csb_4/5 - * Bit 6:7 (mask 0x03000000) : 0x2 - * Ethernet 100Mbit with MD - * Bits 12:15 (mask 0x000f0000): 0x5 - * USB - Two UARTs - * Bits 18:19 (mask 0x00003000) : 0x2 - * PSC3 - USB2 on PSC3 - * Bits 20:23 (mask 0x00000f00) : 0x1 - * PSC2 - CAN1&2 on PSC2 pins - * Bits 25:27 (mask 0x00000070) : 0x1 - * PSC1 - AC97 functionality - * Bits 29:31 (mask 0x00000007) : 0x2 - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0xA2552112 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_CMDLINE_EDITING 1 - -#define CONFIG_MX_CYCLIC 1 - -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 32 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_ALT_MEMTEST -#define CONFIG_SYS_MEMTEST_SCRATCH 0x00001000 -#define CONFIG_SYS_MEMTEST_START 0x00010000 -#define CONFIG_SYS_MEMTEST_END 0x019fffff - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -/* - * Various low-level settings - */ -#define CONFIG_SYS_SDRAM_CS1 1 -#define CONFIG_SYS_XLB_PIPELINING 1 - -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#if defined(CONFIG_SYS_LOWBOOT) -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x0002DD00 -#endif - -#define CONFIG_SYS_CS4_START 0x60000000 -#define CONFIG_SYS_CS4_SIZE 0x1000 -#define CONFIG_SYS_CS4_CFG 0x0008FC00 - -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_CS0_CFG 0x0002DD00 - -#if defined(CONFIG_DIGSY_REV5) -#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE_CS1 -#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_CS1_CFG 0x0002DD00 -#endif - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x11111111 - -#if !defined(CONFIG_SYS_LOWBOOT) -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 -#else -#define CONFIG_SYS_RESET_ADDRESS 0xff000100 -#endif - -/* - * USB - */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_OHCI_BE_CONTROLLER - -#define CONFIG_USB_CLOCK 0x00013333 -#define CONFIG_USB_CONFIG 0x00002000 - -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 -#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" -#define CONFIG_SYS_USB_OHCI_CPU_INIT - -/* - * IDE/ATA - */ -#define CONFIG_IDE_RESET -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_ATA_CS_ON_I2C2 -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) -#define CONFIG_SYS_ATA_STRIDE 4 - -#define CONFIG_ATAPI 1 -#define CONFIG_LBA48 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 17608a54cd..d6c4a71ab2 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -27,7 +27,7 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ #define CONFIG_ENV_SIZE (128 << 10) -#define CONFIG_ENV_OFFSET 0xE0000 +#define CONFIG_ENV_OFFSET 0x260000 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) #define CONFIG_SYS_REDUNDAND_ENVIRONMENT #endif @@ -57,7 +57,7 @@ "partitions_android=" \ "uuid_disk=${uuid_gpt_disk};" \ "name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \ - "name=bootloader,size=768K,uuid=${uuid_gpt_bootloader};" \ + "name=bootloader,size=1792K,uuid=${uuid_gpt_bootloader};" \ "name=environment,size=128K,uuid=${uuid_gpt_environment};" \ "name=misc,size=128K,uuid=${uuid_gpt_misc};" \ "name=reserved,size=256K,uuid=${uuid_gpt_reserved};" \ diff --git a/include/configs/ea20.h b/include/configs/ea20.h index fc0f5e6017..6fc6ec90af 100644 --- a/include/configs/ea20.h +++ b/include/configs/ea20.h @@ -270,4 +270,6 @@ "ubootupd_nand=echo run load_magic,run load_nand,run upd;\0" \ "bootcmd=run net_testrfs\0" +#include <asm/arch/hardware.h> + #endif /* __CONFIG_H */ diff --git a/include/configs/evb_px5.h b/include/configs/evb_px5.h new file mode 100644 index 0000000000..228683739b --- /dev/null +++ b/include/configs/evb_px5.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIGS_PX5_EVB_H +#define __CONFIGS_PX5_EVB_H + +#include <configs/rk3368_common.h> + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x2000 + +#define CONFIG_CONSOLE_SCROLL_LINES 10 + +#endif diff --git a/include/configs/evb_rv1108.h b/include/configs/evb_rv1108.h new file mode 100644 index 0000000000..ff3531b321 --- /dev/null +++ b/include/configs/evb_rv1108.h @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/rv1108_common.h> + +/* + * Default environment settings + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ipaddr=172.16.12.50\0" \ + "serverip=172.16.12.69\0" \ + "" +#define CONFIG_BOOTCOMMAND \ + "sf probe;" \ + "sf read 0x62000000 0x140800 0x500000;" \ + "dcache off;" \ + "go 0x62000000" + +#endif diff --git a/include/configs/geekbox.h b/include/configs/geekbox.h new file mode 100644 index 0000000000..6f6007e65b --- /dev/null +++ b/include/configs/geekbox.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2016 Andreas Färber + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIGS_GEEKBOX_H +#define __CONFIGS_GEEKBOX_H + +#include <configs/rk3368_common.h> + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x2000 + +#define CONFIG_CONSOLE_SCROLL_LINES 10 + +#endif diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h deleted file mode 100644 index d651eff4b2..0000000000 --- a/include/configs/inka4x0.h +++ /dev/null @@ -1,310 +0,0 @@ -/* - * (C) Copyright 2009 - * Detlev Zundel, DENX Software Engineering, dzu@denx.de. - * - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_INKA4X0 1 /* INKA4x0 board */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFFE00000 boot low - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFE00000 /* Standard: boot low */ -#endif -#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds" - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_SYS_XLB_PIPELINING 1 - -/* Partitions */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_PCI - -#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ - -#if (CONFIG_SYS_TEXT_BASE == 0xFFE00000) /* Boot low */ -# define CONFIG_SYS_LOWBOOT 1 -#endif - -/* - * Autobooting - */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_IPADDR 192.168.100.2 -#define CONFIG_SERVERIP 192.168.100.1 -#define CONFIG_NETMASK 255.255.255.0 -#define HOSTNAME inka4x0 -#define CONFIG_BOOTFILE "/tftpboot/inka4x0/uImage" -#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addcons=setenv bootargs ${bootargs} " \ - "console=ttyS0,${baudrate}\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};" \ - "run nfsargs addip addcons;bootm\0" \ - "enable_disp=mw.l 100000 04000000 1;" \ - "cp.l 100000 f0000b20 1;" \ - "cp.l 100000 f0000b28 1\0" \ - "ideargs=setenv bootargs root=/dev/hda1 rw\0" \ - "ide_boot=ext2load ide 0:1 200000 uImage;" \ - "run ideargs addip addcons enable_disp;bootm\0" \ - "brightness=255\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run ide_boot" - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_BASE 0xffe00000 -#define CONFIG_SYS_FLASH_SIZE 0x00200000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* - * SDRAM controller configuration - */ -#undef CONFIG_SDR_MT48LC16M16A2 -#undef CONFIG_DDR_MT46V16M16 -#undef CONFIG_DDR_MT46V32M16 -#undef CONFIG_DDR_HYB25D512160BF -#define CONFIG_DDR_K4H511638C - -/* Use ON-Chip SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM - -/* preserve space for the post_word at end of on-chip SRAM */ -#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4) - -#ifdef CONFIG_POST -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE -#else -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE -#endif - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -/* - * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb - */ -/* #define CONFIG_MPC5xxx_FEC_MII10 */ -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_MII - -/* - * GPIO configuration - * - * use CS1 as gpio_wkup_6 output - * Bit 0 (mask: 0x80000000): 0 - * use ALT CAN position: Bits 2-3 (mask: 0x30000000): - * 00 -> No Alternatives, I2C1 is used for onboard EEPROM - * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard - * EEPROM - * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 - * use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100 - * use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100 - * use PSC6 as UART: Bits 9-11 (mask: 0x00700000): 0101 - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x01501444 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* Enable an alternate, more extensive memory test */ -#define CONFIG_SYS_ALT_MEMTEST - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00087800 /* for pci_clk = 66 MHz */ -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -/* 32Mbit SRAM @0x30000000 */ -#define CONFIG_SYS_CS1_START 0x30000000 -#define CONFIG_SYS_CS1_SIZE 0x00400000 -#define CONFIG_SYS_CS1_CFG 0x31800 /* for pci_clk = 33 MHz */ - -/* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */ -#define CONFIG_SYS_CS2_START 0x80000000 -#define CONFIG_SYS_CS2_SIZE 0x0001000 -#define CONFIG_SYS_CS2_CFG 0x21800 /* for pci_clk = 33 MHz */ - -/* GPIO in @0x30400000 */ -#define CONFIG_SYS_CS3_START 0x30400000 -#define CONFIG_SYS_CS3_SIZE 0x00100000 -#define CONFIG_SYS_CS3_CFG 0x31800 /* for pci_clk = 33 MHz */ - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_OHCI -#define CONFIG_USB_CLOCK 0x00015555 -#define CONFIG_USB_CONFIG 0x00001000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0060 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x005C /* Offset for alternate registers */ -#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ - -#define CONFIG_ATAPI 1 - -#define CONFIG_SYS_BRIGHTNESS 0xFF /* LCD Default Brightness (255 = off) */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h index 127e7e7396..f78aa47ae2 100644 --- a/include/configs/ipam390.h +++ b/include/configs/ipam390.h @@ -301,4 +301,6 @@ #define CONFIG_IPAM390_GPIO_LED_RED ((16 * 7) + 11) #define CONFIG_IPAM390_GPIO_LED_GREEN ((16 * 7) + 12) +#include <asm/arch/hardware.h> + #endif /* __CONFIG_H */ diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h deleted file mode 100644 index c6390dbdbe..0000000000 --- a/include/configs/ipek01.h +++ /dev/null @@ -1,321 +0,0 @@ -/* - * (C) Copyright 2006 - * MicroSys GmbH - * - * (C) Copyright 2009 - * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -#define CONFIG_MPC5200 -#define CONFIG_MPX5200 1 /* MPX5200 board */ -#define CONFIG_MPC5200_DDR 1 /* use DDR RAM */ -#define CONFIG_IPEK01 /* Motherboard is ipek01 */ - -#define CONFIG_SYS_TEXT_BASE 0xfc000000 - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -/* - * Video configuration for LIME GDC - */ -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_MB862xx -#define CONFIG_VIDEO_MB862xx_ACCEL -#define VIDEO_FB_16BPP_WORD_SWAP -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_SPLASH_SCREEN -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ -/* Lime clock frequency */ -#define CONFIG_SYS_MB862xx_CCF 0x90000 /* geo 166MHz other 133MHz */ -/* SDRAM parameter */ -#define CONFIG_SYS_MB862xx_MMR 0x41c767e3 -#endif - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#define CONFIG_PCI_SCAN_SHOW 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_MII 1 -#define CONFIG_EEPRO100 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ - -/* USB */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_OHCI_BE_CONTROLLER - -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 - -/* - * Command line configuration. - */ -#define CONFIG_CMD_PCI /* pciinfo */ - -#define CONFIG_SYS_LOWBOOT 1 - -/* - * Autobooting - */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyPSC0\0" \ - "hostname=ipek01\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} " \ - "console=${consoledev},${baudrate}\0" \ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr} - ${fdtaddr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0" \ - "net_nfs=tftp 200000 ${bootfile}; tftp ${fdtaddr} ${fdtfile};" \ - "run nfsargs addip addtty;" \ - "bootm ${loadaddr} - ${fdtaddr}\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=ipek01/uImage\0" \ - "load=tftp 100000 ipek01/u-boot.bin\0" \ - "update=protect off FC000000 +60000; era FC000000 +60000; " \ - "cp.b 100000 FC000000 ${filesize}\0" \ - "upd=run load;run update\0" \ - "fdtaddr=800000\0" \ - "loadaddr=400000\0" \ - "fdtfile=ipek01/ipek01.dtb\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* for 133MHz */ -/* PCI clock must be 33, because board will not boot */ -#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for 66MHz */ - -/* - * Open firmware flat tree support - */ -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) - -#define CONFIG_SYS_FLASH_BASE 0xFC000000 -#define CONFIG_SYS_FLASH_SIZE 0x01000000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ - CONFIG_SYS_MONITOR_LEN) - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ - -/* use CFI flash driver */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xf0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 -#define CONFIG_SYS_SRAM_BASE 0xF1000000 -#define CONFIG_SYS_SRAM_SIZE 0x00200000 -#define CONFIG_SYS_LIME_BASE 0xE4000000 -#define CONFIG_SYS_LIME_SIZE 0x04000000 -#define CONFIG_SYS_FPGA_BASE 0xC0000000 -#define CONFIG_SYS_FPGA_SIZE 0x10000000 -#define CONFIG_SYS_MPEG_BASE 0xe2000000 -#define CONFIG_SYS_MPEG_SIZE 0x01000000 -#define CONFIG_SYS_CF_BASE 0xe1000000 -#define CONFIG_SYS_CF_SIZE 0x01000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -/* End of used area in DPRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x1d556624 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1...15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE -#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_SRAM_SIZE -#define CONFIG_SYS_CS3_START CONFIG_SYS_LIME_BASE -#define CONFIG_SYS_CS3_SIZE CONFIG_SYS_LIME_SIZE -#define CONFIG_SYS_CS6_START CONFIG_SYS_FPGA_BASE -#define CONFIG_SYS_CS6_SIZE CONFIG_SYS_FPGA_SIZE -#define CONFIG_SYS_CS5_START CONFIG_SYS_CF_BASE -#define CONFIG_SYS_CS5_SIZE CONFIG_SYS_CF_SIZE -#define CONFIG_SYS_CS7_START CONFIG_SYS_MPEG_BASE -#define CONFIG_SYS_CS7_SIZE CONFIG_SYS_MPEG_SIZE - -#ifdef CONFIG_SYS_PCISPEED_66 -#define CONFIG_SYS_BOOTCS_CFG 0x0006F900 -#define CONFIG_SYS_CS1_CFG 0x0004FB00 -#define CONFIG_SYS_CS2_CFG 0x0006F900 -#else -#define CONFIG_SYS_BOOTCS_CFG 0x0002F900 -#define CONFIG_SYS_CS1_CFG 0x0001FB00 -#define CONFIG_SYS_CS2_CFG 0x0002F90C -#endif - -/* - * Ack active, Muxed mode, AS=24 bit address, DS=32 bit data, 0 - * waitstates, writeswap and readswap enabled - */ -#define CONFIG_SYS_CS3_CFG 0x00FFFB0C -#define CONFIG_SYS_CS6_CFG 0x00FFFB0C -#define CONFIG_SYS_CS7_CFG 0x4040751C - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33330000 - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00005000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#endif /* __CONFIG_H */ diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h deleted file mode 100644 index 4461623118..0000000000 --- a/include/configs/jupiter.h +++ /dev/null @@ -1,246 +0,0 @@ -/* - * (C) Copyright 2007 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_JUPITER 1 /* ... on Jupiter board */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFFF00000 boot high (standard configuration) - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_BOARD_EARLY_INIT_R 1 - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ - -#if defined(CONFIG_PCI) -#define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 -#endif - -#define CONFIG_SYS_XLB_PIPELINING 1 - -#define CONFIG_MII 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ - -/* Partitions */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ - -#if defined(CONFIG_PCI) -#define CODFIG_CMD_PCI -#endif - -/* - * Autobooting - */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "addcons=setenv bootargs ${bootargs} console=${contyp}," \ - "${baudrate}\0" \ - "contyp=ttyS0\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \ - "bootm\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=/tftpboot/jupiter/uImage\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* - * IPB Bus clocking configuration. - */ -#undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */ - -#if 0 -/* pass open firmware flat tree */ -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" -#endif - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_BASE 0xFF000000 -#define CONFIG_SYS_FLASH_SIZE 0x01000000 - -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE + 0x40000) /* third sector */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT -#define CONFIG_SYS_UPDATE_FLASH_SIZE 1 -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OVERWRITE 1 - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -/* - * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb - */ -/* #define CONFIG_MPC5xxx_FEC_MII10 */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ -#define CONFIG_SYS_ALT_MEMTEST 1 - -#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00047801 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/km82xx.h b/include/configs/km82xx.h deleted file mode 100644 index 09c3aa9ca8..0000000000 --- a/include/configs/km82xx.h +++ /dev/null @@ -1,427 +0,0 @@ -/* - * (C) Copyright 2007-2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC8247 -/* MGCOGE */ -#if defined(CONFIG_MGCOGE) -#define CONFIG_HOSTNAME mgcoge -#define CONFIG_KM_BOARD_EXTRA_ENV "" - -/* MGCOGE3NE */ -#elif defined(CONFIG_MGCOGE3NE) -#define CONFIG_HOSTNAME mgcoge3ne -#define CONFIG_KM_82XX -#define CONFIG_KM_BOARD_EXTRA_ENV "bobcatreset=true\0" - -#else -#error ("Board unsupported") -#endif - -#define CONFIG_SYS_TEXT_BASE 0xFE000000 - -#define CONFIG_MISC_INIT_R - -/* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_SIZE 32 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER - -/* MGCOGE */ -#if defined(CONFIG_MGCOGE) -#define CONFIG_SYS_MAX_FLASH_BANKS 3 -/* max num of sects on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -#define CONFIG_SYS_FLASH_BASE_1 0x50000000 -#define CONFIG_SYS_FLASH_SIZE_1 32 -#define CONFIG_SYS_FLASH_BASE_2 0x52000000 -#define CONFIG_SYS_FLASH_SIZE_2 32 - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ - CONFIG_SYS_FLASH_BASE_1, \ - CONFIG_SYS_FLASH_BASE_2 } -#define MTDIDS_DEFAULT "nor3=app" - -/* - * Bank 1 - 60x bus SDRAM - */ -#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */ - -/* SDRAM initialization values -*/ - -#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \ - ORxS_SDAM_MSK) |\ - ORxS_BPD_8 |\ - ORxS_ROWST_PBI0_A7 |\ - ORxS_NUMR_13) - -#define CONFIG_SYS_PSDMR ( \ - PSDMR_SDAM_A14_IS_A5 |\ - PSDMR_BSMA_A14_A16 |\ - PSDMR_SDA10_PBI0_A9 |\ - PSDMR_RFRC_5_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - -/* MGCOGE3NE */ -#elif defined(CONFIG_MGCOGE3NE) -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* - * max num of sects on one - * chip - */ - -#define CONFIG_SYS_FLASH_BASE_1 0x50000000 -#define CONFIG_SYS_FLASH_SIZE_1 128 - -#define CONFIG_SYS_FLASH_SIZE_2 0 /* dummy value to calc SYS_OR5 */ - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ - CONFIG_SYS_FLASH_BASE_1 } - -#define MTDIDS_DEFAULT "nor2=app" - -/* - * Bank 1 - 60x bus SDRAM - * mgcoge3ne has 256MB - * mgcoge2ne has 128MB - */ -#define SDRAM_MAX_SIZE 0x10000000 /* max. 256 MB */ -#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512 << 20) /* less than 512 MB */ - -#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \ - ORxS_SDAM_MSK) |\ - ORxS_BPD_4 |\ - ORxS_NUMR_13 |\ - ORxS_IBID) - -#define CONFIG_SYS_PSDMR ( \ - PSDMR_PBI |\ - PSDMR_RFEN |\ - PSDMR_BSMA_A13_A15 |\ - PSDMR_RFRC_5_CLK |\ - PSDMR_PRETOACT_2W |\ - PSDMR_ACTTORW_2W |\ - PSDMR_LDOTOPRE_1C |\ - PSDMR_WRC_1C |\ - PSDMR_CL_2) - -#define CONFIG_SYS_SDRAM_LIST { \ - { .size = 256 << 20, \ - .or1 = ORxS_ROWST_PBI1_A4, \ - .psdmr = PSDMR_SDAM_A17_IS_A5 | PSDMR_SDA10_PBI1_A6, \ - }, \ - { .size = 128 << 20, \ - .or1 = ORxS_ROWST_PBI1_A5, \ - .psdmr = PSDMR_SDAM_A16_IS_A5 | PSDMR_SDA10_PBI1_A7, \ - }, \ -} -#endif /* defined(CONFIG_MGCOGE3NE) */ - -/* include further common stuff for all keymile 82xx boards */ -/* - * Select serial console configuration - * - * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then - * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 - * for SCC). - */ -#define CONFIG_CONS_ON_SMC /* Console is on SMC */ -#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ -#undef CONFIG_CONS_NONE /* It's not on external UART */ -#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 - -/* - * Select ethernet configuration - * - * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, - * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for - * SCC, 1-3 for FCC) - * - * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CONFIG_CMD_NET - * must be unset. - */ -#define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */ -#undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */ -#undef CONFIG_ETHER_NONE /* No external Ethernet */ - -#define CONFIG_ETHER_INDEX 4 -#define CONFIG_HAS_ETH0 -#define CONFIG_SYS_SCC_TOUT_LOOP 10000000 - -#define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8) - -#ifndef CONFIG_8260_CLKIN -#define CONFIG_8260_CLKIN 66000000 /* in Hz */ -#endif - -#define BOOTFLASH_START 0xFE000000 - -#define CONFIG_KM_CONSOLE_TTY "ttyCPM0" - -#define MTDPARTS_DEFAULT "mtdparts=" \ - "app:" \ - "768k(u-boot)," \ - "128k(env)," \ - "128k(envred)," \ - "3072k(free)," \ - "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ")" - -/* - * Default environment settings - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_BOARD_EXTRA_ENV \ - CONFIG_KM_DEF_ENV \ - "unlock=yes\0" \ - "newenv=" \ - "prot off 0xFE0C0000 +0x40000 && " \ - "era 0xFE0C0000 +0x40000\0" \ - "arch=ppc_82xx\0" \ - "" - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_MONITOR_LEN (768 << 10) - -#define CONFIG_ENV_IS_IN_FLASH - -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif /* CONFIG_ENV_IS_IN_FLASH */ - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_SYS_NUM_I2C_BUSES 3 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SPEED CONFIG_SYS_I2C_SOFT_SPEED -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9542, 0x70, 0} } }, \ - {0, {{I2C_MUX_PCA9542, 0x70, 1} } } } - -#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ -#define CONFIG_KM_I2C_ABORT - -/* - * Software (bit-bang) I2C driver configuration - */ - -#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ -#define I2C_ACTIVE (iop->pdir |= 0x00010000) -#define I2C_TRISTATE (iop->pdir &= ~0x00010000) -#define I2C_READ ((iop->pdat & 0x00010000) != 0) -#define I2C_SDA(bit) do { \ - if (bit) \ - iop->pdat |= 0x00010000; \ - else \ - iop->pdat &= ~0x00010000; \ - } while (0) -#define I2C_SCL(bit) do { \ - if (bit) \ - iop->pdat |= 0x00020000; \ - else \ - iop->pdat &= ~0x00020000; \ - } while (0) -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#ifndef __ASSEMBLY__ -void set_sda(int state); -void set_scl(int state); -int get_sda(void); -int get_scl(void); -#endif - -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -#define CONFIG_SYS_IMMR 0xF0000000 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* used size in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* Hard reset configuration word */ -#define CONFIG_SYS_HRCW_MASTER 0x0604b211 - -/* No slaves */ -#define CONFIG_SYS_HRCW_SLAVE1 0 -#define CONFIG_SYS_HRCW_SLAVE2 0 -#define CONFIG_SYS_HRCW_SLAVE3 0 -#define CONFIG_SYS_HRCW_SLAVE4 0 -#define CONFIG_SYS_HRCW_SLAVE5 0 -#define CONFIG_SYS_HRCW_SLAVE6 0 -#define CONFIG_SYS_HRCW_SLAVE7 0 - -/* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) - -#define CONFIG_SYS_HID2 0 - -#define CONFIG_SYS_SIUMCR 0x4020c200 -#define CONFIG_SYS_SYPCR 0xFFFFFF83 -#define CONFIG_SYS_BCR 0x10000000 -#define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK) - -/* - *----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - *----------------------------------------------------------------------- - * turn on Checkstop Reset Enable - */ -#define CONFIG_SYS_RMR 0 - -/* - *----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control 4-40 - *----------------------------------------------------------------------- - * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, - * and enable Time Counter - */ -#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) - -/* - *----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 4-42 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable - * Periodic timer - */ -#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) - -/* - *----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration 13-7 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0 - -/* - * Init Memory Controller: - * - * Bank Bus Machine PortSz Device - * ---- --- ------- ------ ------ - * 0 60x GPCM 8 bit FLASH - * 1 60x SDRAM 32 bit SDRAM - * 3 60x GPCM 8 bit GPIO/PIGGY - * 5 60x GPCM 16 bit CFG-Flash - * - */ -/* Bank 0 - FLASH - */ -#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV2 |\ - ORxG_SCY_5_CLK |\ - ORxG_TRLX) - -#define CONFIG_SYS_MPTPR 0x1800 - -/* - *----------------------------------------------------------------------------- - * Address for Mode Register Set (MRS) command - *----------------------------------------------------------------------------- - */ -#define CONFIG_SYS_MRS_OFFS 0x00000110 -#define CONFIG_SYS_PSRT 0x0e - -#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) - -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1 - -/* - * UPIO FPGA (GPIO/PIGGY) on CS3 initialization values - */ -#define CONFIG_SYS_KMBEC_FPGA_BASE 0x30000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 - -#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_KMBEC_FPGA_BASE & BRx_BA_MSK) |\ - BRx_PS_8 | BRx_MS_GPCM_P | BRx_V) - -#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) |\ - ORxG_CSNT | ORxG_ACS_DIV2 |\ - ORxG_SCY_3_CLK | ORxG_TRLX) - -/* - * BFTICU board FPGA on CS4 initialization values - */ -#define CONFIG_SYS_FPGA_BASE 0x40000000 -#define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/ - -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\ - BRx_PS_8 | BRx_MS_GPCM_P | BRx_V) - -#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\ - ORxG_CSNT | ORxG_ACS_DIV2 |\ - ORxG_SCY_3_CLK | ORxG_TRLX) - -/* - * CFG-Flash on CS5 initialization values - */ -#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\ - BRx_PS_16 | BRx_MS_GPCM_P | BRx_V) - -#define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \ - CONFIG_SYS_FLASH_SIZE_2) |\ - ORxG_CSNT | ORxG_ACS_DIV2 |\ - ORxG_SCY_5_CLK | ORxG_TRLX) - -#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ - -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc/cpm/serial@11a90" - -#endif /* __CONFIG_H */ diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index f230f40d76..15da4074f2 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -214,4 +214,6 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x80010000 +#include <asm/arch/hardware.h> + #endif /* __CONFIG_H */ diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index bd9b0d30a5..42bbc028d3 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -121,4 +121,6 @@ #define CONFIG_PANIC_HANG #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ +#include <asm/arch/soc.h> + #endif /* __LS1012A_COMMON_H */ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 7fd3464fa5..32f7162bbc 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -300,4 +300,6 @@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ +#include <asm/arch/soc.h> + #endif /* __LS1043A_COMMON_H */ diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index b66b8ac72c..1b91676c2d 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -237,4 +237,6 @@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ +#include <asm/arch/soc.h> + #endif /* __LS1046A_COMMON_H */ diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index e311d0b149..dbca05a3f6 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -250,4 +250,6 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ +#include <asm/arch/soc.h> + #endif /* __LS2_COMMON_H */ diff --git a/include/configs/manroland/mpc5200-common.h b/include/configs/manroland/mpc5200-common.h deleted file mode 100644 index 68874dc029..0000000000 --- a/include/configs/manroland/mpc5200-common.h +++ /dev/null @@ -1,176 +0,0 @@ -/* - * (C) Copyright 2009 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MANROLAND_MPC52XX__COMMON_H -#define __MANROLAND_MPC52XX__COMMON_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC5200 1 /* MPC5200 CPU */ - -/* ... running at 33.000000MHz */ -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200,\ - 230400 } - -#if (CONFIG_SYS_TEXT_BASE == 0xFFF00000) /* Boot low */ -# define CONFIG_SYS_LOWBOOT 1 -#endif - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_BASE 0xFF800000 - -#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ - -#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout [ms]*/ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout [ms]*/ - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_CFI_AMD_RESET - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -\ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SRAM_BASE 0x80100000 /* CS 1 */ -#define CONFIG_SYS_DISPLAY_BASE 0x80600000 /* CS 3 */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_DDR 1 -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE -#else -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE -#endif - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) -#define CONFIG_SYS_MALLOC_LEN (512 << 10) -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_MII 1 - -/*use Hardware WDT */ -#define CONFIG_HW_WATCHDOG - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -/* 8Mbit SRAM @0x80100000 */ -#define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ - -#define CONFIG_IDE_PREINIT 1 - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#define CONFIG_ATAPI 1 - -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" -#define CONFIG_OF_IDE_FIXUP - -#endif /* __MANROLAND_MPC52XX__COMMON_H */ diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h deleted file mode 100644 index 17a97dfc3a..0000000000 --- a/include/configs/mecp5123.h +++ /dev/null @@ -1,398 +0,0 @@ -/* - * (C) Copyright 2009 Wolfgang Denk <wd@denx.de> - * (C) Copyright 2009, DAVE Srl <www.dave.eu> - * - * SPDX-License-Identifier: GPL-2.0+ - * modifications for the MECP5123 by reinhard.arlt@esd-electronics.com - * - */ - -/* - * MECP5123 board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MECP5123 1 - -/* - * Memory map for the MECP5123 board: - * - * 0x0000_0000 - 0x1FFF_FFFF DDR RAM (512 MB) - * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB) - * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) - * 0x8200_0000 - 0x8200_FFFF VPC-3 (64 KB) - * 0xFFC0_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB) - */ - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 Family */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_SYS_IMMR 0x80000000 -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100) - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * DDR Setup - manually set all parameters as there's no SPD etc. - */ -#define CONFIG_SYS_DDR_SIZE 512 /* MB */ - -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 - -#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036 - -/* DDR Controller Configuration - * - * SYS_CFG: - * [31:31] MDDRC Soft Reset: Diabled - * [30:30] DRAM CKE pin: Enabled - * [29:29] DRAM CLK: Enabled - * [28:28] Command Mode: Enabled (For initialization only) - * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] - * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] - * [20:19] Read Test: DON'T USE - * [18:18] Self Refresh: Enabled - * [17:17] 16bit Mode: Disabled - * [16:13] Ready Delay: 2 - * [12:12] Half DQS Delay: Disabled - * [11:11] Quarter DQS Delay: Disabled - * [10:08] Write Delay: 2 - * [07:07] Early ODT: Disabled - * [06:06] On DIE Termination: Disabled - * [05:05] FIFO Overflow Clear: DON'T USE here - * [04:04] FIFO Underflow Clear: DON'T USE here - * [03:03] FIFO Overflow Pending: DON'T USE here - * [02:02] FIFO Underlfow Pending: DON'T USE here - * [01:01] FIFO Overlfow Enabled: Enabled - * [00:00] FIFO Underflow Enabled: Enabled - * TIME_CFG0 - * [31:16] DRAM Refresh Time: 0 CSB clocks - * [15:8] DRAM Command Time: 0 CSB clocks - * [07:00] DRAM Precharge Time: 0 CSB clocks - * TIME_CFG1 - * [31:26] DRAM tRFC: - * [25:21] DRAM tWR1: - * [20:17] DRAM tWRT1: - * [16:11] DRAM tDRR: - * [10:05] DRAM tRC: - * [04:00] DRAM tRAS: - * TIME_CFG2 - * [31:28] DRAM tRCD: - * [27:23] DRAM tFAW: - * [22:19] DRAM tRTW1: - * [18:15] DRAM tCCD: - * [14:10] DRAM tRTP: - * [09:05] DRAM tRP: - * [04:00] DRAM tRPA - */ -#define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00 -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E -#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 -#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 - -#define CONFIG_SYS_DDRCMD_NOP 0x01380000 -#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 -#define CONFIG_SYS_DDRCMD_EM2 0x01020000 -#define CONFIG_SYS_DDRCMD_EM3 0x01030000 -#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000 -#define CONFIG_SYS_DDRCMD_RFSH 0x01080000 -#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x01010780 - -/* DDR Priority Manager Configuration */ -#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 -#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 -#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 -#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC -#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA -#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 -#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 -#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 - -/* - * NOR FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ - -#define CONFIG_SYS_FLASH_BASE 0xFFC00000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 0x00400000 /* max flash size */ - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM - -/* - * NAND FLASH - * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only) - */ -#define CONFIG_CMD_NAND -#define CONFIG_NAND_MPC5121_NFC -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -/* - * Configuration parameters for MPC5121 NAND driver - */ -#define CONFIG_FSL_NFC_WIDTH 1 -#define CONFIG_FSL_NFC_WRITE_SIZE 2048 -#define CONFIG_FSL_NFC_SPARE_SIZE 64 -#define CONFIG_FSL_NFC_CHIPS 1 - -#define CONFIG_SYS_SRAM_BASE 0x30000000 -#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ - -/* Initialize Local Window for NOR FLASH access */ -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -/* ALE active low, data size 4bytes */ -#define CONFIG_SYS_CS0_CFG 0x05051150 - -/* Use not alternative CS timing */ -#define CONFIG_SYS_CS_ALETIMING 0x00000000 - -/* ALE active low, data size 4bytes */ -#define CONFIG_SYS_CS1_CFG 0x1f1f3090 -#define CONFIG_SYS_VPC3_BASE 0x82000000 /* start of VPC3 space */ -#define CONFIG_SYS_VPC3_SIZE 0x00010000 /* max VPC3 size */ -/* Initialize Local Window for VPC3 access */ -#define CONFIG_SYS_CS1_START CONFIG_SYS_VPC3_BASE -#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_VPC3_SIZE - -/* Use SRAM for initial stack */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Init RAM addr */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of monitor */ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Monitor length */ -#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Malloc size */ - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ -#define CONFIG_SYS_PSC3 -#if CONFIG_PSC_CONSOLE != 3 -#error CONFIG_PSC_CONSOLE must be 3 -#endif -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE -#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR -#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE -#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR - -/* - * Clocks in use - */ -#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ - CLOCK_SCCR1_LPC_EN | \ - CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ - CLOCK_SCCR1_PSCFIFO_EN | \ - CLOCK_SCCR1_DDR_EN | \ - CLOCK_SCCR1_FEC_EN | \ - CLOCK_SCCR1_NFC_EN | \ - CLOCK_SCCR1_PCI_EN | \ - CLOCK_SCCR1_TPR_EN) - -#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ - CLOCK_SCCR2_I2C_EN) - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -/* - * IIM - IC Identification Module - */ -#undef CONFIG_FSL_IIM - -/* - * Ethernet configuration - */ -#define CONFIG_MPC512x_FEC 1 -#define CONFIG_PHY_ADDR 0x1 -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_FEC_AN_TIMEOUT 1 -#define CONFIG_HAS_ETH0 - -/* - * Configure on-board RTC - */ -#define CONFIG_SYS_RTC_BUS_NUM 0x01 -#define CONFIG_SYS_I2C_RTC_ADDR 0x32 -#define CONFIG_RTC_RX8025 - -/* - * Environment - */ -#define CONFIG_ENV_IS_NOWHERE /* Store env in I2C EEPROM */ -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_OFFSET 0x0000 /* environment starts here */ - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -#define CONFIG_CMD_REGINFO - -/* - * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. - * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set - * to 0xFFFF, watchdog timeouts after about 64s. For details refer - * to chapter 36 of the MPC5121e Reference Manual. - */ -/* #define CONFIG_WATCHDOG */ /* enable watchdog */ -#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF - - /* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -#ifdef CONFIG_CMD_KGDB -# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 32 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Linux initial memory map */ - -/* Cache Configuration */ -#define CONFIG_SYS_DCACHE_SIZE 32768 -#define CONFIG_SYS_CACHELINE_SIZE 32 -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CACHELINE_SHIFT 5 -#endif - -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK -#define CONFIG_SYS_HID2 HID2_HBE - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_TIMESTAMP - -#define CONFIG_HOSTNAME mecp512x -#define CONFIG_BOOTFILE "/tftpboot/mecp512x/uImage" -#define CONFIG_ROOTPATH "/tftpboot/mecp512x/target_root" - -#define CONFIG_LOADADDR 400000 /* def. location for tftp and bootm */ - -#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ - -#define CONFIG_PREBOOT "echo;" \ - "echo Welcome to MECP5123" \ - "echo" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "u-boot_addr_r=200000\0" \ - "kernel_addr_r=600000\0" \ - "fdt_addr_r=880000\0" \ - "ramdisk_addr_r=900000\0" \ - "u-boot_addr=FFF00000\0" \ - "kernel_addr=FFC40000\0" \ - "fdt_addr=FFEC0000\0" \ - "ramdisk_addr=FC040000\0" \ - "ramdiskfile=/tftpboot/mecp512x/uRamdisk\0" \ - "u-boot=/tftpboot/mecp512x/u-boot.bin\0" \ - "bootfile=/tftpboot/mecp512x/uImage\0" \ - "fdtfile=/tftpboot/mecp512x/mecp512x.dtb\0" \ - "rootpath=/tftpboot/mecp512x/target_root\n" \ - "netdev=eth0\0" \ - "consdev=ttyPSC0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} " \ - "console=${consdev},${baudrate}\0" \ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${fdt_addr_r} ${fdtfile};" \ - "run nfsargs addip addtty;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "net_self=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ - "tftp ${fdt_addr_r} ${fdtfile};" \ - "run ramargs addip addtty;" \ - "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ - "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ - "update=protect off ${u-boot_addr} +${filesize};" \ - "era ${u-boot_addr} +${filesize};" \ - "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ - "upd=run load update\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define OF_CPU "PowerPC,5121@0" -#define OF_SOC_COMPAT "fsl,mpc5121-immr" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc@80000000/serial@11300" - -#endif /* __CONFIG_H */ diff --git a/include/configs/meson-gxbb-common.h b/include/configs/meson-gxbb-common.h index 12a4dfce6b..89e3807a14 100644 --- a/include/configs/meson-gxbb-common.h +++ b/include/configs/meson-gxbb-common.h @@ -40,6 +40,7 @@ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ + func(PXE, pxe, na) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h deleted file mode 100644 index 75633f66ef..0000000000 --- a/include/configs/motionpro.h +++ /dev/null @@ -1,329 +0,0 @@ -/* - * (C) Copyright 2003-2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Based on Motion-PRO board config file by Robert McCullough, rob@promessinc.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -/* CPU and board */ -#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ -#define CONFIG_MOTIONPRO 1 /* ... on Promess Motion-PRO board */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_REGINFO - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_NETCONSOLE 1 /* network console */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x2 -#define CONFIG_PHY_TYPE 0x79c874 -#define CONFIG_RESET_PHY_R 1 - -/* - * Autobooting - */ -#undef CONFIG_BOOTARGS - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -/* - * Default environment settings - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=motionpro\0" \ - "netmask=255.255.255.0\0" \ - "ipaddr=192.168.1.106\0" \ - "serverip=192.168.1.100\0" \ - "gatewayip=192.168.1.100\0" \ - "console=ttyPSC0,115200\0" \ - "u-boot_addr=400000\0" \ - "kernel_addr=400000\0" \ - "fdt_addr=700000\0" \ - "ramdisk_addr=800000\0" \ - "multi_image_addr=800000\0" \ - "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ - "u-boot=/tftpboot/motionpro/u-boot.bin\0" \ - "bootfile=/tftpboot/motionpro/uImage\0" \ - "fdt_file=/tftpboot/motionpro/motionpro.dtb\0" \ - "ramdisk_file=/tftpboot/motionpro/uRamdisk\0" \ - "multi_image_file=kernel+initrd+dtb.img\0" \ - "load=tftp ${u-boot_addr} ${u-boot}\0" \ - "update=prot off fff00000 +${filesize};" \ - "era fff00000 +${filesize}; " \ - "cp.b ${u-boot_addr} fff00000 ${filesize};" \ - "prot on fff00000 +${filesize}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "fat_args=setenv bootargs root=/dev/sda rw\0" \ - "mtdids=nor0=ff000000.flash\0" \ - "mtdparts=ff000000.flash:13m(fs),2m(kernel),384k(uboot)," \ - "128k(env),128k(redund_env)," \ - "128k(dtb),128k(user_data)\0" \ - "addcons=setenv bootargs ${bootargs} console=${console}\0" \ - "addmtd=setenv bootargs ${bootargs} mtdparts=${mtdparts}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off panic=1 " \ - "console=${console}\0" \ - "net_nfs=tftp ${kernel_addr} ${bootfile}; " \ - "tftp ${fdt_addr} ${fdt_file}; " \ - "run nfsargs addip addmtd; " \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "net_self=tftp ${kernel_addr} ${bootfile}; " \ - "tftp ${fdt_addr} ${fdt_file}; " \ - "tftp ${ramdisk_addr} ${ramdisk_file}; " \ - "nfs ${ramdisk_addr} ${serverip}:${rootpath}/images/uRamdisk; " \ - "run ramargs addip addcons addmtd; " \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "fat_multi=run fat_args addip addmtd; fatload ide 0:1 " \ - "${multi_image_addr} ${multi_image_file}; " \ - "bootm ${multi_image_addr}\0" \ - "" -#define CONFIG_BOOTCOMMAND "run fat_multi" - -/* - * do board-specific init - */ -#define CONFIG_BOARD_EARLY_INIT_R 1 - -/* - * Low level configuration - */ - -/* - * Clock configuration: SYS_XTALIN = 33MHz - */ -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 - -/* - * Set IPB speed to 100MHz - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK - -/* - * Memory map - */ -/* - * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000. - * Setting MBAR to otherwise will cause system hang when using SmartDMA such - * as network commands. - */ -#define CONFIG_SYS_MBAR 0xf0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* - * If building for running out of SDRAM, then MBAR has been set up beforehand - * (e.g., by the BDI). Otherwise we must specify the default boot-up value of - * MBAR, as given in the doccumentation. - */ -#if CONFIG_SYS_TEXT_BASE == 0x00100000 -#define CONFIG_SYS_DEFAULT_MBAR 0xf0000000 -#else /* CONFIG_SYS_TEXT_BASE != 0x00100000 */ -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 -#define CONFIG_SYS_LOWBOOT 1 -#endif /* CONFIG_SYS_TEXT_BASE == 0x00100000 */ - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* 1 MiB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */ - -/* - * Chip selects configuration - */ -/* Boot Chipselect */ -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00045D00 - -/* Flash memory addressing */ -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_CS0_CFG CONFIG_SYS_BOOTCS_CFG - -/* Dual Port SRAM -- Kollmorgen Drive memory addressing */ -#define CONFIG_SYS_CS1_START 0x50000000 -#define CONFIG_SYS_CS1_SIZE 0x10000 -#define CONFIG_SYS_CS1_CFG 0x05055800 - -/* Local register access */ -#define CONFIG_SYS_CS2_START 0x50010000 -#define CONFIG_SYS_CS2_SIZE 0x10000 -#define CONFIG_SYS_CS2_CFG 0x05055800 - -/* Anybus CompactCom Module memory addressing */ -#define CONFIG_SYS_CS3_START 0x50020000 -#define CONFIG_SYS_CS3_SIZE 0x10000 -#define CONFIG_SYS_CS3_CFG 0x05055800 - -/* No burst and dead cycle = 2 for all CSs */ -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x22222222 - -/* - * SDRAM configuration - */ -/* 2 x MT48LC16M16A2BG-75 IT:D, CASL 3, 32 bit data bus */ -#define SDRAM_CONFIG1 0x62322900 -#define SDRAM_CONFIG2 0x88c70000 -#define SDRAM_CONTROL 0x504f0000 -#define SDRAM_MODE 0x00cd0000 - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_BASE 0xff000000 -#define CONFIG_SYS_FLASH_SIZE 0x01000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ -#define CONFIG_FLASH_16BIT /* Flash is 16-bit */ - -/* - * MTD configuration - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=motionpro-0" -#define MTDPARTS_DEFAULT "mtdparts=motionpro-0:" \ - "13m(fs),2m(kernel),384k(uboot)," \ - "128k(env),128k(redund_env)," \ - "128k(dtb),-(user_data)" - -/* - * IDE/ATA configuration - */ -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0060 -#define CONFIG_SYS_ATA_REG_OFFSET CONFIG_SYS_ATA_DATA_OFFSET -#define CONFIG_SYS_ATA_STRIDE 4 - -/* - * RTC configuration - */ -#define CONFIG_RTC_DS1337 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * Status LED configuration - */ - -#define ENABLE_GPIO_OUT 0x00000024 -#define LED_ON 0x00000010 - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -/* This has to be a multiple of the Flash sector size */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_SECT_SIZE 0x20000 - -/* Configuration of redundant environment */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/* - * Pin multiplexing configuration - */ - -/* PSC1: UART1 - * PSC2: GPIO (default) - * PSC3: GPIO (default) - * USB: 2xUART4/5 - * Ethernet: Ethernet 100Mbit with MD - * Timer: CAN2/GPIO - * PSC6/IRDA: GPIO (default) - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x1105a004 - -/* - * Motion-PRO's CPLD revision control register - */ -#define CPLD_REV_REGISTER (CONFIG_SYS_CS2_START + 0x06) - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x03e00000 /* 1 ... 62 MiB in DRAM */ -#define CONFIG_SYS_ALT_MEMTEST - -#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default kernel load addr */ - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ - -/* Not needed for MPC 5xxx U-Boot, but used by tools/updater */ -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 - -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" - -#endif /* __CONFIG_H */ diff --git a/include/configs/mpc5121-common.h b/include/configs/mpc5121-common.h deleted file mode 100644 index d252297e89..0000000000 --- a/include/configs/mpc5121-common.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * (C) Copyright 2010 DENX Software Engineering - * Anatolij Gustschin <agust@denx.de> - * - * Common configuration options for MPC5121 based boards - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __MPC5121_COMMON_H -#define __MPC5121_COMMON_H - -/* Use SRAM for initial stack */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Init RAM base */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE /* Size of area */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * Serial console - */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_CMDLINE_EDITING 1 /* command line history */ - -#endif /* __MPC5121_COMMON_H */ diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h deleted file mode 100644 index e11a0e628a..0000000000 --- a/include/configs/mpc5121ads.h +++ /dev/null @@ -1,581 +0,0 @@ -/* - * (C) Copyright 2007-2009 DENX Software Engineering - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * MPC5121ADS board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MPC5121ADS 1 - -/* - * Memory map for the MPC5121ADS board: - * - * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB) - * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB) - * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) - * 0x8200_0000 - 0x8200_001F CPLD (32 B) - * 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB) - * 0xA000_0000 - 0xAFFF_FFFF PCI memory space (256 MB) - * 0xB000_0000 - 0xBFFF_FFFF PCI memory mapped I/O space (256 MB) - * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB) - */ - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 Family */ - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -/* video */ -#ifdef CONFIG_FSL_DIU_FB -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR + 0x2100) -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#endif - -/* CONFIG_PCI is defined at config time */ - -#ifdef CONFIG_MPC5121ADS_REV2 -#define CONFIG_SYS_MPC512X_CLKIN 66000000 /* in Hz */ -#else -#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */ -#endif - -#define CONFIG_MISC_INIT_R - -#define CONFIG_SYS_IMMR 0x80000000 - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * DDR Setup - manually set all parameters as there's no SPD etc. - */ -#ifdef CONFIG_MPC5121ADS_REV2 -#define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#else -#define CONFIG_SYS_DDR_SIZE 512 /* MB */ -#endif -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 - -#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036 - -/* DDR Controller Configuration - * - * SYS_CFG: - * [31:31] MDDRC Soft Reset: Diabled - * [30:30] DRAM CKE pin: Enabled - * [29:29] DRAM CLK: Enabled - * [28:28] Command Mode: Enabled (For initialization only) - * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] - * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] - * [20:19] Read Test: DON'T USE - * [18:18] Self Refresh: Enabled - * [17:17] 16bit Mode: Disabled - * [16:13] Ready Delay: 2 - * [12:12] Half DQS Delay: Disabled - * [11:11] Quarter DQS Delay: Disabled - * [10:08] Write Delay: 2 - * [07:07] Early ODT: Disabled - * [06:06] On DIE Termination: Disabled - * [05:05] FIFO Overflow Clear: DON'T USE here - * [04:04] FIFO Underflow Clear: DON'T USE here - * [03:03] FIFO Overflow Pending: DON'T USE here - * [02:02] FIFO Underlfow Pending: DON'T USE here - * [01:01] FIFO Overlfow Enabled: Enabled - * [00:00] FIFO Underflow Enabled: Enabled - * TIME_CFG0 - * [31:16] DRAM Refresh Time: 0 CSB clocks - * [15:8] DRAM Command Time: 0 CSB clocks - * [07:00] DRAM Precharge Time: 0 CSB clocks - * TIME_CFG1 - * [31:26] DRAM tRFC: - * [25:21] DRAM tWR1: - * [20:17] DRAM tWRT1: - * [16:11] DRAM tDRR: - * [10:05] DRAM tRC: - * [04:00] DRAM tRAS: - * TIME_CFG2 - * [31:28] DRAM tRCD: - * [27:23] DRAM tFAW: - * [22:19] DRAM tRTW1: - * [18:15] DRAM tCCD: - * [14:10] DRAM tRTP: - * [09:05] DRAM tRP: - * [04:00] DRAM tRPA - */ -#ifdef CONFIG_MPC5121ADS_REV2 -#define CONFIG_SYS_MDDRC_SYS_CFG 0xE8604A00 -#define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168 -#define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864 -#else -#define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00 -#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 -#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 -#endif -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E - -#define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA 0xEA802B00 -#define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA 0x690e1189 -#define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA 0x35310864 - -#define CONFIG_SYS_DDRCMD_NOP 0x01380000 -#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 -#define CONFIG_SYS_DDRCMD_EM2 0x01020000 -#define CONFIG_SYS_DDRCMD_EM3 0x01030000 -#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000 -#define CONFIG_SYS_DDRCMD_RFSH 0x01080000 - -#define DDRCMD_EMR_OCD(pr, ohm) ( \ - (1 << 24) | /* MDDRC Command Request */ \ - (1 << 16) | /* MODE Reg BA[2:0] */ \ - (0 << 12) | /* Outputs 0=Enabled */ \ - (0 << 11) | /* RDQS */ \ - (1 << 10) | /* DQS# */ \ - (pr << 7) | /* OCD prog 7=deflt,0=exit */ \ - /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \ - ((ohm & 0x2) << 5)| /* Rtt1 */ \ - (0 << 3) | /* additive posted CAS# */ \ - ((ohm & 0x1) << 2)| /* Rtt0 */ \ - (0 << 0) | /* Output Drive Strength */ \ - (0 << 0)) /* DLL Enable 0=Normal */ - -#define CONFIG_SYS_DDRCMD_OCD_DEFAULT DDRCMD_EMR_OCD(7, 0) -#define CONFIG_SYS_ELPIDA_OCD_EXIT DDRCMD_EMR_OCD(0, 0) - -#define DDRCMD_MODE_REG(cas, wr) ( \ - (1 << 24) | /* MDDRC Command Request */ \ - (0 << 16) | /* MODE Reg BA[2:0] */ \ - ((wr-1) << 9)| /* Write Recovery */ \ - (cas << 4) | /* CAS */ \ - (0 << 3) | /* Burst Type:0=Sequential,1=Interleaved */ \ - (2 << 0)) /* 4 or 8 Burst Length:0x2=4 0x3=8 */ - -#define CONFIG_SYS_MICRON_INIT_DEV_OP DDRCMD_MODE_REG(3, 3) -#define CONFIG_SYS_ELPIDA_INIT_DEV_OP DDRCMD_MODE_REG(4, 4) -#define CONFIG_SYS_ELPIDA_RES_DLL (DDRCMD_MODE_REG(4, 4) | (1 << 8)) - -/* DDR Priority Manager Configuration */ -#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 -#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 -#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 -#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC -#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA -#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 -#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 -#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 - -/* - * NOR FLASH on the Local Bus - */ -#undef CONFIG_BKUP_FLASH -#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ -#ifdef CONFIG_BKUP_FLASH -#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* max flash size in bytes */ -#else -#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size in bytes */ -#endif -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM - -/* - * NAND FLASH - * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only) - */ -#define CONFIG_CMD_NAND /* enable NAND support */ -#define CONFIG_JFFS2_NAND /* with JFFS2 on it */ -#define CONFIG_NAND_MPC5121_NFC -#define CONFIG_SYS_NAND_BASE 0x40000000 - -#define CONFIG_SYS_MAX_NAND_DEVICE 2 -#define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */ - -/* - * Configuration parameters for MPC5121 NAND driver - */ -#define CONFIG_FSL_NFC_WIDTH 1 -#define CONFIG_FSL_NFC_WRITE_SIZE 2048 -#define CONFIG_FSL_NFC_SPARE_SIZE 64 -#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE - -/* - * CPLD registers area is really only 32 bytes in size, but the smallest possible LP - * window is 64KB - */ -#define CONFIG_SYS_CPLD_BASE 0x82000000 -#define CONFIG_SYS_CPLD_SIZE 0x00010000 /* 64 KB */ -#define CONFIG_SYS_CS2_START CONFIG_SYS_CPLD_BASE -#define CONFIG_SYS_CS2_SIZE CONFIG_SYS_CPLD_SIZE - -#define CONFIG_SYS_SRAM_BASE 0x30000000 -#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ - -#define CONFIG_SYS_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */ -#define CONFIG_SYS_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */ -#define CONFIG_SYS_CS_ALETIMING 0x00000005 /* Use alternative CS timing for CS0 and CS2 */ - -/* Use SRAM for initial stack */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of monitor */ -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#ifdef CONFIG_FSL_DIU_FB -#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ -#else -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) -#endif - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ -#define CONFIG_SYS_PSC3 -#if CONFIG_PSC_CONSOLE != 3 -#error CONFIG_PSC_CONSOLE must be 3 -#endif -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE -#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR -#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE -#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -/* - * Clocks in use - */ -#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ - CLOCK_SCCR1_DDR_EN | \ - CLOCK_SCCR1_FEC_EN | \ - CLOCK_SCCR1_LPC_EN | \ - CLOCK_SCCR1_NFC_EN | \ - CLOCK_SCCR1_PATA_EN | \ - CLOCK_SCCR1_PCI_EN | \ - CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ - CLOCK_SCCR1_PSCFIFO_EN | \ - CLOCK_SCCR1_TPR_EN) - -#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \ - CLOCK_SCCR2_I2C_EN | \ - CLOCK_SCCR2_MEM_EN | \ - CLOCK_SCCR2_SPDIF_EN | \ - CLOCK_SCCR2_USB1_EN | \ - CLOCK_SCCR2_USB2_EN) - -/* - * PCI - */ -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE - -/* - * General PCI - */ -#define CONFIG_SYS_PCI_MEM_BASE 0xA0000000 -#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE) -#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE -#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI_IO_PHYS 0x84000000 -#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */ - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#endif - -/* - * IIM - IC Identification Module - */ -#undef CONFIG_FSL_IIM - -/* - * Ethernet configuration - */ -#define CONFIG_MPC512x_FEC 1 -#define CONFIG_PHY_ADDR 0x1 -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_FEC_AN_TIMEOUT 1 -#define CONFIG_HAS_ETH0 - -/* - * Configure on-board RTC - */ -#define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* - * USB Support - */ - -#if defined(CONFIG_CMD_USB) -#define CONFIG_USB_EHCI_FSL /* On a FSL platform */ -#define CONFIG_EHCI_MMIO_BIG_ENDIAN /* With big-endian regs */ -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_IS_TDI -#endif - -/* - * Environment - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -/* This has to be a multiple of the Flash sector size */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SIZE 0x2000 -#ifdef CONFIG_BKUP_FLASH -#define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) for env */ -#else -#define CONFIG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */ -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_PCI -#endif - -/* - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=fc000000.flash,nand0=mpc5121.nand" - -/* - * NOR flash layout: - * - * FC000000 - FEABFFFF 42.75 MiB User Data - * FEAC0000 - FFABFFFF 16 MiB Root File System - * FFAC0000 - FFEBFFFF 4 MiB Linux Kernel - * FFEC0000 - FFEFFFFF 256 KiB Device Tree - * FFF00000 - FFFFFFFF 1 MiB U-Boot (up to 512 KiB) and 2 x * env - * - * NAND flash layout: one big partition - */ -#define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:43776k(user)," \ - "16m(rootfs)," \ - "4m(kernel)," \ - "256k(dtb)," \ - "1m(u-boot);" \ - "mpc5121.nand:-(data)" - -#if defined(CONFIG_IDE) || defined(CONFIG_CMD_EXT2) || defined(CONFIG_CMD_USB) -#define CONFIG_SUPPORT_VFAT - -#endif /* defined(CONFIG_IDE) */ - -/* - * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. - * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set - * to 0xFFFF, watchdog timeouts after about 64s. For details refer - * to chapter 36 of the MPC5121e Reference Manual. - */ -/* #define CONFIG_WATCHDOG */ /* enable watchdog */ -#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF - - /* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -#ifdef CONFIG_CMD_KGDB - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ - -/* Cache Configuration */ -#define CONFIG_SYS_DCACHE_SIZE 32768 -#define CONFIG_SYS_CACHELINE_SIZE 32 -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | HID0_ICE) -#define CONFIG_SYS_HID2 HID2_HBE - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_TIMESTAMP - -#define CONFIG_HOSTNAME mpc5121ads -#define CONFIG_BOOTFILE "mpc5121ads/uImage" -#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx" - -#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */ - -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "u-boot_addr_r=200000\0" \ - "kernel_addr_r=600000\0" \ - "fdt_addr_r=880000\0" \ - "ramdisk_addr_r=900000\0" \ - "u-boot_addr=FFF00000\0" \ - "kernel_addr=FFAC0000\0" \ - "fdt_addr=FFEC0000\0" \ - "ramdisk_addr=FEAC0000\0" \ - "ramdiskfile=mpc5121ads/uRamdisk\0" \ - "u-boot=mpc5121ads/u-boot.bin\0" \ - "bootfile=mpc5121ads/uImage\0" \ - "fdtfile=mpc5121ads/mpc5121ads.dtb\0" \ - "rootpath=/opt/eldk/ppc_6xx\n" \ - "netdev=eth0\0" \ - "consdev=ttyPSC0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} " \ - "console=${consdev},${baudrate}\0" \ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${fdt_addr_r} ${fdtfile};" \ - "run nfsargs addip addtty;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "net_self=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ - "tftp ${fdt_addr_r} ${fdtfile};" \ - "run ramargs addip addtty;" \ - "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ - "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ - "update=protect off ${u-boot_addr} +${filesize};" \ - "era ${u-boot_addr} +${filesize};" \ - "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ - "upd=run load update\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1 - -#define OF_CPU "PowerPC,5121@0" -#define OF_SOC_COMPAT "fsl,mpc5121-immr" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc@80000000/serial@11300" - -/*----------------------------------------------------------------------- - * IDE/ATA stuff - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for IDE not supported */ - -#define CONFIG_IDE_RESET /* reset for IDE supported */ -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_BASE_ADDR get_pata_base() - -/* Offset for data I/O RefMan MPC5121EE Table 28-10 */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers RefMan MPC5121EE Table 28-23 */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#define ATA_BASE_ADDR get_pata_base() - -/* - * Control register bit definitions - */ -#define FSL_ATA_CTRL_FIFO_RST_B 0x80000000 -#define FSL_ATA_CTRL_ATA_RST_B 0x40000000 -#define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000 -#define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000 -#define FSL_ATA_CTRL_DMA_PENDING 0x08000000 -#define FSL_ATA_CTRL_DMA_ULTRA 0x04000000 -#define FSL_ATA_CTRL_DMA_WRITE 0x02000000 -#define FSL_ATA_CTRL_IORDY_EN 0x01000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/munices.h b/include/configs/munices.h deleted file mode 100644 index ad2d69e6a5..0000000000 --- a/include/configs/munices.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * (C) Copyright 2007 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */ -#define CONFIG_MUNICES 1 /* ... on MUNICes board */ - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Command line configuration. - */ -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ -#undef CONFIG_BOOTARGS - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run net_nfs\" to load Kernel over TFTP and to mount root filesystem over NFS;" \ - "echo" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):$(netdev):off panic=5\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm $(kernel_addr)\0" \ - "flash_self=run ramargs addip;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=/tftpboot/munices/u-boot.bin\0" \ - "update=tftpboot 200000 ${bootfile};protect off fff00000 fff3ffff;" \ - "erase fff00000 fff3ffff; cp.b 200000 FFF00000 ${filesize}\0" \ - "" -#define CONFIG_BOOTCOMMAND "run net_nfs" - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */ -#if defined(CONFIG_SYS_IPBSPEED_133) -/* - * PCI Bus clocking configuration - * - * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CONFIG_SYS_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't - * been tested with a IPB Bus Clock of 66 MHz. - */ -#define CONFIG_SYS_PCISPEED_66 /* define for 66MHz speed */ -#else -#undef CONFIG_SYS_PCISPEED_66 /* for 33MHz speed */ -#endif - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR hast to be switched by other bootloader or debugger config */ - -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_BASE 0xFF000000 -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_SIZE 0x01000000 /* 16 MByte */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks (= chip selects) */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ - -/* - * Chip selects configuration - */ -/* Boot Chipselect */ -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00047800 - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET_REDUND) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x01 -#define CONFIG_MII 1 - -/* - * GPIO configuration - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x00058044 /* PSC1=UART, PSC2=UART ; Ether=100MBit with MD - no PCI */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ - -#define CONFIG_CMDLINE_EDITING 1 - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -#define OF_CPU "PowerPC,5200@0" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_SOC "soc5200@f0000000" -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" - -#endif /* __CONFIG_H */ diff --git a/include/configs/o2d.h b/include/configs/o2d.h deleted file mode 100644 index 4b36af699a..0000000000 --- a/include/configs/o2d.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2012 - * DENX Software Engineering, Anatolij Gustschin <agust@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFC000000 boot low boot high (standard configuration) - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xfc000000 /* Standard: boot low */ -#endif - -/* Board specific flash config */ -#define CONFIG_SYS_FLASH_BASE 0xfc000000 -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* maximum 64MB */ -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -/* - * Include common defines for all ifm boards - */ -#include "o2dnt-common.h" - -/* - * GPIO configuration: - * CS1 SDRAM activate + no CAN + no PCI - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x8000A004 - -/* Other board specific configs */ -#define CONFIG_SYS_BOOTCS_CFG 0x00057d01 -#define CONFIG_SYS_RESET_ADDRESS 0xfc000000 - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x07f00000 /* 1 - 127 MB in DRAM */ - -#define CONFIG_BOARD_NAME "o2d" -#define CONFIG_BOARD_BOOTCMD "run dhcp_boot" -#define CONFIG_BOARD_MEM_LIMIT __stringify(126) -#define BOARD_POST_CRC32_END __stringify(0x01000000) - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_IFM_DEFAULT_ENV_SETTINGS \ - CONFIG_IFM_DEFAULT_ENV_OLD \ - CONFIG_IFM_DEFAULT_ENV_NEW \ - "linbot=fc060000\0" \ - "lintop=fc15ffff\0" \ - "rambot=fc160000\0" \ - "ramtop=fc55ffff\0" \ - "jffbot=fc560000\0" \ - "jfftop=fcffffff\0" \ - "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ - "ubotop=fc03ffff\0" \ - "kernel_addr=0xfc060000\0" \ - "ramdisk_addr=0xfc160000\0" \ - "progCram=tftp ${fileaddr} ${cramfsname};" \ - "erase ${rambot} ${ramtop};" \ - "cp.b ${fileaddr} ${rambot} ${filesize}\0" \ - "flash_for_configs=22396\0" \ - "flash_mtd=run mtd_args addip addmem;" \ - "bootm ${kernel_addr}\0" \ - "mtd_args=setenv bootargs root=/dev/mtdblock3 " \ - "rw rootfstype=cramfs\0" \ - "master=mw f0000b00 0x8005A006;mw f0000b0c ${IOpin};" \ - "mw f0000b04 ${IOpin};mw f0000b10 0x20\0" \ - "dhcp_boot=run dhcpcmd;run flash_mtd\0" \ - "hostname=IFM_SENSOR\0" \ - "netretry=once\0" \ - "autoload=no\0" \ - "sensorType=O2D222AG\0" diff --git a/include/configs/o2d300.h b/include/configs/o2d300.h deleted file mode 100644 index a8222d9f97..0000000000 --- a/include/configs/o2d300.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * (C) Copyright 2012 - * DENX Software Engineering, Anatolij Gustschin <agust@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFC000000 boot low boot high (standard configuration) - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xfc000000 /* Standard: boot low */ -#endif - -/* Board specific flash config */ -#define CONFIG_SYS_FLASH_BASE 0xfc000000 -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* maximum 64MB */ -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -/* - * Include common defines for all ifm boards - */ -#include "o2dnt-common.h" - -/* - * GPIO configuration: - * CS1 SDRAM activate + no CAN + no PCI - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x8000A004 - -/* Other board specific configs */ -#define CONFIG_SYS_BOOTCS_CFG 0x00057d01 -#define CONFIG_SYS_RESET_ADDRESS 0xfc000000 - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x07f00000 /* 1 - 127 MB in DRAM */ - -/* Use redundant environment */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_BOARD_NAME "o2d300" -#define CONFIG_BOARD_BOOTCMD "run dhcp_boot" -#define CONFIG_BOARD_MEM_LIMIT __stringify(126) -#define BOARD_POST_CRC32_END __stringify(0x02000000) - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_IFM_DEFAULT_ENV_SETTINGS \ - CONFIG_IFM_DEFAULT_ENV_OLD \ - CONFIG_IFM_DEFAULT_ENV_NEW \ - "autoload=no\0" \ - "dhcp_boot=run dhcpcmd;run flash_mtd\0" \ - "flash_mtd=run mtd_args addip addmem;" \ - "bootm ${kernel_addr}\0" \ - "mtd_args=setenv bootargs root=/dev/mtdblock4 " \ - "rw rootfstype=cramfs\0" \ - "linbot=fc080000\0" \ - "lintop=fc17ffff\0" \ - "rambot=fc180000\0" \ - "ramtop=fc57ffff\0" \ - "jffbot=fc580000\0" \ - "jfftop=fd39ffff\0" \ - "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ - "ubotop=fc03ffff\0" \ - "halname="CONFIG_BOARD_NAME"/"CONFIG_BOARD_NAME"_halcon\0" \ - "halbot=fd3a0000\0" \ - "haltop=fdf9ffff\0" \ - "progHal=tftp 200000 ${halname};erase ${halbot} ${haltop};" \ - "cp.b ${fileaddr} ${halbot} ${filesize}\0" \ - "kernel_addr=0xfc060000\0" \ - "ramdisk_addr=0xfc160000\0" \ - "master=mw f0000b00 0x8005A006;mw f0000b0c ${IOpin};" \ - "mw f0000b04 ${IOpin};mw f0000b10 0x20\0" \ - "netretry=once\0" \ - "protcmd=protect on ${linbot} ${lintop};" \ - "protect on ${rambot} ${ramtop}\0" \ - "o2derror=def_env\0" \ - "sensorType=O2D300AA\0" diff --git a/include/configs/o2dnt-common.h b/include/configs/o2dnt-common.h deleted file mode 100644 index 1b4200bcbf..0000000000 --- a/include/configs/o2dnt-common.h +++ /dev/null @@ -1,300 +0,0 @@ -/* - * Common configuration options for ifm camera boards - * - * (C) Copyright 2005 - * Sebastien Cazaux, ifm electronic gmbh - * - * (C) Copyright 2012 - * DENX Software Engineering, Anatolij Gustschin <agust@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __O2D_CONFIG_H -#define __O2D_CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_MPC5200 - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* running at 33.000000MHz */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -/* log base 2 of the above value */ -#define CONFIG_SYS_CACHELINE_SHIFT 5 -#endif - -/* -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_I2C) -*/ - -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4) -#endif - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 5 /* console is on PSC5 */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_SYS_XLB_PIPELINING 1 - -/* Partitions */ - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_SYS_ALT_MEMTEST /* Much more complex memory test */ - -/* - * Supported commands - */ -#ifdef CONFIG_PCI -#define CONFIG_CMD_PCI -#endif - -#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) || (CONFIG_SYS_TEXT_BASE == 0xFF000000) -/* Boot low with 16 or 32 MB Flash */ -#define CONFIG_SYS_LOWBOOT 1 -#elif (CONFIG_SYS_TEXT_BASE != 0x00100000) -#error "CONFIG_SYS_TEXT_BASE value is invalid" -#endif - - -#define CONFIG_PREBOOT "run master" - -#undef CONFIG_BOOTARGS - -#if !defined(CONSOLE_DEV) -#define CONSOLE_DEV "ttyPSC1" -#endif - -/* - * Default environment for booting old and new kernel versions - */ -#define CONFIG_IFM_DEFAULT_ENV_OLD \ - "flash_self_old=run ramargs addip addmem;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs_old=run nfsargs addip addmem;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \ - "run nfsargs addip addmem;" \ - "bootm ${kernel_addr_r}\0" - -#define CONFIG_IFM_DEFAULT_ENV_NEW \ - "fdt_addr_r=900000\0" \ - "fdt_file="CONFIG_BOARD_NAME"/"CONFIG_BOARD_NAME".dtb\0" \ - "flash_self=run ramargs addip addtty addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "flash_nfs=run nfsargs addip addtty addmisc;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "tftp ${fdt_addr_r} ${fdt_file}; " \ - "run nfsargs addip addtty addmisc;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - -#define CONFIG_IFM_DEFAULT_ENV_SETTINGS \ - "IOpin=0x64\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addmem=setenv bootargs ${bootargs} ${memlimit}\0" \ - "addmisc=sete bootargs ${bootargs} ${miscargs}\0" \ - "addtty=sete bootargs ${bootargs} console=" \ - CONSOLE_DEV ",${baudrate}\0" \ - "bootfile="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0" \ - "kernel_addr_r=600000\0" \ - "initrd_high=0x03e00000\0" \ - "memlimit=mem="CONFIG_BOARD_MEM_LIMIT"M\0" \ - "memtest=mtest 0x00100000 "__stringify(CONFIG_SYS_MEMTEST_END)" 0 1\0" \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "linuxname="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0"\ - "progLinux=tftp 200000 ${linuxname};erase ${linbot} ${lintop};" \ - "cp.b ${fileaddr} ${linbot} ${filesize}\0" \ - "ramname="CONFIG_BOARD_NAME"/uRamdisk_"CONFIG_BOARD_NAME"_act\0"\ - "progRam=tftp 200000 ${ramname};erase ${rambot} ${ramtop};" \ - "cp.b ${fileaddr} ${rambot} ${filesize}\0" \ - "jffname="CONFIG_BOARD_NAME"/uJFFS2_"CONFIG_BOARD_NAME"_act\0" \ - "progJff=tftp 200000 ${jffname};erase ${jffbot} ${jfftop};" \ - "cp.b ${fileaddr} ${jffbot} ${filesize}\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "uboname=" CONFIG_BOARD_NAME \ - "/u-boot.bin_" CONFIG_BOARD_NAME "_act\0" \ - "progubo=tftp 200000 ${uboname};" \ - "protect off ${ubobot} ${ubotop};" \ - "erase ${ubobot} ${ubotop};" \ - "cp.b ${fileaddr} ${ubobot} ${filesize}\0" \ - "unlock=yes\0" \ - "post=echo !!! "CONFIG_BOARD_NAME" POWER ON SELF TEST !!!;" \ - "setenv bootdelay 1;" \ - "crc32 "__stringify(CONFIG_SYS_TEXT_BASE)" " \ - BOARD_POST_CRC32_END";" \ - "setenv bootcmd "CONFIG_BOARD_BOOTCMD";saveenv;reset\0" - -#define CONFIG_BOOTCOMMAND "run post" - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) -/* - * PCI Bus clocking configuration - * - * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock - * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. - */ -#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ -#endif - -/* - * There is no write delay with FRAM, write operations are performed at bus - * speed. Thus, no status polling or write delay is needed. - */ - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_FLASH_16BIT -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_FLASH_CFI_AMD_RESET -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (in ms) */ -/* Timeout for Flash Clear Lock Bits (in ms) */ -#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 -/* "Real" (hardware) sectors protection */ -#define CONFIG_SYS_FLASH_PROTECTION - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE -#else -/* End of used area in DPRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE -#endif - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial map for Linux */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT 1 -#endif - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_RESET_PHY_R - -/* - * GPIO configuration - */ -#define CONFIG_SYS_GPIO_DATADIR 0x00000064 /* PSC1_2, PSC2_1,2 output */ -#define CONFIG_SYS_GPIO_OPENDRAIN 0x00000000 /* No open drain */ -#define CONFIG_SYS_GPIO_DATAVALUE 0x00000000 /* PSC1_1 to 1, rest to 0 */ -#define CONFIG_SYS_GPIO_ENABLE 0x00000064 /* PSC1_2, PSC2_1,2 enable */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x100000 - -/* decrementer freq: 1 ms ticks */ - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_BOARD_EARLY_INIT_R - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -/* - * DT support - */ -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) - -#endif /* __O2D_CONFIG_H */ diff --git a/include/configs/o2dnt2.h b/include/configs/o2dnt2.h deleted file mode 100644 index 00a8d9618d..0000000000 --- a/include/configs/o2dnt2.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * (C) Copyright 2012 - * DENX Software Engineering, Anatolij Gustschin <agust@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFC000000 boot low boot high (standard configuration) - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xfc000000 /* Standard: boot low */ -#endif - -/* Board specific flash config */ -#define CONFIG_SYS_FLASH_BASE 0xfc000000 -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* maximum 64MB */ -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -/* - * Include common defines for all ifm boards - */ -#include "o2dnt-common.h" - -/* - * GPIO configuration: - * CS1 SDRAM activate + no CAN + no PCI - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x8000A004 - -/* Other board specific configs */ -#define CONFIG_SYS_BOOTCS_CFG 0x00057d01 -#define CONFIG_SYS_RESET_ADDRESS 0xfc000000 - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x07f00000 /* 1 - 127 MB in DRAM */ - -#define CONFIG_BOARD_NAME "o2dnt2" -#define CONFIG_BOARD_BOOTCMD "run flash_self" -#define CONFIG_BOARD_MEM_LIMIT __stringify(126) -#define BOARD_POST_CRC32_END __stringify(0x01000000) - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_IFM_DEFAULT_ENV_SETTINGS \ - CONFIG_IFM_DEFAULT_ENV_OLD \ - CONFIG_IFM_DEFAULT_ENV_NEW \ - "linbot=fc060000\0" \ - "lintop=fc15ffff\0" \ - "rambot=fc160000\0" \ - "ramtop=fc55ffff\0" \ - "jffbot=fc560000\0" \ - "jfftop=fce5ffff\0" \ - "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ - "ubotop=fc03ffff\0" \ - "calname="CONFIG_BOARD_NAME"/uCal_"CONFIG_BOARD_NAME"_act\0" \ - "calbot=fce60000\0" \ - "caltop=fcffffff\0" \ - "progCal=tftp 200000 ${calname};erase ${calbot} ${caltop};" \ - "cp.b ${fileaddr} ${calbot} ${filesize}\0" \ - "kernel_addr=0xfc060000\0" \ - "ramdisk_addr=0xfc160000\0" \ - "master=mw f0000b00 0x8005A006;mw f0000b0c ${IOpin};" \ - "mw f0000b04 ${IOpin};mw f0000b10 0x20\0" diff --git a/include/configs/o2i.h b/include/configs/o2i.h deleted file mode 100644 index c0fcedaf10..0000000000 --- a/include/configs/o2i.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * (C) Copyright 2012 - * DENX Software Engineering, Anatolij Gustschin <agust@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFF000000 boot low boot high (standard configuration) - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xff000000 /* Standard: boot low */ -#endif - -/* Board specific flash config */ -#define CONFIG_SYS_FLASH_BASE 0xff000000 -#define CONFIG_SYS_FLASH_SIZE 0x01000000 /* maximum 16MB */ -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 - -/* - * Include common defines for all ifm boards - */ -#include "o2dnt-common.h" - -/* GPIO configuration */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x00002006 /* no CAN */ - -/* Other board specific configs */ -#define CONFIG_SYS_BOOTCS_CFG 0x00087801 -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x03f00000 /* 1 - 63 MB in DRAM */ - -#define CONFIG_BOARD_NAME "o2i" -#define CONFIG_BOARD_BOOTCMD "run dhcp_boot" -#define CONFIG_BOARD_MEM_LIMIT __stringify(62) -#define BOARD_POST_CRC32_END __stringify(0x01000000) - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_IFM_DEFAULT_ENV_SETTINGS \ - CONFIG_IFM_DEFAULT_ENV_OLD \ - CONFIG_IFM_DEFAULT_ENV_NEW \ - "linbot=ff060000\0" \ - "lintop=ff15ffff\0" \ - "rambot=ff160000\0" \ - "ramtop=ff55ffff\0" \ - "jffbot=ff560000\0" \ - "jfftop=ffebffff\0" \ - "kernel_addr=0xff060000\0" \ - "ramdisk_addr=0xff160000\0" \ - "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ - "ubotop=ff03ffff\0" \ - "autoload=no\0" \ - "dhcp_boot=run dhcpcmd; run flash_mtd\0" \ - "hostname=IFM_SENSOR\0" \ - "flash_mtd=run mtd_args addip addmem;bootm ${kernel_addr}\0" \ - "mtd_args=setenv bootargs root=/dev/mtdblock3 " \ - "rw rootfstype=cramfs\0" \ - "sensorType=O2I100AA\0" \ - "netretry=once\0" \ - "master=mw f0000b00 0x00052006;mw f0000b0c ${IOpin};" \ - "mw f0000b04 ${IOpin};mw f0000b10 0x20\0" diff --git a/include/configs/o2mnt.h b/include/configs/o2mnt.h deleted file mode 100644 index eb63cb0c85..0000000000 --- a/include/configs/o2mnt.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2012 - * DENX Software Engineering, Anatolij Gustschin <agust@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFF000000 boot low boot high (standard configuration) - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xff000000 /* Standard: boot low */ -#endif - -/* Board specific flash config */ -#define CONFIG_SYS_FLASH_BASE 0xff000000 -#define CONFIG_SYS_FLASH_SIZE 0x01000000 /* maximum 16MB */ -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 - -/* - * Include common defines for all ifm boards - */ -#include "o2dnt-common.h" - -/* GPIO configuration */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x00002004 /* no CAN */ - -/* Other board specific configs */ -#define CONFIG_NETCONSOLE - -#define CONFIG_SYS_BOOTCS_CFG 0x00087801 -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x03f00000 /* 1 - 63 MB in DRAM */ - -#define CONFIG_BOARD_NAME "o2mnt" -#define CONFIG_BOARD_BOOTCMD "${newcmd}" -#define CONFIG_BOARD_MEM_LIMIT __stringify(62) -#define BOARD_POST_CRC32_END __stringify(0x01000000) - -#ifndef CONFIG_IFM_SENSOR_TYPE -#define CONFIG_IFM_SENSOR_TYPE "O2M110" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_IFM_DEFAULT_ENV_SETTINGS \ - CONFIG_IFM_DEFAULT_ENV_OLD \ - CONFIG_IFM_DEFAULT_ENV_NEW \ - "linbot=ff060000\0" \ - "lintop=ff25ffff\0" \ - "rambot=ff260000\0" \ - "ramtop=ffc5ffff\0" \ - "jffbot=ffc60000\0" \ - "jfftop=ffffffff\0" \ - "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ - "ubotop=ff03ffff\0" \ - "kernel_addr=0xff060000\0" \ - "ramdisk_addr=0xff260000\0" \ - "newcmd=run scrprot;run flash_ext2\0" \ - "scrprot=protect on ${linbot} ${lintop};protect on ${rambot} " \ - "${ramtop}\0" \ - "flash_ext2=run ext2args addip addmem;bootm ${kernel_addr}\0" \ - "ext2args=setenv bootargs root=/dev/mtdblock3 ro " \ - "rootfstype=ext2\0" \ - "pwm=mw f0000674 0x10006;mw f0000678 0x30000;" \ - "mw f0000678 0x30001;mw f0000670 0x3\0" \ - "master=mw f0000b00 0x00052006;mw f0000b0c $(IOpin);" \ - "mw f0000b04 $(IOpin);mw f0000b10 0x24;run pwm\0" \ - "sensortyp="CONFIG_IFM_SENSOR_TYPE"\0" \ - "srelease=0.00\0" diff --git a/include/configs/o3dnt.h b/include/configs/o3dnt.h deleted file mode 100644 index f0fcedaffc..0000000000 --- a/include/configs/o3dnt.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2012 - * DENX Software Engineering, Anatolij Gustschin <agust@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFC000000 boot low boot high (standard configuration) - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xfc000000 /* Standard: boot low */ -#endif - -/* Board specific flash config */ -#define CONFIG_SYS_FLASH_BASE 0xfc000000 -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* maximum 64MB */ -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -/* - * Include common defines for all ifm boards - */ -#include "o2dnt-common.h" - -/* Additional commands */ -#define CONFIG_CMD_REGINFO - -/* - * GPIO configuration: - * no CAN + no PCI - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x0000A000 - -/* Other board specific configs */ -#define CONFIG_SYS_BOOTCS_CFG 0x00057d01 -#define CONFIG_SYS_RESET_ADDRESS 0xfc000000 - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x03f00000 /* 1 - 63 MB in DRAM */ - -#define CONFIG_BOARD_NAME "o3dnt" -#define CONFIG_BOARD_BOOTCMD "run flash_self" -#define CONFIG_BOARD_MEM_LIMIT __stringify(62) -#define BOARD_POST_CRC32_END __stringify(0x01000000) - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_IFM_DEFAULT_ENV_SETTINGS \ - CONFIG_IFM_DEFAULT_ENV_OLD \ - CONFIG_IFM_DEFAULT_ENV_NEW \ - "linbot=fc060000\0" \ - "lintop=fc15ffff\0" \ - "rambot=fc160000\0" \ - "ramtop=fc55ffff\0" \ - "jffbot=fc560000\0" \ - "jfftop=fce5ffff\0" \ - "ubobot=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ - "ubotop=fc03ffff\0" \ - "calname="CONFIG_BOARD_NAME"/uCal_"CONFIG_BOARD_NAME"_act\0" \ - "calbot=fce60000\0" \ - "caltop=fcffffff\0" \ - "progCal=tftp 200000 ${calname};erase ${calbot} ${caltop};" \ - "cp.b ${fileaddr} ${calbot} ${filesize}\0" \ - "kernel_addr=0xfc060000\0" \ - "ramdisk_addr=0xfc160000\0" \ - "master=mw f0000b00 0x0005A006;mw f0000b0c ${IOpin};" \ - "mw f0000b04 ${IOpin};mw f0000b10 0x20\0" diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index d8b0c023b9..e7fac6d1e1 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -37,7 +37,7 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ #define CONFIG_ENV_SIZE (128 << 10) -#define CONFIG_ENV_OFFSET 0xE0000 +#define CONFIG_ENV_OFFSET 0x260000 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) #define CONFIG_SYS_REDUNDAND_ENVIRONMENT diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 8904cd5cc7..5f118950aa 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -110,7 +110,7 @@ (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ - (10 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ + (20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ (2 << DV_DDR_SDTMR2_CKE_SHIFT)) @@ -341,4 +341,7 @@ #define CONFIG_SYS_SDRAM_BASE 0xc0000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ GENERATED_GBL_DATA_SIZE) + +#include <asm/arch/hardware.h> + #endif /* __CONFIG_H */ diff --git a/include/configs/pcm030.h b/include/configs/pcm030.h deleted file mode 100644 index 6da17be11c..0000000000 --- a/include/configs/pcm030.h +++ /dev/null @@ -1,378 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2006 - * Eric Schumann, Phytec Messatechnik GmbH - * - * (C) Copyright 2009 - * Jon Smirl <jonsmirl@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_BOARDINFO "phyCORE-MPC5200B-tiny" - -/*----------------------------------------------------------------------------- -High Level Configuration Options -(easy to change) ------------------------------------------------------------------------------*/ -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */ -#define CONFIG_PHYCORE_MPC5200B_TINY 1 /* phyCORE-MPC5200B -> */ - /* FEC configuration and IDE */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFFF00000 boot high (standard configuration) - * 0xFF000000 boot low - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */ - -/*----------------------------------------------------------------------------- -Serial console configuration ------------------------------------------------------------------------------*/ -#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 -> */ - /*define gps port conf. */ - /* register later on to */ - /*enable UART function! */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * Command line configuration. - */ -#define CONFIG_CMD_PCI - -#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ - -#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low */ -#define CONFIG_SYS_LOWBOOT 1 -#endif -/* RAMBOOT will be defined automatically in memory section */ - -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=physmap-flash.0" -#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \ - "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)" - -#undef CONFIG_BOOTARGS - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run bootcmd_net\" to load Kernel over TFTP and to "\ - "mount root filesystem over NFS;" \ - "echo" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uimage=uImage-pcm030\0" \ - "oftree=oftree-pcm030.dtb\0" \ - "jffs2=root-pcm030.jffs2\0" \ - "uboot=u-boot-pcm030.bin\0" \ - "bargs_base=setenv bootargs console=ttyPSC0,$(baudrate)" \ - " $(mtdparts) rw\0" \ - "bargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2" \ - " rootfstype=jffs2\0" \ - "bargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs" \ - " ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)::" \ - "$(netdev):off nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ - "bcmd_net=run bargs_base bargs_nfs; tftpboot 0x500000 $(uimage);" \ - " tftp 0x400000 $(oftree); bootm 0x500000 - 0x400000\0" \ - "bcmd_flash=run bargs_base bargs_flash; bootm 0xff040000 - " \ - "0xfff40000\0" \ - " cp.b 0x400000 0xff040000 $(filesize)\0" \ - "prg_jffs2=tftp 0x400000 $(jffs2); erase 0xff200000 0xffefffff; " \ - "cp.b 0x400000 0xff200000 $(filesize)\0" \ - "prg_oftree=tftp 0x400000 $(oftree); erase 0xfff40000 0xfff5ffff;" \ - " cp.b 0x400000 0xfff40000 $(filesize)\0" \ - "update=tftpboot 0x400000 $(uboot);erase 0xFFF00000 0xfff3ffff;" \ - " cp.b 0x400000 0xFFF00000 $(filesize)\0" \ - "unlock=yes\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run bcmd_flash" - -/*-------------------------------------------------------------------------- -IPB Bus clocking configuration. - ---------------------------------------------------------------------------*/ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/*------------------------------------------------------------------------- - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - * -----------------------------------------------------------------------*/ -#define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 -#define CONFIG_SYS_XLB_PIPELINING 1 - -/*--------------------------------------------------------------------------- - Flash configuration ----------------------------------------------------------------------------*/ - -#define CONFIG_SYS_FLASH_BASE 0xff000000 -#define CONFIG_SYS_FLASH_SIZE 0x01000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_MAX_FLASH_SECT 260 /* max num of sects on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ - /* (= chip selects) */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE - -/* - * Use also hardware protection. This seems required, as the BDI uses - * hardware protection. Without this, U-Boot can't work with this sectors, - * as its protection is software only by default - */ -#define CONFIG_SYS_FLASH_PROTECTION 1 - -/*--------------------------------------------------------------------------- - Environment settings ----------------------------------------------------------------------------*/ - -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */ - /*beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 2048 - -#define CONFIG_ENV_OVERWRITE 1 - -/*----------------------------------------------------------------------------- - Memory map ------------------------------------------------------------------------------*/ -#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */ - /* bootloader or debugger config */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used */ - /* area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------------- - Ethernet configuration ------------------------------------------------------------------------------*/ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x01 - -/*--------------------------------------------------------------------------- - GPIO configuration - ---------------------------------------------------------------------------*/ - -/* GPIO port configuration - * - * Pin mapping: - * - * [29:31] = 01x - * PSC1_0 -> AC97 SDATA out - * PSC1_1 -> AC97 SDTA in - * PSC1_2 -> AC97 SYNC out - * PSC1_3 -> AC97 bitclock out - * PSC1_4 -> AC97 reset out - * - * [25:27] = 001 - * PSC2_0 -> CAN 1 Tx out - * PSC2_1 -> CAN 1 Rx in - * PSC2_2 -> CAN 2 Tx out - * PSC2_3 -> CAN 2 Rx in - * PSC2_4 -> GPIO (claimed for ATA reset, active low) - * - * - * [20:23] = 1100 - * PSC3_0 -> UART Tx out - * PSC3_1 -> UART Rx in - * PSC3_2 -> UART RTS (in/out FIXME) - * PSC3_3 -> UART CTS (in/out FIXME) - * PSC3_4 -> LocalPlus Bus CS6 \ - * PSC3_5 -> LocalPlus Bus CS7 / --> see [4] and [5] - * PSC3_6 -> dedicated SPI MOSI out (master case) - * PSC3_7 -> dedicated SPI MISO in (master case) - * PSC3_8 -> dedicated SPI SS out (master case) - * PSC3_9 -> dedicated SPI CLK out (master case) - * - * [18:19] = 01 - * USB_0 -> USB OE out - * USB_1 -> USB Tx- out - * USB_2 -> USB Tx+ out - * USB_3 -> USB RxD (in/out FIXME) - * USB_4 -> USB Rx+ in - * USB_5 -> USB Rx- in - * USB_6 -> USB PortPower out - * USB_7 -> USB speed out - * USB_8 -> USB suspend (in/out FIXME) - * USB_9 -> USB overcurrent in - * - * [17] = 0 - * USB differential mode - * - * [16] = 0 - * PCI enabled - * - * [12:15] = 0101 - * ETH_0 -> ETH Txen - * ETH_1 -> ETH TxD0 - * ETH_2 -> ETH TxD1 - * ETH_3 -> ETH TxD2 - * ETH_4 -> ETH TxD3 - * ETH_5 -> ETH Txerr - * ETH_6 -> ETH MDC - * ETH_7 -> ETH MDIO - * ETH_8 -> ETH RxDv - * ETH_9 -> ETH RxCLK - * ETH_10 -> ETH Collision - * ETH_11 -> ETH TxD - * ETH_12 -> ETH RxD0 - * ETH_13 -> ETH RxD1 - * ETH_14 -> ETH RxD2 - * ETH_15 -> ETH RxD3 - * ETH_16 -> ETH Rxerr - * ETH_17 -> ETH CRS - * - * [9:11] = 101 - * PSC6_0 -> UART RxD in - * PSC6_1 -> UART CTS (in/out FIXME) - * PSC6_2 -> UART TxD out - * PSC6_3 -> UART RTS (in/out FIXME) - * - * [2:3/6:7] = 00/11 - * TMR_0 -> ATA_CS0 out - * TMR_1 -> ATA_CS1 out - * TMR_2 -> GPIO - * TMR_3 -> GPIO - * TMR_4 -> GPIO - * TMR_5 -> GPIO - * TMR_6 -> GPIO - * TMR_7 -> GPIO - * I2C_0 -> I2C 1 Clock out - * I2C_1 -> I2C 1 IO in/out - * I2C_2 -> I2C 2 Clock out - * I2C_3 -> I2C 2 IO in/out - * - * [4] = 1 - * PSC3_5 is used as CS7 - * - * [5] = 1 - * PSC3_4 is used as CS6 - * - * [1] = 0 - * gpio_wkup_7 is GPIO - * - * [0] = 0 - * gpio_wkup_6 is GPIO - * - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x0f551c12 - -/*----------------------------------------------------------------------------- - Miscellaneous configurable options --------------------------------------------------------------------------------*/ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ - -/*----------------------------------------------------------------------------- - Various low-level settings ------------------------------------------------------------------------------*/ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -/* no burst access on the LPB */ -#define CONFIG_SYS_CS_BURST 0x00000000 -/* one deadcycle for the 33MHz statemachine */ -#define CONFIG_SYS_CS_DEADCYCLE 0x33333331 -/* one additional waitstate for the 33MHz statemachine */ -#define CONFIG_SYS_BOOTCS_CFG 0x0001dd00 -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/*--------------------------------------------------------------------------- - IDE/ATA stuff Supports IDE harddisk -----------------------------------------------------------------------------*/ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ -#define CONFIG_SYS_ATA_CS_ON_TIMER01 -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ -#define CONFIG_IDE_PREINIT -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 -#define CONFIG_ATAPI 1 - -/* USB */ -#define CONFIG_USB_OHCI - -/* pass open firmware flat tree */ -#define OF_CPU "PowerPC,5200@0" -#define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN -#define OF_SOC "soc5200@f0000000" -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2400" - -#endif /* __CONFIG_H */ diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h deleted file mode 100644 index 676d55f5e8..0000000000 --- a/include/configs/pdm360ng.h +++ /dev/null @@ -1,420 +0,0 @@ -/* - * (C) Copyright 2009-2010 - * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * pdm360ng board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_PDM360NG 1 - -/* - * Memory map for the PDM360NG board: - * - * 0x0000_0000 - 0x1FFF_FFFF DDR RAM (512 MB) - * 0x2000_0000 - 0x3FFF_FFFF reserved (DDR RAM (512 MB) - * 0x5000_0000 - 0x5001_FFFF SRAM (128 KB) - * 0x5004_0000 - 0x5005_FFFF MRAM (CS2) (128 KB) - * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) - * 0xF000_0000 - 0xF7FF_FFFF NOR FLASH (CS0) (128 MB) - * 0xF800_0000 - 0xFFFF_FFFF NOR FLASH (CS1) (128 MB) optional - */ - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ - -#define CONFIG_SYS_TEXT_BASE 0xF0000000 - -/* Used for silent command in environment */ -#define CONFIG_SYS_DEVICE_NULLDEV - -/* Video */ - -#if defined(CONFIG_VIDEO) -#define CONFIG_SPLASH_SCREEN -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_RLE8 -#endif - -#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_SYS_IMMR 0x80000000 -#define CONFIG_SYS_DIU_ADDR ((CONFIG_SYS_IMMR) + 0x2100) - -/* - * DDR Setup - */ - -/* DDR is system memory */ -#define CONFIG_SYS_DDR_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_MAX_RAM_SIZE 0x40000000 - -/* DDR pin mux and slew rate */ -#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000012 - -/* Manually set all parameters as there's no SPD etc. */ -/* - * DDR Controller Configuration for Micron DDR2 SDRAM MT47H128M8-3 - * - * SYS_CFG: - * [31:31] MDDRC Soft Reset: Diabled - * [30:30] DRAM CKE pin: Enabled - * [29:29] DRAM CLK: Enabled - * [28:28] Command Mode: Enabled (For initialization only) - * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] - * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] - * [20:19] Read Test: DON'T USE - * [18:18] Self Refresh: Enabled - * [17:17] 16bit Mode: Disabled - * [16:13] Read Delay: 3 - * [12:12] Half DQS Delay: Disabled - * [11:11] Quarter DQS Delay: Disabled - * [10:08] Write Delay: 2 - * [07:07] Early ODT: Disabled - * [06:06] On DIE Termination: Enabled - * [05:05] FIFO Overflow Clear: DON'T USE here - * [04:04] FIFO Underflow Clear: DON'T USE here - * [03:03] FIFO Overflow Pending: DON'T USE here - * [02:02] FIFO Underlfow Pending: DON'T USE here - * [01:01] FIFO Overlfow Enabled: Enabled - * [00:00] FIFO Underflow Enabled: Enabled - * TIME_CFG0 - * [31:16] DRAM Refresh Time: 0 CSB clocks - * [15:8] DRAM Command Time: 0 CSB clocks - * [07:00] DRAM Precharge Time: 0 CSB clocks - * TIME_CFG1 - * [31:26] DRAM tRFC: - * [25:21] DRAM tWR1: - * [20:17] DRAM tWRT1: - * [16:11] DRAM tDRR: - * [10:05] DRAM tRC: - * [04:00] DRAM tRAS: - * TIME_CFG2 - * [31:28] DRAM tRCD: - * [27:23] DRAM tFAW: - * [22:19] DRAM tRTW1: - * [18:15] DRAM tCCD: - * [14:10] DRAM tRTP: - * [09:05] DRAM tRP: - * [04:00] DRAM tRPA - */ -#define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A40 -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E -#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 -#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 - -/* - * Alternative 1: small RAM (128 MB) configuration - */ -#define CONFIG_SYS_MDDRC_SYS_CFG_ALT1 0xE8604A40 -#define CONFIG_SYS_MDDRC_TIME_CFG0_ALT1 0x030C3D2E -#define CONFIG_SYS_MDDRC_TIME_CFG1_ALT1 0x3CEC1168 -#define CONFIG_SYS_MDDRC_TIME_CFG2_ALT1 0x33310863 - -#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 - -#define CONFIG_SYS_DDRCMD_NOP 0x01380000 -#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 -#define CONFIG_SYS_DDRCMD_EM2 0x01020000 /* EMR2 */ -#define CONFIG_SYS_DDRCMD_EM3 0x01030000 /* EMR3 */ -/* EMR with 150 ohm ODT todo: verify */ -#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010040 -#define CONFIG_SYS_DDRCMD_RES_DLL 0x01000100 -#define CONFIG_SYS_DDRCMD_RFSH 0x01080000 -#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -/* EMR with 150 ohm ODT todo: verify */ -#define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x010107C0 -/* EMR new command with 150 ohm ODT todo: verify */ -#define CONFIG_SYS_DDRCMD_OCD_EXIT 0x01010440 - -/* DDR Priority Manager Configuration */ -#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 -#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 -#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 -#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC -#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA -#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 -#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 -#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 - -/* - * NOR FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_CFI /* use Common Flash Interface */ -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE - -#define CONFIG_SYS_FLASH_BASE 0xF0000000 /* start of FLASH-Bank0 */ -#define CONFIG_SYS_FLASH_SIZE 0x08000000 /* max size of a Bank */ -/* start of FLASH-Bank1 */ -#define CONFIG_SYS_FLASH1_BASE (CONFIG_SYS_FLASH_BASE + \ - CONFIG_SYS_FLASH_SIZE) -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST \ - {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH1_BASE} - -#define CONFIG_SYS_SRAM_BASE 0x50000000 -#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ - -#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH1_BASE -#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE - -/* ALE active low, data size 4 bytes */ -#define CONFIG_SYS_CS0_CFG 0x05059350 -/* ALE active low, data size 4 bytes */ -#define CONFIG_SYS_CS1_CFG 0x05059350 - -#define CONFIG_SYS_MRAM_BASE 0x50040000 -#define CONFIG_SYS_MRAM_SIZE 0x00020000 -#define CONFIG_SYS_CS2_START CONFIG_SYS_MRAM_BASE -#define CONFIG_SYS_CS2_SIZE CONFIG_SYS_MRAM_SIZE - -/* ALE active low, data size 4 bytes */ -#define CONFIG_SYS_CS2_CFG 0x05059110 - -/* alt. CS timing for CS0, CS1, CS2 */ -#define CONFIG_SYS_CS_ALETIMING 0x00000007 - -/* - * NAND FLASH - */ -#define CONFIG_CMD_NAND /* enable NAND support */ -#define CONFIG_NAND_MPC5121_NFC -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */ - -/* - * Configuration parameters for MPC5121 NAND driver - */ -#define CONFIG_FSL_NFC_WIDTH 1 -#define CONFIG_FSL_NFC_WRITE_SIZE 2048 -#define CONFIG_FSL_NFC_SPARE_SIZE 64 -#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE - -/* - * Dynamic MTD partition support - */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=f0000000.flash,nor1=f8000000.flash," \ - "nand0=MPC5121 NAND" - -/* - * Flash layout - */ -#define MTDPARTS_DEFAULT "mtdparts=f0000000.flash:512k(u-boot)," \ - "256k(environment1)," \ - "256k(environment2)," \ - "256k(splash-factory)," \ - "2m(FIT: recovery)," \ - "4608k(fs-recovery)," \ - "256k(splash-customer),"\ - "5m(FIT: kernel+dtb)," \ - "64m(rootfs squash)ro," \ - "51m(userfs ubi);" \ - "f8000000.flash:-(unused);" \ - "MPC5121 NAND:1024m(extended-userfs)" - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of monitor */ -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* 512 kB for monitor */ -#ifdef CONFIG_FSL_DIU_FB -#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* for malloc */ -#else -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) -#endif - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 6 /* console is on PSC6 */ -#if CONFIG_PSC_CONSOLE != 6 -#error CONFIG_PSC_CONSOLE must be 6 -#endif - -#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC6_TX_SIZE -#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC6_TX_ADDR -#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC6_RX_SIZE -#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC6_RX_ADDR - -/* - * Clocks in use - */ -#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ - CLOCK_SCCR1_LPC_EN | \ - CLOCK_SCCR1_NFC_EN | \ - CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ - CLOCK_SCCR1_PSCFIFO_EN | \ - CLOCK_SCCR1_DDR_EN | \ - CLOCK_SCCR1_FEC_EN | \ - CLOCK_SCCR1_TPR_EN) - -#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ - CLOCK_SCCR2_SPDIF_EN | \ - CLOCK_SCCR2_DIU_EN | \ - CLOCK_SCCR2_I2C_EN) - -/* - * Used PSC UART devices - */ -#define CONFIG_SYS_PSC1 -#define CONFIG_SYS_PSC4 -#define CONFIG_SYS_PSC6 - -/* - * Co-processor communication parameters - */ -#define CONFIG_SYS_PDM360NG_COPROC_READ_DELAY 5000 -#define CONFIG_SYS_PDM360NG_COPROC_BAUDRATE 38400 - -/* - * IIM - IC Identification Module - */ -#undef CONFIG_FSL_IIM - -/* - * Enabled only to delete "ethaddr" before testing - * "ethaddr" setting from EEPROM - */ -#define CONFIG_ENV_OVERWRITE - -/* - * Ethernet configuration - */ -#define CONFIG_MPC512x_FEC 1 -#define CONFIG_PHY_ADDR 0x1F -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_FEC_AN_TIMEOUT 1 -#define CONFIG_HAS_ETH0 - -/* - * Environment - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -/* This has to be a multiple of the Flash sector size */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_CMD_REGINFO - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -#ifdef CONFIG_CMD_KGDB - #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else - #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -/* Max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* Decrementer freq: 1ms ticks */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -/* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) - -/* Cache Configuration */ -#define CONFIG_SYS_DCACHE_SIZE 32768 -#define CONFIG_SYS_CACHELINE_SIZE 32 -#ifdef CONFIG_CMD_KGDB -/* log base 2 of the above value */ -#define CONFIG_SYS_CACHELINE_SHIFT 5 -#endif - -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | HID0_ICE) -#define CONFIG_SYS_HID2 HID2_HBE - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_COPROC) - -/* - * Environment Configuration - */ -#define CONFIG_TIMESTAMP - -#define CONFIG_HOSTNAME pdm360ng -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 400000 - - -#define CONFIG_PREBOOT "echo;" \ - "echo PDM360NG SAMPLE;" \ - "echo" - -#define CONFIG_BOOTCOMMAND "run env_cont" - -#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1 - -#define OF_CPU "PowerPC,5121@0" -#define OF_SOC_COMPAT "fsl,mpc5121-immr" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc@80000000/serial@11600" - -/* - * Include common options for all mpc5121 boards - */ -#include "mpc5121-common.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/puma_rk3399.h b/include/configs/puma_rk3399.h index f778744319..af1dae88ed 100644 --- a/include/configs/puma_rk3399.h +++ b/include/configs/puma_rk3399.h @@ -22,4 +22,12 @@ #define SDRAM_BANK_SIZE (2UL << 30) +#define CONFIG_MISC_INIT_R +#define CONFIG_SERIAL_TAG +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BMP_16BPP +#define CONFIG_BMP_24BPP +#define CONFIG_BMP_32BPP + #endif diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 7ccbc9b241..5a06244594 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -59,4 +59,10 @@ #endif +/* rockchip ohci host driver */ +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 + +/* xhci host */ +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #endif diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h new file mode 100644 index 0000000000..8ebf2324c5 --- /dev/null +++ b/include/configs/rk3368_common.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2016 Andreas Färber + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_RK3368_COMMON_H +#define __CONFIG_RK3368_COMMON_H + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#include <asm/arch/hardware.h> +#include <linux/sizes.h> + +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_SYS_TEXT_BASE 0x00200000 +#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 +#define CONFIG_SYS_LOAD_ADDR 0x00280000 + +#define CONFIG_BOUNCE_BUFFER + +#ifndef CONFIG_SPL_BUILD +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00500000\0" \ + "pxefile_addr_r=0x00600000\0" \ + "fdt_addr_r=0x5600000\0" \ + "kernel_addr_r=0x280000\0" \ + "ramdisk_addr_r=0x5bf0000\0" + +#include <config_distro_defaults.h> + +#define BOOT_TARGET_DEVICES(func) + +#include <config_distro_bootcmd.h> + +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV + +#endif + +#endif diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index 9d183cee6a..0573571e6e 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -54,4 +54,6 @@ #define CONFIG_ENV_OFFSET (96 * 1024) #endif +#define CONFIG_DISPLAY_BOARDINFO_LATE + #endif /* _ROCKCHIP_COMMON_H_ */ diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h new file mode 100644 index 0000000000..52750cb81b --- /dev/null +++ b/include/configs/rv1108_common.h @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_RV1108_COMMON_H +#define __CONFIG_RV1108_COMMON_H + +#include <asm/arch/hardware.h> +#include "rockchip-common.h" + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) +/* TIMER1,initialized by ddr initialize code */ +#define CONFIG_SYS_TIMER_BASE 0x10350020 +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_TEXT_BASE CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000) + +#endif diff --git a/include/configs/sheep_rk3368.h b/include/configs/sheep_rk3368.h new file mode 100644 index 0000000000..ec33565d09 --- /dev/null +++ b/include/configs/sheep_rk3368.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIGS_PX5_EVB_H +#define __CONFIGS_PX5_EVB_H + +#include <configs/rk3368_common.h> + +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define KERNEL_LOAD_ADDR 0x280000 +#define DTB_LOAD_ADDR 0x5600000 +#define INITRD_LOAD_ADDR 0x5bf0000 +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x2000 + +#define CONFIG_CONSOLE_SCROLL_LINES 10 + +#endif diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index b5705b7169..21029d10ae 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -14,8 +14,6 @@ #ifndef __CONFIG_SIEMENS_AM33X_COMMON_H #define __CONFIG_SIEMENS_AM33X_COMMON_H -#define CONFIG_AM33XX - #include <asm/arch/omap.h> #define CONFIG_DMA_COHERENT diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index 1ee58156e0..4e0edcbc01 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -10,14 +10,20 @@ #define CONFIG_SYS_FLASH_BASE 0x08000000 #define CONFIG_SYS_INIT_SP_ADDR 0x20050000 -#define CONFIG_SYS_TEXT_BASE 0x08000000 + +#ifdef CONFIG_SUPPORT_SPL +#define CONFIG_SYS_TEXT_BASE 0x08008000 +#define CONFIG_SYS_LOAD_ADDR 0x08008000 +#else +#define CONFIG_SYS_TEXT_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LOAD_ADDR 0xC0400000 +#define CONFIG_LOADADDR 0xC0400000 +#endif /* * Configuration of the external SDRAM memory */ #define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_LOAD_ADDR 0xC0400000 -#define CONFIG_LOADADDR 0xC0400000 #define CONFIG_SYS_MAX_FLASH_SECT 8 #define CONFIG_SYS_MAX_FLASH_BANKS 1 @@ -69,4 +75,23 @@ #define CONFIG_CMD_CACHE #define CONFIG_BOARD_LATE_INIT #define CONFIG_DISPLAY_BOARDINFO + +/* For SPL */ +#ifdef CONFIG_SUPPORT_SPL +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_SPL_LEN 0x00008000 +#define CONFIG_SYS_UBOOT_START 0x080083FD +#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ + CONFIG_SYS_SPL_LEN) + +/* DT blob (fdt) address */ +#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \ + 0x1C0000) +#endif +/* For SPL ends */ + #endif /* __CONFIG_H */ diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index c03efd852a..dd72e5b4db 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -105,7 +105,7 @@ /* overrides for SPL build here */ #ifdef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY /* remove I2C support */ #ifdef CONFIG_SYS_I2C_TEGRA diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index a4066a8494..ea83ea2495 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -16,9 +16,6 @@ #ifndef __CONFIG_TI814X_EVM_H #define __CONFIG_TI814X_EVM_H -#define CONFIG_TI81XX -#define CONFIG_TI814X - #include <asm/arch/omap.h> #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 68eb08f812..defcad4518 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -10,24 +10,16 @@ #ifndef __CONFIG_TI816X_EVM_H #define __CONFIG_TI816X_EVM_H -#define CONFIG_TI81XX -#define CONFIG_TI816X - -#define CONFIG_ARCH_CPU_INIT - +#include <configs/ti_armv7_omap.h> #include <asm/arch/omap.h> #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (32 * 1024)) -#define CONFIG_SYS_LONGHELP /* undef save memory */ #define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG /* required for ramdisk support */ - #define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x81000000\0" \ + DEFAULT_LINUX_BOOT_ENV \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ #define CONFIG_BOOTCOMMAND \ "mmc rescan;" \ @@ -40,41 +32,10 @@ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) -#define CONFIG_SYS_MAXARGS 32 -#define CONFIG_SYS_CBSIZE 512 /* console I/O buffer size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot arg buffer size */ - -#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ - #define CONFIG_CMD_ASKENV -/* - * Only one of the following two options (DDR3/DDR2) should be enabled - * CONFIG_TI816X_EVM_DDR2 - * CONFIG_TI816X_EVM_DDR3 - */ -#define CONFIG_TI816X_EVM_DDR3 - -/* - * Supported values: 400, 531, 675 or 796 MHz - */ -#define CONFIG_TI816X_DDR_PLL_796 - -#define CONFIG_TI816X_USE_EMIF0 1 -#define CONFIG_TI816X_USE_EMIF1 1 - -#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */ -#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ -#define PHYS_DRAM_1_SIZE 0x40000000 /* 1 GB */ -#define PHYS_DRAM_2 0xC0000000 /* DRAM Bank #2 */ -#define PHYS_DRAM_2_SIZE 0x40000000 /* 1 GB */ - #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_SDRAM_BASE 0x80000000 /** * Platform/Board specific defs @@ -83,8 +44,6 @@ #define CONFIG_SYS_TIMERBASE 0x4802E000 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#undef CONFIG_NAND_OMAP_GPMC - /* * NS16550 Configuration */ @@ -101,28 +60,68 @@ #define CONFIG_SERIAL3 #define CONFIG_CONS_INDEX 1 -#define CONFIG_ENV_IS_NOWHERE +/* + * GPMC NAND block. We support 1 device and the physical address to + * access CS0 at is 0x8000000. + */ +#define CONFIG_SYS_NAND_BASE 0x8000000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* NAND: SPL related configs */ +#define CONFIG_SPL_NAND_AM33XX_BCH + +/* NAND: device related configs */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +/* NAND: driver related configs */ +#define CONFIG_NAND_OMAP_GPMC_PREFETCH +#define CONFIG_NAND_OMAP_ELM +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW +#define MTDIDS_DEFAULT "nand0=nand.0" +#define MTDPARTS_DEFAULT "mtdparts=nand.0:" \ + "128k(NAND.SPL)," \ + "128k(NAND.SPL.backup1)," \ + "128k(NAND.SPL.backup2)," \ + "128k(NAND.SPL.backup3)," \ + "256k(NAND.u-boot-spl-os)," \ + "1m(NAND.u-boot)," \ + "128k(NAND.u-boot-env)," \ + "128k(NAND.u-boot-env.backup1)," \ + "8m(NAND.kernel)," \ + "-(NAND.file-system)" +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x001c0000 +#define CONFIG_ENV_OFFSET_REDUND 0x001e0000 +#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE /* SPL */ /* Defines for SPL */ -#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ #define CONFIG_SPL_TEXT_BASE 0x40400000 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ CONFIG_SPL_TEXT_BASE) -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 -#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" #define CONFIG_SYS_TEXT_BASE 0x80800000 -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* Since SPL did pll and ddr initialization for us, * we don't need to do it twice. @@ -131,4 +130,13 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #endif +/* + * Disable MMC DM for SPL build and can be re-enabled after adding + * DM support in SPL + */ +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_DM_MMC +#undef CONFIG_TIMER +#undef CONFIG_DM_USB +#endif #endif diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 5321ed6b09..a4676d3a7f 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -199,9 +199,10 @@ #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" /* RAW SD card / eMMC */ -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1700 /* address 0x2E0000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x1500 /* address 0x2A0000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x200 /* 256KiB */ + /* spl export command */ #define CONFIG_CMD_SPL diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h index a28922585c..ee46d3ac7e 100644 --- a/include/configs/topic_miami.h +++ b/include/configs/topic_miami.h @@ -56,7 +56,6 @@ #undef CONFIG_SF_DEFAULT_SPEED #define CONFIG_SF_DEFAULT_SPEED 108000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -#undef CONFIG_SF_DUAL_FLASH #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED #undef CONFIG_SPI_FLASH_WINBOND #undef CONFIG_SPI_FLASH_ISSI diff --git a/include/configs/topic_miamiplus.h b/include/configs/topic_miamiplus.h deleted file mode 100644 index 46ca6bda04..0000000000 --- a/include/configs/topic_miamiplus.h +++ /dev/null @@ -1,2 +0,0 @@ -#include "topic_miami.h" -#define CONFIG_SF_DUAL_FLASH diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index 4ab4c6559d..4e99cdbb59 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -29,7 +29,7 @@ #define CONFIG_SYS_RTC_BUS_NUM 2 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* Turn off RTC square-wave output to save battery */ -#define CONFIG_SYS_RTC_DS1337_NOOSC +#define CONFIG_RTC_DS1337_NOOSC /* LED */ diff --git a/include/configs/v38b.h b/include/configs/v38b.h deleted file mode 100644 index 2bd6cc11ae..0000000000 --- a/include/configs/v38b.h +++ /dev/null @@ -1,284 +0,0 @@ -/* - * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering, - * wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ -#define CONFIG_V38B 1 /* ...on V38B board */ - -#define CONFIG_SYS_TEXT_BASE 0xFF000000 - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ...running at 33.000000MHz */ - -#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ -#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ - -#undef CONFIG_HW_WATCHDOG /* don't use watchdog */ - -#define CONFIG_NETCONSOLE 1 - -#define CONFIG_BOARD_EARLY_INIT_R 1 /* do board-specific init */ -#define CONFIG_MISC_INIT_R - -#define CONFIG_SYS_XLB_PIPELINING 1 /* gives better performance */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* - * DDR - */ -#define SDRAM_DDR 1 /* is DDR */ -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x704f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 - -/* - * PCI - no support - */ - -/* - * USB - */ -#define CONFIG_USB_OHCI -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_SDRAM - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * Boot low with 16 MB Flash - */ -#define CONFIG_SYS_LOWBOOT 1 -#define CONFIG_SYS_LOWBOOT16 1 - -/* - * Autobooting - */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootcmd=run net_nfs\0" \ - "bootdelay=3\0" \ - "baudrate=115200\0" \ - "preboot=echo;echo Type \"run flash_nfs\" to mount root " \ - "filesystem over NFS; echo\0" \ - "netdev=eth0\0" \ - "ramargs=setenv bootargs root=/dev/ram rw wdt=off \0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):" \ - "$(netmask):$(hostname):$(netdev):off panic=1\0" \ - "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ - "flash_self=run ramargs addip;bootm $(kernel_addr) " \ - "$(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath) wdt=off\0" \ - "hostname=v38b\0" \ - "ethact=FEC\0" \ - "rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \ - "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \ - "cp.b 200000 ff000000 $(filesize);" \ - "prot on ff000000 ff03ffff\0" \ - "load=tftp 200000 $(u-boot)\0" \ - "netmask=255.255.0.0\0" \ - "ipaddr=192.168.160.18\0" \ - "serverip=192.168.1.1\0" \ - "bootfile=/tftpboot/v38b/uImage\0" \ - "u-boot=/tftpboot/v38b/u-boot.bin\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -/* - * IPB Bus clocking configuration. - */ -#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/* - * Flash configuration - use CFI driver - */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 -#define CONFIG_SYS_FLASH_BASE 0xFF000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_SIZE 0x01000000 /* 16 MiB */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */ - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_OVERWRITE 1 - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Linux initial memory map */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_MII 1 - -/* - * GPIO configuration - */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x90001404 - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x00047801 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/* - * IDE/ATA (supports IDE harddisk) - */ -#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */ -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) /* data I/O offset */ - -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* normal register accesses offset */ - -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) /* alternate registers offset */ - -#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ - -/* - * Status LED - */ - -#define CONFIG_SYS_LED_BASE MPC5XXX_GPT7_ENABLE /* Timer 7 GPIO */ -#ifndef __ASSEMBLY__ -typedef unsigned int led_id_t; - -#define __led_toggle(_msk) \ - do { \ - *((volatile long *) (CONFIG_SYS_LED_BASE)) ^= (_msk); \ - } while(0) - -#define __led_set(_msk, _st) \ - do { \ - if ((_st)) \ - *((volatile long *) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \ - else \ - *((volatile long *) (CONFIG_SYS_LED_BASE)) |= (_msk); \ - } while(0) - -#define __led_init(_msk, st) \ - do { \ - *((volatile long *) (CONFIG_SYS_LED_BASE)) |= 0x34; \ - } while(0) -#endif /* __ASSEMBLY__ */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/whistler.h b/include/configs/whistler.h deleted file mode 100644 index 9f350d556a..0000000000 --- a/include/configs/whistler.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * (C) Copyright 2010-2012 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/sizes.h> -#include "tegra20-common.h" - -/* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Whistler" - -/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_TEGRA_UARTA_UAA_UAB -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - -#define CONFIG_MACH_TYPE MACH_TYPE_WHISTLER - -/* I2C */ -#define CONFIG_SYS_I2C_TEGRA - -/* - * Environment in eMMC, at the end of 2nd "boot sector". Note: This assumes - * the user plugged the standard 8GB MoviNAND card into J29/HSMMC/POP. If - * they didn't, the boot sector layout may be different. However, use of that - * particular card is standard practice as far as I know. - */ -#define CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 2 - -/* USB Host support */ -#define CONFIG_USB_EHCI_TEGRA - -/* USB networking support */ -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_ASIX - -/* General networking support */ - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index c56cd8c98b..86a4579fbd 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -29,9 +29,6 @@ #define CONFIG_SYS_MEMTEST_START 0 #define CONFIG_SYS_MEMTEST_END 1000 -/* Have release address at the end of 256MB for now */ -#define CPU_RELEASE_ADDR 0xFFFFFF0 - #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE /* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */ @@ -292,11 +289,13 @@ # define CONFIG_ENV_MAX_ENTRIES 10 # define CONFIG_SYS_SPL_MALLOC_START 0x20000000 -# define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000000 +# define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 #ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE # error "Disable CONFIG_SPL_SYS_MALLOC_SIMPLE. Full malloc needs to be used" #endif #endif +#define CONFIG_BOARD_EARLY_INIT_F + #endif /* __XILINX_ZYNQMP_H */ diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h new file mode 100644 index 0000000000..9c5dd9ba2f --- /dev/null +++ b/include/dt-bindings/clock/rk3368-cru.h @@ -0,0 +1,384 @@ +/* + * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H + +/* core clocks */ +#define PLL_APLLB 1 +#define PLL_APLLL 2 +#define PLL_DPLL 3 +#define PLL_CPLL 4 +#define PLL_GPLL 5 +#define PLL_NPLL 6 +#define ARMCLKB 7 +#define ARMCLKL 8 + +/* sclk gates (special clocks) */ +#define SCLK_GPU_CORE 64 +#define SCLK_SPI0 65 +#define SCLK_SPI1 66 +#define SCLK_SPI2 67 +#define SCLK_SDMMC 68 +#define SCLK_SDIO0 69 +#define SCLK_EMMC 71 +#define SCLK_TSADC 72 +#define SCLK_SARADC 73 +#define SCLK_NANDC0 75 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_UART3 80 +#define SCLK_UART4 81 +#define SCLK_I2S_8CH 82 +#define SCLK_SPDIF_8CH 83 +#define SCLK_I2S_2CH 84 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_TIMER4 89 +#define SCLK_TIMER5 90 +#define SCLK_TIMER6 91 +#define SCLK_OTGPHY0 93 +#define SCLK_OTG_ADP 96 +#define SCLK_HSICPHY480M 97 +#define SCLK_HSICPHY12M 98 +#define SCLK_MACREF 99 +#define SCLK_VOP0_PWM 100 +#define SCLK_MAC_RX 102 +#define SCLK_MAC_TX 103 +#define SCLK_EDP_24M 104 +#define SCLK_EDP 105 +#define SCLK_RGA 106 +#define SCLK_ISP 107 +#define SCLK_HDCP 108 +#define SCLK_HDMI_HDCP 109 +#define SCLK_HDMI_CEC 110 +#define SCLK_HEVC_CABAC 111 +#define SCLK_HEVC_CORE 112 +#define SCLK_I2S_8CH_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO0_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO0_SAMPLE 119 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_USBPHY480M 122 +#define SCLK_PVTM_CORE 123 +#define SCLK_PVTM_GPU 124 +#define SCLK_PVTM_PMU 125 +#define SCLK_SFC 126 +#define SCLK_MAC 127 +#define SCLK_MACREF_OUT 128 + +#define DCLK_VOP 190 +#define MCLK_CRYPTO 191 + +/* aclk gates */ +#define ACLK_GPU_MEM 192 +#define ACLK_GPU_CFG 193 +#define ACLK_DMAC_BUS 194 +#define ACLK_DMAC_PERI 195 +#define ACLK_PERI_MMU 196 +#define ACLK_GMAC 197 +#define ACLK_VOP 198 +#define ACLK_VOP_IEP 199 +#define ACLK_RGA 200 +#define ACLK_HDCP 201 +#define ACLK_IEP 202 +#define ACLK_VIO0_NOC 203 +#define ACLK_VIP 204 +#define ACLK_ISP 205 +#define ACLK_VIO1_NOC 206 +#define ACLK_VIDEO 208 +#define ACLK_BUS 209 +#define ACLK_PERI 210 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GPIO3 323 +#define PCLK_PMUGRF 324 +#define PCLK_MAILBOX 325 +#define PCLK_GRF 329 +#define PCLK_SGRF 330 +#define PCLK_PMU 331 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_I2C3 335 +#define PCLK_I2C4 336 +#define PCLK_I2C5 337 +#define PCLK_SPI0 338 +#define PCLK_SPI1 339 +#define PCLK_SPI2 340 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_UART3 344 +#define PCLK_UART4 345 +#define PCLK_TSADC 346 +#define PCLK_SARADC 347 +#define PCLK_SIM 348 +#define PCLK_GMAC 349 +#define PCLK_PWM0 350 +#define PCLK_PWM1 351 +#define PCLK_TIMER0 353 +#define PCLK_TIMER1 354 +#define PCLK_EDP_CTRL 355 +#define PCLK_MIPI_DSI0 356 +#define PCLK_MIPI_CSI 358 +#define PCLK_HDCP 359 +#define PCLK_HDMI_CTRL 360 +#define PCLK_VIO_H2P 361 +#define PCLK_BUS 362 +#define PCLK_PERI 363 +#define PCLK_DDRUPCTL 364 +#define PCLK_DDRPHY 365 +#define PCLK_ISP 366 +#define PCLK_VIP 367 +#define PCLK_WDT 368 + +/* hclk gates */ +#define HCLK_SFC 448 +#define HCLK_OTG0 449 +#define HCLK_HOST0 450 +#define HCLK_HOST1 451 +#define HCLK_HSIC 452 +#define HCLK_NANDC0 453 +#define HCLK_TSP 455 +#define HCLK_SDMMC 456 +#define HCLK_SDIO0 457 +#define HCLK_EMMC 459 +#define HCLK_HSADC 460 +#define HCLK_CRYPTO 461 +#define HCLK_I2S_2CH 462 +#define HCLK_I2S_8CH 463 +#define HCLK_SPDIF 464 +#define HCLK_VOP 465 +#define HCLK_ROM 467 +#define HCLK_IEP 468 +#define HCLK_ISP 469 +#define HCLK_RGA 470 +#define HCLK_VIO_AHB_ARBI 471 +#define HCLK_VIO_NOC 472 +#define HCLK_VIP 473 +#define HCLK_VIO_H2P 474 +#define HCLK_VIO_HDCPMMU 475 +#define HCLK_VIDEO 476 +#define HCLK_BUS 477 +#define HCLK_PERI 478 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_CORE_B0 0 +#define SRST_CORE_B1 1 +#define SRST_CORE_B2 2 +#define SRST_CORE_B3 3 +#define SRST_CORE_B0_PO 4 +#define SRST_CORE_B1_PO 5 +#define SRST_CORE_B2_PO 6 +#define SRST_CORE_B3_PO 7 +#define SRST_L2_B 8 +#define SRST_ADB_B 9 +#define SRST_PD_CORE_B_NIU 10 +#define SRST_PDBUS_STRSYS 11 +#define SRST_SOCDBG_B 14 +#define SRST_CORE_B_DBG 15 + +#define SRST_DMAC1 18 +#define SRST_INTMEM 19 +#define SRST_ROM 20 +#define SRST_SPDIF8CH 21 +#define SRST_I2S8CH 23 +#define SRST_MAILBOX 24 +#define SRST_I2S2CH 25 +#define SRST_EFUSE_256 26 +#define SRST_MCU_SYS 28 +#define SRST_MCU_PO 29 +#define SRST_MCU_NOC 30 +#define SRST_EFUSE 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_GPIO3 35 +#define SRST_GPIO4 36 +#define SRST_PMUGRF 41 +#define SRST_I2C0 42 +#define SRST_I2C1 43 +#define SRST_I2C2 44 +#define SRST_I2C3 45 +#define SRST_I2C4 46 +#define SRST_I2C5 47 + +#define SRST_DWPWM 48 +#define SRST_MMC_PERI 49 +#define SRST_PERIPH_MMU 50 +#define SRST_GRF 55 +#define SRST_PMU 56 +#define SRST_PERIPH_AXI 57 +#define SRST_PERIPH_AHB 58 +#define SRST_PERIPH_APB 59 +#define SRST_PERIPH_NIU 60 +#define SRST_PDPERI_AHB_ARBI 61 +#define SRST_EMEM 62 +#define SRST_USB_PERI 63 + +#define SRST_DMAC2 64 +#define SRST_MAC 66 +#define SRST_GPS 67 +#define SRST_RKPWM 69 +#define SRST_USBHOST0 72 +#define SRST_HSIC 73 +#define SRST_HSIC_AUX 74 +#define SRST_HSIC_PHY 75 +#define SRST_HSADC 76 +#define SRST_NANDC0 77 +#define SRST_SFC 79 + +#define SRST_SPI0 83 +#define SRST_SPI1 84 +#define SRST_SPI2 85 +#define SRST_SARADC 87 +#define SRST_PDALIVE_NIU 88 +#define SRST_PDPMU_INTMEM 89 +#define SRST_PDPMU_NIU 90 +#define SRST_SGRF 91 + +#define SRST_VIO_ARBI 96 +#define SRST_RGA_NIU 97 +#define SRST_VIO0_NIU_AXI 98 +#define SRST_VIO_NIU_AHB 99 +#define SRST_LCDC0_AXI 100 +#define SRST_LCDC0_AHB 101 +#define SRST_LCDC0_DCLK 102 +#define SRST_VIP 104 +#define SRST_RGA_CORE 105 +#define SRST_IEP_AXI 106 +#define SRST_IEP_AHB 107 +#define SRST_RGA_AXI 108 +#define SRST_RGA_AHB 109 +#define SRST_ISP 110 +#define SRST_EDP_24M 111 + +#define SRST_VIDEO_AXI 112 +#define SRST_VIDEO_AHB 113 +#define SRST_MIPIDPHYTX 114 +#define SRST_MIPIDSI0 115 +#define SRST_MIPIDPHYRX 116 +#define SRST_MIPICSI 117 +#define SRST_GPU 120 +#define SRST_HDMI 121 +#define SRST_EDP 122 +#define SRST_PMU_PVTM 123 +#define SRST_CORE_PVTM 124 +#define SRST_GPU_PVTM 125 +#define SRST_GPU_SYS 126 +#define SRST_GPU_MEM_NIU 127 + +#define SRST_MMC0 128 +#define SRST_SDIO0 129 +#define SRST_EMMC 131 +#define SRST_USBOTG_AHB 132 +#define SRST_USBOTG_PHY 133 +#define SRST_USBOTG_CON 134 +#define SRST_USBHOST0_AHB 135 +#define SRST_USBHOST0_PHY 136 +#define SRST_USBHOST0_CON 137 +#define SRST_USBOTG_UTMI 138 +#define SRST_USBHOST1_UTMI 139 +#define SRST_USB_ADP 141 + +#define SRST_CORESIGHT 144 +#define SRST_PD_CORE_AHB_NOC 145 +#define SRST_PD_CORE_APB_NOC 146 +#define SRST_GIC 148 +#define SRST_LCDC_PWM0 149 +#define SRST_RGA_H2P_BRG 153 +#define SRST_VIDEO 154 +#define SRST_GPU_CFG_NIU 157 +#define SRST_TSADC 159 + +#define SRST_DDRPHY0 160 +#define SRST_DDRPHY0_APB 161 +#define SRST_DDRCTRL0 162 +#define SRST_DDRCTRL0_APB 163 +#define SRST_VIDEO_NIU 165 +#define SRST_VIDEO_NIU_AHB 167 +#define SRST_DDRMSCH0 170 +#define SRST_PDBUS_AHB 173 +#define SRST_CRYPTO 174 + +#define SRST_UART0 179 +#define SRST_UART1 180 +#define SRST_UART2 181 +#define SRST_UART3 182 +#define SRST_UART4 183 +#define SRST_SIMC 186 +#define SRST_TSP 188 +#define SRST_TSP_CLKIN0 189 + +#define SRST_CORE_L0 192 +#define SRST_CORE_L1 193 +#define SRST_CORE_L2 194 +#define SRST_CORE_L3 195 +#define SRST_CORE_L0_PO 195 +#define SRST_CORE_L1_PO 197 +#define SRST_CORE_L2_PO 198 +#define SRST_CORE_L3_PO 199 +#define SRST_L2_L 200 +#define SRST_ADB_L 201 +#define SRST_PD_CORE_L_NIU 202 +#define SRST_CCI_SYS 203 +#define SRST_CCI_DDR 204 +#define SRST_CCI 205 +#define SRST_SOCDBG_L 206 +#define SRST_CORE_L_DBG 207 + +#define SRST_CORE_B0_NC 208 +#define SRST_CORE_B0_PO_NC 209 +#define SRST_L2_B_NC 210 +#define SRST_ADB_B_NC 211 +#define SRST_PD_CORE_B_NIU_NC 212 +#define SRST_PDBUS_STRSYS_NC 213 +#define SRST_CORE_L0_NC 214 +#define SRST_CORE_L0_PO_NC 215 +#define SRST_L2_L_NC 216 +#define SRST_ADB_L_NC 217 +#define SRST_PD_CORE_L_NIU_NC 218 +#define SRST_CCI_SYS_NC 219 +#define SRST_CCI_DDR_NC 220 +#define SRST_CCI_NC 221 +#define SRST_TRACE_NC 222 + +#define SRST_TIMER00 224 +#define SRST_TIMER01 225 +#define SRST_TIMER02 226 +#define SRST_TIMER03 227 +#define SRST_TIMER04 228 +#define SRST_TIMER05 229 +#define SRST_TIMER10 230 +#define SRST_TIMER11 231 +#define SRST_TIMER12 232 +#define SRST_TIMER13 233 +#define SRST_TIMER14 234 +#define SRST_TIMER15 235 +#define SRST_TIMER0_APB 236 +#define SRST_TIMER1_APB 237 + +#endif diff --git a/include/dt-bindings/clock/rv1108-cru.h b/include/dt-bindings/clock/rv1108-cru.h new file mode 100644 index 0000000000..d2ad3bb52d --- /dev/null +++ b/include/dt-bindings/clock/rv1108-cru.h @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * Author: Shawn Lin <shawn.lin@rock-chips.com> + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H + +/* pll id */ +#define PLL_APLL 0 +#define PLL_DPLL 1 +#define PLL_GPLL 2 +#define ARMCLK 3 + +/* sclk gates (special clocks) */ +#define SCLK_MAC 64 +#define SCLK_SPI0 65 +#define SCLK_NANDC 67 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_UART0 72 +#define SCLK_UART1 73 +#define SCLK_UART2 74 +#define SCLK_I2S0 75 +#define SCLK_I2S1 76 +#define SCLK_I2S2 77 +#define SCLK_TIMER0 78 +#define SCLK_TIMER1 79 +#define SCLK_SFC 80 +#define SCLK_SDMMC_DRV 81 +#define SCLK_SDIO_DRV 82 +#define SCLK_EMMC_DRV 83 +#define SCLK_SDMMC_SAMPLE 84 +#define SCLK_SDIO_SAMPLE 85 +#define SCLK_EMMC_SAMPLE 86 +#define SCLK_MAC_RX 87 +#define SCLK_MAC_TX 88 +#define SCLK_MACREF 89 +#define SCLK_MACREF_OUT 90 + + +/* aclk gates */ +#define ACLK_DMAC 192 +#define ACLK_PRE 193 +#define ACLK_CORE 194 +#define ACLK_ENMCORE 195 +#define ACLK_GMAC 196 + + +/* pclk gates */ +#define PCLK_GPIO1 256 +#define PCLK_GPIO2 257 +#define PCLK_GPIO3 258 +#define PCLK_GRF 259 +#define PCLK_I2C1 260 +#define PCLK_I2C2 261 +#define PCLK_I2C3 262 +#define PCLK_SPI 263 +#define PCLK_SFC 264 +#define PCLK_UART0 265 +#define PCLK_UART1 266 +#define PCLK_UART2 267 +#define PCLK_TSADC 268 +#define PCLK_PWM 269 +#define PCLK_TIMER 270 +#define PCLK_PERI 271 +#define PCLK_GMAC 272 + +/* hclk gates */ +#define HCLK_I2S0_8CH 320 +#define HCLK_I2S1_8CH 321 +#define HCLK_I2S2_2CH 322 +#define HCLK_NANDC 323 +#define HCLK_SDMMC 324 +#define HCLK_SDIO 325 +#define HCLK_EMMC 326 +#define HCLK_PERI 327 +#define HCLK_SFC 328 + +#define CLK_NR_CLKS (HCLK_SFC + 1) + +/* reset id */ +#define SRST_CORE_PO_AD 0 +#define SRST_CORE_AD 1 +#define SRST_L2_AD 2 +#define SRST_CPU_NIU_AD 3 +#define SRST_CORE_PO 4 +#define SRST_CORE 5 +#define SRST_L2 6 +#define SRST_CORE_DBG 8 +#define PRST_DBG 9 +#define RST_DAP 10 +#define PRST_DBG_NIU 11 +#define ARST_STRC_SYS_AD 15 + +#define SRST_DDRPHY_CLKDIV 16 +#define SRST_DDRPHY 17 +#define PRST_DDRPHY 18 +#define PRST_HDMIPHY 19 +#define PRST_VDACPHY 20 +#define PRST_VADCPHY 21 +#define PRST_MIPI_CSI_PHY 22 +#define PRST_MIPI_DSI_PHY 23 +#define PRST_ACODEC 24 +#define ARST_BUS_NIU 25 +#define PRST_TOP_NIU 26 +#define ARST_INTMEM 27 +#define HRST_ROM 28 +#define ARST_DMAC 29 +#define SRST_MSCH_NIU 30 +#define PRST_MSCH_NIU 31 + +#define PRST_DDRUPCTL 32 +#define NRST_DDRUPCTL 33 +#define PRST_DDRMON 34 +#define HRST_I2S0_8CH 35 +#define MRST_I2S0_8CH 36 +#define HRST_I2S1_2CH 37 +#define MRST_IS21_2CH 38 +#define HRST_I2S2_2CH 39 +#define MRST_I2S2_2CH 40 +#define HRST_CRYPTO 41 +#define SRST_CRYPTO 42 +#define PRST_SPI 43 +#define SRST_SPI 44 +#define PRST_UART0 45 +#define PRST_UART1 46 +#define PRST_UART2 47 + +#define SRST_UART0 48 +#define SRST_UART1 49 +#define SRST_UART2 50 +#define PRST_I2C1 51 +#define PRST_I2C2 52 +#define PRST_I2C3 53 +#define SRST_I2C1 54 +#define SRST_I2C2 55 +#define SRST_I2C3 56 +#define PRST_PWM1 58 +#define SRST_PWM1 60 +#define PRST_WDT 61 +#define PRST_GPIO1 62 +#define PRST_GPIO2 63 + +#define PRST_GPIO3 64 +#define PRST_GRF 65 +#define PRST_EFUSE 66 +#define PRST_EFUSE512 67 +#define PRST_TIMER0 68 +#define SRST_TIMER0 69 +#define SRST_TIMER1 70 +#define PRST_TSADC 71 +#define SRST_TSADC 72 +#define PRST_SARADC 73 +#define SRST_SARADC 74 +#define HRST_SYSBUS 75 +#define PRST_USBGRF 76 + +#define ARST_PERIPH_NIU 80 +#define HRST_PERIPH_NIU 81 +#define PRST_PERIPH_NIU 82 +#define HRST_PERIPH 83 +#define HRST_SDMMC 84 +#define HRST_SDIO 85 +#define HRST_EMMC 86 +#define HRST_NANDC 87 +#define NRST_NANDC 88 +#define HRST_SFC 89 +#define SRST_SFC 90 +#define ARST_GMAC 91 +#define HRST_OTG 92 +#define SRST_OTG 93 +#define SRST_OTG_ADP 94 +#define HRST_HOST0 95 + +#define HRST_HOST0_AUX 96 +#define HRST_HOST0_ARB 97 +#define SRST_HOST0_EHCIPHY 98 +#define SRST_HOST0_UTMI 99 +#define SRST_USBPOR 100 +#define SRST_UTMI0 101 +#define SRST_UTMI1 102 + +#define ARST_VIO0_NIU 102 +#define ARST_VIO1_NIU 103 +#define HRST_VIO_NIU 104 +#define PRST_VIO_NIU 105 +#define ARST_VOP 106 +#define HRST_VOP 107 +#define DRST_VOP 108 +#define ARST_IEP 109 +#define HRST_IEP 110 +#define ARST_RGA 111 +#define HRST_RGA 112 +#define SRST_RGA 113 +#define PRST_CVBS 114 +#define PRST_HDMI 115 +#define SRST_HDMI 116 +#define PRST_MIPI_DSI 117 + +#define ARST_ISP_NIU 118 +#define HRST_ISP_NIU 119 +#define HRST_ISP 120 +#define SRST_ISP 121 +#define ARST_VIP0 122 +#define HRST_VIP0 123 +#define PRST_VIP0 124 +#define ARST_VIP1 125 +#define HRST_VIP1 126 +#define PRST_VIP1 127 +#define ARST_VIP2 128 +#define HRST_VIP2 129 +#define PRST_VIP2 120 +#define ARST_VIP3 121 +#define HRST_VIP3 122 +#define PRST_VIP4 123 + +#define PRST_CIF1TO4 124 +#define SRST_CVBS_CLK 125 +#define HRST_CVBS 126 + +#define ARST_VPU_NIU 140 +#define HRST_VPU_NIU 141 +#define ARST_VPU 142 +#define HRST_VPU 143 +#define ARST_RKVDEC_NIU 144 +#define HRST_RKVDEC_NIU 145 +#define ARST_RKVDEC 146 +#define HRST_RKVDEC 147 +#define SRST_RKVDEC_CABAC 148 +#define SRST_RKVDEC_CORE 149 +#define ARST_RKVENC_NIU 150 +#define HRST_RKVENC_NIU 151 +#define ARST_RKVENC 152 +#define HRST_RKVENC 153 +#define SRST_RKVENC_CORE 154 + +#define SRST_DSP_CORE 156 +#define SRST_DSP_SYS 157 +#define SRST_DSP_GLOBAL 158 +#define SRST_DSP_OECM 159 +#define PRST_DSP_IOP_NIU 160 +#define ARST_DSP_EPP_NIU 161 +#define ARST_DSP_EDP_NIU 162 +#define PRST_DSP_DBG_NIU 163 +#define PRST_DSP_CFG_NIU 164 +#define PRST_DSP_GRF 165 +#define PRST_DSP_MAILBOX 166 +#define PRST_DSP_INTC 167 +#define PRST_DSP_PFM_MON 169 +#define SRST_DSP_PFM_MON 170 +#define ARST_DSP_EDAP_NIU 171 + +#define SRST_PMU 172 +#define SRST_PMU_I2C0 173 +#define PRST_PMU_I2C0 174 +#define PRST_PMU_GPIO0 175 +#define PRST_PMU_INTMEM 176 +#define PRST_PMU_PWM0 177 +#define SRST_PMU_PWM0 178 +#define PRST_PMU_GRF 179 +#define SRST_PMU_NIU 180 +#define SRST_PMU_PVTM 181 +#define ARST_DSP_EDP_PERF 184 +#define ARST_DSP_EPP_PERF 185 + +#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */ diff --git a/include/environment/ti/dfu.h b/include/environment/ti/dfu.h index caf71a3fe6..c89005ff4c 100644 --- a/include/environment/ti/dfu.h +++ b/include/environment/ti/dfu.h @@ -6,15 +6,19 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#ifndef __TI_DFU_H +#define __TI_DFU_H + #define DFU_ALT_INFO_MMC \ "dfu_alt_info_mmc=" \ "boot part 0 1;" \ "rootfs part 0 2;" \ "MLO fat 0 1;" \ "MLO.raw raw 0x100 0x100;" \ - "u-boot.img.raw raw 0x300 0x400;" \ - "spl-os-args.raw raw 0x80 0x80;" \ - "spl-os-image.raw raw 0x900 0x2000;" \ + "u-boot.img.raw raw 0x300 0x1000;" \ + "u-env.raw raw 0x1300 0x200;" \ + "spl-os-args.raw raw 0x1500 0x200;" \ + "spl-os-image.raw raw 0x1700 0x6900;" \ "spl-os-args fat 0 1;" \ "spl-os-image fat 0 1;" \ "u-boot.img fat 0 1;" \ @@ -28,8 +32,9 @@ "MLO fat 1 1;" \ "MLO.raw raw 0x100 0x100;" \ "u-boot.img.raw raw 0x300 0x1000;" \ - "spl-os-args.raw raw 0x80 0x80;" \ - "spl-os-image.raw raw 0x900 0x2000;" \ + "u-env.raw raw 0x1300 0x200;" \ + "spl-os-args.raw raw 0x1500 0x200;" \ + "spl-os-image.raw raw 0x1700 0x6900;" \ "spl-os-args fat 1 1;" \ "spl-os-image fat 1 1;" \ "u-boot.img fat 1 1;" \ @@ -73,3 +78,5 @@ "u-boot-env raw 0x1C0000 0x010000;" \ "u-boot-env.backup raw 0x1D0000 0x010000;" \ "kernel raw 0x1E0000 0x800000\0" + +#endif /* __TI_DFU_H */ diff --git a/include/environment/ti/mmc.h b/include/environment/ti/mmc.h index b987f71516..4305ebdaaf 100644 --- a/include/environment/ti/mmc.h +++ b/include/environment/ti/mmc.h @@ -6,6 +6,9 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#ifndef __TI_MMC_H +#define __TI_MMC_H + #define DEFAULT_MMC_TI_ARGS \ "mmcdev=0\0" \ "mmcrootfstype=ext4 rootwait\0" \ @@ -66,3 +69,5 @@ "fi;" \ "fi;" \ "fi;\0" + +#endif /* __TI_MMC_H */ diff --git a/include/fdt.h b/include/fdt.h index 526aedb515..7ead62e777 100644 --- a/include/fdt.h +++ b/include/fdt.h @@ -1,111 +1 @@ -#ifndef _FDT_H -#define _FDT_H -/* - * libfdt - Flat Device Tree manipulation - * Copyright (C) 2006 David Gibson, IBM Corporation. - * Copyright 2012 Kim Phillips, Freescale Semiconductor. - * - * libfdt is dual licensed: you can use it either under the terms of - * the GPL, or the BSD license, at your option. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Alternatively, - * - * b) Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * 1. Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __ASSEMBLY__ - -struct fdt_header { - fdt32_t magic; /* magic word FDT_MAGIC */ - fdt32_t totalsize; /* total size of DT block */ - fdt32_t off_dt_struct; /* offset to structure */ - fdt32_t off_dt_strings; /* offset to strings */ - fdt32_t off_mem_rsvmap; /* offset to memory reserve map */ - fdt32_t version; /* format version */ - fdt32_t last_comp_version; /* last compatible version */ - - /* version 2 fields below */ - fdt32_t boot_cpuid_phys; /* Which physical CPU id we're - booting on */ - /* version 3 fields below */ - fdt32_t size_dt_strings; /* size of the strings block */ - - /* version 17 fields below */ - fdt32_t size_dt_struct; /* size of the structure block */ -}; - -struct fdt_reserve_entry { - fdt64_t address; - fdt64_t size; -}; - -struct fdt_node_header { - fdt32_t tag; - char name[0]; -}; - -struct fdt_property { - fdt32_t tag; - fdt32_t len; - fdt32_t nameoff; - char data[0]; -}; - -#endif /* !__ASSEMBLY */ - -#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */ -#define FDT_TAGSIZE sizeof(fdt32_t) - -#define FDT_BEGIN_NODE 0x1 /* Start node: full name */ -#define FDT_END_NODE 0x2 /* End node */ -#define FDT_PROP 0x3 /* Property: name off, - size, content */ -#define FDT_NOP 0x4 /* nop */ -#define FDT_END 0x9 - -#define FDT_V1_SIZE (7*sizeof(fdt32_t)) -#define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(fdt32_t)) -#define FDT_V3_SIZE (FDT_V2_SIZE + sizeof(fdt32_t)) -#define FDT_V16_SIZE FDT_V3_SIZE -#define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(fdt32_t)) - -#endif /* _FDT_H */ +#include <../lib/libfdt/fdt.h> diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index a86f2162aa..29aa687507 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -11,6 +11,9 @@ #ifdef CONFIG_FSL_IFC #include <config.h> #include <common.h> +#ifdef CONFIG_ARM +#include <asm/arch/soc.h> +#endif #define FSL_IFC_V1_1_0 0x01010000 #define FSL_IFC_V2_0_0 0x02000000 diff --git a/include/i2c.h b/include/i2c.h index 7726028044..695cb7655f 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -660,12 +660,7 @@ extern struct i2c_bus_hose i2c_bus[]; #endif #ifndef I2C_SOFT_DECLARATIONS -# if defined(CONFIG_MPC8260) -# define I2C_SOFT_DECLARATIONS volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT); -# elif defined(CONFIG_8xx) -# define I2C_SOFT_DECLARATIONS volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - -# elif (defined(CONFIG_AT91RM9200) || \ +# if (defined(CONFIG_AT91RM9200) || \ defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ defined(CONFIG_AT91SAM9263)) # define I2C_SOFT_DECLARATIONS at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; @@ -674,15 +669,6 @@ extern struct i2c_bus_hose i2c_bus[]; # endif #endif -#ifdef CONFIG_8xx -/* Set default value for the I2C bus speed on 8xx. In the - * future, we'll define these in all 8xx board config files. - */ -#ifndef CONFIG_SYS_I2C_SPEED -#define CONFIG_SYS_I2C_SPEED 50000 -#endif -#endif - /* * Many boards/controllers/drivers don't support an I2C slave interface so * provide a default slave address for them for use in common code. A real @@ -814,11 +800,6 @@ static inline u8 i2c_reg_read(u8 addr, u8 reg) { u8 buf; -#ifdef CONFIG_8xx - /* MPC8xx needs this. Maybe one day we can get rid of it. */ - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif - #ifdef DEBUG printf("%s: addr=0x%02x, reg=0x%02x\n", __func__, addr, reg); #endif @@ -830,11 +811,6 @@ static inline u8 i2c_reg_read(u8 addr, u8 reg) static inline void i2c_reg_write(u8 addr, u8 reg, u8 val) { -#ifdef CONFIG_8xx - /* MPC8xx needs this. Maybe one day we can get rid of it. */ - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif - #ifdef DEBUG printf("%s: addr=0x%02x, reg=0x%02x, val=0x%02x\n", __func__, addr, reg, val); diff --git a/include/image.h b/include/image.h index 8d380e0e84..fcfe730204 100644 --- a/include/image.h +++ b/include/image.h @@ -785,7 +785,8 @@ static inline int image_check_type(const image_header_t *hdr, uint8_t type) } static inline int image_check_arch(const image_header_t *hdr, uint8_t arch) { - return (image_get_arch(hdr) == arch); + return (image_get_arch(hdr) == arch) || + (image_get_arch(hdr) == IH_ARCH_ARM && arch == IH_ARCH_ARM64); } static inline int image_check_os(const image_header_t *hdr, uint8_t os) { diff --git a/include/keyboard.h b/include/keyboard.h index 5cbd9f8ba8..9b51e20322 100644 --- a/include/keyboard.h +++ b/include/keyboard.h @@ -98,7 +98,7 @@ extern int kbd_init_hw(void); extern void pckbd_leds(unsigned char leds); #endif /* !CONFIG_DM_KEYBOARD */ -#if defined(CONFIG_MPC5xxx) || defined(CONFIG_ARCH_MPC8540) || \ +#if defined(CONFIG_ARCH_MPC8540) || \ defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555) int ps2ser_check(void); #endif diff --git a/include/lcd.h b/include/lcd.h index f76fca77f9..797d0b0de1 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -40,9 +40,7 @@ void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue); */ void lcd_set_flush_dcache(int flush); -#if defined CONFIG_MPC823 -#include <mpc823_lcd.h> -#elif defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \ +#if defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \ defined CONFIG_CPU_MONAHANS #include <pxa_lcd.h> #elif defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD) diff --git a/include/libfdt.h b/include/libfdt.h index e2bc2e00c1..10296a21ad 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -1,2137 +1 @@ -#ifndef _LIBFDT_H -#define _LIBFDT_H -/* - * libfdt - Flat Device Tree manipulation - * Copyright (C) 2006 David Gibson, IBM Corporation. - * - * libfdt is dual licensed: you can use it either under the terms of - * the GPL, or the BSD license, at your option. - * - * a) This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this library; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Alternatively, - * - * b) Redistribution and use in source and binary forms, with or - * without modification, are permitted provided that the following - * conditions are met: - * - * 1. Redistributions of source code must retain the above - * copyright notice, this list of conditions and the following - * disclaimer. - * 2. Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <libfdt_env.h> -#include <fdt.h> - -#define FDT_FIRST_SUPPORTED_VERSION 0x10 -#define FDT_LAST_SUPPORTED_VERSION 0x11 - -/* Error codes: informative error codes */ -#define FDT_ERR_NOTFOUND 1 - /* FDT_ERR_NOTFOUND: The requested node or property does not exist */ -#define FDT_ERR_EXISTS 2 - /* FDT_ERR_EXISTS: Attempted to create a node or property which - * already exists */ -#define FDT_ERR_NOSPACE 3 - /* FDT_ERR_NOSPACE: Operation needed to expand the device - * tree, but its buffer did not have sufficient space to - * contain the expanded tree. Use fdt_open_into() to move the - * device tree to a buffer with more space. */ - -/* Error codes: codes for bad parameters */ -#define FDT_ERR_BADOFFSET 4 - /* FDT_ERR_BADOFFSET: Function was passed a structure block - * offset which is out-of-bounds, or which points to an - * unsuitable part of the structure for the operation. */ -#define FDT_ERR_BADPATH 5 - /* FDT_ERR_BADPATH: Function was passed a badly formatted path - * (e.g. missing a leading / for a function which requires an - * absolute path) */ -#define FDT_ERR_BADPHANDLE 6 - /* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle. - * This can be caused either by an invalid phandle property - * length, or the phandle value was either 0 or -1, which are - * not permitted. */ -#define FDT_ERR_BADSTATE 7 - /* FDT_ERR_BADSTATE: Function was passed an incomplete device - * tree created by the sequential-write functions, which is - * not sufficiently complete for the requested operation. */ - -/* Error codes: codes for bad device tree blobs */ -#define FDT_ERR_TRUNCATED 8 - /* FDT_ERR_TRUNCATED: Structure block of the given device tree - * ends without an FDT_END tag. */ -#define FDT_ERR_BADMAGIC 9 - /* FDT_ERR_BADMAGIC: Given "device tree" appears not to be a - * device tree at all - it is missing the flattened device - * tree magic number. */ -#define FDT_ERR_BADVERSION 10 - /* FDT_ERR_BADVERSION: Given device tree has a version which - * can't be handled by the requested operation. For - * read-write functions, this may mean that fdt_open_into() is - * required to convert the tree to the expected version. */ -#define FDT_ERR_BADSTRUCTURE 11 - /* FDT_ERR_BADSTRUCTURE: Given device tree has a corrupt - * structure block or other serious error (e.g. misnested - * nodes, or subnodes preceding properties). */ -#define FDT_ERR_BADLAYOUT 12 - /* FDT_ERR_BADLAYOUT: For read-write functions, the given - * device tree has it's sub-blocks in an order that the - * function can't handle (memory reserve map, then structure, - * then strings). Use fdt_open_into() to reorganize the tree - * into a form suitable for the read-write operations. */ - -/* "Can't happen" error indicating a bug in libfdt */ -#define FDT_ERR_INTERNAL 13 - /* FDT_ERR_INTERNAL: libfdt has failed an internal assertion. - * Should never be returned, if it is, it indicates a bug in - * libfdt itself. */ - -/* Errors in device tree content */ -#define FDT_ERR_BADNCELLS 14 - /* FDT_ERR_BADNCELLS: Device tree has a #address-cells, #size-cells - * or similar property with a bad format or value */ - -#define FDT_ERR_BADVALUE 15 - /* FDT_ERR_BADVALUE: Device tree has a property with an unexpected - * value. For example: a property expected to contain a string list - * is not NUL-terminated within the length of its value. */ - -#define FDT_ERR_BADOVERLAY 16 - /* FDT_ERR_BADOVERLAY: The device tree overlay, while - * correctly structured, cannot be applied due to some - * unexpected or missing value, property or node. */ - -#define FDT_ERR_NOPHANDLES 17 - /* FDT_ERR_NOPHANDLES: The device tree doesn't have any - * phandle available anymore without causing an overflow */ - -#define FDT_ERR_TOODEEP 18 - /* FDT_ERR_TOODEEP: The depth of a node has exceeded the internal - * libfdt limit. This can happen if you have more than - * FDT_MAX_DEPTH nested nodes. */ - -#define FDT_ERR_MAX 18 - -/**********************************************************************/ -/* Low-level functions (you probably don't need these) */ -/**********************************************************************/ - -const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen); -static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen) -{ - return (void *)(uintptr_t)fdt_offset_ptr(fdt, offset, checklen); -} - -uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset); - -/**********************************************************************/ -/* Traversal functions */ -/**********************************************************************/ - -int fdt_next_node(const void *fdt, int offset, int *depth); - -/** - * fdt_first_subnode() - get offset of first direct subnode - * - * @fdt: FDT blob - * @offset: Offset of node to check - * @return offset of first subnode, or -FDT_ERR_NOTFOUND if there is none - */ -int fdt_first_subnode(const void *fdt, int offset); - -/** - * fdt_next_subnode() - get offset of next direct subnode - * - * After first calling fdt_first_subnode(), call this function repeatedly to - * get direct subnodes of a parent node. - * - * @fdt: FDT blob - * @offset: Offset of previous subnode - * @return offset of next subnode, or -FDT_ERR_NOTFOUND if there are no more - * subnodes - */ -int fdt_next_subnode(const void *fdt, int offset); - -/** - * fdt_for_each_subnode - iterate over all subnodes of a parent - * - * @node: child node (int, lvalue) - * @fdt: FDT blob (const void *) - * @parent: parent node (int) - * - * This is actually a wrapper around a for loop and would be used like so: - * - * fdt_for_each_subnode(node, fdt, parent) { - * Use node - * ... - * } - * - * if ((node < 0) && (node != -FDT_ERR_NOT_FOUND)) { - * Error handling - * } - * - * Note that this is implemented as a macro and @node is used as - * iterator in the loop. The parent variable be constant or even a - * literal. - * - */ -#define fdt_for_each_subnode(node, fdt, parent) \ - for (node = fdt_first_subnode(fdt, parent); \ - node >= 0; \ - node = fdt_next_subnode(fdt, node)) - -/**********************************************************************/ -/* General functions */ -/**********************************************************************/ - -#define fdt_get_header(fdt, field) \ - (fdt32_to_cpu(((const struct fdt_header *)(fdt))->field)) -#define fdt_magic(fdt) (fdt_get_header(fdt, magic)) -#define fdt_totalsize(fdt) (fdt_get_header(fdt, totalsize)) -#define fdt_off_dt_struct(fdt) (fdt_get_header(fdt, off_dt_struct)) -#define fdt_off_dt_strings(fdt) (fdt_get_header(fdt, off_dt_strings)) -#define fdt_off_mem_rsvmap(fdt) (fdt_get_header(fdt, off_mem_rsvmap)) -#define fdt_version(fdt) (fdt_get_header(fdt, version)) -#define fdt_last_comp_version(fdt) (fdt_get_header(fdt, last_comp_version)) -#define fdt_boot_cpuid_phys(fdt) (fdt_get_header(fdt, boot_cpuid_phys)) -#define fdt_size_dt_strings(fdt) (fdt_get_header(fdt, size_dt_strings)) -#define fdt_size_dt_struct(fdt) (fdt_get_header(fdt, size_dt_struct)) - -#define __fdt_set_hdr(name) \ - static inline void fdt_set_##name(void *fdt, uint32_t val) \ - { \ - struct fdt_header *fdth = (struct fdt_header *)fdt; \ - fdth->name = cpu_to_fdt32(val); \ - } -__fdt_set_hdr(magic); -__fdt_set_hdr(totalsize); -__fdt_set_hdr(off_dt_struct); -__fdt_set_hdr(off_dt_strings); -__fdt_set_hdr(off_mem_rsvmap); -__fdt_set_hdr(version); -__fdt_set_hdr(last_comp_version); -__fdt_set_hdr(boot_cpuid_phys); -__fdt_set_hdr(size_dt_strings); -__fdt_set_hdr(size_dt_struct); -#undef __fdt_set_hdr - -/** - * fdt_check_header - sanity check a device tree or possible device tree - * @fdt: pointer to data which might be a flattened device tree - * - * fdt_check_header() checks that the given buffer contains what - * appears to be a flattened device tree with sane information in its - * header. - * - * returns: - * 0, if the buffer appears to contain a valid device tree - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, standard meanings, as above - */ -int fdt_check_header(const void *fdt); - -/** - * fdt_move - move a device tree around in memory - * @fdt: pointer to the device tree to move - * @buf: pointer to memory where the device is to be moved - * @bufsize: size of the memory space at buf - * - * fdt_move() relocates, if possible, the device tree blob located at - * fdt to the buffer at buf of size bufsize. The buffer may overlap - * with the existing device tree blob at fdt. Therefore, - * fdt_move(fdt, fdt, fdt_totalsize(fdt)) - * should always succeed. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, bufsize is insufficient to contain the device tree - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, standard meanings - */ -int fdt_move(const void *fdt, void *buf, int bufsize); - -/**********************************************************************/ -/* Read-only functions */ -/**********************************************************************/ - -/** - * fdt_string - retrieve a string from the strings block of a device tree - * @fdt: pointer to the device tree blob - * @stroffset: offset of the string within the strings block (native endian) - * - * fdt_string() retrieves a pointer to a single string from the - * strings block of the device tree blob at fdt. - * - * returns: - * a pointer to the string, on success - * NULL, if stroffset is out of bounds - */ -const char *fdt_string(const void *fdt, int stroffset); - -/** - * fdt_get_max_phandle - retrieves the highest phandle in a tree - * @fdt: pointer to the device tree blob - * - * fdt_get_max_phandle retrieves the highest phandle in the given - * device tree. This will ignore badly formatted phandles, or phandles - * with a value of 0 or -1. - * - * returns: - * the highest phandle on success - * 0, if no phandle was found in the device tree - * -1, if an error occurred - */ -uint32_t fdt_get_max_phandle(const void *fdt); - -/** - * fdt_num_mem_rsv - retrieve the number of memory reserve map entries - * @fdt: pointer to the device tree blob - * - * Returns the number of entries in the device tree blob's memory - * reservation map. This does not include the terminating 0,0 entry - * or any other (0,0) entries reserved for expansion. - * - * returns: - * the number of entries - */ -int fdt_num_mem_rsv(const void *fdt); - -/** - * fdt_get_mem_rsv - retrieve one memory reserve map entry - * @fdt: pointer to the device tree blob - * @address, @size: pointers to 64-bit variables - * - * On success, *address and *size will contain the address and size of - * the n-th reserve map entry from the device tree blob, in - * native-endian format. - * - * returns: - * 0, on success - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, standard meanings - */ -int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size); - -/** - * fdt_subnode_offset_namelen - find a subnode based on substring - * @fdt: pointer to the device tree blob - * @parentoffset: structure block offset of a node - * @name: name of the subnode to locate - * @namelen: number of characters of name to consider - * - * Identical to fdt_subnode_offset(), but only examine the first - * namelen characters of name for matching the subnode name. This is - * useful for finding subnodes based on a portion of a larger string, - * such as a full path. - */ -int fdt_subnode_offset_namelen(const void *fdt, int parentoffset, - const char *name, int namelen); -/** - * fdt_subnode_offset - find a subnode of a given node - * @fdt: pointer to the device tree blob - * @parentoffset: structure block offset of a node - * @name: name of the subnode to locate - * - * fdt_subnode_offset() finds a subnode of the node at structure block - * offset parentoffset with the given name. name may include a unit - * address, in which case fdt_subnode_offset() will find the subnode - * with that unit address, or the unit address may be omitted, in - * which case fdt_subnode_offset() will find an arbitrary subnode - * whose name excluding unit address matches the given name. - * - * returns: - * structure block offset of the requested subnode (>=0), on success - * -FDT_ERR_NOTFOUND, if the requested subnode does not exist - * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE - * tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings. - */ -int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name); - -/** - * fdt_path_offset_namelen - find a tree node by its full path - * @fdt: pointer to the device tree blob - * @path: full path of the node to locate - * @namelen: number of characters of path to consider - * - * Identical to fdt_path_offset(), but only consider the first namelen - * characters of path as the path name. - */ -int fdt_path_offset_namelen(const void *fdt, const char *path, int namelen); - -/** - * fdt_path_offset - find a tree node by its full path - * @fdt: pointer to the device tree blob - * @path: full path of the node to locate - * - * fdt_path_offset() finds a node of a given path in the device tree. - * Each path component may omit the unit address portion, but the - * results of this are undefined if any such path component is - * ambiguous (that is if there are multiple nodes at the relevant - * level matching the given component, differentiated only by unit - * address). - * - * returns: - * structure block offset of the node with the requested path (>=0), on - * success - * -FDT_ERR_BADPATH, given path does not begin with '/' or is invalid - * -FDT_ERR_NOTFOUND, if the requested node does not exist - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings. - */ -int fdt_path_offset(const void *fdt, const char *path); - -/** - * fdt_get_name - retrieve the name of a given node - * @fdt: pointer to the device tree blob - * @nodeoffset: structure block offset of the starting node - * @lenp: pointer to an integer variable (will be overwritten) or NULL - * - * fdt_get_name() retrieves the name (including unit address) of the - * device tree node at structure block offset nodeoffset. If lenp is - * non-NULL, the length of this name is also returned, in the integer - * pointed to by lenp. - * - * returns: - * pointer to the node's name, on success - * If lenp is non-NULL, *lenp contains the length of that name - * (>=0) - * NULL, on error - * if lenp is non-NULL *lenp contains an error code (<0): - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE - * tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, standard meanings - */ -const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp); - -/** - * fdt_first_property_offset - find the offset of a node's first property - * @fdt: pointer to the device tree blob - * @nodeoffset: structure block offset of a node - * - * fdt_first_property_offset() finds the first property of the node at - * the given structure block offset. - * - * returns: - * structure block offset of the property (>=0), on success - * -FDT_ERR_NOTFOUND, if the requested node has no properties - * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings. - */ -int fdt_first_property_offset(const void *fdt, int nodeoffset); - -/** - * fdt_next_property_offset - step through a node's properties - * @fdt: pointer to the device tree blob - * @offset: structure block offset of a property - * - * fdt_next_property_offset() finds the property immediately after the - * one at the given structure block offset. This will be a property - * of the same node as the given property. - * - * returns: - * structure block offset of the next property (>=0), on success - * -FDT_ERR_NOTFOUND, if the given property is the last in its node - * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_PROP tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings. - */ -int fdt_next_property_offset(const void *fdt, int offset); - -/** - * fdt_for_each_property_offset - iterate over all properties of a node - * - * @property_offset: property offset (int, lvalue) - * @fdt: FDT blob (const void *) - * @node: node offset (int) - * - * This is actually a wrapper around a for loop and would be used like so: - * - * fdt_for_each_property_offset(property, fdt, node) { - * Use property - * ... - * } - * - * if ((property < 0) && (property != -FDT_ERR_NOT_FOUND)) { - * Error handling - * } - * - * Note that this is implemented as a macro and property is used as - * iterator in the loop. The node variable can be constant or even a - * literal. - */ -#define fdt_for_each_property_offset(property, fdt, node) \ - for (property = fdt_first_property_offset(fdt, node); \ - property >= 0; \ - property = fdt_next_property_offset(fdt, property)) - -/** - * fdt_get_property_by_offset - retrieve the property at a given offset - * @fdt: pointer to the device tree blob - * @offset: offset of the property to retrieve - * @lenp: pointer to an integer variable (will be overwritten) or NULL - * - * fdt_get_property_by_offset() retrieves a pointer to the - * fdt_property structure within the device tree blob at the given - * offset. If lenp is non-NULL, the length of the property value is - * also returned, in the integer pointed to by lenp. - * - * returns: - * pointer to the structure representing the property - * if lenp is non-NULL, *lenp contains the length of the property - * value (>=0) - * NULL, on error - * if lenp is non-NULL, *lenp contains an error code (<0): - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -const struct fdt_property *fdt_get_property_by_offset(const void *fdt, - int offset, - int *lenp); - -/** - * fdt_get_property_namelen - find a property based on substring - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to find - * @name: name of the property to find - * @namelen: number of characters of name to consider - * @lenp: pointer to an integer variable (will be overwritten) or NULL - * - * Identical to fdt_get_property(), but only examine the first namelen - * characters of name for matching the property name. - */ -const struct fdt_property *fdt_get_property_namelen(const void *fdt, - int nodeoffset, - const char *name, - int namelen, int *lenp); - -/** - * fdt_get_property - find a given property in a given node - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to find - * @name: name of the property to find - * @lenp: pointer to an integer variable (will be overwritten) or NULL - * - * fdt_get_property() retrieves a pointer to the fdt_property - * structure within the device tree blob corresponding to the property - * named 'name' of the node at offset nodeoffset. If lenp is - * non-NULL, the length of the property value is also returned, in the - * integer pointed to by lenp. - * - * returns: - * pointer to the structure representing the property - * if lenp is non-NULL, *lenp contains the length of the property - * value (>=0) - * NULL, on error - * if lenp is non-NULL, *lenp contains an error code (<0): - * -FDT_ERR_NOTFOUND, node does not have named property - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE - * tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -const struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset, - const char *name, int *lenp); -static inline struct fdt_property *fdt_get_property_w(void *fdt, int nodeoffset, - const char *name, - int *lenp) -{ - return (struct fdt_property *)(uintptr_t) - fdt_get_property(fdt, nodeoffset, name, lenp); -} - -/** - * fdt_getprop_by_offset - retrieve the value of a property at a given offset - * @fdt: pointer to the device tree blob - * @ffset: offset of the property to read - * @namep: pointer to a string variable (will be overwritten) or NULL - * @lenp: pointer to an integer variable (will be overwritten) or NULL - * - * fdt_getprop_by_offset() retrieves a pointer to the value of the - * property at structure block offset 'offset' (this will be a pointer - * to within the device blob itself, not a copy of the value). If - * lenp is non-NULL, the length of the property value is also - * returned, in the integer pointed to by lenp. If namep is non-NULL, - * the property's namne will also be returned in the char * pointed to - * by namep (this will be a pointer to within the device tree's string - * block, not a new copy of the name). - * - * returns: - * pointer to the property's value - * if lenp is non-NULL, *lenp contains the length of the property - * value (>=0) - * if namep is non-NULL *namep contiains a pointer to the property - * name. - * NULL, on error - * if lenp is non-NULL, *lenp contains an error code (<0): - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -const void *fdt_getprop_by_offset(const void *fdt, int offset, - const char **namep, int *lenp); - -/** - * fdt_getprop_namelen - get property value based on substring - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to find - * @name: name of the property to find - * @namelen: number of characters of name to consider - * @lenp: pointer to an integer variable (will be overwritten) or NULL - * - * Identical to fdt_getprop(), but only examine the first namelen - * characters of name for matching the property name. - */ -const void *fdt_getprop_namelen(const void *fdt, int nodeoffset, - const char *name, int namelen, int *lenp); -static inline void *fdt_getprop_namelen_w(void *fdt, int nodeoffset, - const char *name, int namelen, - int *lenp) -{ - return (void *)(uintptr_t)fdt_getprop_namelen(fdt, nodeoffset, name, - namelen, lenp); -} - -/** - * fdt_getprop - retrieve the value of a given property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to find - * @name: name of the property to find - * @lenp: pointer to an integer variable (will be overwritten) or NULL - * - * fdt_getprop() retrieves a pointer to the value of the property - * named 'name' of the node at offset nodeoffset (this will be a - * pointer to within the device blob itself, not a copy of the value). - * If lenp is non-NULL, the length of the property value is also - * returned, in the integer pointed to by lenp. - * - * returns: - * pointer to the property's value - * if lenp is non-NULL, *lenp contains the length of the property - * value (>=0) - * NULL, on error - * if lenp is non-NULL, *lenp contains an error code (<0): - * -FDT_ERR_NOTFOUND, node does not have named property - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE - * tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -const void *fdt_getprop(const void *fdt, int nodeoffset, - const char *name, int *lenp); -static inline void *fdt_getprop_w(void *fdt, int nodeoffset, - const char *name, int *lenp) -{ - return (void *)(uintptr_t)fdt_getprop(fdt, nodeoffset, name, lenp); -} - -/** - * fdt_get_phandle - retrieve the phandle of a given node - * @fdt: pointer to the device tree blob - * @nodeoffset: structure block offset of the node - * - * fdt_get_phandle() retrieves the phandle of the device tree node at - * structure block offset nodeoffset. - * - * returns: - * the phandle of the node at nodeoffset, on success (!= 0, != -1) - * 0, if the node has no phandle, or another error occurs - */ -uint32_t fdt_get_phandle(const void *fdt, int nodeoffset); - -/** - * fdt_get_alias_namelen - get alias based on substring - * @fdt: pointer to the device tree blob - * @name: name of the alias th look up - * @namelen: number of characters of name to consider - * - * Identical to fdt_get_alias(), but only examine the first namelen - * characters of name for matching the alias name. - */ -const char *fdt_get_alias_namelen(const void *fdt, - const char *name, int namelen); - -/** - * fdt_get_alias - retrieve the path referenced by a given alias - * @fdt: pointer to the device tree blob - * @name: name of the alias th look up - * - * fdt_get_alias() retrieves the value of a given alias. That is, the - * value of the property named 'name' in the node /aliases. - * - * returns: - * a pointer to the expansion of the alias named 'name', if it exists - * NULL, if the given alias or the /aliases node does not exist - */ -const char *fdt_get_alias(const void *fdt, const char *name); - -/** - * fdt_get_path - determine the full path of a node - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose path to find - * @buf: character buffer to contain the returned path (will be overwritten) - * @buflen: size of the character buffer at buf - * - * fdt_get_path() computes the full path of the node at offset - * nodeoffset, and records that path in the buffer at buf. - * - * NOTE: This function is expensive, as it must scan the device tree - * structure from the start to nodeoffset. - * - * returns: - * 0, on success - * buf contains the absolute path of the node at - * nodeoffset, as a NUL-terminated string. - * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag - * -FDT_ERR_NOSPACE, the path of the given node is longer than (bufsize-1) - * characters and will not fit in the given buffer. - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, standard meanings - */ -int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen); - -/** - * fdt_supernode_atdepth_offset - find a specific ancestor of a node - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose parent to find - * @supernodedepth: depth of the ancestor to find - * @nodedepth: pointer to an integer variable (will be overwritten) or NULL - * - * fdt_supernode_atdepth_offset() finds an ancestor of the given node - * at a specific depth from the root (where the root itself has depth - * 0, its immediate subnodes depth 1 and so forth). So - * fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, NULL); - * will always return 0, the offset of the root node. If the node at - * nodeoffset has depth D, then: - * fdt_supernode_atdepth_offset(fdt, nodeoffset, D, NULL); - * will return nodeoffset itself. - * - * NOTE: This function is expensive, as it must scan the device tree - * structure from the start to nodeoffset. - * - * returns: - * structure block offset of the node at node offset's ancestor - * of depth supernodedepth (>=0), on success - * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag - * -FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of - * nodeoffset - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, standard meanings - */ -int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset, - int supernodedepth, int *nodedepth); - -/** - * fdt_node_depth - find the depth of a given node - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose parent to find - * - * fdt_node_depth() finds the depth of a given node. The root node - * has depth 0, its immediate subnodes depth 1 and so forth. - * - * NOTE: This function is expensive, as it must scan the device tree - * structure from the start to nodeoffset. - * - * returns: - * depth of the node at nodeoffset (>=0), on success - * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, standard meanings - */ -int fdt_node_depth(const void *fdt, int nodeoffset); - -/** - * fdt_parent_offset - find the parent of a given node - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose parent to find - * - * fdt_parent_offset() locates the parent node of a given node (that - * is, it finds the offset of the node which contains the node at - * nodeoffset as a subnode). - * - * NOTE: This function is expensive, as it must scan the device tree - * structure from the start to nodeoffset, *twice*. - * - * returns: - * structure block offset of the parent of the node at nodeoffset - * (>=0), on success - * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, standard meanings - */ -int fdt_parent_offset(const void *fdt, int nodeoffset); - -/** - * fdt_node_offset_by_prop_value - find nodes with a given property value - * @fdt: pointer to the device tree blob - * @startoffset: only find nodes after this offset - * @propname: property name to check - * @propval: property value to search for - * @proplen: length of the value in propval - * - * fdt_node_offset_by_prop_value() returns the offset of the first - * node after startoffset, which has a property named propname whose - * value is of length proplen and has value equal to propval; or if - * startoffset is -1, the very first such node in the tree. - * - * To iterate through all nodes matching the criterion, the following - * idiom can be used: - * offset = fdt_node_offset_by_prop_value(fdt, -1, propname, - * propval, proplen); - * while (offset != -FDT_ERR_NOTFOUND) { - * // other code here - * offset = fdt_node_offset_by_prop_value(fdt, offset, propname, - * propval, proplen); - * } - * - * Note the -1 in the first call to the function, if 0 is used here - * instead, the function will never locate the root node, even if it - * matches the criterion. - * - * returns: - * structure block offset of the located node (>= 0, >startoffset), - * on success - * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the - * tree after startoffset - * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, standard meanings - */ -int fdt_node_offset_by_prop_value(const void *fdt, int startoffset, - const char *propname, - const void *propval, int proplen); - -/** - * fdt_node_offset_by_phandle - find the node with a given phandle - * @fdt: pointer to the device tree blob - * @phandle: phandle value - * - * fdt_node_offset_by_phandle() returns the offset of the node - * which has the given phandle value. If there is more than one node - * in the tree with the given phandle (an invalid tree), results are - * undefined. - * - * returns: - * structure block offset of the located node (>= 0), on success - * -FDT_ERR_NOTFOUND, no node with that phandle exists - * -FDT_ERR_BADPHANDLE, given phandle value was invalid (0 or -1) - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, standard meanings - */ -int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle); - -/** - * fdt_node_check_compatible: check a node's compatible property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of a tree node - * @compatible: string to match against - * - * - * fdt_node_check_compatible() returns 0 if the given node contains a - * 'compatible' property with the given string as one of its elements, - * it returns non-zero otherwise, or on error. - * - * returns: - * 0, if the node has a 'compatible' property listing the given string - * 1, if the node has a 'compatible' property, but it does not list - * the given string - * -FDT_ERR_NOTFOUND, if the given node has no 'compatible' property - * -FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, standard meanings - */ -int fdt_node_check_compatible(const void *fdt, int nodeoffset, - const char *compatible); - -/** - * fdt_node_offset_by_compatible - find nodes with a given 'compatible' value - * @fdt: pointer to the device tree blob - * @startoffset: only find nodes after this offset - * @compatible: 'compatible' string to match against - * - * fdt_node_offset_by_compatible() returns the offset of the first - * node after startoffset, which has a 'compatible' property which - * lists the given compatible string; or if startoffset is -1, the - * very first such node in the tree. - * - * To iterate through all nodes matching the criterion, the following - * idiom can be used: - * offset = fdt_node_offset_by_compatible(fdt, -1, compatible); - * while (offset != -FDT_ERR_NOTFOUND) { - * // other code here - * offset = fdt_node_offset_by_compatible(fdt, offset, compatible); - * } - * - * Note the -1 in the first call to the function, if 0 is used here - * instead, the function will never locate the root node, even if it - * matches the criterion. - * - * returns: - * structure block offset of the located node (>= 0, >startoffset), - * on success - * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the - * tree after startoffset - * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, standard meanings - */ -int fdt_node_offset_by_compatible(const void *fdt, int startoffset, - const char *compatible); - -/** - * fdt_stringlist_contains - check a string list property for a string - * @strlist: Property containing a list of strings to check - * @listlen: Length of property - * @str: String to search for - * - * This is a utility function provided for convenience. The list contains - * one or more strings, each terminated by \0, as is found in a device tree - * "compatible" property. - * - * @return: 1 if the string is found in the list, 0 not found, or invalid list - */ -int fdt_stringlist_contains(const char *strlist, int listlen, const char *str); - -/** - * fdt_stringlist_count - count the number of strings in a string list - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of a tree node - * @property: name of the property containing the string list - * @return: - * the number of strings in the given property - * -FDT_ERR_BADVALUE if the property value is not NUL-terminated - * -FDT_ERR_NOTFOUND if the property does not exist - */ -int fdt_stringlist_count(const void *fdt, int nodeoffset, const char *property); - -/** - * fdt_stringlist_search - find a string in a string list and return its index - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of a tree node - * @property: name of the property containing the string list - * @string: string to look up in the string list - * - * Note that it is possible for this function to succeed on property values - * that are not NUL-terminated. That's because the function will stop after - * finding the first occurrence of @string. This can for example happen with - * small-valued cell properties, such as #address-cells, when searching for - * the empty string. - * - * @return: - * the index of the string in the list of strings - * -FDT_ERR_BADVALUE if the property value is not NUL-terminated - * -FDT_ERR_NOTFOUND if the property does not exist or does not contain - * the given string - */ -int fdt_stringlist_search(const void *fdt, int nodeoffset, const char *property, - const char *string); - -/** - * fdt_stringlist_get() - obtain the string at a given index in a string list - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of a tree node - * @property: name of the property containing the string list - * @index: index of the string to return - * @lenp: return location for the string length or an error code on failure - * - * Note that this will successfully extract strings from properties with - * non-NUL-terminated values. For example on small-valued cell properties - * this function will return the empty string. - * - * If non-NULL, the length of the string (on success) or a negative error-code - * (on failure) will be stored in the integer pointer to by lenp. - * - * @return: - * A pointer to the string at the given index in the string list or NULL on - * failure. On success the length of the string will be stored in the memory - * location pointed to by the lenp parameter, if non-NULL. On failure one of - * the following negative error codes will be returned in the lenp parameter - * (if non-NULL): - * -FDT_ERR_BADVALUE if the property value is not NUL-terminated - * -FDT_ERR_NOTFOUND if the property does not exist - */ -const char *fdt_stringlist_get(const void *fdt, int nodeoffset, - const char *property, int index, - int *lenp); - -/**********************************************************************/ -/* Read-only functions (addressing related) */ -/**********************************************************************/ - -/** - * FDT_MAX_NCELLS - maximum value for #address-cells and #size-cells - * - * This is the maximum value for #address-cells, #size-cells and - * similar properties that will be processed by libfdt. IEE1275 - * requires that OF implementations handle values up to 4. - * Implementations may support larger values, but in practice higher - * values aren't used. - */ -#define FDT_MAX_NCELLS 4 - -/** - * fdt_address_cells - retrieve address size for a bus represented in the tree - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node to find the address size for - * - * When the node has a valid #address-cells property, returns its value. - * - * returns: - * 0 <= n < FDT_MAX_NCELLS, on success - * 2, if the node has no #address-cells property - * -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid - * #address-cells property - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_address_cells(const void *fdt, int nodeoffset); - -/** - * fdt_size_cells - retrieve address range size for a bus represented in the - * tree - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node to find the address range size for - * - * When the node has a valid #size-cells property, returns its value. - * - * returns: - * 0 <= n < FDT_MAX_NCELLS, on success - * 2, if the node has no #address-cells property - * -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid - * #size-cells property - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_size_cells(const void *fdt, int nodeoffset); - - -/**********************************************************************/ -/* Write-in-place functions */ -/**********************************************************************/ - -/** - * fdt_setprop_inplace_namelen_partial - change a property's value, - * but not its size - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @namelen: number of characters of name to consider - * @idx: index of the property to change in the array - * @val: pointer to data to replace the property value with - * @len: length of the property value - * - * Identical to fdt_setprop_inplace(), but modifies the given property - * starting from the given index, and using only the first characters - * of the name. It is useful when you want to manipulate only one value of - * an array and you have a string that doesn't end with \0. - */ -int fdt_setprop_inplace_namelen_partial(void *fdt, int nodeoffset, - const char *name, int namelen, - uint32_t idx, const void *val, - int len); - -/** - * fdt_setprop_inplace - change a property's value, but not its size - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @val: pointer to data to replace the property value with - * @len: length of the property value - * - * fdt_setprop_inplace() replaces the value of a given property with - * the data in val, of length len. This function cannot change the - * size of a property, and so will only work if len is equal to the - * current length of the property. - * - * This function will alter only the bytes in the blob which contain - * the given property value, and will not alter or move any other part - * of the tree. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, if len is not equal to the property's current length - * -FDT_ERR_NOTFOUND, node does not have the named property - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, - const void *val, int len); - -/** - * fdt_setprop_inplace_u32 - change the value of a 32-bit integer property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @val: 32-bit integer value to replace the property with - * - * fdt_setprop_inplace_u32() replaces the value of a given property - * with the 32-bit integer value in val, converting val to big-endian - * if necessary. This function cannot change the size of a property, - * and so will only work if the property already exists and has length - * 4. - * - * This function will alter only the bytes in the blob which contain - * the given property value, and will not alter or move any other part - * of the tree. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, if the property's length is not equal to 4 - * -FDT_ERR_NOTFOUND, node does not have the named property - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset, - const char *name, uint32_t val) -{ - fdt32_t tmp = cpu_to_fdt32(val); - return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); -} - -/** - * fdt_setprop_inplace_u64 - change the value of a 64-bit integer property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @val: 64-bit integer value to replace the property with - * - * fdt_setprop_inplace_u64() replaces the value of a given property - * with the 64-bit integer value in val, converting val to big-endian - * if necessary. This function cannot change the size of a property, - * and so will only work if the property already exists and has length - * 8. - * - * This function will alter only the bytes in the blob which contain - * the given property value, and will not alter or move any other part - * of the tree. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, if the property's length is not equal to 8 - * -FDT_ERR_NOTFOUND, node does not have the named property - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset, - const char *name, uint64_t val) -{ - fdt64_t tmp = cpu_to_fdt64(val); - return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); -} - -/** - * fdt_setprop_inplace_cell - change the value of a single-cell property - * - * This is an alternative name for fdt_setprop_inplace_u32() - */ -static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset, - const char *name, uint32_t val) -{ - return fdt_setprop_inplace_u32(fdt, nodeoffset, name, val); -} - -/** - * fdt_nop_property - replace a property with nop tags - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to nop - * @name: name of the property to nop - * - * fdt_nop_property() will replace a given property's representation - * in the blob with FDT_NOP tags, effectively removing it from the - * tree. - * - * This function will alter only the bytes in the blob which contain - * the property, and will not alter or move any other part of the - * tree. - * - * returns: - * 0, on success - * -FDT_ERR_NOTFOUND, node does not have the named property - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_nop_property(void *fdt, int nodeoffset, const char *name); - -/** - * fdt_nop_node - replace a node (subtree) with nop tags - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node to nop - * - * fdt_nop_node() will replace a given node's representation in the - * blob, including all its subnodes, if any, with FDT_NOP tags, - * effectively removing it from the tree. - * - * This function will alter only the bytes in the blob which contain - * the node and its properties and subnodes, and will not alter or - * move any other part of the tree. - * - * returns: - * 0, on success - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_nop_node(void *fdt, int nodeoffset); - -/**********************************************************************/ -/* Sequential write functions */ -/**********************************************************************/ - -int fdt_create(void *buf, int bufsize); -int fdt_resize(void *fdt, void *buf, int bufsize); -int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size); -int fdt_finish_reservemap(void *fdt); -int fdt_begin_node(void *fdt, const char *name); -int fdt_property(void *fdt, const char *name, const void *val, int len); -static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val) -{ - fdt32_t tmp = cpu_to_fdt32(val); - return fdt_property(fdt, name, &tmp, sizeof(tmp)); -} -static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val) -{ - fdt64_t tmp = cpu_to_fdt64(val); - return fdt_property(fdt, name, &tmp, sizeof(tmp)); -} -static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val) -{ - return fdt_property_u32(fdt, name, val); -} - -/** - * fdt_property_placeholder - add a new property and return a ptr to its value - * - * @fdt: pointer to the device tree blob - * @name: name of property to add - * @len: length of property value in bytes - * @valp: returns a pointer to where where the value should be placed - * - * returns: - * 0, on success - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_NOSPACE, standard meanings - */ -int fdt_property_placeholder(void *fdt, const char *name, int len, void **valp); - -#define fdt_property_string(fdt, name, str) \ - fdt_property(fdt, name, str, strlen(str)+1) -int fdt_end_node(void *fdt); -int fdt_finish(void *fdt); - -/**********************************************************************/ -/* Read-write functions */ -/**********************************************************************/ - -int fdt_create_empty_tree(void *buf, int bufsize); -int fdt_open_into(const void *fdt, void *buf, int bufsize); -int fdt_pack(void *fdt); - -/** - * fdt_add_mem_rsv - add one memory reserve map entry - * @fdt: pointer to the device tree blob - * @address, @size: 64-bit values (native endian) - * - * Adds a reserve map entry to the given blob reserving a region at - * address address of length size. - * - * This function will insert data into the reserve map and will - * therefore change the indexes of some entries in the table. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new reservation entry - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size); - -/** - * fdt_del_mem_rsv - remove a memory reserve map entry - * @fdt: pointer to the device tree blob - * @n: entry to remove - * - * fdt_del_mem_rsv() removes the n-th memory reserve map entry from - * the blob. - * - * This function will delete data from the reservation table and will - * therefore change the indexes of some entries in the table. - * - * returns: - * 0, on success - * -FDT_ERR_NOTFOUND, there is no entry of the given index (i.e. there - * are less than n+1 reserve map entries) - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_del_mem_rsv(void *fdt, int n); - -/** - * fdt_set_name - change the name of a given node - * @fdt: pointer to the device tree blob - * @nodeoffset: structure block offset of a node - * @name: name to give the node - * - * fdt_set_name() replaces the name (including unit address, if any) - * of the given node with the given string. NOTE: this function can't - * efficiently check if the new name is unique amongst the given - * node's siblings; results are undefined if this function is invoked - * with a name equal to one of the given node's siblings. - * - * This function may insert or delete data from the blob, and will - * therefore change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob - * to contain the new name - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, standard meanings - */ -int fdt_set_name(void *fdt, int nodeoffset, const char *name); - -/** - * fdt_setprop - create or change a property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @val: pointer to data to set the property value to - * @len: length of the property value - * - * fdt_setprop() sets the value of the named property in the given - * node to the given value and length, creating the property if it - * does not already exist. - * - * This function may insert or delete data from the blob, and will - * therefore change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new property value - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_setprop(void *fdt, int nodeoffset, const char *name, - const void *val, int len); - -/** - * fdt_setprop_u32 - set a property to a 32-bit integer - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @val: 32-bit integer value for the property (native endian) - * - * fdt_setprop_u32() sets the value of the named property in the given - * node to the given 32-bit integer value (converting to big-endian if - * necessary), or creates a new property with that value if it does - * not already exist. - * - * This function may insert or delete data from the blob, and will - * therefore change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new property value - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name, - uint32_t val) -{ - fdt32_t tmp = cpu_to_fdt32(val); - return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); -} - -/** - * fdt_setprop_u64 - set a property to a 64-bit integer - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @val: 64-bit integer value for the property (native endian) - * - * fdt_setprop_u64() sets the value of the named property in the given - * node to the given 64-bit integer value (converting to big-endian if - * necessary), or creates a new property with that value if it does - * not already exist. - * - * This function may insert or delete data from the blob, and will - * therefore change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new property value - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name, - uint64_t val) -{ - fdt64_t tmp = cpu_to_fdt64(val); - return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); -} - -/** - * fdt_setprop_cell - set a property to a single cell value - * - * This is an alternative name for fdt_setprop_u32() - */ -static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name, - uint32_t val) -{ - return fdt_setprop_u32(fdt, nodeoffset, name, val); -} - -/** - * fdt_setprop_string - set a property to a string value - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @str: string value for the property - * - * fdt_setprop_string() sets the value of the named property in the - * given node to the given string value (using the length of the - * string to determine the new length of the property), or creates a - * new property with that value if it does not already exist. - * - * This function may insert or delete data from the blob, and will - * therefore change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new property value - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -#define fdt_setprop_string(fdt, nodeoffset, name, str) \ - fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) - -/** - * fdt_appendprop - append to or create a property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to append to - * @val: pointer to data to append to the property value - * @len: length of the data to append to the property value - * - * fdt_appendprop() appends the value to the named property in the - * given node, creating the property if it does not already exist. - * - * This function may insert data into the blob, and will therefore - * change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new property value - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_appendprop(void *fdt, int nodeoffset, const char *name, - const void *val, int len); - -/** - * fdt_appendprop_u32 - append a 32-bit integer value to a property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @val: 32-bit integer value to append to the property (native endian) - * - * fdt_appendprop_u32() appends the given 32-bit integer value - * (converting to big-endian if necessary) to the value of the named - * property in the given node, or creates a new property with that - * value if it does not already exist. - * - * This function may insert data into the blob, and will therefore - * change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new property value - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -static inline int fdt_appendprop_u32(void *fdt, int nodeoffset, - const char *name, uint32_t val) -{ - fdt32_t tmp = cpu_to_fdt32(val); - return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); -} - -/** - * fdt_appendprop_u64 - append a 64-bit integer value to a property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @val: 64-bit integer value to append to the property (native endian) - * - * fdt_appendprop_u64() appends the given 64-bit integer value - * (converting to big-endian if necessary) to the value of the named - * property in the given node, or creates a new property with that - * value if it does not already exist. - * - * This function may insert data into the blob, and will therefore - * change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new property value - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -static inline int fdt_appendprop_u64(void *fdt, int nodeoffset, - const char *name, uint64_t val) -{ - fdt64_t tmp = cpu_to_fdt64(val); - return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); -} - -/** - * fdt_appendprop_cell - append a single cell value to a property - * - * This is an alternative name for fdt_appendprop_u32() - */ -static inline int fdt_appendprop_cell(void *fdt, int nodeoffset, - const char *name, uint32_t val) -{ - return fdt_appendprop_u32(fdt, nodeoffset, name, val); -} - -/** - * fdt_appendprop_string - append a string to a property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to change - * @name: name of the property to change - * @str: string value to append to the property - * - * fdt_appendprop_string() appends the given string to the value of - * the named property in the given node, or creates a new property - * with that value if it does not already exist. - * - * This function may insert data into the blob, and will therefore - * change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to - * contain the new property value - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_TRUNCATED, standard meanings - */ -#define fdt_appendprop_string(fdt, nodeoffset, name, str) \ - fdt_appendprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) - -/** - * fdt_delprop - delete a property - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node whose property to nop - * @name: name of the property to nop - * - * fdt_del_property() will delete the given property. - * - * This function will delete data from the blob, and will therefore - * change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_NOTFOUND, node does not have the named property - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_delprop(void *fdt, int nodeoffset, const char *name); - -/** - * fdt_add_subnode_namelen - creates a new node based on substring - * @fdt: pointer to the device tree blob - * @parentoffset: structure block offset of a node - * @name: name of the subnode to locate - * @namelen: number of characters of name to consider - * - * Identical to fdt_add_subnode(), but use only the first namelen - * characters of name as the name of the new node. This is useful for - * creating subnodes based on a portion of a larger string, such as a - * full path. - */ -int fdt_add_subnode_namelen(void *fdt, int parentoffset, - const char *name, int namelen); - -/** - * fdt_add_subnode - creates a new node - * @fdt: pointer to the device tree blob - * @parentoffset: structure block offset of a node - * @name: name of the subnode to locate - * - * fdt_add_subnode() creates a new node as a subnode of the node at - * structure block offset parentoffset, with the given name (which - * should include the unit address, if any). - * - * This function will insert data into the blob, and will therefore - * change the offsets of some existing nodes. - - * returns: - * structure block offset of the created nodeequested subnode (>=0), on - * success - * -FDT_ERR_NOTFOUND, if the requested subnode does not exist - * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE - * tag - * -FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of - * the given name - * -FDT_ERR_NOSPACE, if there is insufficient free space in the - * blob to contain the new node - * -FDT_ERR_NOSPACE - * -FDT_ERR_BADLAYOUT - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings. - */ -int fdt_add_subnode(void *fdt, int parentoffset, const char *name); - -/** - * fdt_del_node - delete a node (subtree) - * @fdt: pointer to the device tree blob - * @nodeoffset: offset of the node to nop - * - * fdt_del_node() will remove the given node, including all its - * subnodes if any, from the blob. - * - * This function will delete data from the blob, and will therefore - * change the offsets of some existing nodes. - * - * returns: - * 0, on success - * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_del_node(void *fdt, int nodeoffset); - -/** - * fdt_overlay_apply - Applies a DT overlay on a base DT - * @fdt: pointer to the base device tree blob - * @fdto: pointer to the device tree overlay blob - * - * fdt_overlay_apply() will apply the given device tree overlay on the - * given base device tree. - * - * Expect the base device tree to be modified, even if the function - * returns an error. - * - * returns: - * 0, on success - * -FDT_ERR_NOSPACE, there's not enough space in the base device tree - * -FDT_ERR_NOTFOUND, the overlay points to some inexistant nodes or - * properties in the base DT - * -FDT_ERR_BADPHANDLE, - * -FDT_ERR_BADOVERLAY, - * -FDT_ERR_NOPHANDLES, - * -FDT_ERR_INTERNAL, - * -FDT_ERR_BADLAYOUT, - * -FDT_ERR_BADMAGIC, - * -FDT_ERR_BADOFFSET, - * -FDT_ERR_BADPATH, - * -FDT_ERR_BADVERSION, - * -FDT_ERR_BADSTRUCTURE, - * -FDT_ERR_BADSTATE, - * -FDT_ERR_TRUNCATED, standard meanings - */ -int fdt_overlay_apply(void *fdt, void *fdto); - -/**********************************************************************/ -/* Debugging / informational functions */ -/**********************************************************************/ - -const char *fdt_strerror(int errval); - -/** - * fdt_remove_unused_strings() - Remove any unused strings from an FDT - * - * This creates a new device tree in @new with unused strings removed. The - * called can then use fdt_pack() to minimise the space consumed. - * - * @old: Old device tree blog - * @new: Place to put new device tree blob, which must be as large as - * @old - * @return - * 0, on success - * -FDT_ERR_BADOFFSET, corrupt device tree - * -FDT_ERR_NOSPACE, out of space, which should not happen unless there - * is something very wrong with the device tree input - */ -int fdt_remove_unused_strings(const void *old, void *new); - -struct fdt_region { - int offset; - int size; -}; - -/* - * Flags for fdt_find_regions() - * - * Add a region for the string table (always the last region) - */ -#define FDT_REG_ADD_STRING_TAB (1 << 0) - -/* - * Add all supernodes of a matching node/property, useful for creating a - * valid subset tree - */ -#define FDT_REG_SUPERNODES (1 << 1) - -/* Add the FDT_BEGIN_NODE tags of subnodes, including their names */ -#define FDT_REG_DIRECT_SUBNODES (1 << 2) - -/* Add all subnodes of a matching node */ -#define FDT_REG_ALL_SUBNODES (1 << 3) - -/* Add a region for the mem_rsvmap table (always the first region) */ -#define FDT_REG_ADD_MEM_RSVMAP (1 << 4) - -/* Indicates what an fdt part is (node, property, value) */ -#define FDT_IS_NODE (1 << 0) -#define FDT_IS_PROP (1 << 1) -#define FDT_IS_VALUE (1 << 2) /* not supported */ -#define FDT_IS_COMPAT (1 << 3) /* used internally */ -#define FDT_NODE_HAS_PROP (1 << 4) /* node contains prop */ - -#define FDT_ANY_GLOBAL (FDT_IS_NODE | FDT_IS_PROP | FDT_IS_VALUE | \ - FDT_IS_COMPAT) -#define FDT_IS_ANY 0x1f /* all the above */ - -/* We set a reasonable limit on the number of nested nodes */ -#define FDT_MAX_DEPTH 32 - -/* Decribes what we want to include from the current tag */ -enum want_t { - WANT_NOTHING, - WANT_NODES_ONLY, /* No properties */ - WANT_NODES_AND_PROPS, /* Everything for one level */ - WANT_ALL_NODES_AND_PROPS /* Everything for all levels */ -}; - -/* Keeps track of the state at parent nodes */ -struct fdt_subnode_stack { - int offset; /* Offset of node */ - enum want_t want; /* The 'want' value here */ - int included; /* 1 if we included this node, 0 if not */ -}; - -struct fdt_region_ptrs { - int depth; /* Current tree depth */ - int done; /* What we have completed scanning */ - enum want_t want; /* What we are currently including */ - char *end; /* Pointer to end of full node path */ - int nextoffset; /* Next node offset to check */ -}; - -/* The state of our finding algortihm */ -struct fdt_region_state { - struct fdt_subnode_stack stack[FDT_MAX_DEPTH]; /* node stack */ - struct fdt_region *region; /* Contains list of regions found */ - int count; /* Numnber of regions found */ - const void *fdt; /* FDT blob */ - int max_regions; /* Maximum regions to find */ - int can_merge; /* 1 if we can merge with previous region */ - int start; /* Start position of current region */ - struct fdt_region_ptrs ptrs; /* Pointers for what we are up to */ -}; - -/** - * fdt_find_regions() - find regions in device tree - * - * Given a list of nodes to include and properties to exclude, find - * the regions of the device tree which describe those included parts. - * - * The intent is to get a list of regions which will be invariant provided - * those parts are invariant. For example, if you request a list of regions - * for all nodes but exclude the property "data", then you will get the - * same region contents regardless of any change to "data" properties. - * - * This function can be used to produce a byte-stream to send to a hashing - * function to verify that critical parts of the FDT have not changed. - * - * Nodes which are given in 'inc' are included in the region list, as - * are the names of the immediate subnodes nodes (but not the properties - * or subnodes of those subnodes). - * - * For eaxample "/" means to include the root node, all root properties - * and the FDT_BEGIN_NODE and FDT_END_NODE of all subnodes of /. The latter - * ensures that we capture the names of the subnodes. In a hashing situation - * it prevents the root node from changing at all Any change to non-excluded - * properties, names of subnodes or number of subnodes would be detected. - * - * When used with FITs this provides the ability to hash and sign parts of - * the FIT based on different configurations in the FIT. Then it is - * impossible to change anything about that configuration (include images - * attached to the configuration), but it may be possible to add new - * configurations, new images or new signatures within the existing - * framework. - * - * Adding new properties to a device tree may result in the string table - * being extended (if the new property names are different from those - * already added). This function can optionally include a region for - * the string table so that this can be part of the hash too. - * - * The device tree header is not included in the list. - * - * @fdt: Device tree to check - * @inc: List of node paths to included - * @inc_count: Number of node paths in list - * @exc_prop: List of properties names to exclude - * @exc_prop_count: Number of properties in exclude list - * @region: Returns list of regions - * @max_region: Maximum length of region list - * @path: Pointer to a temporary string for the function to use for - * building path names - * @path_len: Length of path, must be large enough to hold the longest - * path in the tree - * @add_string_tab: 1 to add a region for the string table - * @return number of regions in list. If this is >max_regions then the - * region array was exhausted. You should increase max_regions and try - * the call again. - */ -int fdt_find_regions(const void *fdt, char * const inc[], int inc_count, - char * const exc_prop[], int exc_prop_count, - struct fdt_region region[], int max_regions, - char *path, int path_len, int add_string_tab); - -/** - * fdt_first_region() - find regions in device tree - * - * Given a nodes and properties to include and properties to exclude, find - * the regions of the device tree which describe those included parts. - * - * The use for this function is twofold. Firstly it provides a convenient - * way of performing a structure-aware grep of the tree. For example it is - * possible to grep for a node and get all the properties associated with - * that node. Trees can be subsetted easily, by specifying the nodes that - * are required, and then writing out the regions returned by this function. - * This is useful for small resource-constrained systems, such as boot - * loaders, which want to use an FDT but do not need to know about all of - * it. - * - * Secondly it makes it easy to hash parts of the tree and detect changes. - * The intent is to get a list of regions which will be invariant provided - * those parts are invariant. For example, if you request a list of regions - * for all nodes but exclude the property "data", then you will get the - * same region contents regardless of any change to "data" properties. - * - * This function can be used to produce a byte-stream to send to a hashing - * function to verify that critical parts of the FDT have not changed. - * Note that semantically null changes in order could still cause false - * hash misses. Such reordering might happen if the tree is regenerated - * from source, and nodes are reordered (the bytes-stream will be emitted - * in a different order and mnay hash functions will detect this). However - * if an existing tree is modified using libfdt functions, such as - * fdt_add_subnode() and fdt_setprop(), then this problem is avoided. - * - * The nodes/properties to include/exclude are defined by a function - * provided by the caller. This function is called for each node and - * property, and must return: - * - * 0 - to exclude this part - * 1 - to include this part - * -1 - for FDT_IS_PROP only: no information is available, so include - * if its containing node is included - * - * The last case is only used to deal with properties. Often a property is - * included if its containing node is included - this is the case where - * -1 is returned.. However if the property is specifically required to be - * included/excluded, then 0 or 1 can be returned. Note that including a - * property when the FDT_REG_SUPERNODES flag is given will force its - * containing node to be included since it is not valid to have a property - * that is not in a node. - * - * Using the information provided, the inclusion of a node can be controlled - * either by a node name or its compatible string, or any other property - * that the function can determine. - * - * As an example, including node "/" means to include the root node and all - * root properties. A flag provides a way of also including supernodes (of - * which there is none for the root node), and another flag includes - * immediate subnodes, so in this case we would get the FDT_BEGIN_NODE and - * FDT_END_NODE of all subnodes of /. - * - * The subnode feature helps in a hashing situation since it prevents the - * root node from changing at all. Any change to non-excluded properties, - * names of subnodes or number of subnodes would be detected. - * - * When used with FITs this provides the ability to hash and sign parts of - * the FIT based on different configurations in the FIT. Then it is - * impossible to change anything about that configuration (include images - * attached to the configuration), but it may be possible to add new - * configurations, new images or new signatures within the existing - * framework. - * - * Adding new properties to a device tree may result in the string table - * being extended (if the new property names are different from those - * already added). This function can optionally include a region for - * the string table so that this can be part of the hash too. This is always - * the last region. - * - * The FDT also has a mem_rsvmap table which can also be included, and is - * always the first region if so. - * - * The device tree header is not included in the region list. Since the - * contents of the FDT are changing (shrinking, often), the caller will need - * to regenerate the header anyway. - * - * @fdt: Device tree to check - * @h_include: Function to call to determine whether to include a part or - * not: - * - * @priv: Private pointer as passed to fdt_find_regions() - * @fdt: Pointer to FDT blob - * @offset: Offset of this node / property - * @type: Type of this part, FDT_IS_... - * @data: Pointer to data (node name, property name, compatible - * string, value (not yet supported) - * @size: Size of data, or 0 if none - * @return 0 to exclude, 1 to include, -1 if no information is - * available - * @priv: Private pointer passed to h_include - * @region: Returns list of regions, sorted by offset - * @max_regions: Maximum length of region list - * @path: Pointer to a temporary string for the function to use for - * building path names - * @path_len: Length of path, must be large enough to hold the longest - * path in the tree - * @flags: Various flags that control the region algortihm, see - * FDT_REG_... - * @return number of regions in list. If this is >max_regions then the - * region array was exhausted. You should increase max_regions and try - * the call again. Only the first max_regions elements are available in the - * array. - * - * On error a -ve value is return, which can be: - * - * -FDT_ERR_BADSTRUCTURE (too deep or more END tags than BEGIN tags - * -FDT_ERR_BADLAYOUT - * -FDT_ERR_NOSPACE (path area is too small) - */ -int fdt_first_region(const void *fdt, - int (*h_include)(void *priv, const void *fdt, int offset, - int type, const char *data, int size), - void *priv, struct fdt_region *region, - char *path, int path_len, int flags, - struct fdt_region_state *info); - -/** fdt_next_region() - find next region - * - * See fdt_first_region() for full description. This function finds the - * next region according to the provided parameters, which must be the same - * as passed to fdt_first_region(). - * - * This function can additionally return -FDT_ERR_NOTFOUND when there are no - * more regions - */ -int fdt_next_region(const void *fdt, - int (*h_include)(void *priv, const void *fdt, int offset, - int type, const char *data, int size), - void *priv, struct fdt_region *region, - char *path, int path_len, int flags, - struct fdt_region_state *info); - -/** - * fdt_add_alias_regions() - find aliases that point to existing regions - * - * Once a device tree grep is complete some of the nodes will be present - * and some will have been dropped. This function checks all the alias nodes - * to figure out which points point to nodes which are still present. These - * aliases need to be kept, along with the nodes they reference. - * - * Given a list of regions function finds the aliases that still apply and - * adds more regions to the list for these. This function is called after - * fdt_next_region() has finished returning regions and requires the same - * state. - * - * @fdt: Device tree file to reference - * @region: List of regions that will be kept - * @count: Number of regions - * @max_regions: Number of entries that can fit in @region - * @info: Region state as returned from fdt_next_region() - * @return new number of regions in @region (i.e. count + the number added) - * or -FDT_ERR_NOSPACE if there was not enough space. - */ -int fdt_add_alias_regions(const void *fdt, struct fdt_region *region, int count, - int max_regions, struct fdt_region_state *info); - -#endif /* _LIBFDT_H */ +#include <../lib/libfdt/libfdt.h> diff --git a/include/linux/compat.h b/include/linux/compat.h index 03f9bef0da..2336b56cf5 100644 --- a/include/linux/compat.h +++ b/include/linux/compat.h @@ -109,7 +109,7 @@ static inline void kmem_cache_destroy(struct kmem_cache *cachep) #define WARN_ON(condition) ({ \ int __ret_warn_on = !!(condition); \ if (unlikely(__ret_warn_on)) \ - printf("WARNING in %s line %d\n", __FILE__, __LINE__);; \ + printf("WARNING in %s line %d\n", __FILE__, __LINE__); \ unlikely(__ret_warn_on); \ }) diff --git a/include/mpc5xx.h b/include/mpc5xx.h deleted file mode 100644 index 6c170dcb0a..0000000000 --- a/include/mpc5xx.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * (C) Copyright 2003 - * Martin Winistoerfer, martinwinistoerfer@gmx.ch. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * File: mpc5xx.h - * - * Discription: mpc5xx specific definitions - * - */ - -#ifndef __MPC5XX_H__ -#define __MPC5XX_H__ - - -/*----------------------------------------------------------------------- - * Exception offsets (PowerPC standard) - */ -#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ -#define _START_OFFSET EXC_OFF_SYS_RESET - -/*----------------------------------------------------------------------- - * ISB bit in IMMR to set internal memory map - */ - -#define CONFIG_SYS_ISB ((CONFIG_SYS_IMMR / 0x00400000) << 1) - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control Register - */ -#define SYPCR_SWTC 0xffff0000 /* Software Watchdog Timer Count */ -#define SYPCR_BMT 0x0000ff00 /* Bus Monitor Timing */ -#define SYPCR_BME 0x00000080 /* Bus Monitor Enable */ -#define SYPCR_SWF 0x00000008 /* Software Watchdog Freeze */ -#define SYPCR_SWE 0x00000004 /* Software Watchdog Enable */ -#define SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int Select */ -#define SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration Register - */ -#define SIUMCR_EARB 0x80000000 /* External Arbitration */ -#define SIUMCR_EARP0 0x00000000 /* External Arbi. Request priority 0 */ -#define SIUMCR_EARP1 0x10000000 /* External Arbi. Request priority 1 */ -#define SIUMCR_EARP2 0x20000000 /* External Arbi. Request priority 2 */ -#define SIUMCR_EARP3 0x30000000 /* External Arbi. Request priority 3 */ -#define SIUMCR_EARP4 0x40000000 /* External Arbi. Request priority 4 */ -#define SIUMCR_EARP5 0x50000000 /* External Arbi. Request priority 5 */ -#define SIUMCR_EARP6 0x60000000 /* External Arbi. Request priority 6 */ -#define SIUMCR_EARP7 0x70000000 /* External Arbi. Request priority 7 */ -#define SIUMCR_DSHW 0x00800000 /* Data Showcycles */ -#define SIUMCR_DBGC00 0x00000000 /* Debug pins configuration */ -#define SIUMCR_DBGC01 0x00200000 /* - " - */ -#define SIUMCR_DBGC10 0x00400000 /* - " - */ -#define SIUMCR_DBGC11 0x00600000 /* - " - */ -#define SIUMCR_DBPC00 0x00000000 /* Debug Port pins Config. */ -#define SIUMCR_DBPC01 0x00080000 /* - " - */ -#define SIUMCR_DBPC10 0x00100000 /* - " - */ -#define SIUMCR_DBPC11 0x00180000 /* - " - */ -#define SIUMCR_GPC00 0x00000000 /* General Pins Config */ -#define SIUMCR_GPC01 0x00020000 /* General Pins Config */ -#define SIUMCR_GPC10 0x00040000 /* General Pins Config */ -#define SIUMCR_GPC11 0x00060000 /* General Pins Config */ -#define SIUMCR_DLK 0x00010000 /* Debug Register Lock */ -#define SIUMCR_SC00 0x00000000 /* Multi Chip 32 bit */ -#define SIUMCR_SC01 0x00004000 /* Muilt Chip 16 bit */ -#define SIUMCR_SC10 0x00004000 /* Single adress show */ -#define SIUMCR_SC11 0x00006000 /* Single adress */ -#define SIUMCR_RCTX 0x00001000 /* Data Parity pins Config. */ -#define SIUMCR_MLRC00 0x00000000 /* Multi Level Reserva. Ctrl */ -#define SIUMCR_MLRC01 0x00000400 /* - " - */ -#define SIUMCR_MLRC10 0x00000800 /* - " - */ -#define SIUMCR_MLRC11 0x00000c00 /* - " - */ -#define SIUMCR_MTSC 0x00000100 /* Memory transfer */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control Register - */ -#define TBSCR_REFA ((ushort)0x0080) /* Reference Interrupt Status A */ -#define TBSCR_REFB ((ushort)0x0040) /* Reference Interrupt Status B */ -#define TBSCR_TBF ((ushort)0x0002) /* Time Base stops while FREEZE */ - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control Register - */ -#define PISCR_PITF ((ushort)0x0002) /* PIT stops when FREEZE */ -#define PISCR_PS 0x0080 /* Periodic Interrupt Status */ - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register - */ -#define PLPRCR_MF_MSK 0xfff00000 /* MF mask */ -#define PLPRCR_DIVF_MSK 0x0000001f /* DIVF mask */ -#define PLPRCR_CSRC_MSK 0x00000400 /* CSRC mask */ -#define PLPRCR_MF_SHIFT 0x00000014 /* Multiplication factor shift value */ -#define PLPRCR_DIVF_0 0x00000000 /* Division factor 0 */ -#define PLPRCR_MF_9 0x00900000 /* Mulitipliaction factor 9 */ -#define PLPRCR_TEXPS 0x00004000 /* TEXP Status */ -#define PLPRCR_TMIST 0x00001000 /* Timers Interrupt Status */ -#define PLPRCR_CSR 0x00000080 /* CheskStop Reset value */ -#define PLPRCR_SPLSS 0x00008000 /* SPLL Lock Status Sticky bit */ - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register - */ -#define SCCR_DFNL_MSK 0x00000070 /* DFNL mask */ -#define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */ -#define SCCR_DFNL_SHIFT 0x0000004 /* DFNL shift value */ -#define SCCR_RTSEL 0x00100000 /* RTC circuit input source select */ -#define SCCR_EBDF00 0x00000000 /* Division factor 1. CLKOUT is GCLK2 */ -#define SCCR_EBDF11 0x00060000 /* reserved */ -#define SCCR_TBS 0x02000000 /* Time Base Source */ -#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */ -#define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */ -#define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */ -#define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */ -#define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */ - -/*----------------------------------------------------------------------- - * MC - Memory Controller - */ -#define BR_V 0x00000001 /* Bank valid */ -#define BR_BI 0x00000002 /* Burst inhibit */ -#define BR_PS_8 0x00000400 /* 8 bit port size */ -#define BR_PS_16 0x00000800 /* 16 bit port size */ -#define BR_PS_32 0x00000000 /* 32 bit port size */ -#define BR_LBDIR 0x00000008 /* Late burst data in progess */ -#define BR_SETA 0x00000004 /* External Data Acknowledge */ -#define OR_SCY_3 0x00000030 /* 3 clock cycles wait states */ -#define OR_SCY_1 0x00000000 /* 1 clock cycle wait state */ -#define OR_SCY_8 0x00000080 /* 8 clock cycles wait states */ -#define OR_TRLX 0x00000001 /* Timing relaxed */ -#define OR_BSCY 0x00000060 /* Burst beats length in clocks */ -#define OR_ACS_10 0x00000600 /* Adress to chip-select setup */ -#define OR_CSNT 0x00000800 /* Chip-select negotation time */ -#define OR_ETHR 0x00000100 /* Extended hold time on read */ -#define OR_ADDR_MK_FF 0xFF000000 -#define OR_ADDR_MK_FFFF 0xFFFF0000 - -/*----------------------------------------------------------------------- - * UMCR - UIMB Module Configuration Register - */ -#define UMCR_FSPEED 0x00000000 /* Full speed. Opposit of UMCR_HSPEED */ -#define UMCR_HSPEED 0x10000000 /* Half speed */ - -/*----------------------------------------------------------------------- - * ICTRL - I-Bus Support Control Register - */ -#define ICTRL_ISCT_SER_7 0x00000007 /* All indirect change of flow */ - - -#define NR_IRQS 0 /* Place this later in a separate file */ - -/*----------------------------------------------------------------------- - * SCI - Serial communication interface - */ - -#define SCI_TDRE 0x0100 /* Transmit data register empty */ -#define SCI_TE 0x0008 /* Transmitter enabled */ -#define SCI_RE 0x0004 /* Receiver enabled */ -#define SCI_RDRF 0x0040 /* Receive data register full */ -#define SCI_PE 0x0400 /* Parity enable */ -#define SCI_SCXBR_MK 0x1fff /* Baudrate mask */ -#define SCI_SCXDR_MK 0x00ff /* Data register mask */ -#define SCI_M_11 0x0200 /* Frame size is 11 bit */ -#define SCI_M_10 0x0000 /* Frame size is 10 bit */ -#define SCI_PORT_1 ((int)1) /* Place this later somewhere better */ -#define SCI_PORT_2 ((int)2) - -#endif /* __MPC5XX_H__ */ diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h deleted file mode 100644 index 10daf0944b..0000000000 --- a/include/mpc5xxx.h +++ /dev/null @@ -1,893 +0,0 @@ -/* - * include/asm-ppc/mpc5xxx.h - * - * Prototypes, etc. for the Motorola MPC5xxx - * embedded cpu chips - * - * 2003 (c) MontaVista, Software, Inc. - * Author: Dale Farnsworth <dfarnsworth@mvista.com> - * - * 2003 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASMPPC_MPC5XXX_H -#define __ASMPPC_MPC5XXX_H - -#include <asm/types.h> - -/* Processor name */ -#define CPU_ID_STR "MPC5200" - -/* Exception offsets (PowerPC standard) */ -#define EXC_OFF_SYS_RESET 0x0100 -#define _START_OFFSET EXC_OFF_SYS_RESET - -/* useful macros for manipulating CSx_START/STOP */ -#define START_REG(start) ((start) >> 16) -#define STOP_REG(start, size) (((start) + (size) - 1) >> 16) - -/* Internal memory map */ - -#define MPC5XXX_CS0_START (CONFIG_SYS_MBAR + 0x0004) -#define MPC5XXX_CS0_STOP (CONFIG_SYS_MBAR + 0x0008) -#define MPC5XXX_CS1_START (CONFIG_SYS_MBAR + 0x000c) -#define MPC5XXX_CS1_STOP (CONFIG_SYS_MBAR + 0x0010) -#define MPC5XXX_CS2_START (CONFIG_SYS_MBAR + 0x0014) -#define MPC5XXX_CS2_STOP (CONFIG_SYS_MBAR + 0x0018) -#define MPC5XXX_CS3_START (CONFIG_SYS_MBAR + 0x001c) -#define MPC5XXX_CS3_STOP (CONFIG_SYS_MBAR + 0x0020) -#define MPC5XXX_CS4_START (CONFIG_SYS_MBAR + 0x0024) -#define MPC5XXX_CS4_STOP (CONFIG_SYS_MBAR + 0x0028) -#define MPC5XXX_CS5_START (CONFIG_SYS_MBAR + 0x002c) -#define MPC5XXX_CS5_STOP (CONFIG_SYS_MBAR + 0x0030) -#define MPC5XXX_BOOTCS_START (CONFIG_SYS_MBAR + 0x004c) -#define MPC5XXX_BOOTCS_STOP (CONFIG_SYS_MBAR + 0x0050) -#define MPC5XXX_ADDECR (CONFIG_SYS_MBAR + 0x0054) - -#define MPC5XXX_CS6_START (CONFIG_SYS_MBAR + 0x0058) -#define MPC5XXX_CS6_STOP (CONFIG_SYS_MBAR + 0x005c) -#define MPC5XXX_CS7_START (CONFIG_SYS_MBAR + 0x0060) -#define MPC5XXX_CS7_STOP (CONFIG_SYS_MBAR + 0x0064) -#define MPC5XXX_SDRAM_CS0CFG (CONFIG_SYS_MBAR + 0x0034) -#define MPC5XXX_SDRAM_CS1CFG (CONFIG_SYS_MBAR + 0x0038) - -#define MPC5XXX_SDRAM (CONFIG_SYS_MBAR + 0x0100) -#define MPC5XXX_CDM (CONFIG_SYS_MBAR + 0x0200) -#define MPC5XXX_LPB (CONFIG_SYS_MBAR + 0x0300) -#define MPC5XXX_ICTL (CONFIG_SYS_MBAR + 0x0500) -#define MPC5XXX_GPT (CONFIG_SYS_MBAR + 0x0600) -#define MPC5XXX_GPIO (CONFIG_SYS_MBAR + 0x0b00) -#define MPC5XXX_WU_GPIO (CONFIG_SYS_MBAR + 0x0c00) -#define MPC5XXX_PCI (CONFIG_SYS_MBAR + 0x0d00) -#define MPC5XXX_SPI (CONFIG_SYS_MBAR + 0x0f00) -#define MPC5XXX_USB (CONFIG_SYS_MBAR + 0x1000) -#define MPC5XXX_SDMA (CONFIG_SYS_MBAR + 0x1200) -#define MPC5XXX_XLBARB (CONFIG_SYS_MBAR + 0x1f00) - -#define MPC5XXX_PSC1 (CONFIG_SYS_MBAR + 0x2000) -#define MPC5XXX_PSC2 (CONFIG_SYS_MBAR + 0x2200) -#define MPC5XXX_PSC3 (CONFIG_SYS_MBAR + 0x2400) -#define MPC5XXX_PSC4 (CONFIG_SYS_MBAR + 0x2600) -#define MPC5XXX_PSC5 (CONFIG_SYS_MBAR + 0x2800) -#define MPC5XXX_PSC6 (CONFIG_SYS_MBAR + 0x2c00) - -#define MPC5XXX_FEC (CONFIG_SYS_MBAR + 0x3000) -#define MPC5XXX_ATA (CONFIG_SYS_MBAR + 0x3A00) - -#define MPC5XXX_I2C1 (CONFIG_SYS_MBAR + 0x3D00) -#define MPC5XXX_I2C2 (CONFIG_SYS_MBAR + 0x3D40) - -#define MPC5XXX_SRAM (CONFIG_SYS_MBAR + 0x8000) -#define MPC5XXX_SRAM_SIZE (16*1024) - -/* SDRAM Controller */ -#define MPC5XXX_SDRAM_MODE (MPC5XXX_SDRAM + 0x0000) -#define MPC5XXX_SDRAM_CTRL (MPC5XXX_SDRAM + 0x0004) -#define MPC5XXX_SDRAM_CONFIG1 (MPC5XXX_SDRAM + 0x0008) -#define MPC5XXX_SDRAM_CONFIG2 (MPC5XXX_SDRAM + 0x000c) -#define MPC5XXX_SDRAM_SDELAY (MPC5XXX_SDRAM + 0x0090) - -/* Clock Distribution Module */ -#define MPC5XXX_CDM_JTAGID (MPC5XXX_CDM + 0x0000) -#define MPC5XXX_CDM_PORCFG (MPC5XXX_CDM + 0x0004) -#define MPC5XXX_CDM_BRDCRMB (MPC5XXX_CDM + 0x0008) -#define MPC5XXX_CDM_CFG (MPC5XXX_CDM + 0x000c) -#define MPC5XXX_CDM_48_FDC (MPC5XXX_CDM + 0x0010) -#define MPC5XXX_CDM_CLK_ENA (MPC5XXX_CDM + 0x0014) -#define MPC5XXX_CDM_SRESET (MPC5XXX_CDM + 0x0020) - -/* Local Plus Bus interface */ -#define MPC5XXX_CS0_CFG (MPC5XXX_LPB + 0x0000) -#define MPC5XXX_CS1_CFG (MPC5XXX_LPB + 0x0004) -#define MPC5XXX_CS2_CFG (MPC5XXX_LPB + 0x0008) -#define MPC5XXX_CS3_CFG (MPC5XXX_LPB + 0x000c) -#define MPC5XXX_CS4_CFG (MPC5XXX_LPB + 0x0010) -#define MPC5XXX_CS5_CFG (MPC5XXX_LPB + 0x0014) -#define MPC5XXX_BOOTCS_CFG MPC5XXX_CS0_CFG -#define MPC5XXX_CS_CTRL (MPC5XXX_LPB + 0x0018) -#define MPC5XXX_CS_STATUS (MPC5XXX_LPB + 0x001c) -#define MPC5XXX_CS6_CFG (MPC5XXX_LPB + 0x0020) -#define MPC5XXX_CS7_CFG (MPC5XXX_LPB + 0x0024) -#define MPC5XXX_CS_BURST (MPC5XXX_LPB + 0x0028) -#define MPC5XXX_CS_DEADCYCLE (MPC5XXX_LPB + 0x002c) - -/* XLB Arbiter registers */ -#define MPC5XXX_XLBARB_CFG (MPC5XXX_XLBARB + 0x40) -#define MPC5XXX_XLBARB_MPRIEN (MPC5XXX_XLBARB + 0x64) -#define MPC5XXX_XLBARB_MPRIVAL (MPC5XXX_XLBARB + 0x68) - -/* GPIO registers */ -#define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000) - -/* Standard GPIO registers (simple, output only and simple interrupt */ -#define MPC5XXX_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004) -#define MPC5XXX_GPIO_ODE (MPC5XXX_GPIO + 0x0008) -#define MPC5XXX_GPIO_DIR (MPC5XXX_GPIO + 0x000c) -#define MPC5XXX_GPIO_DATA_O (MPC5XXX_GPIO + 0x0010) -#define MPC5XXX_GPIO_DATA_I (MPC5XXX_GPIO + 0x0014) -#define MPC5XXX_GPIO_OO_ENABLE (MPC5XXX_GPIO + 0x0018) -#define MPC5XXX_GPIO_OO_DATA (MPC5XXX_GPIO + 0x001C) -#define MPC5XXX_GPIO_SI_ENABLE (MPC5XXX_GPIO + 0x0020) -#define MPC5XXX_GPIO_SI_ODE (MPC5XXX_GPIO + 0x0024) -#define MPC5XXX_GPIO_SI_DIR (MPC5XXX_GPIO + 0x0028) -#define MPC5XXX_GPIO_SI_DATA (MPC5XXX_GPIO + 0x002C) -#define MPC5XXX_GPIO_SI_IEN (MPC5XXX_GPIO + 0x0030) -#define MPC5XXX_GPIO_SI_ITYPE (MPC5XXX_GPIO + 0x0034) -#define MPC5XXX_GPIO_SI_MEN (MPC5XXX_GPIO + 0x0038) -#define MPC5XXX_GPIO_SI_STATUS (MPC5XXX_GPIO + 0x003C) - -/* WakeUp GPIO registers */ -#define MPC5XXX_WU_GPIO_ENABLE (MPC5XXX_WU_GPIO + 0x0000) -#define MPC5XXX_WU_GPIO_ODE (MPC5XXX_WU_GPIO + 0x0004) -#define MPC5XXX_WU_GPIO_DIR (MPC5XXX_WU_GPIO + 0x0008) -#define MPC5XXX_WU_GPIO_DATA_O (MPC5XXX_WU_GPIO + 0x000c) -#define MPC5XXX_WU_GPIO_DATA_I (MPC5XXX_WU_GPIO + 0x0020) - -/* GPIO pins, for Rev.B chip */ -#define GPIO_WKUP_7 0x80000000UL -#define GPIO_PSC6_0 0x10000000UL -#define GPIO_PSC3_9 0x04000000UL -#define GPIO_PSC1_4 0x01000000UL -#define GPIO_PSC2_4 0x02000000UL - -#define MPC5XXX_GPIO_SIMPLE_PSC6_3 0x20000000UL -#define MPC5XXX_GPIO_SIMPLE_PSC6_2 0x10000000UL -#define MPC5XXX_GPIO_SIMPLE_PSC3_7 0x00002000UL -#define MPC5XXX_GPIO_SIMPLE_PSC3_6 0x00001000UL -#define MPC5XXX_GPIO_SIMPLE_PSC3_3 0x00000800UL -#define MPC5XXX_GPIO_SIMPLE_PSC3_2 0x00000400UL -#define MPC5XXX_GPIO_SIMPLE_PSC3_1 0x00000200UL -#define MPC5XXX_GPIO_SIMPLE_PSC3_0 0x00000100UL -#define MPC5XXX_GPIO_SIMPLE_PSC2_3 0x00000080UL -#define MPC5XXX_GPIO_SIMPLE_PSC2_2 0x00000040UL -#define MPC5XXX_GPIO_SIMPLE_PSC2_1 0x00000020UL -#define MPC5XXX_GPIO_SIMPLE_PSC2_0 0x00000010UL -#define MPC5XXX_GPIO_SIMPLE_PSC1_3 0x00000008UL -#define MPC5XXX_GPIO_SIMPLE_PSC1_2 0x00000004UL -#define MPC5XXX_GPIO_SIMPLE_PSC1_1 0x00000002UL -#define MPC5XXX_GPIO_SIMPLE_PSC1_0 0x00000001UL - -#define MPC5XXX_GPIO_SINT_ETH_16 0x80 -#define MPC5XXX_GPIO_SINT_ETH_15 0x40 -#define MPC5XXX_GPIO_SINT_ETH_14 0x20 -#define MPC5XXX_GPIO_SINT_ETH_13 0x10 -#define MPC5XXX_GPIO_SINT_USB1_9 0x08 -#define MPC5XXX_GPIO_SINT_PSC3_8 0x04 -#define MPC5XXX_GPIO_SINT_PSC3_5 0x02 -#define MPC5XXX_GPIO_SINT_PSC3_4 0x01 - -#define MPC5XXX_GPIO_WKUP_7 0x80 -#define MPC5XXX_GPIO_WKUP_6 0x40 -#define MPC5XXX_GPIO_WKUP_PSC6_1 0x20 -#define MPC5XXX_GPIO_WKUP_PSC6_0 0x10 -#define MPC5XXX_GPIO_WKUP_ETH17 0x08 -#define MPC5XXX_GPIO_WKUP_PSC3_9 0x04 -#define MPC5XXX_GPIO_WKUP_PSC2_4 0x02 -#define MPC5XXX_GPIO_WKUP_PSC1_4 0x01 - -/* PCI registers */ -#define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04) -#define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c) -#define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10) -#define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14) -#define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60) -#define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64) -#define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68) -#define MPC5XXX_PCI_TCR (MPC5XXX_PCI + 0x6c) -#define MPC5XXX_PCI_IW0BTAR (MPC5XXX_PCI + 0x70) -#define MPC5XXX_PCI_IW1BTAR (MPC5XXX_PCI + 0x74) -#define MPC5XXX_PCI_IW2BTAR (MPC5XXX_PCI + 0x78) -#define MPC5XXX_PCI_IWCR (MPC5XXX_PCI + 0x80) -#define MPC5XXX_PCI_ICR (MPC5XXX_PCI + 0x84) -#define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88) -#define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c) -#define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8) - -/* Interrupt Controller registers */ -#define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000) -#define MPC5XXX_ICTL_PER_PRIO1 (MPC5XXX_ICTL + 0x0004) -#define MPC5XXX_ICTL_PER_PRIO2 (MPC5XXX_ICTL + 0x0008) -#define MPC5XXX_ICTL_PER_PRIO3 (MPC5XXX_ICTL + 0x000c) -#define MPC5XXX_ICTL_EXT (MPC5XXX_ICTL + 0x0010) -#define MPC5XXX_ICTL_CRIT (MPC5XXX_ICTL + 0x0014) -#define MPC5XXX_ICTL_MAIN_PRIO1 (MPC5XXX_ICTL + 0x0018) -#define MPC5XXX_ICTL_MAIN_PRIO2 (MPC5XXX_ICTL + 0x001c) -#define MPC5XXX_ICTL_STS (MPC5XXX_ICTL + 0x0024) -#define MPC5XXX_ICTL_CRIT_STS (MPC5XXX_ICTL + 0x0028) -#define MPC5XXX_ICTL_MAIN_STS (MPC5XXX_ICTL + 0x002c) -#define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030) -#define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038) - -#define NR_IRQS 64 - -/* IRQ mapping - these are our logical IRQ numbers */ -#define MPC5XXX_CRIT_IRQ_NUM 4 -#define MPC5XXX_MAIN_IRQ_NUM 17 -#define MPC5XXX_SDMA_IRQ_NUM 17 -#define MPC5XXX_PERP_IRQ_NUM 23 - -#define MPC5XXX_CRIT_IRQ_BASE 1 -#define MPC5XXX_MAIN_IRQ_BASE (MPC5XXX_CRIT_IRQ_BASE + MPC5XXX_CRIT_IRQ_NUM) -#define MPC5XXX_SDMA_IRQ_BASE (MPC5XXX_MAIN_IRQ_BASE + MPC5XXX_MAIN_IRQ_NUM) -#define MPC5XXX_PERP_IRQ_BASE (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM) - -#define MPC5XXX_IRQ0 (MPC5XXX_CRIT_IRQ_BASE + 0) -#define MPC5XXX_SLICE_TIMER_0_IRQ (MPC5XXX_CRIT_IRQ_BASE + 1) -#define MPC5XXX_HI_INT_IRQ (MPC5XXX_CRIT_IRQ_BASE + 2) -#define MPC5XXX_CCS_IRQ (MPC5XXX_CRIT_IRQ_BASE + 3) - -#define MPC5XXX_IRQ1 (MPC5XXX_MAIN_IRQ_BASE + 1) -#define MPC5XXX_IRQ2 (MPC5XXX_MAIN_IRQ_BASE + 2) -#define MPC5XXX_IRQ3 (MPC5XXX_MAIN_IRQ_BASE + 3) -#define MPC5XXX_RTC_PINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 5) -#define MPC5XXX_RTC_SINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 6) -#define MPC5XXX_RTC_GPIO_STD_IRQ (MPC5XXX_MAIN_IRQ_BASE + 7) -#define MPC5XXX_RTC_GPIO_WKUP_IRQ (MPC5XXX_MAIN_IRQ_BASE + 8) -#define MPC5XXX_TMR0_IRQ (MPC5XXX_MAIN_IRQ_BASE + 9) -#define MPC5XXX_TMR1_IRQ (MPC5XXX_MAIN_IRQ_BASE + 10) -#define MPC5XXX_TMR2_IRQ (MPC5XXX_MAIN_IRQ_BASE + 11) -#define MPC5XXX_TMR3_IRQ (MPC5XXX_MAIN_IRQ_BASE + 12) -#define MPC5XXX_TMR4_IRQ (MPC5XXX_MAIN_IRQ_BASE + 13) -#define MPC5XXX_TMR5_IRQ (MPC5XXX_MAIN_IRQ_BASE + 14) -#define MPC5XXX_TMR6_IRQ (MPC5XXX_MAIN_IRQ_BASE + 15) -#define MPC5XXX_TMR7_IRQ (MPC5XXX_MAIN_IRQ_BASE + 16) - -#define MPC5XXX_SDMA_IRQ (MPC5XXX_PERP_IRQ_BASE + 0) -#define MPC5XXX_PSC1_IRQ (MPC5XXX_PERP_IRQ_BASE + 1) -#define MPC5XXX_PSC2_IRQ (MPC5XXX_PERP_IRQ_BASE + 2) -#define MPC5XXX_PSC3_IRQ (MPC5XXX_PERP_IRQ_BASE + 3) -#define MPC5XXX_PSC6_IRQ (MPC5XXX_PERP_IRQ_BASE + 4) -#define MPC5XXX_IRDA_IRQ (MPC5XXX_PERP_IRQ_BASE + 4) -#define MPC5XXX_FEC_IRQ (MPC5XXX_PERP_IRQ_BASE + 5) -#define MPC5XXX_USB_IRQ (MPC5XXX_PERP_IRQ_BASE + 6) -#define MPC5XXX_ATA_IRQ (MPC5XXX_PERP_IRQ_BASE + 7) -#define MPC5XXX_PCI_CNTRL_IRQ (MPC5XXX_PERP_IRQ_BASE + 8) -#define MPC5XXX_PCI_SCIRX_IRQ (MPC5XXX_PERP_IRQ_BASE + 9) -#define MPC5XXX_PCI_SCITX_IRQ (MPC5XXX_PERP_IRQ_BASE + 10) -#define MPC5XXX_PSC4_IRQ (MPC5XXX_PERP_IRQ_BASE + 11) -#define MPC5XXX_PSC5_IRQ (MPC5XXX_PERP_IRQ_BASE + 12) -#define MPC5XXX_SPI_MODF_IRQ (MPC5XXX_PERP_IRQ_BASE + 13) -#define MPC5XXX_SPI_SPIF_IRQ (MPC5XXX_PERP_IRQ_BASE + 14) -#define MPC5XXX_I2C1_IRQ (MPC5XXX_PERP_IRQ_BASE + 15) -#define MPC5XXX_I2C2_IRQ (MPC5XXX_PERP_IRQ_BASE + 16) -#define MPC5XXX_MSCAN1_IRQ (MPC5XXX_PERP_IRQ_BASE + 17) -#define MPC5XXX_MSCAN2_IRQ (MPC5XXX_PERP_IRQ_BASE + 18) -#define MPC5XXX_IR_RX_IRQ (MPC5XXX_PERP_IRQ_BASE + 19) -#define MPC5XXX_IR_TX_IRQ (MPC5XXX_PERP_IRQ_BASE + 20) -#define MPC5XXX_XLB_ARB_IRQ (MPC5XXX_PERP_IRQ_BASE + 21) -#define MPC5XXX_BDLC_IRQ (MPC5XXX_PERP_IRQ_BASE + 22) - -/* General Purpose Timers registers */ -#define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0) -#define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4) -#define MPC5XXX_GPT0_STATUS (MPC5XXX_GPT + 0x0C) -#define MPC5XXX_GPT1_ENABLE (MPC5XXX_GPT + 0x10) -#define MPC5XXX_GPT1_COUNTER (MPC5XXX_GPT + 0x14) -#define MPC5XXX_GPT1_STATUS (MPC5XXX_GPT + 0x1C) -#define MPC5XXX_GPT2_ENABLE (MPC5XXX_GPT + 0x20) -#define MPC5XXX_GPT2_COUNTER (MPC5XXX_GPT + 0x24) -#define MPC5XXX_GPT2_STATUS (MPC5XXX_GPT + 0x2C) -#define MPC5XXX_GPT3_ENABLE (MPC5XXX_GPT + 0x30) -#define MPC5XXX_GPT3_COUNTER (MPC5XXX_GPT + 0x34) -#define MPC5XXX_GPT3_STATUS (MPC5XXX_GPT + 0x3C) -#define MPC5XXX_GPT4_ENABLE (MPC5XXX_GPT + 0x40) -#define MPC5XXX_GPT4_COUNTER (MPC5XXX_GPT + 0x44) -#define MPC5XXX_GPT4_STATUS (MPC5XXX_GPT + 0x4C) -#define MPC5XXX_GPT5_ENABLE (MPC5XXX_GPT + 0x50) -#define MPC5XXX_GPT5_STATUS (MPC5XXX_GPT + 0x5C) -#define MPC5XXX_GPT5_COUNTER (MPC5XXX_GPT + 0x54) -#define MPC5XXX_GPT6_ENABLE (MPC5XXX_GPT + 0x60) -#define MPC5XXX_GPT6_COUNTER (MPC5XXX_GPT + 0x64) -#define MPC5XXX_GPT6_STATUS (MPC5XXX_GPT + 0x6C) -#define MPC5XXX_GPT7_ENABLE (MPC5XXX_GPT + 0x70) -#define MPC5XXX_GPT7_COUNTER (MPC5XXX_GPT + 0x74) -#define MPC5XXX_GPT7_STATUS (MPC5XXX_GPT + 0x7C) - -#define MPC5XXX_GPT_GPIO_PIN(status) ((0x00000100 & (status)) >> 8) - -#define MPC5XXX_GPT7_PWMCFG (MPC5XXX_GPT + 0x78) - -/* ATA registers */ -#define MPC5XXX_ATA_HOST_CONFIG (MPC5XXX_ATA + 0x0000) -#define MPC5XXX_ATA_PIO1 (MPC5XXX_ATA + 0x0008) -#define MPC5XXX_ATA_PIO2 (MPC5XXX_ATA + 0x000C) -#define MPC5XXX_ATA_SHARE_COUNT (MPC5XXX_ATA + 0x002C) - -/* I2Cn control register bits */ -#define I2C_EN 0x80 -#define I2C_IEN 0x40 -#define I2C_STA 0x20 -#define I2C_TX 0x10 -#define I2C_TXAK 0x08 -#define I2C_RSTA 0x04 -#define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA) - -/* I2Cn status register bits */ -#define I2C_CF 0x80 -#define I2C_AAS 0x40 -#define I2C_BB 0x20 -#define I2C_AL 0x10 -#define I2C_SRW 0x04 -#define I2C_IF 0x02 -#define I2C_RXAK 0x01 - -/* SPI control register 1 bits */ -#define SPI_CR_LSBFE 0x01 -#define SPI_CR_SSOE 0x02 -#define SPI_CR_CPHA 0x04 -#define SPI_CR_CPOL 0x08 -#define SPI_CR_MSTR 0x10 -#define SPI_CR_SWOM 0x20 -#define SPI_CR_SPE 0x40 -#define SPI_CR_SPIE 0x80 - -/* SPI status register bits */ -#define SPI_SR_MODF 0x10 -#define SPI_SR_WCOL 0x40 -#define SPI_SR_SPIF 0x80 - -/* SPI port data register bits */ -#define SPI_PDR_SS 0x08 - -/* Programmable Serial Controller (PSC) status register bits */ -#define PSC_SR_CDE 0x0080 -#define PSC_SR_RXRDY 0x0100 -#define PSC_SR_RXFULL 0x0200 -#define PSC_SR_TXRDY 0x0400 -#define PSC_SR_TXEMP 0x0800 -#define PSC_SR_OE 0x1000 -#define PSC_SR_PE 0x2000 -#define PSC_SR_FE 0x4000 -#define PSC_SR_RB 0x8000 - -/* PSC Command values */ -#define PSC_RX_ENABLE 0x0001 -#define PSC_RX_DISABLE 0x0002 -#define PSC_TX_ENABLE 0x0004 -#define PSC_TX_DISABLE 0x0008 -#define PSC_SEL_MODE_REG_1 0x0010 -#define PSC_RST_RX 0x0020 -#define PSC_RST_TX 0x0030 -#define PSC_RST_ERR_STAT 0x0040 -#define PSC_RST_BRK_CHG_INT 0x0050 -#define PSC_START_BRK 0x0060 -#define PSC_STOP_BRK 0x0070 - -/* PSC Rx FIFO status bits */ -#define PSC_RX_FIFO_ERR 0x0040 -#define PSC_RX_FIFO_UF 0x0020 -#define PSC_RX_FIFO_OF 0x0010 -#define PSC_RX_FIFO_FR 0x0008 -#define PSC_RX_FIFO_FULL 0x0004 -#define PSC_RX_FIFO_ALARM 0x0002 -#define PSC_RX_FIFO_EMPTY 0x0001 - -/* PSC interrupt mask bits */ -#define PSC_IMR_TXRDY 0x0100 -#define PSC_IMR_RXRDY 0x0200 -#define PSC_IMR_DB 0x0400 -#define PSC_IMR_IPC 0x8000 - -/* PSC input port change bits */ -#define PSC_IPCR_CTS 0x01 -#define PSC_IPCR_DCD 0x02 - -/* PSC mode fields */ -#define PSC_MODE_5_BITS 0x00 -#define PSC_MODE_6_BITS 0x01 -#define PSC_MODE_7_BITS 0x02 -#define PSC_MODE_8_BITS 0x03 -#define PSC_MODE_PAREVEN 0x00 -#define PSC_MODE_PARODD 0x04 -#define PSC_MODE_PARFORCE 0x08 -#define PSC_MODE_PARNONE 0x10 -#define PSC_MODE_ERR 0x20 -#define PSC_MODE_FFULL 0x40 -#define PSC_MODE_RXRTS 0x80 - -#define PSC_MODE_ONE_STOP_5_BITS 0x00 -#define PSC_MODE_ONE_STOP 0x07 -#define PSC_MODE_TWO_STOP 0x0f - -/* ATA config fields */ -#define MPC5xxx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine - reset */ -#define MPC5xxx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */ -#define MPC5xxx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt - in PIO */ -#define MPC5xxx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports - IORDY protocol */ - -#ifndef __ASSEMBLY__ -/* Memory map registers */ -struct mpc5xxx_mmap_ctl { - volatile u32 mbar; - volatile u32 cs0_start; /* 0x0004 */ - volatile u32 cs0_stop; - volatile u32 cs1_start; /* 0x000c */ - volatile u32 cs1_stop; - volatile u32 cs2_start; /* 0x0014 */ - volatile u32 cs2_stop; - volatile u32 cs3_start; /* 0x001c */ - volatile u32 cs3_stop; - volatile u32 cs4_start; /* 0x0024 */ - volatile u32 cs4_stop; - volatile u32 cs5_start; /* 0x002c */ - volatile u32 cs5_stop; - volatile u32 sdram0; /* 0x0034 */ - volatile u32 sdram1; /* 0x0038 */ - volatile u32 dummy1[4]; /* 0x003c */ - volatile u32 boot_start; /* 0x004c */ - volatile u32 boot_stop; - volatile u32 ipbi_ws_ctrl; /* 0x0054 */ - volatile u32 cs6_start; /* 0x0058 */ - volatile u32 cs6_stop; - volatile u32 cs7_start; /* 0x0060 */ - volatile u32 cs7_stop; -}; - -/* Clock distribution module */ -struct mpc5xxx_cdm { - volatile u32 jtagid; /* 0x0000 */ - volatile u32 porcfg; - volatile u32 brdcrmb; /* 0x0008 */ - volatile u32 cfg; - volatile u32 fourtyeight_fdc;/* 0x0010 */ - volatile u32 clock_enable; - volatile u32 system_osc; /* 0x0018 */ - volatile u32 ccscr; - volatile u32 sreset; /* 0x0020 */ - volatile u32 pll_status; - volatile u32 psc1_mccr; /* 0x0028 */ - volatile u32 psc2_mccr; - volatile u32 psc3_mccr; /* 0x0030 */ - volatile u32 psc6_mccr; -}; - -/* SDRAM controller */ -struct mpc5xxx_sdram { - volatile u32 mode; - volatile u32 ctrl; - volatile u32 config1; - volatile u32 config2; - volatile u32 dummy[32]; - volatile u32 sdelay; -}; - -struct mpc5xxx_lpb { - volatile u32 cs0_cfg; - volatile u32 cs1_cfg; - volatile u32 cs2_cfg; - volatile u32 cs3_cfg; - volatile u32 cs4_cfg; - volatile u32 cs5_cfg; - volatile u32 cs_ctrl; - volatile u32 cs_status; - volatile u32 cs6_cfg; - volatile u32 cs7_cfg; - volatile u32 cs_burst; - volatile u32 cs_deadcycle; -}; - - -struct mpc5xxx_psc { - volatile u8 mode; /* PSC + 0x00 */ - volatile u8 reserved0[3]; - union { /* PSC + 0x04 */ - volatile u16 status; - volatile u16 clock_select; - } sr_csr; -#define psc_status sr_csr.status -#define psc_clock_select sr_csr.clock_select - volatile u16 reserved1; - volatile u8 command; /* PSC + 0x08 */ - volatile u8 reserved2[3]; - union { /* PSC + 0x0c */ - volatile u8 buffer_8; - volatile u16 buffer_16; - volatile u32 buffer_32; - } buffer; -#define psc_buffer_8 buffer.buffer_8 -#define psc_buffer_16 buffer.buffer_16 -#define psc_buffer_32 buffer.buffer_32 - union { /* PSC + 0x10 */ - volatile u8 ipcr; - volatile u8 acr; - } ipcr_acr; -#define psc_ipcr ipcr_acr.ipcr -#define psc_acr ipcr_acr.acr - volatile u8 reserved3[3]; - union { /* PSC + 0x14 */ - volatile u16 isr; - volatile u16 imr; - } isr_imr; -#define psc_isr isr_imr.isr -#define psc_imr isr_imr.imr - volatile u16 reserved4; - volatile u8 ctur; /* PSC + 0x18 */ - volatile u8 reserved5[3]; - volatile u8 ctlr; /* PSC + 0x1c */ - volatile u8 reserved6[3]; - volatile u16 ccr; /* PSC + 0x20 */ - volatile u8 reserved7[14]; - volatile u8 ivr; /* PSC + 0x30 */ - volatile u8 reserved8[3]; - volatile u8 ip; /* PSC + 0x34 */ - volatile u8 reserved9[3]; - volatile u8 op1; /* PSC + 0x38 */ - volatile u8 reserved10[3]; - volatile u8 op0; /* PSC + 0x3c */ - volatile u8 reserved11[3]; - volatile u32 sicr; /* PSC + 0x40 */ - volatile u8 ircr1; /* PSC + 0x44 */ - volatile u8 reserved12[3]; - volatile u8 ircr2; /* PSC + 0x44 */ - volatile u8 reserved13[3]; - volatile u8 irsdr; /* PSC + 0x4c */ - volatile u8 reserved14[3]; - volatile u8 irmdr; /* PSC + 0x50 */ - volatile u8 reserved15[3]; - volatile u8 irfdr; /* PSC + 0x54 */ - volatile u8 reserved16[3]; - volatile u16 rfnum; /* PSC + 0x58 */ - volatile u16 reserved17; - volatile u16 tfnum; /* PSC + 0x5c */ - volatile u16 reserved18; - volatile u32 rfdata; /* PSC + 0x60 */ - volatile u16 rfstat; /* PSC + 0x64 */ - volatile u16 reserved20; - volatile u8 rfcntl; /* PSC + 0x68 */ - volatile u8 reserved21[5]; - volatile u16 rfalarm; /* PSC + 0x6e */ - volatile u16 reserved22; - volatile u16 rfrptr; /* PSC + 0x72 */ - volatile u16 reserved23; - volatile u16 rfwptr; /* PSC + 0x76 */ - volatile u16 reserved24; - volatile u16 rflrfptr; /* PSC + 0x7a */ - volatile u16 reserved25; - volatile u16 rflwfptr; /* PSC + 0x7e */ - volatile u32 tfdata; /* PSC + 0x80 */ - volatile u16 tfstat; /* PSC + 0x84 */ - volatile u16 reserved26; - volatile u8 tfcntl; /* PSC + 0x88 */ - volatile u8 reserved27[5]; - volatile u16 tfalarm; /* PSC + 0x8e */ - volatile u16 reserved28; - volatile u16 tfrptr; /* PSC + 0x92 */ - volatile u16 reserved29; - volatile u16 tfwptr; /* PSC + 0x96 */ - volatile u16 reserved30; - volatile u16 tflrfptr; /* PSC + 0x9a */ - volatile u16 reserved31; - volatile u16 tflwfptr; /* PSC + 0x9e */ -}; - -struct mpc5xxx_intr { - volatile u32 per_mask; /* INTR + 0x00 */ - volatile u32 per_pri1; /* INTR + 0x04 */ - volatile u32 per_pri2; /* INTR + 0x08 */ - volatile u32 per_pri3; /* INTR + 0x0c */ - volatile u32 ctrl; /* INTR + 0x10 */ - volatile u32 main_mask; /* INTR + 0x14 */ - volatile u32 main_pri1; /* INTR + 0x18 */ - volatile u32 main_pri2; /* INTR + 0x1c */ - volatile u32 reserved1; /* INTR + 0x20 */ - volatile u32 enc_status; /* INTR + 0x24 */ - volatile u32 crit_status; /* INTR + 0x28 */ - volatile u32 main_status; /* INTR + 0x2c */ - volatile u32 per_status; /* INTR + 0x30 */ - volatile u32 reserved2; /* INTR + 0x34 */ - volatile u32 per_error; /* INTR + 0x38 */ -}; - -struct mpc5xxx_gpio { - volatile u32 port_config; /* GPIO + 0x00 */ - volatile u32 simple_gpioe; /* GPIO + 0x04 */ - volatile u32 simple_ode; /* GPIO + 0x08 */ - volatile u32 simple_ddr; /* GPIO + 0x0c */ - volatile u32 simple_dvo; /* GPIO + 0x10 */ - volatile u32 simple_ival; /* GPIO + 0x14 */ - volatile u8 outo_gpioe; /* GPIO + 0x18 */ - volatile u8 reserved1[3]; /* GPIO + 0x19 */ - volatile u8 outo_dvo; /* GPIO + 0x1c */ - volatile u8 reserved2[3]; /* GPIO + 0x1d */ - volatile u8 sint_gpioe; /* GPIO + 0x20 */ - volatile u8 reserved3[3]; /* GPIO + 0x21 */ - volatile u8 sint_ode; /* GPIO + 0x24 */ - volatile u8 reserved4[3]; /* GPIO + 0x25 */ - volatile u8 sint_ddr; /* GPIO + 0x28 */ - volatile u8 reserved5[3]; /* GPIO + 0x29 */ - volatile u8 sint_dvo; /* GPIO + 0x2c */ - volatile u8 reserved6[3]; /* GPIO + 0x2d */ - volatile u8 sint_inten; /* GPIO + 0x30 */ - volatile u8 reserved7[3]; /* GPIO + 0x31 */ - volatile u16 sint_itype; /* GPIO + 0x34 */ - volatile u16 reserved8; /* GPIO + 0x36 */ - volatile u8 gpio_control; /* GPIO + 0x38 */ - volatile u8 reserved9[3]; /* GPIO + 0x39 */ - volatile u8 sint_istat; /* GPIO + 0x3c */ - volatile u8 sint_ival; /* GPIO + 0x3d */ - volatile u8 bus_errs; /* GPIO + 0x3e */ - volatile u8 reserved10; /* GPIO + 0x3f */ -}; - -struct mpc5xxx_wu_gpio { - volatile u8 enable; /* WU_GPIO + 0x00 */ - volatile u8 reserved1[3]; /* WU_GPIO + 0x01 */ - volatile u8 ode; /* WU_GPIO + 0x04 */ - volatile u8 reserved2[3]; /* WU_GPIO + 0x05 */ - volatile u8 ddr; /* WU_GPIO + 0x08 */ - volatile u8 reserved3[3]; /* WU_GPIO + 0x09 */ - volatile u8 dvo; /* WU_GPIO + 0x0c */ - volatile u8 reserved4[3]; /* WU_GPIO + 0x0d */ - volatile u8 inten; /* WU_GPIO + 0x10 */ - volatile u8 reserved5[3]; /* WU_GPIO + 0x11 */ - volatile u8 iinten; /* WU_GPIO + 0x14 */ - volatile u8 reserved6[3]; /* WU_GPIO + 0x15 */ - volatile u16 itype; /* WU_GPIO + 0x18 */ - volatile u8 reserved7[2]; /* WU_GPIO + 0x1a */ - volatile u8 master_enable; /* WU_GPIO + 0x1c */ - volatile u8 reserved8[3]; /* WU_GPIO + 0x1d */ - volatile u8 ival; /* WU_GPIO + 0x20 */ - volatile u8 reserved9[3]; /* WU_GPIO + 0x21 */ - volatile u8 status; /* WU_GPIO + 0x24 */ - volatile u8 reserved10[3]; /* WU_GPIO + 0x25 */ -}; - -struct mpc5xxx_sdma { - volatile u32 taskBar; /* SDMA + 0x00 */ - volatile u32 currentPointer; /* SDMA + 0x04 */ - volatile u32 endPointer; /* SDMA + 0x08 */ - volatile u32 variablePointer; /* SDMA + 0x0c */ - - volatile u8 IntVect1; /* SDMA + 0x10 */ - volatile u8 IntVect2; /* SDMA + 0x11 */ - volatile u16 PtdCntrl; /* SDMA + 0x12 */ - - volatile u32 IntPend; /* SDMA + 0x14 */ - volatile u32 IntMask; /* SDMA + 0x18 */ - - volatile u16 tcr_0; /* SDMA + 0x1c */ - volatile u16 tcr_1; /* SDMA + 0x1e */ - volatile u16 tcr_2; /* SDMA + 0x20 */ - volatile u16 tcr_3; /* SDMA + 0x22 */ - volatile u16 tcr_4; /* SDMA + 0x24 */ - volatile u16 tcr_5; /* SDMA + 0x26 */ - volatile u16 tcr_6; /* SDMA + 0x28 */ - volatile u16 tcr_7; /* SDMA + 0x2a */ - volatile u16 tcr_8; /* SDMA + 0x2c */ - volatile u16 tcr_9; /* SDMA + 0x2e */ - volatile u16 tcr_a; /* SDMA + 0x30 */ - volatile u16 tcr_b; /* SDMA + 0x32 */ - volatile u16 tcr_c; /* SDMA + 0x34 */ - volatile u16 tcr_d; /* SDMA + 0x36 */ - volatile u16 tcr_e; /* SDMA + 0x38 */ - volatile u16 tcr_f; /* SDMA + 0x3a */ - - volatile u8 IPR0; /* SDMA + 0x3c */ - volatile u8 IPR1; /* SDMA + 0x3d */ - volatile u8 IPR2; /* SDMA + 0x3e */ - volatile u8 IPR3; /* SDMA + 0x3f */ - volatile u8 IPR4; /* SDMA + 0x40 */ - volatile u8 IPR5; /* SDMA + 0x41 */ - volatile u8 IPR6; /* SDMA + 0x42 */ - volatile u8 IPR7; /* SDMA + 0x43 */ - volatile u8 IPR8; /* SDMA + 0x44 */ - volatile u8 IPR9; /* SDMA + 0x45 */ - volatile u8 IPR10; /* SDMA + 0x46 */ - volatile u8 IPR11; /* SDMA + 0x47 */ - volatile u8 IPR12; /* SDMA + 0x48 */ - volatile u8 IPR13; /* SDMA + 0x49 */ - volatile u8 IPR14; /* SDMA + 0x4a */ - volatile u8 IPR15; /* SDMA + 0x4b */ - volatile u8 IPR16; /* SDMA + 0x4c */ - volatile u8 IPR17; /* SDMA + 0x4d */ - volatile u8 IPR18; /* SDMA + 0x4e */ - volatile u8 IPR19; /* SDMA + 0x4f */ - volatile u8 IPR20; /* SDMA + 0x50 */ - volatile u8 IPR21; /* SDMA + 0x51 */ - volatile u8 IPR22; /* SDMA + 0x52 */ - volatile u8 IPR23; /* SDMA + 0x53 */ - volatile u8 IPR24; /* SDMA + 0x54 */ - volatile u8 IPR25; /* SDMA + 0x55 */ - volatile u8 IPR26; /* SDMA + 0x56 */ - volatile u8 IPR27; /* SDMA + 0x57 */ - volatile u8 IPR28; /* SDMA + 0x58 */ - volatile u8 IPR29; /* SDMA + 0x59 */ - volatile u8 IPR30; /* SDMA + 0x5a */ - volatile u8 IPR31; /* SDMA + 0x5b */ - - volatile u32 res1; /* SDMA + 0x5c */ - volatile u32 res2; /* SDMA + 0x60 */ - volatile u32 res3; /* SDMA + 0x64 */ - volatile u32 MDEDebug; /* SDMA + 0x68 */ - volatile u32 ADSDebug; /* SDMA + 0x6c */ - volatile u32 Value1; /* SDMA + 0x70 */ - volatile u32 Value2; /* SDMA + 0x74 */ - volatile u32 Control; /* SDMA + 0x78 */ - volatile u32 Status; /* SDMA + 0x7c */ - volatile u32 EU00; /* SDMA + 0x80 */ - volatile u32 EU01; /* SDMA + 0x84 */ - volatile u32 EU02; /* SDMA + 0x88 */ - volatile u32 EU03; /* SDMA + 0x8c */ - volatile u32 EU04; /* SDMA + 0x90 */ - volatile u32 EU05; /* SDMA + 0x94 */ - volatile u32 EU06; /* SDMA + 0x98 */ - volatile u32 EU07; /* SDMA + 0x9c */ - volatile u32 EU10; /* SDMA + 0xa0 */ - volatile u32 EU11; /* SDMA + 0xa4 */ - volatile u32 EU12; /* SDMA + 0xa8 */ - volatile u32 EU13; /* SDMA + 0xac */ - volatile u32 EU14; /* SDMA + 0xb0 */ - volatile u32 EU15; /* SDMA + 0xb4 */ - volatile u32 EU16; /* SDMA + 0xb8 */ - volatile u32 EU17; /* SDMA + 0xbc */ - volatile u32 EU20; /* SDMA + 0xc0 */ - volatile u32 EU21; /* SDMA + 0xc4 */ - volatile u32 EU22; /* SDMA + 0xc8 */ - volatile u32 EU23; /* SDMA + 0xcc */ - volatile u32 EU24; /* SDMA + 0xd0 */ - volatile u32 EU25; /* SDMA + 0xd4 */ - volatile u32 EU26; /* SDMA + 0xd8 */ - volatile u32 EU27; /* SDMA + 0xdc */ - volatile u32 EU30; /* SDMA + 0xe0 */ - volatile u32 EU31; /* SDMA + 0xe4 */ - volatile u32 EU32; /* SDMA + 0xe8 */ - volatile u32 EU33; /* SDMA + 0xec */ - volatile u32 EU34; /* SDMA + 0xf0 */ - volatile u32 EU35; /* SDMA + 0xf4 */ - volatile u32 EU36; /* SDMA + 0xf8 */ - volatile u32 EU37; /* SDMA + 0xfc */ -}; - -struct mpc5xxx_i2c { - volatile u32 madr; /* I2Cn + 0x00 */ - volatile u32 mfdr; /* I2Cn + 0x04 */ - volatile u32 mcr; /* I2Cn + 0x08 */ - volatile u32 msr; /* I2Cn + 0x0C */ - volatile u32 mdr; /* I2Cn + 0x10 */ -}; - -struct mpc5xxx_spi { - volatile u8 cr1; /* SPI + 0x0F00 */ - volatile u8 cr2; /* SPI + 0x0F01 */ - volatile u8 reserved1[2]; - volatile u8 brr; /* SPI + 0x0F04 */ - volatile u8 sr; /* SPI + 0x0F05 */ - volatile u8 reserved2[3]; - volatile u8 dr; /* SPI + 0x0F09 */ - volatile u8 reserved3[3]; - volatile u8 pdr; /* SPI + 0x0F0D */ - volatile u8 reserved4[2]; - volatile u8 ddr; /* SPI + 0x0F10 */ -}; - - -struct mpc5xxx_gpt { - volatile u32 emsr; /* GPT + Timer# * 0x10 + 0x00 */ - volatile u32 cir; /* GPT + Timer# * 0x10 + 0x04 */ - volatile u32 pwmcr; /* GPT + Timer# * 0x10 + 0x08 */ - volatile u32 sr; /* GPT + Timer# * 0x10 + 0x0c */ -}; - -struct mpc5xxx_gpt_0_7 { - struct mpc5xxx_gpt gpt0; - struct mpc5xxx_gpt gpt1; - struct mpc5xxx_gpt gpt2; - struct mpc5xxx_gpt gpt3; - struct mpc5xxx_gpt gpt4; - struct mpc5xxx_gpt gpt5; - struct mpc5xxx_gpt gpt6; - struct mpc5xxx_gpt gpt7; -}; - -struct mscan_buffer { - volatile u8 idr[0x8]; /* 0x00 */ - volatile u8 dsr[0x10]; /* 0x08 */ - volatile u8 dlr; /* 0x18 */ - volatile u8 tbpr; /* 0x19 */ /* This register is not applicable for receive buffers */ - volatile u16 rsrv1; /* 0x1A */ - volatile u8 tsrh; /* 0x1C */ - volatile u8 tsrl; /* 0x1D */ - volatile u16 rsrv2; /* 0x1E */ -}; - -struct mpc5xxx_mscan { - volatile u8 canctl0; /* MSCAN + 0x00 */ - volatile u8 canctl1; /* MSCAN + 0x01 */ - volatile u16 rsrv1; /* MSCAN + 0x02 */ - volatile u8 canbtr0; /* MSCAN + 0x04 */ - volatile u8 canbtr1; /* MSCAN + 0x05 */ - volatile u16 rsrv2; /* MSCAN + 0x06 */ - volatile u8 canrflg; /* MSCAN + 0x08 */ - volatile u8 canrier; /* MSCAN + 0x09 */ - volatile u16 rsrv3; /* MSCAN + 0x0A */ - volatile u8 cantflg; /* MSCAN + 0x0C */ - volatile u8 cantier; /* MSCAN + 0x0D */ - volatile u16 rsrv4; /* MSCAN + 0x0E */ - volatile u8 cantarq; /* MSCAN + 0x10 */ - volatile u8 cantaak; /* MSCAN + 0x11 */ - volatile u16 rsrv5; /* MSCAN + 0x12 */ - volatile u8 cantbsel; /* MSCAN + 0x14 */ - volatile u8 canidac; /* MSCAN + 0x15 */ - volatile u16 rsrv6[3]; /* MSCAN + 0x16 */ - volatile u8 canrxerr; /* MSCAN + 0x1C */ - volatile u8 cantxerr; /* MSCAN + 0x1D */ - volatile u16 rsrv7; /* MSCAN + 0x1E */ - volatile u8 canidar0; /* MSCAN + 0x20 */ - volatile u8 canidar1; /* MSCAN + 0x21 */ - volatile u16 rsrv8; /* MSCAN + 0x22 */ - volatile u8 canidar2; /* MSCAN + 0x24 */ - volatile u8 canidar3; /* MSCAN + 0x25 */ - volatile u16 rsrv9; /* MSCAN + 0x26 */ - volatile u8 canidmr0; /* MSCAN + 0x28 */ - volatile u8 canidmr1; /* MSCAN + 0x29 */ - volatile u16 rsrv10; /* MSCAN + 0x2A */ - volatile u8 canidmr2; /* MSCAN + 0x2C */ - volatile u8 canidmr3; /* MSCAN + 0x2D */ - volatile u16 rsrv11; /* MSCAN + 0x2E */ - volatile u8 canidar4; /* MSCAN + 0x30 */ - volatile u8 canidar5; /* MSCAN + 0x31 */ - volatile u16 rsrv12; /* MSCAN + 0x32 */ - volatile u8 canidar6; /* MSCAN + 0x34 */ - volatile u8 canidar7; /* MSCAN + 0x35 */ - volatile u16 rsrv13; /* MSCAN + 0x36 */ - volatile u8 canidmr4; /* MSCAN + 0x38 */ - volatile u8 canidmr5; /* MSCAN + 0x39 */ - volatile u16 rsrv14; /* MSCAN + 0x3A */ - volatile u8 canidmr6; /* MSCAN + 0x3C */ - volatile u8 canidmr7; /* MSCAN + 0x3D */ - volatile u16 rsrv15; /* MSCAN + 0x3E */ - - struct mscan_buffer canrxfg; /* MSCAN + 0x40 */ /* Foreground receive buffer */ - struct mscan_buffer cantxfg; /* MSCAN + 0x60 */ /* Foreground transmit buffer */ - }; - -struct mpc5xxx_xlb { - volatile u8 reserved[0x40]; /* XLB + 0x00 */ - volatile u32 config; /* XLB + 0x40 */ - volatile u32 version; /* XLB + 0x44 */ - volatile u32 status; /* XLB + 0x48 */ - volatile u32 int_enable; /* XLB + 0x4c */ - volatile u32 addr_capture; /* XLB + 0x50 */ - volatile u32 bus_sig_capture; /* XLB + 0x54 */ - volatile u32 addr_timeout; /* XLB + 0x58 */ - volatile u32 data_timeout; /* XLB + 0x5c */ - volatile u32 bus_act_timeout; /* XLB + 0x60 */ - volatile u32 master_pri_enable; /* XLB + 0x64 */ - volatile u32 master_priority; /* XLB + 0x68 */ - volatile u32 base_address; /* XLB + 0x6c */ - volatile u32 snoop_window; /* XLB + 0x70 */ -}; - -struct pci_controller; - -/* function prototypes */ -void loadtask(int basetask, int tasks); -void pci_mpc5xxx_init(struct pci_controller *); - -#endif /* __ASSEMBLY__ */ - -#endif /* __ASMPPC_MPC5XXX_H */ diff --git a/include/mpc5xxx_sdma.h b/include/mpc5xxx_sdma.h deleted file mode 100644 index 821ac0ac62..0000000000 --- a/include/mpc5xxx_sdma.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This file is based on code - * (C) Copyright Motorola, Inc., 2000 - * - * odin smartdma header file - */ - -#ifndef __MPC5XXX_SDMA_H -#define __MPC5XXX_SDMA_H - -#include <common.h> -#include <mpc5xxx.h> - -/* Task number assignment */ -#define FEC_RECV_TASK_NO 0 -#define FEC_XMIT_TASK_NO 1 - -/*---------------------------------------------------------------------*/ - -/* Stuff for Ethernet Tx/Rx tasks */ - -/*---------------------------------------------------------------------*/ - -/* Layout of Ethernet controller Parameter SRAM area: ----------------------------------------------------------------- -0x00: TBD_BASE, base address of TX BD ring -0x04: TBD_NEXT, address of next TX BD to be processed -0x08: RBD_BASE, base address of RX BD ring -0x0C: RBD_NEXT, address of next RX BD to be processed ---------------------------------------------------------------- -ALL PARAMETERS ARE ALL LONGWORDS (FOUR BYTES EACH). -*/ - -/* base address of SRAM area to store parameters used by Ethernet tasks */ -#define FEC_PARAM_BASE (MPC5XXX_SRAM + 0x0800) - -/* base address of SRAM area for buffer descriptors */ -#define FEC_BD_BASE (MPC5XXX_SRAM + 0x0820) - -/*---------------------------------------------------------------------*/ - -/* common shortcuts used by driver C code */ - -/*---------------------------------------------------------------------*/ - -/* Disable SmartDMA task */ -#define SDMA_TASK_DISABLE(tasknum) \ -{ \ - volatile ushort *tcr = (ushort *)(MPC5XXX_SDMA + 0x0000001c + 2 * tasknum); \ - *tcr = (*tcr) & (~0x8000); \ -} - -/* Enable SmartDMA task */ -#define SDMA_TASK_ENABLE(tasknum) \ -{ \ - volatile ushort *tcr = (ushort *) (MPC5XXX_SDMA + 0x0000001c + 2 * tasknum); \ - *tcr = (*tcr) | 0x8000; \ -} - -/* Enable interrupt */ -#define SDMA_INT_ENABLE(tasknum) \ -{ \ - struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \ - sdma->IntMask &= ~(1 << tasknum); \ -} - -/* Disable interrupt */ -#define SDMA_INT_DISABLE(tasknum) \ -{ \ - struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \ - sdma->IntMask |= (1 << tasknum); \ -} - - -/* Clear interrupt pending bits */ -#define SDMA_CLEAR_IEVENT(tasknum) \ -{ \ - struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \ - sdma->IntPend = (1 << tasknum); \ -} - -/* get interrupt pending bit of a task */ -#define SDMA_GET_PENDINGBIT(tasknum) \ - ((*(vu_long *)(MPC5XXX_SDMA + 0x14)) & (1<<(tasknum))) - -/* get interrupt mask bit of a task */ -#define SDMA_GET_MASKBIT(tasknum) \ - ((*(vu_long *)(MPC5XXX_SDMA + 0x18)) & (1<<(tasknum))) - -#endif /* __MPC5XXX_SDMA_H */ diff --git a/include/mpc823_lcd.h b/include/mpc823_lcd.h deleted file mode 100644 index cc72cde13f..0000000000 --- a/include/mpc823_lcd.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * mpc823_lcd.h - MPC823 LCD Controller structures - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _MPC823_LCD_H_ -#define _MPC823_LCD_H_ - -/* - * LCD controller stucture for MPC823 CPU - */ -typedef struct vidinfo { - ushort vl_col; /* Number of columns (i.e. 640) */ - ushort vl_row; /* Number of rows (i.e. 480) */ - ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */ - ushort vl_width; /* Width of display area in millimeters */ - ushort vl_height; /* Height of display area in millimeters */ - - /* LCD configuration register */ - u_char vl_clkp; /* Clock polarity */ - u_char vl_oep; /* Output Enable polarity */ - u_char vl_hsp; /* Horizontal Sync polarity */ - u_char vl_vsp; /* Vertical Sync polarity */ - u_char vl_dp; /* Data polarity */ - u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */ - u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ - u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */ - u_char vl_clor; /* Color, 0 = mono, 1 = color */ - u_char vl_tft; /* 0 = passive, 1 = TFT */ - - /* Horizontal control register. Timing from data sheet */ - ushort vl_wbl; /* Wait between lines */ - - /* Vertical control register */ - u_char vl_vpw; /* Vertical sync pulse width */ - u_char vl_lcdac; /* LCD AC timing */ - u_char vl_wbf; /* Wait between frames */ -} vidinfo_t; - -#endif diff --git a/include/mpc8260.h b/include/mpc8260.h deleted file mode 100644 index 75f1b0c9df..0000000000 --- a/include/mpc8260.h +++ /dev/null @@ -1,903 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mpc8260.h - * - * MPC8255 / MPC8260 specific definitions - */ - -#ifndef __MPC8260_H__ -#define __MPC8260_H__ - -#ifdef CONFIG_MPC8255 -#define CPU_ID_STR "MPC8255" -#endif -#ifndef CPU_ID_STR -#if defined(CONFIG_MPC8272_FAMILY) -#ifdef CONFIG_MPC8247 -#define CPU_ID_STR "MPC8247" -#else -#define CPU_ID_STR "MPC8272" -#endif -#else -#define CPU_ID_STR "MPC8260" -#endif -#endif /* !CPU_ID_STR */ - -/*----------------------------------------------------------------------- - * Exception offsets (PowerPC standard) - */ -#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ -#define _START_OFFSET EXC_OFF_SYS_RESET - -/*----------------------------------------------------------------------- - * BCR - Bus Configuration Register 4-25 - */ -#define BCR_EBM 0x80000000 /* External Bus Mode */ -#define BCR_APD_MSK 0x70000000 /* Address Phase Delay Mask */ -#define BCR_L2C 0x08000000 /* Secondary Cache Controller */ -#define BCR_L2D_MSK 0x07000000 /* L2 Cache Hit Delay Mask */ -#define BCR_PLDP 0x00800000 /* Pipeline Maximum Depth */ -#define BCR_EAV 0x00400000 /* Enable Address Visibility */ -#define BCR_ETM 0x00080000 /* Compatibility Mode Enable */ -#define BCR_LETM 0x00040000 /* LocalBus Compatibility Mode Enable*/ -#define BCR_EPAR 0x00020000 /* Even Parity */ -#define BCR_LEPAR 0x00010000 /* Local Bus Even Parity */ -#define BCR_NPQM0 0x00008000 /* Non PowerQUICC-II Master 0 */ -#define BCR_NPQM1 0x00004000 /* Non PowerQUICC-II Master 1 */ -#define BCR_NPQM2 0x00002000 /* Non PowerQUICC-II Master 2 */ -#define BCR_EXDD 0x00000400 /* External Master Delay Disable*/ -#define BCR_ISPS 0x00000010 /* Internal Space Port Size */ - - -/*----------------------------------------------------------------------- - * PPC_ACR - 60x Bus Arbiter Configuration Register 4-28 - */ -#define PPC_ACR_DBGD 0x20 /* Data Bus Grant Delay */ -#define PPC_ACR_EARB 0x10 /* External Arbitration */ -#define PPC_ACR_PRKM_MSK 0x0f /* Parking Master */ - -#define PPC_ACR_PRKM_CPMH 0x00 /* CPM high request level */ -#define PPC_ACR_PRKM_CPMM 0x01 /* CPM middle request level */ -#define PPC_ACR_PRKM_CPML 0x02 /* CPM low request level */ -#define PPC_ACR_PRKM_CORE 0x06 /* Internal Core */ -#define PPC_ACR_PRKM_EXT1 0x07 /* External Master 1 */ -#define PPC_ACR_PRKM_EXT2 0x08 /* External Master 2 */ -#define PPC_ACR_PRKM_EXT3 0x09 /* External Master 3 */ - -/*----------------------------------------------------------------------- - * PPC_ALRH/PPC_ALRL - 60x Bus Arbitration-Level Registers 4-28 - */ -#define PPC_ALRH_PF0_MSK 0xf0000000 /* Priority Field 0 Mask */ -#define PPC_ALRH_PF1_MSK 0x0f000000 /* Priority Field 1 Mask */ -#define PPC_ALRH_PF2_MSK 0x00f00000 /* Priority Field 2 Mask */ -#define PPC_ALRH_PF3_MSK 0x000f0000 /* Priority Field 3 Mask */ -#define PPC_ALRH_PF4_MSK 0x0000f000 /* Priority Field 4 Mask */ -#define PPC_ALRH_PF5_MSK 0x00000f00 /* Priority Field 5 Mask */ -#define PPC_ALRH_PF6_MSK 0x000000f0 /* Priority Field 6 Mask */ -#define PPC_ALRH_PF7_MSK 0x0000000f /* Priority Field 7 Mask */ -#define PPC_ALRL_PF8_MSK 0xf0000000 /* Priority Field 8 Mask */ -#define PPC_ALRL_PF9_MSK 0x0f000000 /* Priority Field 9 Mask */ -#define PPC_ALRL_PF10_MSK 0x00f00000 /* Priority Field 10 Mask */ -#define PPC_ALRL_PF11_MSK 0x000f0000 /* Priority Field 11 Mask */ -#define PPC_ALRL_PF12_MSK 0x0000f000 /* Priority Field 12 Mask */ -#define PPC_ALRL_PF13_MSK 0x00000f00 /* Priority Field 13 Mask */ -#define PPC_ALRL_PF14_MSK 0x000000f0 /* Priority Field 14 Mask */ -#define PPC_ALRL_PF15_MSK 0x0000000f /* Priority Field 15 Mask */ - -/*----------------------------------------------------------------------- - * LCL_ACR - Local Bus Arbiter Configuration Register 4-29 - */ -#define LCL_ACR_DBGD 0x20 /* Data Bus Grant Delay */ -#define LCL_ACR_PRKM_MSK 0x0f /* Parking Master */ - -#define LCL_ACR_PRKM_CPMH 0x00 /* CPM high request level */ -#define LCL_ACR_PRKM_CPMM 0x01 /* CPM middle request level */ -#define LCL_ACR_PRKM_CPML 0x02 /* CPM low request level */ -#define LCL_ACR_PRKM_HOST 0x03 /* Host Bridge */ - -/*----------------------------------------------------------------------- - * LCL_ALRH/LCL_ALRL - Local Bus Arbitration Level Registers 4-30 - */ -#define LCL_ALRH_PF0_MSK 0xf0000000 /* Priority Field 0 Mask */ -#define LCL_ALRH_PF1_MSK 0x0f000000 /* Priority Field 1 Mask */ -#define LCL_ALRH_PF2_MSK 0x00f00000 /* Priority Field 2 Mask */ -#define LCL_ALRH_PF3_MSK 0x000f0000 /* Priority Field 3 Mask */ -#define LCL_ALRH_PF4_MSK 0x0000f000 /* Priority Field 4 Mask */ -#define LCL_ALRH_PF5_MSK 0x00000f00 /* Priority Field 5 Mask */ -#define LCL_ALRH_PF6_MSK 0x000000f0 /* Priority Field 6 Mask */ -#define LCL_ALRH_PF7_MSK 0x0000000f /* Priority Field 7 Mask */ -#define LCL_ALRL_PF8_MSK 0xf0000000 /* Priority Field 8 Mask */ -#define LCL_ALRL_PF9_MSK 0x0f000000 /* Priority Field 9 Mask */ -#define LCL_ALRL_PF10_MSK 0x00f00000 /* Priority Field 10 Mask */ -#define LCL_ALRL_PF11_MSK 0x000f0000 /* Priority Field 11 Mask */ -#define LCL_ALRL_PF12_MSK 0x0000f000 /* Priority Field 12 Mask */ -#define LCL_ALRL_PF13_MSK 0x00000f00 /* Priority Field 13 Mask */ -#define LCL_ALRL_PF14_MSK 0x000000f0 /* Priority Field 14 Mask */ -#define LCL_ALRL_PF15_MSK 0x0000000f /* Priority Field 15 Mask */ - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration Register 4-31 - */ -#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */ -#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */ -#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */ -#define SIUMCR_CDIS 0x10000000 /* Core Disable */ -#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/ -#define SIUMCR_DPPC01 0x04000000 /* - " - */ -#define SIUMCR_DPPC10 0x08000000 /* - " - */ -#define SIUMCR_DPPC11 0x0c000000 /* - " - */ -#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */ -#define SIUMCR_L2CPC01 0x01000000 /* - " - */ -#define SIUMCR_L2CPC10 0x02000000 /* - " - */ -#define SIUMCR_L2CPC11 0x03000000 /* - " - */ -#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */ -#define SIUMCR_LBPC01 0x00400000 /* - " - */ -#define SIUMCR_LBPC10 0x00800000 /* - " - */ -#define SIUMCR_LBPC11 0x00c00000 /* - " - */ -#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/ -#define SIUMCR_APPC01 0x00100000 /* - " - */ -#define SIUMCR_APPC10 0x00200000 /* - " - */ -#define SIUMCR_APPC11 0x00300000 /* - " - */ -#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */ -#define SIUMCR_CS10PC01 0x00040000 /* - " - */ -#define SIUMCR_CS10PC10 0x00080000 /* - " - */ -#define SIUMCR_CS10PC11 0x000c0000 /* - " - */ -#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */ -#define SIUMCR_BCTLC01 0x00010000 /* - " - */ -#define SIUMCR_BCTLC10 0x00020000 /* - " - */ -#define SIUMCR_BCTLC11 0x00030000 /* - " - */ -#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */ -#define SIUMCR_MMR01 0x00004000 /* - " - */ -#define SIUMCR_MMR10 0x00008000 /* - " - */ -#define SIUMCR_MMR11 0x0000c000 /* - " - */ -#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/ -#define SIUMCR_ABE 0x00000400 /* Address output buffer impedance*/ - -/*----------------------------------------------------------------------- - * IMMR - Internal Memory Map Register 4-34 - */ -#define IMMR_ISB_MSK 0xfffe0000 /* Internal Space base */ -#define IMMR_PARTNUM_MSK 0x0000ff00 /* Part number */ -#define IMMR_MASKNUM_MSK 0x000000ff /* Mask number */ - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control Register 4-35 - */ -#define SYPCR_SWTC 0xffff0000 /* Software Watchdog Timer Count*/ -#define SYPCR_BMT 0x0000ff00 /* Bus Monitor Timing */ -#define SYPCR_PBME 0x00000080 /* 60x Bus Monitor Enable */ -#define SYPCR_LBME 0x00000040 /* Local Bus Monitor Enable */ -#define SYPCR_SWE 0x00000004 /* Software Watchdog Enable */ -#define SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int Select*/ -#define SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */ - -/*----------------------------------------------------------------------- - * TMCNTSC - Time Counter Status and Control Register 4-40 - */ -#define TMCNTSC_SEC 0x0080 /* Once Per Second Interrupt */ -#define TMCNTSC_ALR 0x0040 /* Alarm Interrupt */ -#define TMCNTSC_SIE 0x0008 /* Second Interrupt Enable */ -#define TMCNTSC_ALE 0x0004 /* Alarm Interrupt Enable */ -#define TMCNTSC_TCF 0x0002 /* Time Counter Frequency */ -#define TMCNTSC_TCE 0x0001 /* Time Counter Enable */ - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control Register 4-42 - */ -#if 0 /* already defined in asm/immap_8260.h */ -#define PISCR_PS 0x0080 /* Periodic Interrupt Status */ -#define PISCR_PIE 0x0004 /* Periodic Interrupt Enable */ -#define PISCR_PTF 0x0002 /* Periodic Timer Frequency */ -#define PISCR_PTE 0x0001 /* Periodic Timer Enable */ -#endif - -/*----------------------------------------------------------------------- - * RSR - Reset Status Register 5-4 - */ -#define RSR_JTRS 0x00000020 /* JTAG Reset Status */ -#define RSR_CSRS 0x00000010 /* Check Stop Reset Status */ -#define RSR_SWRS 0x00000008 /* Software Watchdog Reset Status*/ -#define RSR_BMRS 0x00000004 /* Bus Monitor Reset Status */ -#define RSR_ESRS 0x00000002 /* External Soft Reset Status */ -#define RSR_EHRS 0x00000001 /* External Hard Reset Status */ - -#define RSR_ALLBITS (RSR_JTRS|RSR_CSRS|RSR_SWRS|RSR_BMRS|RSR_ESRS|RSR_EHRS) - -/*----------------------------------------------------------------------- - * RMR - Reset Mode Register 5-5 - */ -#define RMR_CSRE 0x00000001 /* Checkstop Reset Enable */ - -/*----------------------------------------------------------------------- - * Hard Reset Configuration Word 5-8 - */ -#define HRCW_EARB 0x80000000 /* External Arbitration */ -#define HRCW_EXMC 0x40000000 /* External Memory Controller */ -#define HRCW_CDIS 0x20000000 /* Core Disable */ -#define HRCW_EBM 0x10000000 /* External Bus Mode */ -#define HRCW_BPS00 0x00000000 /* Boot Port Size */ -#define HRCW_BPS01 0x04000000 /* - " - */ -#define HRCW_BPS10 0x08000000 /* - " - */ -#define HRCW_BPS11 0x0c000000 /* - " - */ -#define HRCW_CIP 0x02000000 /* Core Initial Prefix */ -#define HRCW_ISPS 0x01000000 /* Internal Space Port Size */ -#define HRCW_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */ -#define HRCW_L2CPC01 0x00400000 /* - " - */ -#define HRCW_L2CPC10 0x00800000 /* - " - */ -#define HRCW_L2CPC11 0x00c00000 /* - " - */ -#define HRCW_DPPC00 0x00000000 /* Data Parity Pin Configuration*/ -#define HRCW_DPPC01 0x00100000 /* - " - */ -#define HRCW_DPPC10 0x00200000 /* - " - */ -#define HRCW_DPPC11 0x00300000 /* - " - */ -#define HRCW_reserved1 0x00080000 /* reserved */ -#define HRCW_ISB000 0x00000000 /* Initial Internal Space Base */ -#define HRCW_ISB001 0x00010000 /* - " - */ -#define HRCW_ISB010 0x00020000 /* - " - */ -#define HRCW_ISB011 0x00030000 /* - " - */ -#define HRCW_ISB100 0x00040000 /* - " - */ -#define HRCW_ISB101 0x00050000 /* - " - */ -#define HRCW_ISB110 0x00060000 /* - " - */ -#define HRCW_ISB111 0x00070000 /* - " - */ -#define HRCW_BMS 0x00008000 /* Boot Memory Space */ -#define HRCW_BBD 0x00004000 /* Bus Busy Disable */ -#define HRCW_MMR00 0x00000000 /* Mask Masters Requests */ -#define HRCW_MMR01 0x00001000 /* - " - */ -#define HRCW_MMR10 0x00002000 /* - " - */ -#define HRCW_MMR11 0x00003000 /* - " - */ -#define HRCW_LBPC00 0x00000000 /* Local Bus Pin Configuration */ -#define HRCW_LBPC01 0x00000400 /* - " - */ -#define HRCW_LBPC10 0x00000800 /* - " - */ -#define HRCW_LBPC11 0x00000c00 /* - " - */ -#define HRCW_APPC00 0x00000000 /* Address Parity Pin Configuration*/ -#define HRCW_APPC01 0x00000100 /* - " - */ -#define HRCW_APPC10 0x00000200 /* - " - */ -#define HRCW_APPC11 0x00000300 /* - " - */ -#define HRCW_CS10PC00 0x00000000 /* CS10 Pin Configuration */ -#define HRCW_CS10PC01 0x00000040 /* - " - */ -#define HRCW_CS10PC10 0x00000080 /* - " - */ -#define HRCW_CS10PC11 0x000000c0 /* - " - */ -#define HRCW_MODCK_H0000 0x00000000 /* High-order bits of MODCK Bus */ -#define HRCW_MODCK_H0001 0x00000001 /* - " - */ -#define HRCW_MODCK_H0010 0x00000002 /* - " - */ -#define HRCW_MODCK_H0011 0x00000003 /* - " - */ -#define HRCW_MODCK_H0100 0x00000004 /* - " - */ -#define HRCW_MODCK_H0101 0x00000005 /* - " - */ -#define HRCW_MODCK_H0110 0x00000006 /* - " - */ -#define HRCW_MODCK_H0111 0x00000007 /* - " - */ -#define HRCW_MODCK_H1000 0x00000008 /* - " - */ -#define HRCW_MODCK_H1001 0x00000009 /* - " - */ -#define HRCW_MODCK_H1010 0x0000000a /* - " - */ -#define HRCW_MODCK_H1011 0x0000000b /* - " - */ -#define HRCW_MODCK_H1100 0x0000000c /* - " - */ -#define HRCW_MODCK_H1101 0x0000000d /* - " - */ -#define HRCW_MODCK_H1110 0x0000000e /* - " - */ -#define HRCW_MODCK_H1111 0x0000000f /* - " - */ - -/*----------------------------------------------------------------------- - * SCCR - System Clock Control Register 9-8 - */ -#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */ -#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */ -#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */ -#define SCCR_PCIDF_SHIFT 3 -#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */ -#define SCCR_DFBRG_MSK 0x00000003 /* Division factor of BRGCLK Mask */ -#define SCCR_DFBRG_SHIFT 0 - -#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */ -#define SCCR_DFBRG01 0x00000001 /* BRGCLK division by 16 (normal op.)*/ -#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ -#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 128 */ - -/*----------------------------------------------------------------------- - * SCMR - System Clock Mode Register 9-9 - */ -#define SCMR_CORECNF_MSK 0x1f000000 /* Core Configuration Mask */ -#define SCMR_CORECNF_SHIFT 24 -#define SCMR_BUSDF_MSK 0x00f00000 /* 60x Bus Division Factor Mask */ -#define SCMR_BUSDF_SHIFT 20 -#define SCMR_CPMDF_MSK 0x000f0000 /* CPM Division Factor Mask */ -#define SCMR_CPMDF_SHIFT 16 -#define SCMR_PLLDF 0x00001000 /* PLL Pre-divider Value */ -#define SCMR_PLLMF_MSK 0x00000fff /* PLL Multiplication Factor Mask*/ -#define SCMR_PLLMF_MSKH7 0x0000000f /* for HiP7 processors */ -#define SCMR_PLLMF_SHIFT 0 - - -/*----------------------------------------------------------------------- - * MxMR - Machine A/B/C Mode Registers 10-13 - */ -#define MxMR_BSEL 0x80000000 /* Bus Select */ -#define MxMR_RFEN 0x40000000 /* Refresh Enable */ -#define MxMR_OP_MSK 0x30000000 /* Command Opcode Mask */ -#define MxMR_AMx_MSK 0x07000000 /* Addess Multiplex Size Mask */ -#define MxMR_DSx_MSK 0x00c00000 /* Disable Timer Period Mask */ -#define MxMR_G0CLx_MSK 0x00380000 /* General Line 0 Control Mask */ -#define MxMR_GPL_x4DIS 0x00040000 /* GPL_A4 Ouput Line Disable */ -#define MxMR_RLFx_MSK 0x0003c000 /* Read Loop Field Mask */ -#define MxMR_WLFx_MSK 0x00003c00 /* Write Loop Field Mask */ -#define MxMR_TLFx_MSK 0x000003c0 /* Refresh Loop Field Mask */ -#define MxMR_MAD_MSK 0x0000003f /* Machine Address Mask */ - -#define MxMR_OP_NORM 0x00000000 /* Normal Operation */ -#define MxMR_OP_WARR 0x10000000 /* Write to Array */ -#define MxMR_OP_RARR 0x20000000 /* Read from Array */ -#define MxMR_OP_RUNP 0x30000000 /* Run Pattern */ - -#define MxMR_AMx_TYPE_0 0x00000000 /* Addess Multiplexing Type 0 */ -#define MxMR_AMx_TYPE_1 0x01000000 /* Addess Multiplexing Type 1 */ -#define MxMR_AMx_TYPE_2 0x02000000 /* Addess Multiplexing Type 2 */ -#define MxMR_AMx_TYPE_3 0x03000000 /* Addess Multiplexing Type 3 */ -#define MxMR_AMx_TYPE_4 0x04000000 /* Addess Multiplexing Type 4 */ -#define MxMR_AMx_TYPE_5 0x05000000 /* Addess Multiplexing Type 5 */ - -#define MxMR_DSx_1_CYCL 0x00000000 /* 1 cycle Disable Period */ -#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */ -#define MxMR_DSx_3_CYCL 0x00800000 /* 3 cycle Disable Period */ -#define MxMR_DSx_4_CYCL 0x00c00000 /* 4 cycle Disable Period */ - -#define MxMR_G0CLx_A12 0x00000000 /* General Line 0 : A12 */ -#define MxMR_G0CLx_A11 0x00080000 /* General Line 0 : A11 */ -#define MxMR_G0CLx_A10 0x00100000 /* General Line 0 : A10 */ -#define MxMR_G0CLx_A9 0x00180000 /* General Line 0 : A9 */ -#define MxMR_G0CLx_A8 0x00200000 /* General Line 0 : A8 */ -#define MxMR_G0CLx_A7 0x00280000 /* General Line 0 : A7 */ -#define MxMR_G0CLx_A6 0x00300000 /* General Line 0 : A6 */ -#define MxMR_G0CLx_A5 0x00380000 /* General Line 0 : A5 */ - -#define MxMR_RLFx_1X 0x00004000 /* Read Loop is executed 1 time */ -#define MxMR_RLFx_2X 0x00008000 /* Read Loop is executed 2 times*/ -#define MxMR_RLFx_3X 0x0000c000 /* Read Loop is executed 3 times*/ -#define MxMR_RLFx_4X 0x00010000 /* Read Loop is executed 4 times*/ -#define MxMR_RLFx_5X 0x00014000 /* Read Loop is executed 5 times*/ -#define MxMR_RLFx_6X 0x00018000 /* Read Loop is executed 6 times*/ -#define MxMR_RLFx_7X 0x0001c000 /* Read Loop is executed 7 times*/ -#define MxMR_RLFx_8X 0x00020000 /* Read Loop is executed 8 times*/ -#define MxMR_RLFx_9X 0x00024000 /* Read Loop is executed 9 times*/ -#define MxMR_RLFx_10X 0x00028000 /* Read Loop is executed 10 times*/ -#define MxMR_RLFx_11X 0x0002c000 /* Read Loop is executed 11 times*/ -#define MxMR_RLFx_12X 0x00030000 /* Read Loop is executed 12 times*/ -#define MxMR_RLFx_13X 0x00034000 /* Read Loop is executed 13 times*/ -#define MxMR_RLFx_14X 0x00038000 /* Read Loop is executed 14 times*/ -#define MxMR_RLFx_15X 0x0003c000 /* Read Loop is executed 15 times*/ -#define MxMR_RLFx_16X 0x00000000 /* Read Loop is executed 16 times*/ - -#define MxMR_WLFx_1X 0x00000400 /* Write Loop is executed 1 time*/ -#define MxMR_WLFx_2X 0x00000800 /* Write Loop is executed 2 times*/ -#define MxMR_WLFx_3X 0x00000c00 /* Write Loop is executed 3 times*/ -#define MxMR_WLFx_4X 0x00001000 /* Write Loop is executed 4 times*/ -#define MxMR_WLFx_5X 0x00001400 /* Write Loop is executed 5 times*/ -#define MxMR_WLFx_6X 0x00001800 /* Write Loop is executed 6 times*/ -#define MxMR_WLFx_7X 0x00001c00 /* Write Loop is executed 7 times*/ -#define MxMR_WLFx_8X 0x00002000 /* Write Loop is executed 8 times*/ -#define MxMR_WLFx_9X 0x00002400 /* Write Loop is executed 9 times*/ -#define MxMR_WLFx_10X 0x00002800 /* Write Loop is executed 10 times*/ -#define MxMR_WLFx_11X 0x00002c00 /* Write Loop is executed 11 times*/ -#define MxMR_WLFx_12X 0x00003000 /* Write Loop is executed 12 times*/ -#define MxMR_WLFx_13X 0x00003400 /* Write Loop is executed 13 times*/ -#define MxMR_WLFx_14X 0x00003800 /* Write Loop is executed 14 times*/ -#define MxMR_WLFx_15X 0x00003c00 /* Write Loop is executed 15 times*/ -#define MxMR_WLFx_16X 0x00000000 /* Write Loop is executed 16 times*/ - -#define MxMR_TLFx_1X 0x00000040 /* Timer Loop is executed 1 time*/ -#define MxMR_TLFx_2X 0x00000080 /* Timer Loop is executed 2 times*/ -#define MxMR_TLFx_3X 0x000000c0 /* Timer Loop is executed 3 times*/ -#define MxMR_TLFx_4X 0x00000100 /* Timer Loop is executed 4 times*/ -#define MxMR_TLFx_5X 0x00000140 /* Timer Loop is executed 5 times*/ -#define MxMR_TLFx_6X 0x00000180 /* Timer Loop is executed 6 times*/ -#define MxMR_TLFx_7X 0x000001c0 /* Timer Loop is executed 7 times*/ -#define MxMR_TLFx_8X 0x00000200 /* Timer Loop is executed 8 times*/ -#define MxMR_TLFx_9X 0x00000240 /* Timer Loop is executed 9 times*/ -#define MxMR_TLFx_10X 0x00000280 /* Timer Loop is executed 10 times*/ -#define MxMR_TLFx_11X 0x000002c0 /* Timer Loop is executed 11 times*/ -#define MxMR_TLFx_12X 0x00000300 /* Timer Loop is executed 12 times*/ -#define MxMR_TLFx_13X 0x00000340 /* Timer Loop is executed 13 times*/ -#define MxMR_TLFx_14X 0x00000380 /* Timer Loop is executed 14 times*/ -#define MxMR_TLFx_15X 0x000003c0 /* Timer Loop is executed 15 times*/ -#define MxMR_TLFx_16X 0x00000000 /* Timer Loop is executed 16 times*/ - - -/*----------------------------------------------------------------------- - * BRx - Memory Controller: Base Register 10-14 - */ -#define BRx_BA_MSK 0xffff8000 /* Base Address Mask */ -#define BRx_PS_MSK 0x00001800 /* Port Size Mask */ -#define BRx_DECC_MSK 0x00000600 /* Data Error Correct+Check Mask*/ -#define BRx_WP 0x00000100 /* Write Protect */ -#define BRx_MS_MSK 0x000000e0 /* Machine Select Mask */ -#define BRx_EMEMC 0x00000010 /* External MEMC Enable */ -#define BRx_ATOM_MSK 0x0000000c /* Atomic Operation Mask */ -#define BRx_DR 0x00000002 /* Data Pipelining */ -#define BRx_V 0x00000001 /* Bank Valid */ - -#define BRx_PS_64 0x00000000 /* 64 bit port size (60x bus only)*/ -#define BRx_PS_8 0x00000800 /* 8 bit port size */ -#define BRx_PS_16 0x00001000 /* 16 bit port size */ -#define BRx_PS_32 0x00001800 /* 32 bit port size */ - -#define BRx_DECC_NONE 0x00000000 /* Data Errors Checking Disabled*/ -#define BRx_DECC_NORMAL 0x00000200 /* Normal Parity Checking */ -#define BRx_DECC_RMWPC 0x00000400 /* Read-Modify-Write Parity Checking*/ -#define BRx_DECC_ECC 0x00000600 /* ECC Correction and Checking */ - -#define BRx_MS_GPCM_P 0x00000000 /* G.P.C.M. 60x Bus Machine Select*/ -#define BRx_MS_GPCM_L 0x00000020 /* G.P.C.M. Local Bus Machine Select*/ -#define BRx_MS_SDRAM_P 0x00000040 /* SDRAM 60x Bus Machine Select */ -#define BRx_MS_SDRAM_L 0x00000060 /* SDRAM Local Bus Machine Select*/ -#define BRx_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */ -#define BRx_MS_UPMB 0x000000a0 /* U.P.M.B Machine Select */ -#define BRx_MS_UPMC 0x000000c0 /* U.P.M.C Machine Select */ - -#define BRx_ATOM_RAWA 0x00000004 /* Read-After-Write-Atomic */ -#define BRx_ATOM_WARA 0x00000008 /* Write-After-Read-Atomic */ - -/*----------------------------------------------------------------------- - * ORx - Memory Controller: Option Register - SDRAM Mode 10-16 - */ -#define ORxS_SDAM_MSK 0xfff00000 /* SDRAM Address Mask Mask */ -#define ORxS_LSDAM_MSK 0x000f8000 /* Lower SDRAM Address Mask Mask*/ -#define ORxS_BPD_MSK 0x00006000 /* Banks Per Device Mask */ -#define ORxS_ROWST_MSK 0x00001e00 /* Row Start Address Bit Mask */ -#define ORxS_NUMR_MSK 0x000001c0 /* Number of Row Addr Lines Mask*/ -#define ORxS_PMSEL 0x00000020 /* Page Mode Select */ -#define ORxS_IBID 0x00000010 /* Internal Bank Interleaving Disable*/ - -#define ORxS_BPD_2 0x00000000 /* 2 Banks Per Device */ -#define ORxS_BPD_4 0x00002000 /* 4 Banks Per Device */ -#define ORxS_BPD_8 0x00004000 /* 8 Banks Per Device */ - -/* ROWST values for xSDMR[PBI] = 0 */ -#define ORxS_ROWST_PBI0_A7 0x00000400 /* Row Start Address Bit is A7 */ -#define ORxS_ROWST_PBI0_A8 0x00000800 /* Row Start Address Bit is A8 */ -#define ORxS_ROWST_PBI0_A9 0x00000c00 /* Row Start Address Bit is A9 */ -#define ORxS_ROWST_PBI0_A10 0x00001000 /* Row Start Address Bit is A10 */ -#define ORxS_ROWST_PBI0_A11 0x00001400 /* Row Start Address Bit is A11 */ -#define ORxS_ROWST_PBI0_A12 0x00001800 /* Row Start Address Bit is A12 */ -#define ORxS_ROWST_PBI0_A13 0x00001c00 /* Row Start Address Bit is A13 */ - -/* ROWST values for xSDMR[PBI] = 1 */ -#define ORxS_ROWST_PBI1_A0 0x00000000 /* Row Start Address Bit is A0 */ -#define ORxS_ROWST_PBI1_A1 0x00000200 /* Row Start Address Bit is A1 */ -#define ORxS_ROWST_PBI1_A2 0x00000400 /* Row Start Address Bit is A2 */ -#define ORxS_ROWST_PBI1_A3 0x00000600 /* Row Start Address Bit is A3 */ -#define ORxS_ROWST_PBI1_A4 0x00000800 /* Row Start Address Bit is A4 */ -#define ORxS_ROWST_PBI1_A5 0x00000a00 /* Row Start Address Bit is A5 */ -#define ORxS_ROWST_PBI1_A6 0x00000c00 /* Row Start Address Bit is A6 */ -#define ORxS_ROWST_PBI1_A7 0x00000e00 /* Row Start Address Bit is A7 */ -#define ORxS_ROWST_PBI1_A8 0x00001000 /* Row Start Address Bit is A8 */ -#define ORxS_ROWST_PBI1_A9 0x00001200 /* Row Start Address Bit is A9 */ -#define ORxS_ROWST_PBI1_A10 0x00001400 /* Row Start Address Bit is A10 */ -#define ORxS_ROWST_PBI1_A11 0x00001600 /* Row Start Address Bit is A11 */ -#define ORxS_ROWST_PBI1_A12 0x00001800 /* Row Start Address Bit is A12 */ - -#define ORxS_NUMR_9 0x00000000 /* 9 Row Address Lines */ -#define ORxS_NUMR_10 0x00000040 /* 10 Row Address Lines */ -#define ORxS_NUMR_11 0x00000080 /* 11 Row Address Lines */ -#define ORxS_NUMR_12 0x000000c0 /* 12 Row Address Lines */ -#define ORxS_NUMR_13 0x00000100 /* 13 Row Address Lines */ -#define ORxS_NUMR_14 0x00000140 /* 14 Row Address Lines */ -#define ORxS_NUMR_15 0x00000180 /* 15 Row Address Lines */ -#define ORxS_NUMR_16 0x000001c0 /* 16 Row Address Lines */ - -/* helper to determine the AM for a given size (SDRAM mode) */ -#define ORxS_SIZE_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */ - -/*----------------------------------------------------------------------- - * ORx - Memory Controller: Option Register - GPCM Mode 10-18 - */ -#define ORxG_AM_MSK 0xffff8000 /* Address Mask Mask */ -#define ORxG_BCTLD 0x00001000 /* Data Buffer Control Disable */ -#define ORxG_CSNT 0x00000800 /* Chip Select Negation Time */ -#define ORxG_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask*/ -#define ORxG_SCY_MSK 0x000000f0 /* Cycle Lenght in Clocks */ -#define ORxG_SETA 0x00000008 /* External Access Termination */ -#define ORxG_TRLX 0x00000004 /* Timing Relaxed */ -#define ORxG_EHTR 0x00000002 /* Extended Hold Time on Read */ - -#define ORxG_ACS_DIV1 0x00000000 /* CS is output at the same time*/ -#define ORxG_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later*/ -#define ORxG_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later*/ - -#define ORxG_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */ -#define ORxG_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */ -#define ORxG_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */ -#define ORxG_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */ -#define ORxG_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */ -#define ORxG_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */ -#define ORxG_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */ -#define ORxG_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */ -#define ORxG_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */ -#define ORxG_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */ -#define ORxG_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */ -#define ORxG_SCY_11_CLK 0x000000b0 /* 11 clock cycles wait states */ -#define ORxG_SCY_12_CLK 0x000000c0 /* 12 clock cycles wait states */ -#define ORxG_SCY_13_CLK 0x000000d0 /* 13 clock cycles wait states */ -#define ORxG_SCY_14_CLK 0x000000e0 /* 14 clock cycles wait states */ -#define ORxG_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */ - -/*----------------------------------------------------------------------- - * ORx - Memory Controller: Option Register - UPM Mode 10-20 - */ -#define ORxU_AM_MSK 0xffff8000 /* Address Mask Mask */ -#define ORxU_BCTLD 0x00001000 /* Data Buffer Control Disable */ -#define ORxU_BI 0x00000100 /* Burst Inhibit */ -#define ORxU_EHTR_MSK 0x00000006 /* Extended Hold Time on Read Mask*/ - -#define ORxU_EHTR_NORM 0x00000000 /* Normal Timing */ -#define ORxU_EHTR_1IDLE 0x00000002 /* One Idle Clock Cycle Inserted*/ -#define ORxU_EHTR_4IDLE 0x00000004 /* Four Idle Clock Cycles Inserted*/ -#define ORxU_EHTR_8IDLE 0x00000006 /* Eight Idle Clock Cycles Inserted*/ - - -/* helpers to convert values into an OR address mask (GPCM mode) */ -#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */ -#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20) - - -/*----------------------------------------------------------------------- - * PSDMR - 60x SDRAM Mode Register 10-21 - */ -#define PSDMR_PBI 0x80000000 /* Page-based Interleaving */ -#define PSDMR_RFEN 0x40000000 /* Refresh Enable */ -#define PSDMR_OP_MSK 0x38000000 /* SDRAM Operation Mask */ -#define PSDMR_SDAM_MSK 0x07000000 /* SDRAM Address Multiplex Mask */ -#define PSDMR_BSMA_MSK 0x00e00000 /* Bank Select Muxd Addr Line Mask*/ -#define PSDMR_SDA10_MSK 0x001c0000 /* A10 Control Mask */ -#define PSDMR_RFRC_MSK 0x00038000 /* Refresh Recovery Mask */ -#define PSDMR_PRETOACT_MSK 0x00007000 /* Precharge to Activate Intvl Mask*/ -#define PSDMR_ACTTORW_MSK 0x00000e00 /* Activate to Read/Write Intvl Mask*/ -#define PSDMR_BL 0x00000100 /* Burst Length */ -#define PSDMR_LDOTOPRE_MSK 0x000000c0 /* Last Data Out to Precharge Mask*/ -#define PSDMR_WRC_MSK 0x00000030 /* Write Recovery Time Mask */ -#define PSDMR_EAMUX 0x00000008 /* External Address Multiplexing*/ -#define PSDMR_BUFCMD 0x00000004 /* SDRAM ctl lines asrtd for 2 cycles*/ -#define PSDMR_CL_MSK 0x00000003 /* CAS Latency Mask */ - -#define PSDMR_OP_NORM 0x00000000 /* Normal Operation */ -#define PSDMR_OP_CBRR 0x08000000 /* CBR Refresh */ -#define PSDMR_OP_SELFR 0x10000000 /* Self Refresh */ -#define PSDMR_OP_MRW 0x18000000 /* Mode Register Write */ -#define PSDMR_OP_PREB 0x20000000 /* Precharge Bank */ -#define PSDMR_OP_PREA 0x28000000 /* Precharge All Banks */ -#define PSDMR_OP_ACTB 0x30000000 /* Activate Bank */ -#define PSDMR_OP_RW 0x38000000 /* Read/Write */ - -#define PSDMR_SDAM_A13_IS_A5 0x00000000 /* SDRAM Address Multiplex A13 is A5 */ -#define PSDMR_SDAM_A14_IS_A5 0x01000000 /* SDRAM Address Multiplex A14 is A5 */ -#define PSDMR_SDAM_A15_IS_A5 0x02000000 /* SDRAM Address Multiplex A15 is A5 */ -#define PSDMR_SDAM_A16_IS_A5 0x03000000 /* SDRAM Address Multiplex A16 is A5 */ -#define PSDMR_SDAM_A17_IS_A5 0x04000000 /* SDRAM Address Multiplex A17 is A5 */ -#define PSDMR_SDAM_A18_IS_A5 0x05000000 /* SDRAM Address Multiplex A18 is A5 */ - -#define PSDMR_BSMA_A12_A14 0x00000000 /* A12 - A14 */ -#define PSDMR_BSMA_A13_A15 0x00200000 /* A13 - A15 */ -#define PSDMR_BSMA_A14_A16 0x00400000 /* A14 - A16 */ -#define PSDMR_BSMA_A15_A17 0x00600000 /* A15 - A17 */ -#define PSDMR_BSMA_A16_A18 0x00800000 /* A16 - A18 */ -#define PSDMR_BSMA_A17_A19 0x00a00000 /* A17 - A19 */ -#define PSDMR_BSMA_A18_A20 0x00c00000 /* A18 - A20 */ -#define PSDMR_BSMA_A19_A21 0x00e00000 /* A19 - A21 */ - -/* SDA10 values for xSDMR[PBI] = 0 */ -#define PSDMR_SDA10_PBI0_A12 0x00000000 /* "A10" Control is A12 */ -#define PSDMR_SDA10_PBI0_A11 0x00040000 /* "A10" Control is A11 */ -#define PSDMR_SDA10_PBI0_A10 0x00080000 /* "A10" Control is A10 */ -#define PSDMR_SDA10_PBI0_A9 0x000c0000 /* "A10" Control is A9 */ -#define PSDMR_SDA10_PBI0_A8 0x00100000 /* "A10" Control is A8 */ -#define PSDMR_SDA10_PBI0_A7 0x00140000 /* "A10" Control is A7 */ -#define PSDMR_SDA10_PBI0_A6 0x00180000 /* "A10" Control is A6 */ -#define PSDMR_SDA10_PBI0_A5 0x001c0000 /* "A10" Control is A5 */ - -/* SDA10 values for xSDMR[PBI] = 1 */ -#define PSDMR_SDA10_PBI1_A10 0x00000000 /* "A10" Control is A10 */ -#define PSDMR_SDA10_PBI1_A9 0x00040000 /* "A10" Control is A9 */ -#define PSDMR_SDA10_PBI1_A8 0x00080000 /* "A10" Control is A8 */ -#define PSDMR_SDA10_PBI1_A7 0x000c0000 /* "A10" Control is A7 */ -#define PSDMR_SDA10_PBI1_A6 0x00100000 /* "A10" Control is A6 */ -#define PSDMR_SDA10_PBI1_A5 0x00140000 /* "A10" Control is A5 */ -#define PSDMR_SDA10_PBI1_A4 0x00180000 /* "A10" Control is A4 */ -#define PSDMR_SDA10_PBI1_A3 0x001c0000 /* "A10" Control is A3 */ - -#define PSDMR_RFRC_3_CLK 0x00008000 /* 3 Clocks */ -#define PSDMR_RFRC_4_CLK 0x00010000 /* 4 Clocks */ -#define PSDMR_RFRC_5_CLK 0x00018000 /* 5 Clocks */ -#define PSDMR_RFRC_6_CLK 0x00020000 /* 6 Clocks */ -#define PSDMR_RFRC_7_CLK 0x00028000 /* 7 Clocks */ -#define PSDMR_RFRC_8_CLK 0x00030000 /* 8 Clocks */ -#define PSDMR_RFRC_16_CLK 0x00038000 /* 16 Clocks */ - -#define PSDMR_PRETOACT_8W 0x00000000 /* 8 Clock-cycle Wait States */ -#define PSDMR_PRETOACT_1W 0x00001000 /* 1 Clock-cycle Wait States */ -#define PSDMR_PRETOACT_2W 0x00002000 /* 2 Clock-cycle Wait States */ -#define PSDMR_PRETOACT_3W 0x00003000 /* 3 Clock-cycle Wait States */ -#define PSDMR_PRETOACT_4W 0x00004000 /* 4 Clock-cycle Wait States */ -#define PSDMR_PRETOACT_5W 0x00005000 /* 5 Clock-cycle Wait States */ -#define PSDMR_PRETOACT_6W 0x00006000 /* 6 Clock-cycle Wait States */ -#define PSDMR_PRETOACT_7W 0x00007000 /* 7 Clock-cycle Wait States */ - -#define PSDMR_ACTTORW_8W 0x00000000 /* 8 Clock-cycle Wait States */ -#define PSDMR_ACTTORW_1W 0x00000200 /* 1 Clock-cycle Wait States */ -#define PSDMR_ACTTORW_2W 0x00000400 /* 2 Clock-cycle Wait States */ -#define PSDMR_ACTTORW_3W 0x00000600 /* 3 Clock-cycle Wait States */ -#define PSDMR_ACTTORW_4W 0x00000800 /* 4 Clock-cycle Wait States */ -#define PSDMR_ACTTORW_5W 0x00000a00 /* 5 Clock-cycle Wait States */ -#define PSDMR_ACTTORW_6W 0x00000c00 /* 6 Clock-cycle Wait States */ -#define PSDMR_ACTTORW_7W 0x00000e00 /* 7 Clock-cycle Wait States */ - -#define PSDMR_LDOTOPRE_0C 0x00000000 /* 0 Clock Cycles */ -#define PSDMR_LDOTOPRE_1C 0x00000040 /* 1 Clock Cycles */ -#define PSDMR_LDOTOPRE_2C 0x00000080 /* 2 Clock Cycles */ - -#define PSDMR_WRC_4C 0x00000000 /* 4 Clock Cycles */ -#define PSDMR_WRC_1C 0x00000010 /* 1 Clock Cycles */ -#define PSDMR_WRC_2C 0x00000020 /* 2 Clock Cycles */ -#define PSDMR_WRC_3C 0x00000030 /* 3 Clock Cycles */ - -#define PSDMR_CL_1 0x00000001 /* CAS Latency = 1 */ -#define PSDMR_CL_2 0x00000002 /* CAS Latency = 2 */ -#define PSDMR_CL_3 0x00000003 /* CAS Latency = 3 */ - -/*----------------------------------------------------------------------- - * LSDMR - Local Bus SDRAM Mode Register 10-24 - */ - -/* - * No definitions here - the LSDMR has the same fields as the PSDMR. - */ - -/*----------------------------------------------------------------------- - * MPTPR - Memory Refresh Timer Prescaler Register 10-32 - * See User's Manual Errata for the changed definition (matches the - * 8xx now). The wrong prescaler definition causes excessive refreshes - * (typically "divide by 2" when "divide by 32" is intended) which will - * cause unnecessary memory subsystem slowdown. - */ -#define MPTPR_PTP_MSK 0xff00 /* Periodic Timers Prescaler Mask */ -#define MPTPR_PTP_DIV2 0x2000 /* BRGCLK divided by 2 */ -#define MPTPR_PTP_DIV4 0x1000 /* BRGCLK divided by 4 */ -#define MPTPR_PTP_DIV8 0x0800 /* BRGCLK divided by 8 */ -#define MPTPR_PTP_DIV16 0x0400 /* BRGCLK divided by 16 */ -#define MPTPR_PTP_DIV32 0x0200 /* BRGCLK divided by 32 */ -#define MPTPR_PTP_DIV64 0x0100 /* BRGCLK divided by 64 */ - - -/*----------------------------------------------------------------------- - * TGCR1/TGCR2 - Timer Global Configuration Registers 17-4 - */ -#define TGCR1_CAS2 0x80 /* Cascade Timer 1 and 2 */ -#define TGCR1_STP2 0x20 /* Stop timer 2 */ -#define TGCR1_RST2 0x10 /* Reset timer 2 */ -#define TGCR1_GM1 0x08 /* Gate Mode for Pin 1 */ -#define TGCR1_STP1 0x02 /* Stop timer 1 */ -#define TGCR1_RST1 0x01 /* Reset timer 1 */ -#define TGCR2_CAS4 0x80 /* Cascade Timer 3 and 4 */ -#define TGCR2_STP4 0x20 /* Stop timer 4 */ -#define TGCR2_RST4 0x10 /* Reset timer 4 */ -#define TGCR2_GM2 0x08 /* Gate Mode for Pin 2 */ -#define TGCR2_STP3 0x02 /* Stop timer 3 */ -#define TGCR2_RST3 0x01 /* Reset timer 3 */ - - -/*----------------------------------------------------------------------- - * TMR1-TMR4 - Timer Mode Registers 17-6 - */ -#define TMRx_PS_MSK 0xff00 /* Prescaler Value */ -#define TMRx_CE_MSK 0x00c0 /* Capture Edge and Enable Interrupt*/ -#define TMRx_OM 0x0020 /* Output Mode */ -#define TMRx_ORI 0x0010 /* Output Reference Interrupt Enable*/ -#define TMRx_FRR 0x0008 /* Free Run/Restart */ -#define TMRx_ICLK_MSK 0x0006 /* Timer Input Clock Source mask */ -#define TMRx_GE 0x0001 /* Gate Enable */ - -#define TMRx_CE_INTR_DIS 0x0000 /* Disable Interrupt on capture event*/ -#define TMRx_CE_RISING 0x0040 /* Capture on Rising TINx edge only */ -#define TMRx_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */ -#define TMRx_CE_ANY 0x00c0 /* Capture on any TINx edge */ - -#define TMRx_ICLK_IN_CAS 0x0000 /* Internally cascaded input */ -#define TMRx_ICLK_IN_GEN 0x0002 /* Internal General system clock*/ -#define TMRx_ICLK_IN_GEN_DIV16 0x0004 /* Internal General system clk div 16*/ -#define TMRx_ICLK_TIN_PIN 0x0006 /* TINx pin */ - - -/*----------------------------------------------------------------------- - * CMXFCR - CMX FCC Clock Route Register 15-12 - */ -#define CMXFCR_FC1 0x40000000 /* FCC1 connection */ -#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */ -#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */ -#define CMXFCR_FC2 0x00400000 /* FCC2 connection */ -#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */ -#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */ -#define CMXFCR_FC3 0x00004000 /* FCC3 connection */ -#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */ -#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */ - -#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */ -#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */ -#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */ -#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */ -#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */ -#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */ -#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */ -#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */ - -#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */ -#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */ -#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */ -#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */ -#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */ -#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */ -#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */ -#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */ - -#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */ -#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */ -#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */ -#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */ -#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */ -#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */ -#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */ -#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */ - -#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */ -#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */ -#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */ -#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */ -#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */ -#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */ -#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */ -#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */ - -#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */ -#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */ -#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */ -#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */ -#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */ -#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */ -#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */ -#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */ - -#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */ -#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */ -#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */ -#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */ -#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */ -#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */ -#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */ -#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */ - -/*----------------------------------------------------------------------- - * CMXSCR - CMX SCC Clock Route Register 15-14 - */ -#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */ -#define CMXSCR_SC1 0x40000000 /* SCC1 connection */ -#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */ -#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */ -#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */ -#define CMXSCR_SC2 0x00400000 /* SCC2 connection */ -#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */ -#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */ -#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */ -#define CMXSCR_SC3 0x00004000 /* SCC3 connection */ -#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */ -#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */ -#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */ -#define CMXSCR_SC4 0x00000040 /* SCC4 connection */ -#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */ -#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */ - -#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */ -#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */ -#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */ -#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */ -#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */ -#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */ -#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */ -#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */ - -#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */ -#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */ -#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */ -#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */ -#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */ -#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */ -#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */ -#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */ - -#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */ -#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */ -#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */ -#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */ -#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */ -#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */ -#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */ -#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */ - -#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */ -#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */ -#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */ -#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */ -#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */ -#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */ -#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */ -#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */ - -#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */ -#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */ -#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */ -#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */ -#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */ -#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */ -#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */ -#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */ - -#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */ -#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */ -#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */ -#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */ -#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */ -#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */ -#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */ -#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */ - -#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */ -#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */ -#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */ -#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */ -#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */ -#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */ -#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */ -#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */ - -#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */ -#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */ -#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */ -#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */ -#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */ -#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */ -#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */ -#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */ - -/*----------------------------------------------------------------------- - * CMXSMR - CMX SMC Clock Route Register 15-17 - */ -#define CMXSMR_SMC1 0x80 /* SMC1 Connection */ -#define CMXSMR_SMC1CS_MSK 0x30 /* SMC1 Clock Source */ -#define CMXSMR_SMC2 0x08 /* SMC2 Connection */ -#define CMXSMR_SMC2CS_MSK 0x03 /* SMC2 Clock Source */ - -#define CMXSMR_SMC1CS_BRG1 0x00 /* SMC1 Tx and Rx Clocks are BRG1 */ -#define CMXSMR_SMC1CS_BRG7 0x10 /* SMC1 Tx and Rx Clocks are BRG7 */ -#define CMXSMR_SMC1CS_CLK7 0x20 /* SMC1 Tx and Rx Clocks are CLK7 */ -#define CMXSMR_SMC1CS_CLK9 0x30 /* SMC1 Tx and Rx Clocks are CLK9 */ - -#define CMXSMR_SMC2CS_BRG2 0x00 /* SMC2 Tx and Rx Clocks are BRG2 */ -#define CMXSMR_SMC2CS_BRG8 0x01 /* SMC2 Tx and Rx Clocks are BRG8 */ -#define CMXSMR_SMC2CS_CLK19 0x02 /* SMC2 Tx and Rx Clocks are CLK19 */ -#define CMXSMR_SMC2CS_CLK20 0x03 /* SMC2 Tx and Rx Clocks are CLK20 */ - -/*----------------------------------------------------------------------- - * miscellaneous - */ - -#define UPMA 1 -#define UPMB 2 -#define UPMC 3 - -#if !defined(__ASSEMBLY__) && defined(CONFIG_WATCHDOG) -static __inline__ void -reset_8260_watchdog(volatile immap_t *immr) -{ - immr->im_siu_conf.sc_swsr = 0x556c; - immr->im_siu_conf.sc_swsr = 0xaa39; -} -#endif /* !__ASSEMBLY && CONFIG_WATCHDOG */ - -#endif /* __MPC8260_H__ */ diff --git a/include/mpc8260_irq.h b/include/mpc8260_irq.h deleted file mode 100644 index 9bee9a335f..0000000000 --- a/include/mpc8260_irq.h +++ /dev/null @@ -1,48 +0,0 @@ -#ifndef _MPC8260_IRQ_H -#define _MPC8260_IRQ_H - -/****************************************************************************/ -/* most of this was ripped out of include/asm-ppc/irq.h from the Linux/PPC */ -/* source. There was no copyright information in the file. */ - -/* - * this is the # irq's for all ppc arch's (pmac/chrp/prep) - * so it is the max of them all - * - * [let's just worry about 8260 for now - mjj] - */ -#define NR_IRQS 64 - -/* The 8260 has an internal interrupt controller with a maximum of - * 64 IRQs. We will use NR_IRQs from above since it is large enough. - * Don't be confused by the 8260 documentation where they list an - * "interrupt number" and "interrupt vector". We are only interested - * in the interrupt vector. There are "reserved" holes where the - * vector number increases, but the interrupt number in the table does not. - * (Document errata updates have fixed this...make sure you have up to - * date processor documentation -- Dan). - */ -#define NR_SIU_INTS 64 - -/* There are many more than these, we will add them as we need them. -*/ -#define SIU_INT_SMC1 ((uint)0x04) -#define SIU_INT_SMC2 ((uint)0x05) -#define SIU_INT_IRQ1 ((uint)0x13) -#define SIU_INT_IRQ2 ((uint)0x14) -#define SIU_INT_IRQ3 ((uint)0x15) -#define SIU_INT_IRQ4 ((uint)0x16) -#define SIU_INT_IRQ5 ((uint)0x17) -#define SIU_INT_IRQ6 ((uint)0x18) -#define SIU_INT_IRQ7 ((uint)0x19) -#define SIU_INT_FCC1 ((uint)0x20) -#define SIU_INT_FCC2 ((uint)0x21) -#define SIU_INT_FCC3 ((uint)0x22) -#define SIU_INT_SCC1 ((uint)0x28) -#define SIU_INT_SCC2 ((uint)0x29) -#define SIU_INT_SCC3 ((uint)0x2a) -#define SIU_INT_SCC4 ((uint)0x2b) - -#define NR_MASK_WORDS ((NR_IRQS + 31) / 32) - -#endif /* _MPC8260_IRQ_H */ diff --git a/include/nand.h b/include/nand.h index a86552878e..bc5dd81901 100644 --- a/include/nand.h +++ b/include/nand.h @@ -132,8 +132,6 @@ void board_nand_select_device(struct nand_chip *nand, int chip); __attribute__((noreturn)) void nand_boot(void); -#endif - #ifdef CONFIG_ENV_OFFSET_OOB #define ENV_OOB_MARKER 0x30425645 /*"EVB0" in little-endian -- offset is stored as block number*/ @@ -146,3 +144,5 @@ int spl_nand_erase_one(int block, int page); /* platform specific init functions */ void sunxi_nand_init(void); + +#endif /* _NAND_H_ */ diff --git a/include/net.h b/include/net.h index ed5259a807..2eaa88224c 100644 --- a/include/net.h +++ b/include/net.h @@ -12,10 +12,6 @@ #ifndef __NET_H__ #define __NET_H__ -#if defined(CONFIG_8xx) -#include <commproc.h> -#endif /* CONFIG_8xx */ - #include <asm/cache.h> #include <asm/byteorder.h> /* for nton* / ntoh* stuff */ diff --git a/include/netdev.h b/include/netdev.h index 8eb8b46619..c06b90886b 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -57,9 +57,6 @@ int lpc32xx_eth_initialize(bd_t *bis); int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); int mcdmafec_initialize(bd_t *bis); int mcffec_initialize(bd_t *bis); -int mpc512x_fec_initialize(bd_t *bis); -int mpc5xxx_fec_initialize(bd_t *bis); -int mpc82xx_scc_enet_initialize(bd_t *bis); int mvgbe_initialize(bd_t *bis); int mvneta_initialize(bd_t *bis, int base_addr, int devnum, int phy_addr); int natsemi_initialize(bd_t *bis); diff --git a/include/pcmcia.h b/include/pcmcia.h index aaaf6511a8..94b54c210d 100644 --- a/include/pcmcia.h +++ b/include/pcmcia.h @@ -15,18 +15,10 @@ * Allow configuration to select PCMCIA slot, * or try to generate a useful default */ -#if defined(CONFIG_CMD_PCMCIA) || \ - (defined(CONFIG_IDE) && \ - (defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) ) +#if defined(CONFIG_CMD_PCMCIA) #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) - -#if defined(CONFIG_TQM8xxL) -# define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */ -#else # error "PCMCIA Slot not configured" -#endif - #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */ /* Make sure exactly one slot is defined - we support only one for now */ @@ -57,17 +49,6 @@ #endif /* - * The TQM850L hardware has two pins swapped! Grrrrgh! - */ -#ifdef CONFIG_TQM850L -#define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXOE -#define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXRESET -#else -#define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXRESET -#define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXOE -#endif - -/* * This structure is used to address each window in the PCMCIA controller. * * Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly @@ -263,13 +244,4 @@ typedef struct { #endif -#ifdef CONFIG_8xx -extern u_int *pcmcia_pgcrx[]; -#define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot]) -#endif - -#if defined(CONFIG_IDE) && defined(CONFIG_IDE_8xx_PCCARD) -extern int check_ide_device(int slot); -#endif - #endif /* _PCMCIA_H */ diff --git a/include/post.h b/include/post.h index 5ebd535823..b9b9c3775b 100644 --- a/include/post.h +++ b/include/post.h @@ -22,22 +22,7 @@ #define _POST_WORD_ADDR CONFIG_SYS_POST_WORD_ADDR #else -#ifdef CONFIG_MPC5xxx -#define _POST_WORD_ADDR (MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE) - -#elif defined(CONFIG_MPC512X) -#define _POST_WORD_ADDR \ - (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET - 0x4) - -#elif defined(CONFIG_8xx) -#define _POST_WORD_ADDR \ - (((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_dpmem + CPM_POST_WORD_ADDR) - -#elif defined(CONFIG_MPC8260) -#include <asm/cpm_8260.h> -#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR) - -#elif defined(CONFIG_MPC8360) +#if defined(CONFIG_MPC8360) #include <linux/immap_qe.h> #define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR) @@ -164,7 +149,6 @@ extern int memory_post_test(int flags); #define CONFIG_SYS_POST_CACHE 0x00000020 #define CONFIG_SYS_POST_UART 0x00000040 #define CONFIG_SYS_POST_ETHER 0x00000080 -#define CONFIG_SYS_POST_SPI 0x00000100 #define CONFIG_SYS_POST_USB 0x00000200 #define CONFIG_SYS_POST_SPR 0x00000400 #define CONFIG_SYS_POST_SYSMON 0x00000800 diff --git a/include/power/lp87565.h b/include/power/lp87565.h new file mode 100644 index 0000000000..5160f5df6c --- /dev/null +++ b/include/power/lp87565.h @@ -0,0 +1,12 @@ +#define LP87565 0x0 +#define LP87565_Q1 0x1 + +#define LP87565_BUCK_NUM 6 + +/* Drivers name */ +#define LP87565_BUCK_DRIVER "lp87565_buck" + +#define LP87565_BUCK_VOLT_MASK 0xFF +#define LP87565_BUCK_VOLT_MAX_HEX 0xFF +#define LP87565_BUCK_VOLT_MAX 3360000 +#define LP87565_BUCK_MODE_MASK 0x80 diff --git a/include/power/tps65217.h b/include/power/tps65217.h index 69a49f76fe..cb07ea5ce6 100644 --- a/include/power/tps65217.h +++ b/include/power/tps65217.h @@ -38,6 +38,7 @@ enum { TPS65217_DEFLS1, TPS65217_DEFLS2, TPS65217_ENABLE, + TPS65217_RESERVED0, /* no 0x17 register available */ TPS65217_DEFUVLO, TPS65217_SEQ1, TPS65217_SEQ2, diff --git a/include/power/tps65218.h b/include/power/tps65218.h index e3538e21f0..43b9c9aa52 100644 --- a/include/power/tps65218.h +++ b/include/power/tps65218.h @@ -63,6 +63,7 @@ enum { #define TPS65218_DCDC_VOLT_SEL_1200MV 0x23 #define TPS65218_DCDC_VOLT_SEL_1260MV 0x29 #define TPS65218_DCDC_VOLT_SEL_1330MV 0x30 +#define TPS65218_DCDC3_VOLT_SEL_1350MV 0x12 #define TPS65218_CC_STAT (BIT(0) | BIT(1)) #define TPS65218_STATE (BIT(2) | BIT(3)) diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl index 379c493919..ce71ee9bc9 100644 --- a/include/ppc_asm.tmpl +++ b/include/ppc_asm.tmpl @@ -81,93 +81,6 @@ #define r30 30 #define r31 31 - -#if defined(CONFIG_8xx) - -/* Some special registers */ - -#define ICR 148 /* Interrupt Cause Register (37-44) */ -#define DER 149 -#define COUNTA 150 /* Breakpoint Counter (37-44) */ -#define COUNTB 151 /* Breakpoint Counter (37-44) */ -#define LCTRL1 156 /* Load/Store Support (37-40) */ -#define LCTRL2 157 /* Load/Store Support (37-41) */ -#define ICTRL 158 - -#endif /* CONFIG_8xx */ - - -#if defined(CONFIG_5xx) -/* Some special purpose registers */ -#define DER 149 /* Debug Enable Register */ -#define COUNTA 150 /* Breakpoint Counter */ -#define COUNTB 151 /* Breakpoint Counter */ -#define LCTRL1 156 /* Load/Store Support */ -#define LCTRL2 157 /* Load/Store Support */ -#define ICTRL 158 /* I-Bus Support Control Register */ -#define EID 81 -#endif /* CONFIG_5xx */ - -#if defined(CONFIG_8xx) - -/* Registers in the processor's internal memory map that we use. -*/ -#define SYPCR 0x00000004 -#define BR0 0x00000100 -#define OR0 0x00000104 -#define BR1 0x00000108 -#define OR1 0x0000010c -#define BR2 0x00000110 -#define OR2 0x00000114 -#define BR3 0x00000118 -#define OR3 0x0000011c -#define BR4 0x00000120 -#define OR4 0x00000124 - -#define MAR 0x00000164 -#define MCR 0x00000168 -#define MAMR 0x00000170 -#define MBMR 0x00000174 -#define MSTAT 0x00000178 -#define MPTPR 0x0000017a -#define MDR 0x0000017c - -#define TBSCR 0x00000200 -#define TBREFF0 0x00000204 - -#define PLPRCR 0x00000284 - -#elif defined(CONFIG_MPC8260) - -#define HID2 1011 - -#define HID0_IFEM (1<<7) - -#define HID0_ICE_BITPOS 16 -#define HID0_DCE_BITPOS 17 - -#define IM_REGBASE 0x10000 -#define IM_SYPCR (IM_REGBASE+0x0004) -#define IM_SWSR (IM_REGBASE+0x000e) -#define IM_BR0 (IM_REGBASE+0x0100) -#define IM_OR0 (IM_REGBASE+0x0104) -#define IM_BR1 (IM_REGBASE+0x0108) -#define IM_OR1 (IM_REGBASE+0x010c) -#define IM_BR2 (IM_REGBASE+0x0110) -#define IM_OR2 (IM_REGBASE+0x0114) -#define IM_MPTPR (IM_REGBASE+0x0184) -#define IM_PSDMR (IM_REGBASE+0x0190) -#define IM_PSRT (IM_REGBASE+0x019c) -#define IM_IMMR (IM_REGBASE+0x01a8) -#define IM_SCCR (IM_REGBASE+0x0c80) - -#elif defined(CONFIG_MPC5xxx) - -#define HID0_ICE_BITPOS 16 -#define HID0_DCE_BITPOS 17 - -#endif - #define curptr r2 #define SYNC \ diff --git a/include/serial.h b/include/serial.h index 47332c5340..a5b555d14c 100644 --- a/include/serial.h +++ b/include/serial.h @@ -29,9 +29,8 @@ extern struct serial_device *default_serial_console(void); #if defined(CONFIG_405GP) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ defined(CONFIG_405EX) || defined(CONFIG_440) || \ - defined(CONFIG_MPC5xxx) || \ defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \ - defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \ + defined(CONFIG_MPC86xx) || \ defined(CONFIG_TEGRA) || defined(CONFIG_SYS_COREBOOT) || \ defined(CONFIG_MICROBLAZE) extern struct serial_device serial0_device; @@ -69,13 +68,6 @@ extern int usbtty_tstc(void); #endif /* CONFIG_USB_TTY */ -#if defined(CONFIG_MPC512X) -extern struct stdio_dev *open_port(int num, int baudrate); -extern int close_port(int num); -extern int write_port(struct stdio_dev *port, char *buf); -extern int read_port(struct stdio_dev *port, char *buf, int size); -#endif - struct udevice; /** @@ -192,10 +184,6 @@ void marvell_serial_initialize(void); void max3100_serial_initialize(void); void mcf_serial_initialize(void); void ml2_serial_initialize(void); -void mpc512x_serial_initialize(void); -void mpc5xx_serial_initialize(void); -void mpc8260_scc_serial_initialize(void); -void mpc8260_smc_serial_initialize(void); void mpc85xx_serial_initialize(void); void mpc8xx_serial_initialize(void); void mxc_serial_initialize(void); diff --git a/include/status_led.h b/include/status_led.h index f838f362dd..8178e93ebf 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -40,17 +40,8 @@ void status_led_init(void); void status_led_tick (unsigned long timestamp); void status_led_set (int led, int state); -/***** TQM8xxL ********************************************************/ -#if defined(CONFIG_TQM8xxL) -# define STATUS_LED_PAR im_cpm.cp_pbpar -# define STATUS_LED_DIR im_cpm.cp_pbdir -# define STATUS_LED_ODR im_cpm.cp_pbodr -# define STATUS_LED_DAT im_cpm.cp_pbdat - -# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - /***** MVS v1 **********************************************************/ -#elif (defined(CONFIG_MVS) && CONFIG_MVS < 2) +#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) # define STATUS_LED_PAR im_ioport.iop_pdpar # define STATUS_LED_DIR im_ioport.iop_pddir # undef STATUS_LED_ODR @@ -65,10 +56,6 @@ void status_led_set (int led, int state); * filling this file up with lots of custom board stuff. */ -#elif defined(CONFIG_V38B) - -# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ - #elif defined(CONFIG_LED_STATUS_BOARD_SPECIFIC) /* led_id_t is unsigned long mask */ typedef unsigned long led_id_t; diff --git a/include/usb/dwc2_udc.h b/include/usb/dwc2_udc.h index 7324d8a62d..1a370e0e86 100644 --- a/include/usb/dwc2_udc.h +++ b/include/usb/dwc2_udc.h @@ -16,7 +16,7 @@ struct dwc2_plat_otg_data { int phy_of_node; int (*phy_control)(int on); unsigned int regs_phy; - unsigned int regs_otg; + uintptr_t regs_otg; unsigned int usb_phy_ctrl; unsigned int usb_flags; unsigned int usb_gusbcfg; diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h index 8f3437a208..847b6989a0 100644 --- a/include/usb/ehci-ci.h +++ b/include/usb/ehci-ci.h @@ -156,9 +156,6 @@ #elif defined(CONFIG_MPC85xx) #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC85xx_USB1_ADDR #define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC85xx_USB2_ADDR -#elif defined(CONFIG_MPC512X) -#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR -#define CONFIG_SYS_FSL_USB2_ADDR 0 #elif defined(CONFIG_ARCH_LS1021A) #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR #define CONFIG_SYS_FSL_USB2_ADDR 0 diff --git a/include/usb/mpc8xx_udc.h b/include/usb/mpc8xx_udc.h deleted file mode 100644 index 9906c75f6a..0000000000 --- a/include/usb/mpc8xx_udc.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (C) 2006 Bryan O'Donoghue, CodeHermit - * bodonoghue@codehermit.ie - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <commproc.h> - -/* Mode Register */ -#define USMOD_EN 0x01 -#define USMOD_HOST 0x02 -#define USMOD_TEST 0x04 -#define USMOD_SFTE 0x08 -#define USMOD_RESUME 0x40 -#define USMOD_LSS 0x80 - -/* Endpoint Registers */ -#define USEP_RHS_NORM 0x00 -#define USEP_RHS_IGNORE 0x01 -#define USEP_RHS_NAK 0x02 -#define USEP_RHS_STALL 0x03 - -#define USEP_THS_NORM 0x00 -#define USEP_THS_IGNORE 0x04 -#define USEP_THS_NAK 0x08 -#define USEP_THS_STALL 0x0C - -#define USEP_RTE 0x10 -#define USEP_MF 0x20 - -#define USEP_TM_CONTROL 0x00 -#define USEP_TM_INT 0x100 -#define USEP_TM_BULK 0x200 -#define USEP_TM_ISO 0x300 - -/* Command Register */ -#define USCOM_EP0 0x00 -#define USCOM_EP1 0x01 -#define USCOM_EP2 0x02 -#define USCOM_EP3 0x03 - -#define USCOM_FLUSH 0x40 -#define USCOM_STR 0x80 - -/* Event Register */ -#define USB_E_RXB 0x0001 -#define USB_E_TXB 0x0002 -#define USB_E_BSY 0x0004 -#define USB_E_SOF 0x0008 -#define USB_E_TXE1 0x0010 -#define USB_E_TXE2 0x0020 -#define USB_E_TXE3 0x0040 -#define USB_E_TXE4 0x0080 -#define USB_TX_ERRMASK (USB_E_TXE1|USB_E_TXE2|USB_E_TXE3|USB_E_TXE4) -#define USB_E_IDLE 0x0100 -#define USB_E_RESET 0x0200 - -/* Mask Register */ -#define USBS_IDLE 0x01 - -/* RX Buffer Descriptor */ -#define RX_BD_OV 0x02 -#define RX_BD_CR 0x04 -#define RX_BD_AB 0x08 -#define RX_BD_NO 0x10 -#define RX_BD_PID_DATA0 0x00 -#define RX_BD_PID_DATA1 0x40 -#define RX_BD_PID_SETUP 0x80 -#define RX_BD_F 0x400 -#define RX_BD_L 0x800 -#define RX_BD_I 0x1000 -#define RX_BD_W 0x2000 -#define RX_BD_E 0x8000 - -/* Useful masks */ -#define RX_BD_PID_BITMASK (RX_BD_PID_DATA1 | RX_BD_PID_SETUP) -#define STALL_BITMASK (USEP_THS_STALL | USEP_RHS_STALL) -#define NAK_BITMASK (USEP_THS_NAK | USEP_RHS_NAK) -#define CBD_TX_BITMASK (TX_BD_R | TX_BD_L | TX_BD_TC | TX_BD_I | TX_BD_CNF) - -/* TX Buffer Descriptor */ -#define TX_BD_UN 0x02 -#define TX_BD_TO 0x04 -#define TX_BD_NO_PID 0x00 -#define TX_BD_PID_DATA0 0x80 -#define TX_BD_PID_DATA1 0xC0 -#define TX_BD_CNF 0x200 -#define TX_BD_TC 0x400 -#define TX_BD_L 0x800 -#define TX_BD_I 0x1000 -#define TX_BD_W 0x2000 -#define TX_BD_R 0x8000 - -/* Implementation specific defines */ - -#define EP_MIN_PACKET_SIZE 0x08 -#define MAX_ENDPOINTS 0x04 -#define FIFO_SIZE 0x10 -#define EP_MAX_PKT FIFO_SIZE -#define TX_RING_SIZE 0x04 -#define RX_RING_SIZE 0x06 -#define USB_MAX_PKT 0x40 -#define TOGGLE_TX_PID(x) x= ((~x)&0x40)|0x80 -#define TOGGLE_RX_PID(x) x^= 0x40 -#define EP_ATTACHED 0x01 /* Endpoint has a urb attached or not */ -#define EP_SEND_ZLP 0x02 /* Send ZLP y/n ? */ - -#define PROFF_USB 0x00000000 -#define CPM_USB_BASE 0x00000A00 - -/* UDC device defines */ -#define EP0_MAX_PACKET_SIZE EP_MAX_PKT - -#define UDC_OUT_PACKET_SIZE EP_MIN_PACKET_SIZE -#define UDC_IN_PACKET_SIZE EP_MIN_PACKET_SIZE -#define UDC_INT_PACKET_SIZE UDC_IN_PACKET_SIZE -#define UDC_BULK_PACKET_SIZE EP_MIN_PACKET_SIZE - -struct mpc8xx_ep { - struct urb * urb; - unsigned char pid; - unsigned char sc; - volatile cbd_t * prx; -}; - -typedef struct mpc8xx_usb{ - char usmod; /* Mode Register */ - char usaddr; /* Slave Address Register */ - char uscom; /* Command Register */ - char res1; /* Reserved */ - ushort usep[4]; - ulong res2; /* Reserved */ - ushort usber; /* Event Register */ - ushort res3; /* Reserved */ - ushort usbmr; /* Mask Register */ - char res4; /* Reserved */ - char usbs; /* Status Register */ - char res5[8]; /* Reserved */ -}usb_t; - -typedef struct mpc8xx_parameter_ram{ - ushort ep0ptr; /* Endpoint Pointer Register 0 */ - ushort ep1ptr; /* Endpoint Pointer Register 1 */ - ushort ep2ptr; /* Endpoint Pointer Register 2 */ - ushort ep3ptr; /* Endpoint Pointer Register 3 */ - uint rstate; /* Receive state */ - uint rptr; /* Receive internal data pointer */ - ushort frame_n; /* Frame number */ - ushort rbcnt; /* Receive byte count */ - uint rtemp; /* Receive temp cp use only */ - uint rxusb; /* Rx Data Temp */ - ushort rxuptr; /* Rx microcode return address temp */ -}usb_pram_t; - -typedef struct endpoint_parameter_block_pointer{ - ushort rbase; /* RxBD base address */ - ushort tbase; /* TxBD base address */ - char rfcr; /* Rx Function code */ - char tfcr; /* Tx Function code */ - ushort mrblr; /* Maximum Receive Buffer Length */ - ushort rbptr; /* RxBD pointer Next Buffer Descriptor */ - ushort tbptr; /* TxBD pointer Next Buffer Descriptor */ - ulong tstate; /* Transmit internal state */ - ulong tptr; /* Transmit internal data pointer */ - ushort tcrc; /* Transmit temp CRC */ - ushort tbcnt; /* Transmit internal bye count */ - ulong ttemp; /* Tx temp */ - ushort txuptr; /* Tx microcode return address */ - ushort res1; /* Reserved */ -}usb_epb_t; - -typedef enum mpc8xx_udc_state{ - STATE_NOT_READY, - STATE_ERROR, - STATE_READY, -}mpc8xx_udc_state_t; - diff --git a/include/watchdog.h b/include/watchdog.h index 174c894e49..322dda79f0 100644 --- a/include/watchdog.h +++ b/include/watchdog.h @@ -72,21 +72,6 @@ int init_func_watchdog_reset(void); * Prototypes from $(CPU)/cpu.c. */ -/* MPC 8xx */ -#if (defined(CONFIG_8xx) || defined(CONFIG_MPC860)) && !defined(__ASSEMBLY__) - void reset_8xx_watchdog(volatile immap_t *immr); -#endif - -/* MPC 5xx */ -#if defined(CONFIG_5xx) && !defined(__ASSEMBLY__) - void reset_5xx_watchdog(volatile immap_t *immr); -#endif - -/* MPC 5xxx */ -#if defined(CONFIG_MPC5xxx) && !defined(__ASSEMBLY__) - void reset_5xxx_watchdog(void); -#endif - /* AMCC 4xx */ #if defined(CONFIG_4xx) && !defined(__ASSEMBLY__) void reset_4xx_watchdog(void); |