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-rw-r--r--include/configs/am335x_sl50.h1
-rw-r--r--include/configs/astro_mcf5373l.h2
-rw-r--r--include/configs/baltos.h1
-rw-r--r--include/configs/bav335x.h1
-rw-r--r--include/configs/ot1200.h1
-rw-r--r--include/configs/socfpga_sr1500.h115
-rw-r--r--include/configs/ti_armv7_keystone2.h1
-rw-r--r--include/configs/xilinx_zynqmp.h8
-rw-r--r--include/configs/xilinx_zynqmp_ep.h2
-rw-r--r--include/fsl_usb.h1
-rw-r--r--include/linux/usb/dwc3.h1
11 files changed, 127 insertions, 7 deletions
diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h
index f655e69f90..1bdb96e34f 100644
--- a/include/configs/am335x_sl50.h
+++ b/include/configs/am335x_sl50.h
@@ -78,7 +78,6 @@
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
/* PMIC support */
#define CONFIG_POWER_TPS65217
diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
index 860615119c..828bc601aa 100644
--- a/include/configs/astro_mcf5373l.h
+++ b/include/configs/astro_mcf5373l.h
@@ -57,7 +57,7 @@
#define ENABLE_JFFS 1
#endif
-/* Define which commmands should be available at u-boot command prompt */
+/* Define which commands should be available at u-boot command prompt */
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
diff --git a/include/configs/baltos.h b/include/configs/baltos.h
index 5545cf0f10..e9b4fe139c 100644
--- a/include/configs/baltos.h
+++ b/include/configs/baltos.h
@@ -213,7 +213,6 @@
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
/* PMIC support */
#define CONFIG_POWER_TPS65910
diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h
index 943ba17002..e61a0988a4 100644
--- a/include/configs/bav335x.h
+++ b/include/configs/bav335x.h
@@ -346,7 +346,6 @@ DEFAULT_LINUX_BOOT_ENV \
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
/* PMIC support */
#define CONFIG_POWER_TPS65217
diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
index 3da454a35b..879ad58fc4 100644
--- a/include/configs/ot1200.h
+++ b/include/configs/ot1200.h
@@ -111,7 +111,6 @@
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#endif
/* Miscellaneous commands */
diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h
new file mode 100644
index 0000000000..bccb235a11
--- /dev/null
+++ b/include/configs/socfpga_sr1500.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIG_SOCFPGA_SR1500_H__
+#define __CONFIG_SOCFPGA_SR1500_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+
+#define CONFIG_HW_WATCHDOG
+
+/* U-Boot Commands */
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_TIME
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE)
+#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
+#define CONFIG_LOADADDR 0x01000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
+
+/* Ethernet on SoC (EMAC) */
+#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
+/* The PHY is autodetected, so no MII PHY address is needed here */
+#define CONFIG_PHY_MARVELL
+#define PHY_ANEG_TIMEOUT 8000
+
+/* Extra Environment */
+#define CONFIG_HOSTNAME sr1500
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=n\0" \
+ "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+ "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "bootimage=zImage\0" \
+ "fdt_addr=100\0" \
+ "fdtimage=socfpga.dtb\0" \
+ "fsloadcmd=ext2load\0" \
+ "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "bootz ${loadaddr} - ${fdt_addr}\0" \
+ "mmcload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootimage};" \
+ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+ "qspiroot=/dev/mtdblock0\0" \
+ "qspirootfstype=jffs2\0" \
+ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+ "bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* Environment */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+
+/* Enable SPI NOR flash reset, needed for SPI booting */
+#define CONFIG_SPI_N25Q256A_RESET
+
+/*
+ * Bootcounter
+ */
+#define CONFIG_BOOTCOUNT_LIMIT
+/* last 2 lwords in OCRAM */
+#define CONFIG_SYS_BOOTCOUNT_ADDR 0xfffffff8
+#define CONFIG_SYS_BOOTCOUNT_BE
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+/* U-Boot payload is stored at offset 0x60000 */
+#undef CONFIG_SYS_SPI_U_BOOT_OFFS
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x60000
+
+/* Environment setting for SPI flash */
+#undef CONFIG_ENV_SIZE
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#define CONFIG_ENV_SIZE (16 * 1024)
+#define CONFIG_ENV_OFFSET 0x00040000
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MODE SPI_MODE_3
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+
+#endif /* __CONFIG_SOCFPGA_SR1500_H__ */
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index de45e71b8e..a7206f4bea 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -158,7 +158,6 @@
#define I2C_BUS_MAX 3
/* EEPROM definitions */
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 6b8b9f83e9..474bbaff05 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -107,6 +107,14 @@
#define CONFIG_SYS_LOAD_ADDR 0x8000000
#if defined(CONFIG_ZYNQMP_USB)
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_XHCI_ZYNQMP
+
#define CONFIG_USB_DWC3
#define CONFIG_USB_DWC3_GADGET
diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h
index 8bdb5c9c6d..b7d506e5e7 100644
--- a/include/configs/xilinx_zynqmp_ep.h
+++ b/include/configs/xilinx_zynqmp_ep.h
@@ -24,6 +24,8 @@
#define CONFIG_SYS_I2C_ZYNQ
#define CONFIG_ZYNQ_EEPROM
#define CONFIG_AHCI
+#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
+ ZYNQMP_USB1_XHCI_BASEADDR}
#include <configs/xilinx_zynqmp.h>
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
index 8e3ddedfad..187e384305 100644
--- a/include/fsl_usb.h
+++ b/include/fsl_usb.h
@@ -181,6 +181,7 @@ static inline bool has_erratum_a007792(void)
switch (soc) {
case SVR_T4240:
case SVR_T4160:
+ case SVR_T4080:
return IS_SVR_REV(svr, 2, 0);
case SVR_T1024:
case SVR_T1023:
diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h
index dd934a0e65..6d1e36505d 100644
--- a/include/linux/usb/dwc3.h
+++ b/include/linux/usb/dwc3.h
@@ -204,7 +204,6 @@ struct dwc3 { /* offset: 0xC100 */
void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode);
void dwc3_core_soft_reset(struct dwc3 *dwc3_reg);
int dwc3_core_init(struct dwc3 *dwc3_reg);
-void usb_phy_reset(struct dwc3 *dwc3_reg);
void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val);
#endif
#endif /* __DWC3_H_ */
generated by cgit (git 2.34.1) at 2024-12-25 19:27:58 +0000