diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-generic/gpio.h | 16 | ||||
| -rw-r--r-- | include/configs/crownbay.h | 2 | ||||
| -rw-r--r-- | include/configs/galileo.h | 3 | ||||
| -rw-r--r-- | include/configs/minnowmax.h | 6 | ||||
| -rw-r--r-- | include/configs/qemu-x86.h | 77 | ||||
| -rw-r--r-- | include/configs/x86-chromebook.h | 1 | ||||
| -rw-r--r-- | include/configs/x86-common.h | 7 | ||||
| -rw-r--r-- | include/dm/uclass-id.h | 8 | ||||
| -rw-r--r-- | include/dt-bindings/gpio/x86-gpio.h | 31 | ||||
| -rw-r--r-- | include/dt-bindings/interrupt-router/intel-irq.h | 31 | ||||
| -rw-r--r-- | include/fdt_support.h | 27 | ||||
| -rw-r--r-- | include/fdtdec.h | 2 | ||||
| -rw-r--r-- | include/os.h | 8 | ||||
| -rw-r--r-- | include/pci_ids.h | 1 |
14 files changed, 193 insertions, 27 deletions
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index 519bb0be27..de91e57efc 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -42,7 +42,7 @@ * Note: With driver model, the label is allocated so there is no need for * the caller to preserve it. * - * @param gp GPIO number + * @param gpio GPIO number * @param label User label for this GPIO * @return 0 if ok, -1 on error */ @@ -127,7 +127,7 @@ struct gpio_desc { }; /** - * dm_gpio_is_valid() - Check if a GPIO is gpio_is_valie + * dm_gpio_is_valid() - Check if a GPIO is valid * * @desc: GPIO description containing device, offset and flags, * previously returned by gpio_request_by_name() @@ -167,7 +167,7 @@ int gpio_get_status(struct udevice *dev, int offset, char *buf, int buffsize); * * @dev: Device to check * @offset: Offset of device GPIO to check - * @namep: If non-NULL, this is set to the nane given when the GPIO + * @namep: If non-NULL, this is set to the name given when the GPIO * was requested, or -1 if it has not been requested * @return -ENODATA if the driver returned an unknown function, * -ENODEV if the device is not active, -EINVAL if the offset is invalid. @@ -186,7 +186,7 @@ int gpio_get_function(struct udevice *dev, int offset, const char **namep); * * @dev: Device to check * @offset: Offset of device GPIO to check - * @namep: If non-NULL, this is set to the nane given when the GPIO + * @namep: If non-NULL, this is set to the name given when the GPIO * was requested, or -1 if it has not been requested * @return -ENODATA if the driver returned an unknown function, * -ENODEV if the device is not active, -EINVAL if the offset is invalid. @@ -219,7 +219,7 @@ struct fdtdec_phandle_args; * Also it would be useful to standardise additional functions like * pullup, slew rate and drive strength. * - * gpio_request)( and gpio_free() are optional - if NULL then they will + * gpio_request() and gpio_free() are optional - if NULL then they will * not be called. * * Note that @offset is the offset from the base GPIO of the device. So @@ -271,7 +271,7 @@ struct dm_gpio_ops { * * @dev: GPIO device * @desc: Place to put GPIO description - * @args: Arguments provided in descripion + * @args: Arguments provided in description * @return 0 if OK, -ve on error */ int (*xlate)(struct udevice *dev, struct gpio_desc *desc, @@ -398,7 +398,7 @@ int gpio_request_by_name(struct udevice *dev, const char *list_name, /** * gpio_request_list_by_name() - Request a list of GPIOs * - * Reads all the GPIOs from a list and requetss them. See + * Reads all the GPIOs from a list and requests them. See * gpio_request_by_name() for additional details. Lists should not be * misused to hold unrelated or optional GPIOs. They should only be used * for things like parallel data lines. A zero phandle terminates the list @@ -533,7 +533,7 @@ int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags); /** * gpio_get_number() - Get the global GPIO number of a GPIO * - * This should only be used for debugging or interest. It returns the nummber + * This should only be used for debugging or interest. It returns the number * that should be used for gpio_get_value() etc. to access this GPIO. * * @desc: GPIO description containing device, offset and flags, diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index 4fef433252..0e1f0467c7 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -17,8 +17,6 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_ARCH_MISC_INIT -#define CONFIG_NR_DRAM_BANKS 1 - #define CONFIG_X86_SERIAL #define CONFIG_SMSC_LPC47M diff --git a/include/configs/galileo.h b/include/configs/galileo.h index f780b8fa51..fd89bf30ef 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -15,8 +15,7 @@ #define CONFIG_SYS_MONITOR_LEN (1 << 20) #define CONFIG_BOARD_EARLY_INIT_F - -#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_ARCH_MISC_INIT #define CONFIG_X86_SERIAL diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 2a1915d872..547765d137 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -15,8 +15,7 @@ #define CONFIG_SYS_MONITOR_LEN (1 << 20) #define CONFIG_BOARD_EARLY_INIT_F - -#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_X86_SERIAL #define CONFIG_SMSC_LPC47M @@ -56,9 +55,6 @@ #define CONFIG_X86_OPTION_ROM_FILE vga.bin #define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 -#ifndef CONFIG_SYS_COREBOOT -#define CONFIG_VIDEO_VESA -#endif #define VIDEO_IO_OFFSET 0 #define CONFIG_X86EMU_RAW_IO #define CONFIG_VGA_AS_SINGLE_DEVICE diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h new file mode 100644 index 0000000000..78c296f5ad --- /dev/null +++ b/include/configs/qemu-x86.h @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/x86-common.h> + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_ARCH_MISC_INIT + +#define CONFIG_X86_SERIAL + +#define CONFIG_PCI_MEM_BUS 0xc0000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_PREF_BUS 0xd0000000 +#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS +#define CONFIG_PCI_PREF_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x2000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0xe000 + +#define CONFIG_PCI_CONFIG_HOST_BRIDGE +#define CONFIG_PCI_PNP +#define CONFIG_E1000 + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga\0" \ + "stdout=serial,vga\0" \ + "stderr=serial,vga\0" + +/* + * ATA/SATA support for QEMU x86 targets + * - Only legacy IDE controller is supported for QEMU '-M pc' target + * - AHCI controller is supported for QEMU '-M q35' target + * + * Default configuraion is to support the QEMU default x86 target + * Undefine CONFIG_CMD_IDE to support q35 target + */ +#define CONFIG_CMD_IDE +#ifdef CONFIG_CMD_IDE +#define CONFIG_SYS_IDE_MAXBUS 2 +#define CONFIG_SYS_IDE_MAXDEVICE 4 +#define CONFIG_SYS_ATA_BASE_ADDR 0 +#define CONFIG_SYS_ATA_DATA_OFFSET 0 +#define CONFIG_SYS_ATA_REG_OFFSET 0 +#define CONFIG_SYS_ATA_ALT_OFFSET 0 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0 +#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 +#define CONFIG_ATAPI + +#undef CONFIG_SCSI_AHCI +#undef CONFIG_CMD_SCSI +#else +#define CONFIG_SCSI_DEV_LIST \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_AHCI} +#endif + +/* GPIO is not supported */ +#undef CONFIG_INTEL_ICH6_GPIO +#undef CONFIG_CMD_GPIO + +/* SPI is not supported */ +#undef CONFIG_ICH_SPI +#undef CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_IS_NOWHERE + +#endif /* __CONFIG_H */ diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index b6a76fe075..e0e7fca9f8 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -14,7 +14,6 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_MISC_INIT_R -#define CONFIG_NR_DRAM_BANKS 8 #define CONFIG_X86_MRC_ADDR 0xfffa0000 #define CONFIG_CACHE_MRC_SIZE_KB 512 diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index bf4758e3b3..1917d87ac5 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -21,6 +21,7 @@ #define CONFIG_DISPLAY_BOARDINFO_LATE #define CONFIG_DISPLAY_CPUINFO #define CONFIG_LAST_STAGE_INIT +#define CONFIG_NR_DRAM_BANKS 8 #define CONFIG_LMB #define CONFIG_OF_LIBFDT @@ -36,6 +37,7 @@ #define CONFIG_SCSI_AHCI #ifdef CONFIG_SCSI_AHCI #define CONFIG_LIBATA +#define CONFIG_LBA48 #define CONFIG_SYS_64BIT_LBA #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 @@ -75,10 +77,6 @@ #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SUPPORT_VFAT -/************************************************************ - * ATAPI support (experimental) - ************************************************************/ -#define CONFIG_ATAPI /************************************************************ * DISK Partition support @@ -246,6 +244,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_STD_DEVICES_SETTINGS \ + "pciconfighost=1\0" \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ "othbootargs=acpi=off\0" \ diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 4d737f46c5..c7310d7ca0 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -39,20 +39,18 @@ enum uclass_id { UCLASS_PCH, /* x86 platform controller hub */ UCLASS_PCI, /* PCI bus */ UCLASS_PCI_GENERIC, /* Generic PCI bus device */ + UCLASS_PMIC, /* PMIC I/O device */ + UCLASS_REGULATOR, /* Regulator device */ UCLASS_RTC, /* Real time clock device */ UCLASS_SERIAL, /* Serial UART */ UCLASS_SPI, /* SPI bus */ - UCLASS_SPI_GENERIC, /* Generic SPI flash target */ UCLASS_SPI_FLASH, /* SPI flash */ + UCLASS_SPI_GENERIC, /* Generic SPI flash target */ UCLASS_THERMAL, /* Thermal sensor */ UCLASS_USB, /* USB bus */ UCLASS_USB_DEV_GENERIC, /* USB generic device */ UCLASS_USB_HUB, /* USB hub */ - /* Power Management */ - UCLASS_PMIC, /* PMIC I/O device */ - UCLASS_REGULATOR, /* REGULATOR device */ - UCLASS_COUNT, UCLASS_INVALID = -1, }; diff --git a/include/dt-bindings/gpio/x86-gpio.h b/include/dt-bindings/gpio/x86-gpio.h new file mode 100644 index 0000000000..7f1de30c0b --- /dev/null +++ b/include/dt-bindings/gpio/x86-gpio.h @@ -0,0 +1,31 @@ +/* + * This header provides constants for binding intel,x86-pinctrl. + */ + +#ifndef _DT_BINDINGS_GPIO_X86_GPIO_H +#define _DT_BINDINGS_GPIO_X86_GPIO_H + +#include <dt-bindings/gpio/gpio.h> + +#define GPIO_MODE_NATIVE 0 +#define GPIO_MODE_GPIO 1 + +#define GPIO_MODE_FUNC0 0 +#define GPIO_MODE_FUNC1 1 +#define GPIO_MODE_FUNC2 2 +#define GPIO_MODE_FUNC3 3 +#define GPIO_MODE_FUNC4 4 +#define GPIO_MODE_FUNC5 5 +#define GPIO_MODE_FUNC6 6 + +#define PIN_INPUT 0 +#define PIN_OUTPUT 1 + +#define PIN_INPUT_NOPULL 0 +#define PIN_INPUT_PULLUP 1 +#define PIN_INPUT_PULLDOWN 2 + +#define PULL_STR_2K 0 +#define PULL_STR_20K 2 + +#endif diff --git a/include/dt-bindings/interrupt-router/intel-irq.h b/include/dt-bindings/interrupt-router/intel-irq.h new file mode 100644 index 0000000000..5092f33dfa --- /dev/null +++ b/include/dt-bindings/interrupt-router/intel-irq.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_INTEL_IRQ_H_ +#define _DT_BINDINGS_INTEL_IRQ_H_ + +/* PCI interrupt pin */ +#define INTA 1 +#define INTB 2 +#define INTC 3 +#define INTD 4 + +/* PIRQs */ +#define PIRQA 0 +#define PIRQB 1 +#define PIRQC 2 +#define PIRQD 3 +#define PIRQE 4 +#define PIRQF 5 +#define PIRQG 6 +#define PIRQH 7 + +/* PCI bdf encoding */ +#ifndef PCI_BDF +#define PCI_BDF(b, d, f) ((b) << 16 | (d) << 11 | (f) << 8) +#endif + +#endif /* _DT_BINDINGS_INTEL_IRQ_H_ */ diff --git a/include/fdt_support.h b/include/fdt_support.h index 5d4f28dc78..0edc4fa5b1 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -16,8 +16,35 @@ u32 fdt_getprop_u32_default_node(const void *fdt, int off, int cell, const char *prop, const u32 dflt); u32 fdt_getprop_u32_default(const void *fdt, const char *path, const char *prop, const u32 dflt); + +/** + * Add data to the root of the FDT before booting the OS. + * + * See doc/device-tree-bindings/root.txt + * + * @param fdt FDT address in memory + * @return 0 if ok, or -FDT_ERR_... on error + */ +int fdt_root(void *fdt); + +/** + * Add chosen data the FDT before booting the OS. + * + * In particular, this adds the kernel command line (bootargs) to the FDT. + * + * @param fdt FDT address in memory + * @return 0 if ok, or -FDT_ERR_... on error + */ int fdt_chosen(void *fdt); + +/** + * Add initrd information to the FDT before booting the OS. + * + * @param fdt FDT address in memory + * @return 0 if ok, or -FDT_ERR_... on error + */ int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end); + void do_fixup_by_path(void *fdt, const char *path, const char *prop, const void *val, int len, int create); void do_fixup_by_path_u32(void *fdt, const char *path, const char *prop, diff --git a/include/fdtdec.h b/include/fdtdec.h index 6bf5f614e8..4fb8a2a1ba 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -176,8 +176,10 @@ enum fdt_compat_id { COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */ COMPAT_INTEL_ICH_SPI, /* Intel ICH7/9 SPI controller */ COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */ + COMPAT_INTEL_X86_PINCTRL, /* Intel ICH7/9 pin control */ COMPAT_SOCIONEXT_XHCI, /* Socionext UniPhier xHCI */ COMPAT_INTEL_PCH, /* Intel PCH */ + COMPAT_INTEL_IRQ_ROUTER, /* Intel Interrupt Router */ COMPAT_COUNT, }; diff --git a/include/os.h b/include/os.h index ffbdce8464..954a48c991 100644 --- a/include/os.h +++ b/include/os.h @@ -112,6 +112,14 @@ void os_exit(int exit_code) __attribute__((noreturn)); void os_tty_raw(int fd, bool allow_sigs); /** + * Restore the tty to its original mode + * + * Call this to restore the original terminal mode, after it has been changed + * by os_tty_raw(). This is an internal function. + */ +void os_fd_restore(void); + +/** * Acquires some memory from the underlying os. * * \param length Number of bytes to be allocated diff --git a/include/pci_ids.h b/include/pci_ids.h index 2e6685112b..5771e12e72 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -2838,6 +2838,7 @@ #define PCI_DEVICE_ID_INTEL_ICH9_6 0x2930 #define PCI_DEVICE_ID_INTEL_ICH9_7 0x2916 #define PCI_DEVICE_ID_INTEL_ICH9_8 0x2918 +#define PCI_DEVICE_ID_INTEL_ICH9_AHCI 0x2922 #define PCI_DEVICE_ID_INTEL_I7_MCR 0x2c18 #define PCI_DEVICE_ID_INTEL_I7_MC_TAD 0x2c19 #define PCI_DEVICE_ID_INTEL_I7_MC_RAS 0x2c1a |