diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-ppc/global_data.h | 3 | ||||
| -rw-r--r-- | include/configs/DU440.h | 16 | ||||
| -rw-r--r-- | include/configs/MPC8315ERDB.h | 23 | ||||
| -rw-r--r-- | include/configs/MPC8323ERDB.h | 12 | ||||
| -rw-r--r-- | include/configs/MPC837XEMDS.h | 28 | ||||
| -rw-r--r-- | include/configs/MPC837XERDB.h | 23 | ||||
| -rw-r--r-- | include/configs/alpr.h | 14 | ||||
| -rw-r--r-- | include/configs/canyonlands.h | 126 | ||||
| -rw-r--r-- | include/configs/korat.h | 67 | ||||
| -rw-r--r-- | include/configs/lwmon5.h | 8 | ||||
| -rw-r--r-- | include/configs/sequoia.h | 4 | ||||
| -rw-r--r-- | include/mpc83xx.h | 95 | ||||
| -rw-r--r-- | include/ppc440.h | 4 | ||||
| -rw-r--r-- | include/ppc4xx_enet.h | 4 |
14 files changed, 307 insertions, 120 deletions
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index b43dba3352..9ccf7d6017 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -74,7 +74,6 @@ typedef struct global_data { u32 enc_clk; u32 lbiu_clk; u32 lclk_clk; - u32 ddr_clk; u32 pci_clk; #if defined(CONFIG_MPC837X) u32 pciexp1_clk; @@ -84,7 +83,7 @@ typedef struct global_data { u32 sata_clk; #endif #if defined(CONFIG_MPC8360) - u32 ddr_sec_clk; + u32 mem_sec_clk; #endif /* CONFIG_MPC8360 */ #endif #if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) diff --git a/include/configs/DU440.h b/include/configs/DU440.h index 4fb6921ead..d54da9717b 100644 --- a/include/configs/DU440.h +++ b/include/configs/DU440.h @@ -157,10 +157,9 @@ */ #define CFG_MBYTES_SDRAM (1024) /* 512 MiB TODO: remove */ #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ +#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ + /* 440EPx errata CHIP 11 */ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ -#if 0 -#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */ -#endif #define CONFIG_DDR_ECC /* Use ECC when available */ #define SPD_EEPROM_ADDRESS {0x50} #define CONFIG_PROG_SDRAM_TLB @@ -244,9 +243,6 @@ "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ "cp.b 100000 FFFA0000 60000\0" \ "" -#if 0 -#define CONFIG_BOOTCOMMAND "run flash_self" -#endif #define CONFIG_PREBOOT /* enable preboot variable */ @@ -264,7 +260,7 @@ int du440_phy_addr(int devnum); #define CONFIG_PHY_ADDR du440_phy_addr(0) /* PHY address */ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_PHY_GIGE 1 /* Include GbE detection */ +#undef CONFIG_PHY_GIGE /* no GbE detection */ #define CONFIG_HAS_ETH0 #define CFG_RX_ETH_BUFFER 128 @@ -295,7 +291,9 @@ int du440_phy_addr(int devnum); #include <config_cmd_default.h> +#define CONFIG_CMD_AUTOSCRIPT #define CONFIG_CMD_BSP +#define CONFIG_CMD_BMP #define CONFIG_CMD_DATE #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DHCP @@ -431,8 +429,6 @@ int du440_phy_addr(int devnum); #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif -#if 0 -#define CONFIG_SHOW_ACTIVITY 1 -#endif +#define CONFIG_AUTOSCRIPT 1 #endif /* __CONFIG_H */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index af7872628e..432fb311de 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -349,6 +349,29 @@ #define CONFIG_ETHPRIME "eTSEC1" /* + * SATA + */ +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CFG_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CFG_SATA1_OFFSET 0x18000 +#define CFG_SATA1 (CFG_IMMR + CFG_SATA1_OFFSET) +#define CFG_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CFG_SATA2_OFFSET 0x19000 +#define CFG_SATA2 (CFG_IMMR + CFG_SATA2_OFFSET) +#define CFG_SATA2_FLAGS FLAGS_DMA + +#ifdef CONFIG_FSL_SATA +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +/* * Environment */ #ifndef CFG_RAMBOOT diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 94c4c6b040..92d7aa42b4 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -323,8 +323,11 @@ /* * Config on-board EEPROM */ -#define CFG_I2C_EEPROM_ADDR 0x50 -#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_EEPROM_PAGE_WRITE_BITS 6 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CFG_EEPROM_PAGE_WRITE_ENABLE /* * General PCI @@ -341,7 +344,7 @@ #define CFG_PCI1_IO_SIZE 0x04000000 /* 64M */ #ifdef CONFIG_PCI - +#define CONFIG_PCI_SKIP_HOST_BRIDGE #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ @@ -549,6 +552,9 @@ #define CONFIG_HAS_ETH1 /* add support for "eth1addr" */ #define CONFIG_ETH1ADDR 00:04:9f:ef:03:02 +/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM (see CFG_I2C_EEPROM) */ +#define CFG_I2C_MAC_OFFSET 0x7f00 /* MAC address offset in I2C EEPROM */ + #define CONFIG_IPADDR 10.0.0.2 #define CONFIG_SERVERIP 10.0.0.1 #define CONFIG_GATEWAYIP 10.0.0.1 diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index b307bf71ef..7c4e76e273 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -389,6 +389,34 @@ /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "eTSEC1" +/* SERDES */ +#define CONFIG_FSL_SERDES +#define CONFIG_FSL_SERDES1 0xe3000 +#define CONFIG_FSL_SERDES2 0xe3100 + +/* + * SATA + */ +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CFG_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CFG_SATA1_OFFSET 0x18000 +#define CFG_SATA1 (CFG_IMMR + CFG_SATA1_OFFSET) +#define CFG_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CFG_SATA2_OFFSET 0x19000 +#define CFG_SATA2 (CFG_IMMR + CFG_SATA2_OFFSET) +#define CFG_SATA2_FLAGS FLAGS_DMA + +#ifdef CONFIG_FSL_SATA +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + /* * Environment */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 90812e92a9..eaac525a35 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -416,6 +416,29 @@ #endif /* + * SATA + */ +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CFG_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CFG_SATA1_OFFSET 0x18000 +#define CFG_SATA1 (CFG_IMMR + CFG_SATA1_OFFSET) +#define CFG_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CFG_SATA2_OFFSET 0x19000 +#define CFG_SATA2 (CFG_IMMR + CFG_SATA2_OFFSET) +#define CFG_SATA2_FLAGS FLAGS_DMA + +#ifdef CONFIG_FSL_SATA +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +/* * Environment */ #ifndef CFG_RAMBOOT diff --git a/include/configs/alpr.h b/include/configs/alpr.h index 38fb7c6c78..3e906c4251 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006-2007 + * (C) Copyright 2006-2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * See file CREDITS for list of people who contributed to this @@ -35,6 +35,7 @@ #define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */ #undef CFG_DRAM_TEST /* Disable-takes long time! */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ +#define CONFIG_4xx_DCACHE /* Enable i- and d-cache */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the @@ -144,6 +145,8 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth3\0" \ "hostname=alpr\0" \ + "fdt_file=alpr/alpr.dtb\0" \ + "fdt_addr=400000\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath} ${init}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ @@ -158,6 +161,10 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ + "net_nfs_fdt=tftp 200000 ${bootfile};" \ + "tftp ${fdt_addr} ${fdt_file};" \ + "run nfsargs addip addtty;" \ + "bootm 200000 - ${fdt_addr}\0" \ "rootpath=/opt/projects/alpr/nfs_root\0" \ "bootfile=/alpr/uImage\0" \ "kernel_addr=fff00000\0" \ @@ -370,4 +377,9 @@ #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index a4bcc655ee..a1c6674b1a 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -27,16 +27,21 @@ /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ -#define CONFIG_CANYONLANDS 1 /* Board is Canyonlands */ +/* This config file is used for Canyonlands (460EX) and Glacier (460GT) */ +#ifndef CONFIG_CANYONLANDS +#define CONFIG_460GT 1 /* Specific PPC460GT */ +#else +#define CONFIG_460EX 1 /* Specific PPC460EX */ +#endif #define CONFIG_440 1 #define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_460EX 1 /* Specific PPC460EX support */ #define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +#define CONFIG_BOARD_TYPES 1 /* support board types */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the @@ -262,8 +267,15 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ #define CONFIG_PHY1_ADDR 1 -#define CONFIG_HAS_ETH0 1 -#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +/* Only Glacier (460GT) has 4 EMAC interfaces */ +#ifdef CONFIG_460GT +#define CONFIG_PHY2_ADDR 2 +#define CONFIG_PHY3_ADDR 3 +#define CONFIG_HAS_ETH2 +#define CONFIG_HAS_ETH3 +#endif #define CONFIG_NET_MULTI 1 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ @@ -275,6 +287,8 @@ /*----------------------------------------------------------------------- * USB-OHCI *----------------------------------------------------------------------*/ +/* Only Canyonlands (460EX) has USB */ +#ifdef CONFIG_460EX #define CONFIG_USB_OHCI_NEW #define CONFIG_USB_STORAGE #undef CFG_OHCI_BE_CONTROLLER /* 460EX has little endian descriptors */ @@ -283,6 +297,7 @@ #define CFG_USB_OHCI_REGS_BASE (CFG_AHB_BASE | 0xd0000) #define CFG_USB_OHCI_SLOT_NAME "ppc440" #define CFG_USB_OHCI_MAX_ROOT_PORTS 15 +#endif /*----------------------------------------------------------------------- * Default environment @@ -293,9 +308,21 @@ #undef CONFIG_BOOTARGS +/* Setup some board specific values for the default environment variables */ +#ifdef CONFIG_CANYONLANDS +#define CONFIG_HOSTNAME canyonlands +#define CFG_BOOTFILE "bootfile=canyonlands/uImage\0" +#define CFG_DTBFILE "fdt_file=canyonlands/canyonlands.dtb\0" +#else +#define CONFIG_HOSTNAME glacier +#define CFG_BOOTFILE "bootfile=glacier/uImage\0" +#define CFG_DTBFILE "fdt_file=glacier/glacier.dtb\0" +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ + CFG_BOOTFILE \ + CFG_DTBFILE \ "netdev=eth0\0" \ - "hostname=canyonlands\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ @@ -315,18 +342,16 @@ "flash_self=run ramargs addip addtty;" \ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "rootpath=/opt/eldk/ppc_4xxFP\0" \ - "bootfile=canyonlands/uImage\0" \ - "fdt_file=canyonlands/canyonlands.dtb\0" \ "fdt_addr=400000\0" \ "kernel_addr=fc000000\0" \ "ramdisk_addr=fc200000\0" \ "initrd_high=30000000\0" \ - "load=tftp 200000 canyonlands/u-boot.bin\0" \ + "load=tftp 200000 ${hostname}/u-boot.bin\0" \ "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \ "cp.b ${fileaddr} fffa0000 ${filesize};" \ "setenv filesize;saveenv\0" \ "upd=run load update\0" \ - "nload=tftp 200000 canyonlands/u-boot-nand.bin\0" \ + "nload=tftp 200000 ${hostname}/u-boot-nand.bin\0" \ "nupdate=nand erase 0 60000;nand write 200000 0 60000;" \ "setenv filesize;saveenv\0" \ "nupd=run nload nupdate\0" \ @@ -361,8 +386,6 @@ #define CONFIG_CMD_DIAG #define CONFIG_CMD_EEPROM #define CONFIG_CMD_ELF -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT #define CONFIG_CMD_I2C #define CONFIG_CMD_IRQ #define CONFIG_CMD_MII @@ -373,7 +396,11 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM +#ifdef CONFIG_460EX +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT #define CONFIG_CMD_USB +#endif /* Partitions */ #define CONFIG_MAC_PARTITION @@ -487,6 +514,8 @@ /* * PPC4xx GPIO Configuration */ +#ifdef CONFIG_460EX +/* 460EX: Use USB configuration */ #define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ { \ /* GPIO Core 0 */ \ @@ -559,6 +588,81 @@ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \ } \ } +#else +/* 460GT: Use EMAC2+3 configuration */ +#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ +{ \ +/* GPIO Core 0 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \ +}, \ +{ \ +/* GPIO Core 1 */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \ +{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \ +} \ +} +#endif /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 diff --git a/include/configs/korat.h b/include/configs/korat.h index dcec9b039d..48d73ac376 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -45,10 +45,10 @@ * Manufacturer's information serial EEPROM parameters */ #define MAN_DATA_EEPROM_ADDR 0x53 /* EEPROM I2C address */ -#define MAN_SERIAL_NO_FIELD 2 -#define MAN_SERIAL_NO_LENGTH 13 +#define MAN_INFO_FIELD 2 +#define MAN_INFO_LENGTH 9 #define MAN_MAC_ADDR_FIELD 3 -#define MAN_MAC_ADDR_LENGTH 17 +#define MAN_MAC_ADDR_LENGTH 12 /* * Base addresses -- Note these are effective addresses where the actual @@ -57,17 +57,18 @@ #define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kiB for Monitor */ #define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kiB for malloc() */ -#define CFG_BOOT_BASE_ADDR 0xf0000000 #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ +#define CFG_FLASH0_SIZE 0x01000000 +#define CFG_FLASH0_ADDR (-CFG_FLASH0_SIZE) +#define CFG_FLASH1_TOP 0xF8000000 +#define CFG_FLASH1_MAX_SIZE 0x08000000 +#define CFG_FLASH1_ADDR (CFG_FLASH1_TOP - CFG_FLASH1_MAX_SIZE) +#define CFG_FLASH_BASE CFG_FLASH1_ADDR /* start of FLASH */ #define CFG_MONITOR_BASE TEXT_BASE #define CFG_OCM_BASE 0xe0010000 /* ocm */ #define CFG_OCM_DATA_ADDR CFG_OCM_BASE #define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */ #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 -#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 -#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 /* Don't change either of these */ #define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ @@ -108,13 +109,14 @@ /* * FLASH related */ -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_FLASH_CFI_LEGACY /* Allow hard-coded config for FLASH0 */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_BANKS_LIST { CFG_FLASH1_ADDR, CFG_FLASH0_ADDR } -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 1024 /* max number of sectors on one chip */ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ @@ -126,12 +128,12 @@ #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ #define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ -#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) +#define CFG_ENV_ADDR (CFG_FLASH1_TOP - CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ -/* Address and size of Redundant Environment Sector */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE /* * DDR SDRAM @@ -144,6 +146,8 @@ #define SPD_EEPROM_ADDRESS {0x50} #define CONFIG_PROG_SDRAM_TLB #define CFG_DRAM_TEST +#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ + /* 440EPx errata CHIP 11 */ /* * I2C @@ -180,6 +184,7 @@ #define CFG_BOOTFILE "bootfile=/tftpboot/korat/uImage\0" #define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0" +/* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */ #define CONFIG_EXTRA_ENV_SETTINGS \ CFG_BOOTFILE \ CFG_ROOTPATH \ @@ -197,8 +202,8 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ - "kernel_addr=FC000000\0" \ - "ramdisk_addr=FC180000\0" \ + "kernel_addr=F4000000\0" \ + "ramdisk_addr=F4400000\0" \ "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \ "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ "cp.b 200000 FFFA0000 60000\0" \ @@ -216,7 +221,7 @@ #define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */ #define CONFIG_PHY_DYNAMIC_ANEG 1 -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#undef CONFIG_PHY_RESET /* Don't do software PHY reset */ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ #define CONFIG_HAS_ETH0 @@ -322,6 +327,11 @@ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ /* + * Korat-specific options + */ +#define CFG_KORAT_MAN_RESET_MS 10000 /* timeout for manufacturer reset */ + +/* * PCI stuff */ /* General PCI */ @@ -350,12 +360,23 @@ */ /* Memory Bank 0 (NOR-FLASH) initialization */ +#if CFG_FLASH0_SIZE == 0x01000000 +#define CFG_EBC_PB0AP 0x04017300 +#define CFG_EBC_PB0CR (CFG_FLASH0_ADDR | 0x0009A000) +#elif CFG_FLASH0_SIZE == 0x04000000 #define CFG_EBC_PB0AP 0x04017300 -#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0x000DA000) +#define CFG_EBC_PB0CR (CFG_FLASH0_ADDR | 0x000DA000) +#else +#error Unable to configure chip select for current CFG_FLASH0_SIZE +#endif /* Memory Bank 1 (NOR-FLASH) initialization */ +#if CFG_FLASH1_MAX_SIZE == 0x08000000 #define CFG_EBC_PB1AP 0x04017300 -#define CFG_EBC_PB1CR (0xF8000000 | 0x000DA000) +#define CFG_EBC_PB1CR (CFG_FLASH1_ADDR | 0x000FA000) +#else +#error Unable to configure chip select for current CFG_FLASH1_MAX_SIZE +#endif /* Memory Bank 2 (CPLD) initialization */ #define CFG_EBC_PB2AP 0x04017300 @@ -426,6 +447,7 @@ * GPIO63 xxxx x x (reserved for trace port) */ +#define CFG_GPIO_ATMEGA_RESET_ 12 #define CFG_GPIO_ATMEGA_SS_ 13 #define CFG_GPIO_PHY0_FIBER_SEL 27 #define CFG_GPIO_PHY1_FIBER_SEL 28 @@ -435,6 +457,7 @@ #define CFG_GPIO_SFP1_TX_EN_ 33 #define CFG_GPIO_PHY0_EN 45 #define CFG_GPIO_PHY1_EN 46 +#define CFG_GPIO_RESET_PRESSED_ 47 /* * PPC440 GPIO Configuration diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index ced7ba6f05..4398b87ae1 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * This program is free software; you can redistribute it and/or @@ -86,6 +86,8 @@ #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET #define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6) /* unused GPT0 COMP reg */ +#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ + /* 440EPx errata CHIP 11 */ /* Additional registers for watchdog timer post test */ @@ -149,12 +151,8 @@ #define CFG_MBYTES_SDRAM (256) /* 256MB */ #define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */ #define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */ -#if 0 /* test-only: disable ECC for now */ #define CONFIG_DDR_ECC 1 /* enable ECC */ #define CFG_POST_ECC_ON CFG_POST_ECC -#else -#define CFG_POST_ECC_ON 0 -#endif /* POST support */ #define CONFIG_POST (CFG_POST_CACHE | \ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index dfa8779bcc..555316ff63 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -221,6 +221,8 @@ #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ #endif +#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ + /* 440EPx errata CHIP 11 */ /* * I2C @@ -275,7 +277,7 @@ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "addmisc=setenv bootargs ${bootargs} mem=${mem}\0" \ + "addmisc=setenv bootargs ${bootargs}\0" \ "flash_nfs=run nfsargs addip addtty addmisc;" \ "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip addtty addmisc;" \ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 4ee38aafa9..d2e1e2bb6c 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -48,71 +48,36 @@ /* SPRIDR - System Part and Revision ID Register */ -#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */ -#define SPRIDR_REVID 0x0000FFFF /* Revision Identification */ - -#define SPR_8349E_REV10 0x80300100 -#define SPR_8349_REV10 0x80310100 -#define SPR_8347E_REV10_TBGA 0x80320100 -#define SPR_8347_REV10_TBGA 0x80330100 -#define SPR_8347E_REV10_PBGA 0x80340100 -#define SPR_8347_REV10_PBGA 0x80350100 -#define SPR_8343E_REV10 0x80360100 -#define SPR_8343_REV10 0x80370100 - -#define SPR_8349E_REV11 0x80300101 -#define SPR_8349_REV11 0x80310101 -#define SPR_8347E_REV11_TBGA 0x80320101 -#define SPR_8347_REV11_TBGA 0x80330101 -#define SPR_8347E_REV11_PBGA 0x80340101 -#define SPR_8347_REV11_PBGA 0x80350101 -#define SPR_8343E_REV11 0x80360101 -#define SPR_8343_REV11 0x80370101 - -#define SPR_8349E_REV31 0x80300300 -#define SPR_8349_REV31 0x80310300 -#define SPR_8347E_REV31_TBGA 0x80320300 -#define SPR_8347_REV31_TBGA 0x80330300 -#define SPR_8347E_REV31_PBGA 0x80340300 -#define SPR_8347_REV31_PBGA 0x80350300 -#define SPR_8343E_REV31 0x80360300 -#define SPR_8343_REV31 0x80370300 - -#define SPR_8360E_REV10 0x80480010 -#define SPR_8360_REV10 0x80490010 -#define SPR_8360E_REV11 0x80480011 -#define SPR_8360_REV11 0x80490011 -#define SPR_8360E_REV12 0x80480012 -#define SPR_8360_REV12 0x80490012 -#define SPR_8360E_REV20 0x80480020 -#define SPR_8360_REV20 0x80490020 -#define SPR_8360E_REV21 0x80480021 -#define SPR_8360_REV21 0x80490021 - -#define SPR_8323E_REV10 0x80620010 -#define SPR_8323_REV10 0x80630010 -#define SPR_8321E_REV10 0x80660010 -#define SPR_8321_REV10 0x80670010 -#define SPR_8323E_REV11 0x80620011 -#define SPR_8323_REV11 0x80630011 -#define SPR_8321E_REV11 0x80660011 -#define SPR_8321_REV11 0x80670011 - -#define SPR_8313E_REV10 0x80B00010 -#define SPR_8313_REV10 0x80B10010 -#define SPR_8311E_REV10 0x80B20010 -#define SPR_8311_REV10 0x80B30010 -#define SPR_8315E_REV10 0x80B40010 -#define SPR_8315_REV10 0x80B50010 -#define SPR_8314E_REV10 0x80B60010 -#define SPR_8314_REV10 0x80B70010 - -#define SPR_8379E_REV10 0x80C20010 -#define SPR_8379_REV10 0x80C30010 -#define SPR_8378E_REV10 0x80C40010 -#define SPR_8378_REV10 0x80C50010 -#define SPR_8377E_REV10 0x80C60010 -#define SPR_8377_REV10 0x80C70010 +#define SPRIDR_PARTID 0xFFFF0000 /* Part Id */ +#define SPRIDR_REVID 0x0000FFFF /* Revision Id */ + +#if defined(CONFIG_MPC834X) +#define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8) +#define REVID_MINOR(spridr) (spridr & 0x000000FF) +#else +#define REVID_MAJOR(spridr) ((spridr & 0x000000F0) >> 4) +#define REVID_MINOR(spridr) (spridr & 0x0000000F) +#endif + +#define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16) +#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000)) /* has SEC */ + +#define SPR_8311 0x80B2 +#define SPR_8313 0x80B0 +#define SPR_8314 0x80B6 +#define SPR_8315 0x80B4 +#define SPR_8321 0x8066 +#define SPR_8323 0x8062 +#define SPR_8343 0x8036 +#define SPR_8347_TBGA_ 0x8032 +#define SPR_8347_PBGA_ 0x8034 +#define SPR_8349 0x8030 +#define SPR_8358_TBGA_ 0x804A +#define SPR_8358_PBGA_ 0x804E +#define SPR_8360 0x8048 +#define SPR_8377 0x80C6 +#define SPR_8378 0x80C4 +#define SPR_8379 0x80C2 /* SPCR - System Priority Configuration Register */ diff --git a/include/ppc440.h b/include/ppc440.h index 10517cbb65..642d1ded76 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -2023,9 +2023,13 @@ #define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */ #define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */ #define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table pointer reg */ +#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table pointer reg */ +#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table pointer reg */ #define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */ #define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */ #define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */ +#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */ +#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */ #endif /* CONFIG_440GX */ diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h index 02084546b2..89ff26f991 100644 --- a/include/ppc4xx_enet.h +++ b/include/ppc4xx_enet.h @@ -213,6 +213,10 @@ typedef struct emac_4xx_hw_st { #define RGMII_FER (RGMII_BASE + 0x00) #define RGMII_SSR (RGMII_BASE + 0x04) +#if defined(CONFIG_460GT) +#define RGMII1_BASE_OFFSET 0x100 +#endif + /* RGMII Function Enable (FER) Register Bit Definitions */ /* Note: for EMAC 2 and 3 only, 440GX only */ #define RGMII_FER_DIS (0x00) |