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-rw-r--r--include/asm-generic/u-boot.h9
-rw-r--r--include/common.h2
-rw-r--r--include/configs/M54451EVB.h2
-rw-r--r--include/configs/M54455EVB.h2
-rw-r--r--include/configs/M5475EVB.h4
-rw-r--r--include/configs/M5485EVB.h4
-rw-r--r--include/configs/T104xRDB.h1
-rw-r--r--include/configs/amcore.h140
-rw-r--r--include/configs/bav335x.h633
-rw-r--r--include/configs/bur_am335x_common.h33
-rw-r--r--include/configs/kwb.h99
-rw-r--r--include/configs/omap3_cairo.h286
-rw-r--r--include/configs/spear-common.h2
-rw-r--r--include/configs/tseries.h123
-rw-r--r--include/configs/vexpress_aemv8a.h46
-rw-r--r--include/configs/x600.h1
-rw-r--r--include/e500.h11
-rw-r--r--include/fsl_sec_mon.h58
-rw-r--r--include/fsl_secboot_err.h128
-rw-r--r--include/fsl_sfp.h85
-rw-r--r--include/fsl_validate.h199
-rw-r--r--include/linux/linkage.h13
-rw-r--r--include/power/tps65217.h1
-rw-r--r--include/stdio_dev.h2
24 files changed, 1785 insertions, 99 deletions
diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h
index a63a87a287..c918049386 100644
--- a/include/asm-generic/u-boot.h
+++ b/include/asm-generic/u-boot.h
@@ -45,7 +45,7 @@ typedef struct bd_info {
|| defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
unsigned long bi_immr_base; /* base of IMMR register */
#endif
-#if defined(CONFIG_MPC5xxx)
+#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K)
unsigned long bi_mbar_base; /* base of internal registers */
#endif
#if defined(CONFIG_MPC83xx)
@@ -66,10 +66,15 @@ typedef struct bd_info {
#if defined(CONFIG_MPC512X)
unsigned long bi_ipsfreq; /* IPS Bus Freq, in MHz */
#endif /* CONFIG_MPC512X */
-#if defined(CONFIG_MPC5xxx)
+#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K)
unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */
unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */
#endif
+#if defined(CONFIG_EXTRA_CLOCK)
+ unsigned long bi_inpfreq; /* input Freq in MHz */
+ unsigned long bi_vcofreq; /* vco Freq in MHz */
+ unsigned long bi_flbfreq; /* Flexbus Freq in MHz */
+#endif
#if defined(CONFIG_405) || \
defined(CONFIG_405GP) || \
defined(CONFIG_405EP) || \
diff --git a/include/common.h b/include/common.h
index 77c55c6f26..6df05b8bb1 100644
--- a/include/common.h
+++ b/include/common.h
@@ -553,7 +553,9 @@ static inline int cpumask_next(int cpu, unsigned int mask)
iter++, cpu = cpumask_next(cpu, mask)) \
int cpu_numcores (void);
+int cpu_num_dspcores(void);
u32 cpu_mask (void);
+u32 cpu_dsp_mask(void);
int is_core_valid (unsigned int);
int probecpu (void);
int checkcpu (void);
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
index 0f4b726f3a..734a77fb4f 100644
--- a/include/configs/M54451EVB.h
+++ b/include/configs/M54451EVB.h
@@ -22,6 +22,8 @@
#define CONFIG_M54451 /* define processor type */
#define CONFIG_M54451EVB /* M54451EVB board */
+#define CONFIG_DISPLAY_BOARDINFO
+
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 7a55d3c619..2faf58156d 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -22,6 +22,8 @@
#define CONFIG_M54455 /* define processor type */
#define CONFIG_M54455EVB /* M54455EVB board */
+#define CONFIG_DISPLAY_BOARDINFO
+
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h
index e88a6bd8d3..2f4549f270 100644
--- a/include/configs/M5475EVB.h
+++ b/include/configs/M5475EVB.h
@@ -22,11 +22,13 @@
#define CONFIG_M547x /* define processor type */
#define CONFIG_M5475 /* define processor type */
+#define CONFIG_DISPLAY_BOARDINFO
+
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
-#define CONFIG_HW_WATCHDOG
+#undef CONFIG_HW_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
/* Command line configuration */
diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
index e4128062a9..9aa02f7c6c 100644
--- a/include/configs/M5485EVB.h
+++ b/include/configs/M5485EVB.h
@@ -22,11 +22,13 @@
#define CONFIG_M548x /* define processor type */
#define CONFIG_M5485 /* define processor type */
+#define CONFIG_DISPLAY_BOARDINFO
+
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
-#define CONFIG_HW_WATCHDOG
+#undef CONFIG_HW_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
/* Command line configuration */
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index d47f1be685..52633181ad 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -220,7 +220,6 @@
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
-#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_SYS_FSL_DDR3
#define CONFIG_SYS_SPD_BUS_NUM 0
diff --git a/include/configs/amcore.h b/include/configs/amcore.h
new file mode 100644
index 0000000000..2a785b3fc3
--- /dev/null
+++ b/include/configs/amcore.h
@@ -0,0 +1,140 @@
+/*
+ * Sysam AMCORE board configuration
+ *
+ * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __AMCORE_CONFIG_H
+#define __AMCORE_CONFIG_H
+
+#define CONFIG_AMCORE
+#define CONFIG_HOSTNAME AMCORE
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+#define CONFIG_MCF530x
+#define CONFIG_M5307
+
+#define CONFIG_MCFTMR
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT 0
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_BOOTCOMMAND "bootm ffc20000"
+
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_AES
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_XIMG
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_TIMER
+#define CONFIG_CMD_DIAG
+
+#define CONFIG_SYS_PROMPT "amcore $ "
+/* undef to save memory */
+#undef CONFIG_SYS_LONGHELP
+
+#if defined(CONFIG_CMD_KGDB)
+/* Console I/O buff. size */
+#define CONFIG_SYS_CBSIZE 1024
+#else
+#define CONFIG_SYS_CBSIZE 256
+#endif
+/* Print buffer size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT)+16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+/* Boot argument buffer size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* no console @ startup */
+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
+#define CONFIG_LOOPW 1 /* enable loopw command */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+
+#define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */
+
+#define CONFIG_SYS_MEMTEST_START 0x0
+#define CONFIG_SYS_MEMTEST_END 0x1000000
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_SYS_CLK 45000000
+#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2)
+/* Register Base Addrs */
+#define CONFIG_SYS_MBAR 0x10000000
+/* Definitions for initial stack pointer and data area (in DPRAM) */
+#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
+/* size of internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_SIZE 0x1000000
+#define CONFIG_SYS_FLASH_BASE 0xffc00000
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 1024
+#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+/* amcore design has flash data bytes wired swapped */
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+/* reserve 128-4KB */
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024)
+#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
+
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE 0x1000
+#define CONFIG_ENV_SECT_SIZE 0x1000
+
+/* memory map space for linux boot data */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+
+/*
+ * Cache Configuration
+ *
+ * Special 8K version 3 core cache.
+ * This is a single unified instruction/data cache.
+ * sdram - single region - no masks
+ */
+#define CONFIG_SYS_CACHELINE_SIZE 16
+
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \
+ CF_ACR_EN)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \
+ CF_CACR_EC)
+
+/* CS0 - AMD Flash, address 0xffc00000 */
+#define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16)
+/* 4MB, AA=0,V=1 C/I BIT for errata */
+#define CONFIG_SYS_CS0_MASK 0x003f0001
+/* WS=10, AA=1, PS=16bit (10) */
+#define CONFIG_SYS_CS0_CTRL 0x1980
+/* CS1 - DM9000 Ethernet Controller, address 0x30000000 */
+#define CONFIG_SYS_CS1_BASE 0x3000
+#define CONFIG_SYS_CS1_MASK 0x00070001
+#define CONFIG_SYS_CS1_CTRL 0x0100
+
+#endif /* __AMCORE_CONFIG_H */
+
diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h
new file mode 100644
index 0000000000..490c53e92f
--- /dev/null
+++ b/include/configs/bav335x.h
@@ -0,0 +1,633 @@
+/*
+ * bav335x.h
+ *
+ * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_BAV335X_H
+#define __CONFIG_BAV335X_H
+
+#include <configs/ti_am335x_common.h>
+#define CONFIG_ENV_IS_NOWHERE
+
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_FIT
+# define CONFIG_TIMESTAMP
+# define CONFIG_LZO
+# ifdef CONFIG_ENABLE_VBOOT
+# define CONFIG_FIT_SIGNATURE
+# define CONFIG_RSA
+# endif
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN (16 << 20)
+
+#define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */
+#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM
+#define CONFIG_BOARD_LATE_INIT
+
+/* Clock Defines */
+#define V_OSCK 24000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK)
+
+/* Custom script for NOR */
+#define CONFIG_SYS_LDSCRIPT "board/birdland/bav335x/u-boot.lds"
+
+/* Always 128 KiB env size */
+#define CONFIG_ENV_SIZE (128 << 10)
+
+/* Enhance our eMMC support / experience. */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+
+#ifdef CONFIG_NAND
+#define NANDARGS \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "nandargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype}\0" \
+ "nandroot=ubi0:rootfs rw ubi.mtd=9,2048\0" \
+ "nandrootfstype=ubifs rootwait=1\0" \
+ "nandboot=echo Booting from nand ...; " \
+ "run nandargs; " \
+ "nand read ${fdtaddr} u-boot-spl-os; " \
+ "nand read ${loadaddr} kernel; " \
+ "bootz ${loadaddr} - ${fdtaddr}\0"
+#else
+#define NANDARGS ""
+#endif
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+DEFAULT_LINUX_BOOT_ENV \
+"boot_fdt=try\0" \
+"bootpart=0:2\0" \
+"bootdir=\0" \
+"fdtdir=/dtbs\0" \
+"bootfile=zImage\0" \
+"fdtfile=undefined\0" \
+"console=ttyO0,115200n8\0" \
+"loadaddr=0x82000000\0" \
+"fdtaddr=0x88000000\0" \
+"rdaddr=0x88080000\0" \
+"initrd_high=0xffffffff\0" \
+"fdt_high=0xffffffff\0" \
+"partitions=" \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
+"optargs=\0" \
+"cmdline=\0" \
+"mmcdev=0\0" \
+"mmcpart=1\0" \
+"mmcroot=/dev/mmcblk0p2 ro\0" \
+"mmcrootfstype=ext4 rootwait fixrtc\0" \
+"rootpath=/export/rootfs\0" \
+"nfsopts=nolock\0" \
+"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
+"ramroot=/dev/ram0 rw\0" \
+"ramrootfstype=ext2\0" \
+"mmcargs=setenv bootargs console=${console} ${optargs} " \
+ "root=${mmcroot} rootfstype=${mmcrootfstype} ${cmdline}\0" \
+"server_ip=192.168.1.100\0" \
+"gw_ip=192.168.1.1\0" \
+"netmask=255.255.255.0\0" \
+"hostname=\0" \
+"device=eth0\0" \
+"autoconf=off\0" \
+"root_dir=/home/userid/targetNFS\0" \
+"nfs_options=,vers=3\0" \
+"nfsrootfstype=ext4 rootwait fixrtc\0" \
+"nfsargs=setenv bootargs console=${console} ${optargs} " \
+ "root=/dev/nfs rw rootfstype=${nfsrootfstype} " \
+ "nfsroot=${nfsroot} ip=${ip} ${cmdline}\0" \
+"netargs=setenv bootargs console=${console} " \
+ "${optargs} root=/dev/nfs " \
+ "nfsroot=${serverip}:${rootpath},${nfsopts} rw ip=dhcp\0" \
+"bootenv=uEnv.txt\0" \
+"script=boot.scr\0" \
+"scriptfile=${script}\0" \
+"loadbootscript=load mmc ${bootpart} ${loadaddr} ${scriptfile};\0" \
+"bootscript=echo Running bootscript from mmc${bootpart} ...; " \
+ "source ${loadaddr}\0" \
+ "loadbootenv=load mmc ${bootpart} ${loadaddr} ${bootenv}\0" \
+"importbootenv=echo Importing environment from mmc ...; " \
+ "env import -t -r $loadaddr $filesize\0" \
+"ramargs=setenv bootargs console=${console} " \
+ "${optargs} root=${ramroot} rootfstype=${ramrootfstype}\0" \
+"loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
+"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+ "loadrd=load mmc ${bootpart} ${rdaddr} " \
+ "${bootdir}/${rdfile}; setenv rdsize ${filesize}\0" \
+"loadfdt=echo loading ${fdtdir}/${fdtfile} ...; " \
+ "load mmc ${bootpart} ${fdtaddr} ${fdtdir}/${fdtfile}\0" \
+"mmcboot=mmc dev ${mmcdev}; " \
+ "if mmc rescan; then " \
+ "gpio set 54;" \
+ "setenv bootpart ${mmcdev}:1; " \
+ "if test -e mmc ${bootpart} /etc/fstab; then " \
+ "setenv mmcpart 1;" \
+ "fi; " \
+ "echo Checking for: /uEnv.txt ...;" \
+ "if test -e mmc ${bootpart} /uEnv.txt; then " \
+ "if run loadbootenv; then " \
+ "gpio set 55;" \
+ "echo Loaded environment from ${bootenv};" \
+ "run importbootenv;" \
+ "fi;" \
+ "echo Checking if uenvcmd is set ...;" \
+ "if test -n ${uenvcmd}; then " \
+ "gpio set 56; " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "echo Checking if client_ip is set ...;" \
+ "if test -n ${client_ip}; then " \
+ "if test -n ${dtb}; then " \
+ "setenv fdtfile ${dtb};" \
+ "echo using ${fdtfile} ...;" \
+ "fi;" \
+ "gpio set 56; " \
+ "if test -n ${uname_r}; then " \
+ "echo Running nfsboot_uname_r ...;" \
+ "run nfsboot_uname_r;" \
+ "fi;" \
+ "echo Running nfsboot ...;" \
+ "run nfsboot;" \
+ "fi;" \
+ "fi; " \
+ "echo Checking for: /${script} ...;" \
+ "if test -e mmc ${bootpart} /${script}; then " \
+ "gpio set 55;" \
+ "setenv scriptfile ${script};" \
+ "run loadbootscript;" \
+ "echo Loaded script from ${scriptfile};" \
+ "gpio set 56; " \
+ "run bootscript;" \
+ "fi; " \
+ "echo Checking for: /boot/${script} ...;" \
+ "if test -e mmc ${bootpart} /boot/${script}; then " \
+ "gpio set 55;" \
+ "setenv scriptfile /boot/${script};" \
+ "run loadbootscript;" \
+ "echo Loaded script from ${scriptfile};" \
+ "gpio set 56; " \
+ "run bootscript;" \
+ "fi; " \
+ "echo Checking for: /boot/uEnv.txt ...;" \
+ "for i in 1 2 3 4 5 6 7 ; do " \
+ "setenv mmcpart ${i};" \
+ "setenv bootpart ${mmcdev}:${mmcpart};" \
+ "if test -e mmc ${bootpart} /boot/uEnv.txt; then " \
+ "gpio set 55;" \
+ "load mmc ${bootpart} ${loadaddr} " \
+ "/boot/uEnv.txt;" \
+ "env import -t ${loadaddr} ${filesize};" \
+ "echo Loaded environment from /boot/uEnv.txt;" \
+ "if test -n ${dtb}; then " \
+ "setenv fdtfile ${dtb};" \
+ "echo Using: dtb=${fdtfile} ...;" \
+ "fi;" \
+ "echo Checking if uname_r is set in " \
+ "/boot/uEnv.txt...;" \
+ "if test -n ${uname_r}; then " \
+ "gpio set 56; " \
+ "echo Running uname_boot ...;" \
+ "setenv mmcroot /dev/mmcblk${mmcdev}" \
+ "p${mmcpart} ro;" \
+ "run uname_boot;" \
+ "fi;" \
+ "fi;" \
+ "done;" \
+ "fi;\0" \
+"netboot=echo Booting from network ...; " \
+ "setenv autoload no; " \
+ "dhcp; " \
+ "tftp ${loadaddr} ${bootfile}; " \
+ "tftp ${fdtaddr} ${fdtfile}; " \
+ "run netargs; " \
+ "bootz ${loadaddr} - ${fdtaddr}\0" \
+"nfsboot=echo Booting from ${server_ip} ...; " \
+ "setenv nfsroot ${server_ip}:${root_dir}${nfs_options}; " \
+ "setenv ip ${client_ip}:${server_ip}:${gw_ip}:${netmask}:${hostname}" \
+ ":${device}:${autoconf}; " \
+ "setenv autoload no; " \
+ "setenv serverip ${server_ip}; " \
+ "setenv ipaddr ${client_ip}; " \
+ "tftp ${loadaddr} ${bootfile}; " \
+ "tftp ${fdtaddr} dtbs/${fdtfile}; " \
+ "run nfsargs; " \
+ "bootz ${loadaddr} - ${fdtaddr}\0" \
+"nfsboot_uname_r=echo Booting from ${server_ip} ...; " \
+ "setenv nfsroot ${server_ip}:${root_dir}${nfs_options}; " \
+ "setenv ip ${client_ip}:${server_ip}:${gw_ip}:${netmask}:${hostname}" \
+ ":${device}:${autoconf}; " \
+ "setenv autoload no; " \
+ "setenv serverip ${server_ip}; " \
+ "setenv ipaddr ${client_ip}; " \
+ "tftp ${loadaddr} vmlinuz-${uname_r}; " \
+ "tftp ${fdtaddr} dtbs/${uname_r}/${fdtfile}; " \
+ "run nfsargs; " \
+ "bootz ${loadaddr} - ${fdtaddr}\0" \
+"ramboot=echo Booting from ramdisk ...; " \
+ "run ramargs; " \
+ "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
+"findfdt="\
+ "if test $board_rev = B; then " \
+ "setenv fdtfile birdland_bav335b.dtb; " \
+ "setenv fdtbase am335x-boneblack; fi; " \
+ "if test $board_rev = A; then " \
+ "setenv fdtfile birdland_bav335a.dtb; " \
+ "setenv fdtbase am335x-boneblack; fi; " \
+ "if test $fdtfile = undefined; then " \
+ "echo WARNING: Could not determine device tree to use; fi; \0" \
+"uname_boot="\
+ "setenv bootdir /boot; " \
+ "setenv bootfile vmlinuz-${uname_r}; " \
+ "if test -e mmc ${bootpart} ${bootdir}/${bootfile}; then " \
+ "echo loading ${bootdir}/${bootfile} ...; "\
+ "run loadimage;" \
+ "setenv fdtdir /boot/dtbs/${uname_r}; " \
+ "if test -e mmc ${bootpart} ${fdtdir}/${fdtfile}; then " \
+ "run loadfdt;" \
+ "else " \
+ "setenv fdtdir /lib/firmware/${uname_r}/device-tree; " \
+ "if test -e mmc ${bootpart} ${fdtdir}/" \
+ "${fdtfile}; then " \
+ "run loadfdt;" \
+ "else " \
+ "setenv fdtdir /boot/dtb-${uname_r}; " \
+ "if test -e mmc ${bootpart} ${fdtdir}" \
+ "/${fdtfile}; then " \
+ "run loadfdt;" \
+ "else " \
+ "setenv fdtdir /boot/dtbs; " \
+ "if test -e mmc ${bootpart} ${fdtdir}" \
+ "/${fdtfile}; then " \
+ "run loadfdt;" \
+ "else " \
+ "echo; echo unable to find " \
+ "[${fdtfile}] " \
+ "did you name it correctly?" \
+ "echo booting fallback " \
+ "[/boot/dtbs/" \
+ "${uname_r}" \
+ "/${fdtbase}.dtb]...;" \
+ "setenv fdtdir /boot/dtbs/" \
+ "${uname_r}; " \
+ "setenv fdtfile " \
+ "${fdtbase}.dtb; " \
+ "run loadfdt;" \
+ "fi;" \
+ "fi;" \
+ "fi;" \
+ "fi;" \
+ "fi; " \
+ "setenv rdfile initrd.img-${uname_r}; " \
+ "if test -e mmc ${bootpart} ${bootdir}/${rdfile}; then " \
+ "echo loading ${bootdir}/${rdfile} ...; "\
+ "run loadrd;" \
+ "if test -n ${uuid}; then " \
+ "setenv mmcroot UUID=${uuid} ro;" \
+ "fi;" \
+ "run mmcargs;" \
+ "echo debug: [${bootargs}] ... ;" \
+ "echo debug: [bootz ${loadaddr} ${rdaddr}:${rdsize} " \
+ "${fdtaddr}] ... ;" \
+ "bootz ${loadaddr} ${rdaddr}:${rdsize} ${fdtaddr}; " \
+ "else " \
+ "run mmcargs;" \
+ "echo debug: [${bootargs}] ... ;" \
+ "echo debug: [bootz ${loadaddr} - ${fdtaddr}] ... ;" \
+ "bootz ${loadaddr} - ${fdtaddr}; " \
+ "fi;" \
+"fi;\0" \
+ NANDARGS \
+ DFUARGS
+#endif
+
+#define CONFIG_BOOTCOMMAND \
+ "gpio set 53; " \
+ "i2c mw 0x24 1 0x3e; " \
+ "run findfdt; " \
+ "setenv mmcdev 0; " \
+ "setenv bootpart 0:1; " \
+ "run mmcboot;" \
+ "gpio clear 56; " \
+ "gpio clear 55; " \
+ "gpio clear 54; " \
+ "setenv mmcdev 1; " \
+ "setenv bootpart 1:1; " \
+ "run mmcboot;"
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
+#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
+#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
+#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
+#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
+#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+
+/* PMIC support */
+#define CONFIG_POWER_TPS65217
+#define CONFIG_POWER_TPS65910
+
+/* SPL */
+#ifndef CONFIG_NOR_BOOT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+
+/* Bootcount using the RTC block */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_AM33XX
+#define CONFIG_SYS_BOOTCOUNT_BE
+
+/* USB gadget RNDIS */
+#define CONFIG_SPL_MUSB_NEW_SUPPORT
+
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
+#endif
+
+#ifdef CONFIG_NAND
+/* NAND: device related configs */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
+ CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
+/* NAND: driver related configs */
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS { \
+ 2, 3, 4, 5, 6, 7, 8, 9, \
+ 10, 11, 12, 13, 14, 15, 16, 17, \
+ 18, 19, 20, 21, 22, 23, 24, 25, \
+ 26, 27, 28, 29, 30, 31, 32, 33, \
+ 34, 35, 36, 37, 38, 39, 40, 41, \
+ 42, 43, 44, 45, 46, 47, 48, 49, \
+ 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 14
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
+#define MTDIDS_DEFAULT "nand0=nand.0"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=nand.0:" \
+ "128k(NAND.SPL)," \
+ "128k(NAND.SPL.backup1)," \
+ "128k(NAND.SPL.backup2)," \
+ "128k(NAND.SPL.backup3)," \
+ "256k(NAND.u-boot-spl-os)," \
+ "1m(NAND.u-boot)," \
+ "128k(NAND.u-boot-env)," \
+ "128k(NAND.u-boot-env.backup1)," \
+ "8m(NAND.kernel)," \
+ "-(NAND.rootfs)"
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x001c0000
+#define CONFIG_ENV_OFFSET_REDUND 0x001e0000
+#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+/* NAND: SPL related configs */
+#ifdef CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_AM33XX_BCH
+#endif
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os parameters */
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
+#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
+#endif
+#endif /* !CONFIG_NAND */
+
+/*
+ * For NOR boot, we must set this to the start of where NOR is mapped
+ * in memory.
+ */
+#ifdef CONFIG_NOR_BOOT
+#define CONFIG_SYS_TEXT_BASE 0x08000000
+#endif
+
+/*
+ * USB configuration. We enable MUSB support, both for host and for
+ * gadget. We set USB0 as peripheral and USB1 as host, based on the
+ * board schematic and physical port wired to each. Then for host we
+ * add mass storage support and for gadget we add both RNDIS ethernet
+ * and DFU.
+ */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_MUSB_GADGET
+#define CONFIG_MUSB_PIO_ONLY
+#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
+#define CONFIG_USB_GADGET
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+#define CONFIG_MUSB_HOST
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+
+#ifndef CONFIG_SPL_USBETH_SUPPORT
+/* Fastboot */
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_ANDROID_BOOT_IMAGE
+#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
+#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000
+
+/* To support eMMC booting */
+#define CONFIG_STORAGE_EMMC
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#endif
+
+#ifdef CONFIG_MUSB_HOST
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#endif
+
+#ifdef CONFIG_MUSB_GADGET
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+
+/* USB TI's IDs */
+#define CONFIG_G_DNL_VENDOR_NUM 0x0451
+#define CONFIG_G_DNL_PRODUCT_NUM 0xD022
+#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
+#endif /* CONFIG_MUSB_GADGET */
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
+/* disable host part of MUSB in SPL */
+#undef CONFIG_MUSB_HOST
+/* disable EFI partitions and partition UUID support */
+#undef CONFIG_PARTITION_UUIDS
+#undef CONFIG_EFI_PARTITION
+/* General network SPL */
+#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NET_VCI_STRING "BAV335x U-Boot SPL"
+#endif
+
+/* USB Device Firmware Update support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_MMC
+#define CONFIG_CMD_DFU
+#define DFU_ALT_INFO_MMC \
+ "dfu_alt_info_mmc=" \
+ "boot part 0 1;" \
+ "rootfs part 0 2;" \
+ "MLO fat 0 1;" \
+ "MLO.raw raw 0x100 0x100;" \
+ "u-boot.img.raw raw 0x300 0x400;" \
+ "spl-os-args.raw raw 0x80 0x80;" \
+ "spl-os-image.raw raw 0x900 0x2000;" \
+ "spl-os-args fat 0 1;" \
+ "spl-os-image fat 0 1;" \
+ "u-boot.img fat 0 1;" \
+ "uEnv.txt fat 0 1\0"
+#ifdef CONFIG_NAND
+#define CONFIG_DFU_NAND
+#define DFU_ALT_INFO_NAND \
+ "dfu_alt_info_nand=" \
+ "SPL part 0 1;" \
+ "SPL.backup1 part 0 2;" \
+ "SPL.backup2 part 0 3;" \
+ "SPL.backup3 part 0 4;" \
+ "u-boot part 0 5;" \
+ "u-boot-spl-os part 0 6;" \
+ "kernel part 0 8;" \
+ "rootfs part 0 9\0"
+#else
+#define DFU_ALT_INFO_NAND ""
+#endif
+#define CONFIG_DFU_RAM
+#define DFU_ALT_INFO_RAM \
+ "dfu_alt_info_ram=" \
+ "kernel ram 0x80200000 0xD80000;" \
+ "fdt ram 0x80F80000 0x80000;" \
+ "ramdisk ram 0x81000000 0x4000000\0"
+#define DFUARGS \
+ "dfu_alt_info_emmc=rawemmc raw 0 3751936\0" \
+ DFU_ALT_INFO_MMC \
+ DFU_ALT_INFO_RAM \
+ DFU_ALT_INFO_NAND
+#endif
+
+/*
+ * Default to using SPI for environment, etc.
+ * 0x000000 - 0x020000 : SPL (128KiB)
+ * 0x020000 - 0x0A0000 : U-Boot (512KiB)
+ * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB)
+ * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB)
+ * 0x0E0000 - 0x442000 : Linux Kernel
+ * 0x442000 - 0x800000 : Userland
+ */
+#if defined(CONFIG_SPI_BOOT)
+/* SPL related */
+#undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
+#define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */
+#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */
+#define MTDIDS_DEFAULT "nor0=m25p80-flash.0"
+#define MTDPARTS_DEFAULT "mtdparts=m25p80-flash.0:128k(SPL)," \
+ "512k(u-boot),128k(u-boot-env1)," \
+ "128k(u-boot-env2),3464k(kernel)," \
+ "-(rootfs)"
+#elif defined(CONFIG_EMMC_BOOT)
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SYS_MMC_ENV_DEV 1
+#define CONFIG_SYS_MMC_ENV_PART 2
+#define CONFIG_ENV_OFFSET 0x0
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#endif
+
+/* SPI flash. */
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_SPEED 24000000
+
+/* Network. */
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+
+/*
+ * NOR Size = 16 MiB
+ * Number of Sectors/Blocks = 128
+ * Sector Size = 128 KiB
+ * Word length = 16 bits
+ * Default layout:
+ * 0x000000 - 0x07FFFF : U-Boot (512 KiB)
+ * 0x080000 - 0x09FFFF : First copy of U-Boot Environment (128 KiB)
+ * 0x0A0000 - 0x0BFFFF : Second copy of U-Boot Environment (128 KiB)
+ * 0x0C0000 - 0x4BFFFF : Linux Kernel (4 MiB)
+ * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB)
+ */
+#if defined(CONFIG_NOR)
+#undef CONFIG_SYS_NO_FLASH
+#define CONFIG_CMD_FLASH
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_SYS_MAX_FLASH_SECT 128
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_FLASH_BASE (0x08000000)
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_SIZE 0x01000000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+/* Reduce SPL size by removing unlikey targets */
+#ifdef CONFIG_NOR_BOOT
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET (512 << 10) /* 512 KiB */
+#define CONFIG_ENV_OFFSET_REDUND (768 << 10) /* 768 KiB */
+#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=physmap-flash.0:" \
+ "512k(u-boot)," \
+ "128k(u-boot-env1)," \
+ "128k(u-boot-env2)," \
+ "4m(kernel),-(rootfs)"
+#endif
+#endif /* NOR support */
+
+#endif /* ! __CONFIG_AM335X_EVM_H */
diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h
index 49afe46e2a..a558e42c90 100644
--- a/include/configs/bur_am335x_common.h
+++ b/include/configs/bur_am335x_common.h
@@ -12,6 +12,31 @@
#ifndef __BUR_AM335X_COMMON_H__
#define __BUR_AM335X_COMMON_H__
/* ------------------------------------------------------------------------- */
+#define BUR_COMMON_ENV \
+"defaultip=192.168.60.253\0" \
+"defaultsip=192.168.60.254\0" \
+"netconsole=echo switching to network console ...; " \
+"if dhcp; then " \
+"setenv ncip ${serverip}; else " \
+"setenv ncip 192.168.60.254; " \
+"setenv serverip 192.168.60.254; " \
+"setenv gatewayip 192.168.60.254; " \
+"setenv ipaddr 192.168.60.1; " \
+"fi;" \
+"setenv netdisplay0 '" \
+"setcurs 1 9; puts myip; setcurs 10 9; puts ${ipaddr};" \
+"setcurs 1 10;puts serverip; setcurs 10 10; puts ${serverip}\;'" \
+"run netdisplay0; " \
+"setenv stdout nc;setenv stdin nc;setenv stderr nc\0"
+
+#define CONFIG_CMD_TIME
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1366*767*4)
+#define CONFIG_CMD_UNZIP
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_24BMP
+#define CONFIG_BMP_32BPP
+
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_AM33XX
@@ -47,7 +72,7 @@
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_NET_RETRY_COUNT 4
+#define CONFIG_NET_RETRY_COUNT 2
#define CONFIG_CMD_PING
#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
#define CONFIG_MII /* Required in net/eth.c */
@@ -57,7 +82,9 @@
#define CONFIG_SPL_NET_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT /* used for a fetching MAC-Address */
#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
-
+/* Network console */
+#define CONFIG_NETCONSOLE 1
+#define CONFIG_BOOTP_MAY_FAIL /* if we don't have DHCP environment */
/*
* SPL related defines. The Public RAM memory map the ROM defines the
* area between 0x402F0400 and 0x4030B800 as a download area and
@@ -110,7 +137,7 @@
* we are on so we do not need to rely on the command prompt. We set a
* console baudrate of 115200 and use the default baud rate table.
*/
-#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
+#define CONFIG_SYS_MALLOC_LEN (5120 << 10)
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "U-Boot (BuR V2.0)# "
#define CONFIG_SYS_CONSOLE_INFO_QUIET
diff --git a/include/configs/kwb.h b/include/configs/kwb.h
index 29b263f301..dd30df27b0 100644
--- a/include/configs/kwb.h
+++ b/include/configs/kwb.h
@@ -14,6 +14,11 @@
#include <configs/bur_am335x_common.h>
/* ------------------------------------------------------------------------- */
+#define CONFIG_AM335X_LCD
+#define CONFIG_LCD
+#define CONFIG_LCD_NOSTDOUT
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define LCD_BPP LCD_COLOR32
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
@@ -38,57 +43,71 @@
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
#define CONFIG_SPL_MMC_SUPPORT
-#undef CONFIG_SPL_OS_BOOT
-#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000
-
-/* RAW SD card / eMMC */
-#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
-#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
-
-#endif /* CONFIG_SPL_OS_BOOT */
-
-/* Always 128 KiB env size */
-#define CONFIG_ENV_SIZE (128 << 10)
+/* Always 64 KiB env size */
+#define CONFIG_ENV_SIZE (64 << 10)
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
- "autoload=0\0" \
- "loadaddr=0x80100000\0" \
- "bootfile=arimg\0" \
- "usbboot=echo Booting from USB-Stick ...; " \
- "usb start; " \
- "fatload usb 0 ${loadaddr} ${bootfile}; " \
- "usb stop; " \
- "go ${loadaddr};\0" \
- "netboot=echo Booting from network ...; " \
- "setenv autoload 0; " \
- "dhcp; " \
- "tftp ${loadaddr} arimg; " \
- "go ${loadaddr}\0" \
- "usbupdate=echo Updating UBOOT from USB-Stick ...; " \
- "usb start; " \
- "fatload usb 0 0x80000000 updateubootusb.img; " \
- "source;\0" \
- "netupdate=echo Updating UBOOT from Network (TFTP) ...; " \
- "setenv autoload 0; " \
- "dhcp;" \
- "tftp 0x80000000 updateUBOOT.img;" \
- "source;\0"
+BUR_COMMON_ENV \
+"vx_romfsbase=0x800E0000\0" \
+"vx_romfssize=0x20000\0" \
+"vx_memtop=0x8FBEF000\0" \
+"loadromfs=mmc read ${vx_romfsbase} 700 100\0" \
+"autoload=0\0" \
+"loadaddr=0x80100000\0" \
+"logoaddr=0x82000000\0" \
+"defaultARlen=0x8000\0" \
+"loaddefaultAR=mmc read ${loadaddr} 800 ${defaultARlen}\0" \
+"defaultAR=run loadromfs; run loaddefaultAR; go ${loadaddr}\0" \
+"logo0=fatload mmc 0:1 ${logoaddr} SYSTEM/ADDON/Bootlogo/Bootlogo.bmp.gz && " \
+ "bmp display ${logoaddr} 0 0\0" \
+"logo1=fatload mmc 0:1 ${logoaddr} SYSTEM/BASE/Bootlogo/Bootlogo.bmp.gz && " \
+ "bmp display ${logoaddr} 0 0\0" \
+"mmcboot=echo booting AR from eMMC-flash ...; "\
+ "run logo0 || run logo1; " \
+ "run loadromfs; " \
+ "fatload mmc 0:1 ${loadaddr} arimg && go ${loadaddr}; " \
+ "run defaultAR;\0" \
+"netboot=echo booting AR from network ...; " \
+ "run loadromfs; " \
+ "tftp ${loadaddr} arimg && go ${loadaddr}; " \
+ "puts 'networkboot failed!';\0" \
+"usbupdate=echo updating u-boot from usb ...; " \
+ "usb start; " \
+ "fatload usb 0 0x80000000 updateubootusb.img && source; " \
+ "puts 'usbupdate failed!'\0" \
+"netscript=echo running script from network (tftp) ...; " \
+ "tftp 0x80000000 netscript.img && source; " \
+ "puts 'netscript load failed!'\0" \
+"netupdate=tftp ${loadddr} MLO && mmc write ${loadaddr} 100 100; " \
+ "tftp ${loadaddr} u-boot.img && mmc write ${loadaddr} 300 300\0" \
+"netupdatedefaultAR=echo updating defaultAR from network (tftp) ...; " \
+ "if tftp 0x80100000 arimg.bin; " \
+ "then mmc write 0x80100000 800 ${defaultARlen}; " \
+ "else setcurs 1 8; puts 'defAR update failed (tftp)!'; fi;\0" \
+"netupdateROMFS=echo updating romfs from network (tftp) ...; " \
+ "if tftp 0x80100000 romfs.bin; " \
+ "then mmc write 0x80100000 700 100; " \
+ "else setcurs 1 8; puts 'romfs update failed (tftp)!'; fi;\0"
+
#endif /* !CONFIG_SPL_BUILD*/
#define CONFIG_BOOTCOMMAND \
"run usbupdate;"
-#define CONFIG_BOOTDELAY 1 /* TODO: für release auf 0 setzen */
+#define CONFIG_BOOTDELAY 0
/* undefine command which we not need here */
-#undef CONFIG_BOOTM_LINUX
#undef CONFIG_BOOTM_NETBSD
#undef CONFIG_BOOTM_PLAN9
#undef CONFIG_BOOTM_RTEMS
-#undef CONFIG_GZIP
-#undef CONFIG_ZLIB
+#undef CONFIG_CMD_CRC32
+
+/* Support both device trees and ATAGs. */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMD_BOOTZ
/* USB configuration */
#define CONFIG_USB_MUSB_DSPS
@@ -100,6 +119,8 @@
#define CONFIG_MUSB_HOST
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_HOST
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
#ifdef CONFIG_MUSB_HOST
#define CONFIG_CMD_USB
diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h
new file mode 100644
index 0000000000..3030054949
--- /dev/null
+++ b/include/configs/omap3_cairo.h
@@ -0,0 +1,286 @@
+/*
+ * Configuration settings for the QUIPOS Cairo board.
+ *
+ * Copyright (C) DENX GmbH
+ *
+ * Author :
+ * Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * Derived from EVM code by
+ * Manikandan Pillai <mani.pillai@ti.com>
+ * Itself derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * Also derived from include/configs/omap3_beagle.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __OMAP3_CAIRO_CONFIG_H
+#define __OMAP3_CAIRO_CONFIG_H
+
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs. We use this rather than the inherited defines from
+ * ti_armv7_common.h for backwards compatibility.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x80100000
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SPL_BSS_START_ADDR 0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
+
+#define CONFIG_NAND
+
+#include <configs/ti_omap3_common.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_ENV_OVERWRITE
+
+/* Enable Multi Bus support for I2C */
+#define CONFIG_I2C_MULTI_BUS 1
+
+/* Probe all devices */
+#define CONFIG_SYS_I2C_NOPROBES { {0x0, 0x0} }
+
+#define CONFIG_NAND
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_SETEXPR /* Evaluate expressions */
+#define CONFIG_CMD_NAND_LOCK_UNLOCK
+
+/* Disable some commands */
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_LED 1
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_QUIET_TEST 1
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
+ /* devices */
+/* override default CONFIG_BOOTDELAY */
+#undef CONFIG_BOOTDELAY
+#define CONFIG_BOOTDELAY 0
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "machid=ffffffff\0" \
+ "fdt_high=0x87000000\0" \
+ "baudrate=115200\0" \
+ "ethaddr=00:50:C2:7E:90:F0\0" \
+ "fec_addr=00:50:C2:7E:90:F0\0" \
+ "netmask=255.255.255.0\0" \
+ "ipaddr=192.168.2.9\0" \
+ "gateway=192.168.2.1\0" \
+ "serverip=192.168.2.10\0" \
+ "nfshost=192.168.2.10\0" \
+ "stdin=serial\0" \
+ "stdout=serial\0" \
+ "stderr=serial\0" \
+ "bootargs_mmc_ramdisk=mem=128M " \
+ "console=ttyO1,115200n8 " \
+ "root=/dev/ram0 rw " \
+ "initrd=0x81600000,16M " \
+ "mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \
+ "omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \
+ "mmcboot=mmc init; " \
+ "fatload mmc 0 0x80000000 uImage; " \
+ "fatload mmc 0 0x81600000 ramdisk.gz; " \
+ "setenv bootargs ${bootargs_mmc_ramdisk}; " \
+ "bootm 0x80000000\0" \
+ "bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \
+ "root=/dev/nfs " \
+ "nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \
+ "mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \
+ "omap_vout.vid1_static_vrfb_alloc=y\0" \
+ "boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \
+ "bootm 0x80000000\0" \
+ "bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \
+ "root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \
+ "omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \
+ "omapfb.rotate_type=1\0" \
+ "boot_nand=nand read.i 0x80000000 280000 300000; setenv " \
+ "bootargs ${bootargs_nand}; bootm 0x80000000\0" \
+ "ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
+ "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
+ "i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
+ "ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
+ "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
+ "mw 60 09 00 1; i2c mw 60 06 10 1\0" \
+ "ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
+ "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
+ "i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
+ "ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
+ "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
+ "i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \
+ "flash_xloader=mw.b 0x81600000 0xff 0x20000; " \
+ "nand erase 0 20000; " \
+ "fatload mmc 0 0x81600000 MLO; " \
+ "nandecc hw; " \
+ "nand write.i 0x81600000 0 20000;\0" \
+ "flash_uboot=mw.b 0x81600000 0xff 0x40000; " \
+ "nand erase 80000 40000; " \
+ "fatload mmc 0 0x81600000 u-boot.bin; " \
+ "nandecc sw; " \
+ "nand write.i 0x81600000 80000 40000;\0" \
+ "flash_kernel=mw.b 0x81600000 0xff 0x300000; " \
+ "nand erase 280000 300000; " \
+ "fatload mmc 0 0x81600000 uImage; " \
+ "nandecc sw; " \
+ "nand write.i 0x81600000 280000 300000;\0" \
+ "flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \
+ "nandecc sw; " \
+ "nand write.jffs2 0x680000 0xFF ${filesize}; " \
+ "nand erase 680000 ${filesize}; " \
+ "nand write.jffs2 81600000 680000 ${filesize};\0" \
+ "flash_scrub=nand scrub; " \
+ "run flash_xloader; " \
+ "run flash_uboot; " \
+ "run flash_kernel; " \
+ "run flash_rootfs;\0" \
+ "flash_all=run ledred; " \
+ "nand erase.chip; " \
+ "run ledorange; " \
+ "run flash_xloader; " \
+ "run flash_uboot; " \
+ "run flash_kernel; " \
+ "run flash_rootfs; " \
+ "run ledgreen; " \
+ "run boot_nand; \0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "if fatload mmc 0 0x81600000 MLO; then run flash_all; " \
+ "else run boot_nand; fi"
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE NAND_BASE
+#endif
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
+
+#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
+#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
+#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+
+#define CONFIG_OMAP3_SPI
+
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
+/* Defines for SPL */
+#define CONFIG_SPL_OMAP3_ID_NAND
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT 64
+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
+#define CONFIG_SYS_NAND_OOBSIZE 64
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
+#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
+ 10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS 0x240000
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
+#endif
+
+/* env defaults */
+#define CONFIG_BOOTFILE "uImage"
+
+/* Override OMAP3 common serial console configuration from UART3
+ * to UART2.
+ *
+ * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3)
+ * are needed and peripheral clocks for UART2 must be enabled in
+ * function per_clocks_enable().
+ */
+#undef CONFIG_CONS_INDEX
+#define CONFIG_CONS_INDEX 2
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_SYS_NS16550_COM3
+#define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2
+#undef CONFIG_SERIAL3
+#define CONFIG_SERIAL2
+#endif
+
+/* Keep old prompt in case some existing script depends on it */
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT "Cairo # "
+
+/* Provide MACH_TYPE for compatibility with non-DT kernels */
+#define MACH_TYPE_OMAP3_CAIRO 3063
+#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CAIRO
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
+ /* on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
+ CONFIG_SYS_MAX_NAND_DEVICE)
+#define CONFIG_SYS_JFFS2_MEM_NAND
+/* use flash_info[2] */
+#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS 1
+
+#endif /* __OMAP3_CAIRO_CONFIG_H */
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index a11f4ed2e1..16281f5ba8 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -11,6 +11,8 @@
* Common configurations used for both spear3xx as well as spear6xx
*/
+#define CONFIG_SYS_GENERIC_BOARD
+
/* U-boot Load Address */
#define CONFIG_SYS_TEXT_BASE 0x00700000
diff --git a/include/configs/tseries.h b/include/configs/tseries.h
index 9a6207048c..a6c7d5f136 100644
--- a/include/configs/tseries.h
+++ b/include/configs/tseries.h
@@ -14,6 +14,19 @@
#include <configs/bur_am335x_common.h>
/* ------------------------------------------------------------------------- */
+#define CONFIG_AM335X_LCD
+#define CONFIG_LCD
+#define CONFIG_LCD_NOSTDOUT
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define LCD_BPP LCD_COLOR32
+
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_OMAP_WATCHDOG
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+/* Bootcount using the RTC block */
+#define CONFIG_SYS_BOOTCOUNT_ADDR 0x44E3E000
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_AM33XX
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
@@ -22,6 +35,8 @@
/* Support both device trees and ATAGs. */
#define CONFIG_OF_LIBFDT
+#define CONFIG_USE_FDT /* use fdt within board code */
+#define CONFIG_OF_BOARD_SETUP
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
@@ -79,8 +94,8 @@
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#endif /* CONFIG_NAND */
-/* Always 128 KiB env size */
-#define CONFIG_ENV_SIZE (128 << 10)
+/* Always 64 KiB env size */
+#define CONFIG_ENV_SIZE (64 << 10)
#ifdef CONFIG_NAND
#define NANDARGS \
@@ -103,47 +118,83 @@
#ifdef CONFIG_MMC
#define MMCARGS \
- "silent=1\0"
+"dtbdev=mmc\0" \
+"dtbpart=0:1\0" \
+"logo0=ext4load mmc 0:3 ${loadaddr} /PPTLogo.bmp.gz && " \
+ "bmp display ${loadaddr} 0 0\0" \
+"logo1=ext4load mmc 0:1 ${loadaddr} /PPTLogo.bmp.gz && " \
+ "bmp display ${loadaddr} 0 0\0" \
+"mmcroot0=setenv bootargs ${optargs} console=${console}\0" \
+"mmcroot1=setenv bootargs ${optargs} console=${console} root=/dev/mmcblk0p2 " \
+ "rootfstype=ext4\0" \
+"mmcboot0=echo booting Updatesystem from mmc (ext4-fs) ...; " \
+ "ext4load mmc 0:1 ${loadaddr} /${kernel}; " \
+ "ext4load mmc 0:1 ${ramaddr} /${ramdisk}; " \
+ "run mmcroot0; bootz ${loadaddr} ${ramaddr} ${dtbaddr};\0" \
+"mmcboot1=echo booting PPT-OS from mmc (ext4-fs) ...; " \
+ "ext4load mmc 0:2 ${loadaddr} /boot/${kernel}; " \
+ "run mmcroot1; bootz ${loadaddr} - ${dtbaddr};\0" \
+"defboot=run logo0 || run logo1; " \
+ "ext4load mmc 0:2 ${loadaddr} /boot/PPTImage.md5 && run mmcboot1; " \
+ "ext4load mmc 0:1 ${dtbaddr} /$dtb && run mmcboot0; " \
+ "run ramboot; run usbupdate;\0" \
+"bootlimit=1\0" \
+"altbootcmd=run logo0 || run logo1; " \
+ "run mmcboot0;\0" \
+"upduboot=dhcp; " \
+ "tftp ${loadaddr} MLO && mmc write ${loadaddr} 100 100; " \
+ "tftp ${loadaddr} u-boot.img && mmc write ${loadaddr} 300 400;\0"
#else
#define MMCARGS ""
#endif /* CONFIG_MMC */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
- "autoload=0\0" \
- "loadaddr=0x80200000\0" \
- "bootfile=zImage\0" \
- "console=ttyO0,115200n8\0" \
- "optargs=\0" \
- "rootpath=/tftpboot/tseries/rootfs-small\0" \
- "nfsopts=nolock\0" \
- "netargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=/dev/nfs " \
- "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
- "ip=dhcp\0" \
- "netboot=echo Booting from network ...; " \
- "setenv autoload no; " \
- "dhcp; " \
- "tftp ${loadaddr} ${bootfile}; " \
- "run netargs; " \
- "bootm ${loadaddr}\0" \
- "usbupdate=echo Updating UBOOT from USB-Stick ...; " \
- "usb start; " \
- "fatload usb 0 0x80000000 updateubootusb.img; " \
- "source;\0" \
- "netupdate=echo Updating UBOOT from Network (TFTP) ...; " \
- "setenv autoload 0; " \
- "dhcp;" \
- "tftp 0x80000000 updateUBOOT.img;" \
- "source;\0" \
- NANDARGS \
- MMCARGS
+BUR_COMMON_ENV \
+"verify=no\0" \
+"autoload=0\0" \
+"dtb=bur-ppt-ts30.dtb\0" \
+"dtbaddr=0x80100000\0" \
+"loadaddr=0x80200000\0" \
+"ramaddr=0x80A00000\0" \
+"kernel=zImage\0" \
+"ramdisk=rootfs.cpio.uboot\0" \
+"console=ttyO0,115200n8\0" \
+"optargs=consoleblank=0 quiet lpj=1191936 panic=2\0" \
+"nfsroot=/tftpboot/tseries/rootfs-small\0" \
+"nfsopts=nolock\0" \
+"ramargs=setenv bootargs ${optargs} console=${console} root=/dev/ram0\0" \
+"netargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=/dev/nfs " \
+ "nfsroot=${serverip}:${nfsroot},${nfsopts} rw " \
+ "ip=dhcp\0" \
+"netboot=echo Booting from network ...; " \
+ "dhcp; " \
+ "tftp ${loadaddr} ${kernel}; " \
+ "tftp ${dtbaddr} ${dtb}; " \
+ "run netargs; " \
+ "bootz ${loadaddr} - ${dtbaddr}\0" \
+"ramboot=echo Booting from network into RAM ...; "\
+ "if dhcp; then; " \
+ "tftp ${loadaddr} ${kernel}; " \
+ "tftp ${ramaddr} ${ramdisk}; " \
+ "if ext4load ${dtbdev} ${dtbpart} ${dtbaddr} /${dtb}; " \
+ "then; else tftp ${dtbaddr} ${dtb}; fi;" \
+ "run mmcroot0; " \
+ "bootz ${loadaddr} ${ramaddr} ${dtbaddr}; fi;\0" \
+"usbupdate=echo Updating UBOOT from USB-Stick ...; " \
+ "usb start && fatload usb 0 0x80000000 updateubootusb.img && source\0" \
+"netupdate=echo Updating UBOOT from Network (TFTP) ...; " \
+ "setenv autoload 0; " \
+ "dhcp && tftp 0x80000000 updateUBOOT.img && source;\0" \
+NANDARGS \
+MMCARGS
#endif /* !CONFIG_SPL_BUILD*/
#define CONFIG_BOOTCOMMAND \
- "run mmcboot1;"
-#define CONFIG_BOOTDELAY 1 /* TODO: für release auf 0 setzen */
+ "run defboot;"
+#define CONFIG_BOOTDELAY 0
#ifdef CONFIG_NAND
/*
@@ -260,6 +311,10 @@
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_FAT
#define CONFIG_FAT_WRITE
+#define CONFIG_FS_EXT4
+#define CONFIG_EXT4_WRITE
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FS_GENERIC
#endif /* CONFIG_MMC, ... */
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
index 7fb28a54ba..e6cd8819dd 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -29,8 +29,6 @@
/*#define CONFIG_ARMV8_SWITCH_TO_EL1*/
-#define CONFIG_SYS_NO_FLASH
-
#define CONFIG_SUPPORT_RAW_INITRD
/* Cache Definitions */
@@ -56,7 +54,6 @@
/* Flat Device Tree Definitions */
#define CONFIG_OF_LIBFDT
-
/* SMP Spin Table Definitions */
#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
@@ -79,13 +76,6 @@
#define V2M_BASE 0x80000000
-/*
- * Physical addresses, offset from V2M_PA_CS0-3
- */
-#define V2M_NOR0 (V2M_PA_CS0)
-#define V2M_NOR1 (V2M_PA_CS4)
-#define V2M_SRAM (V2M_PA_CS1)
-
/* Common peripherals relative to CS7. */
#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
@@ -146,9 +136,17 @@
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
-/* SMSC91C111 Ethernet Configuration */
+/* Ethernet Configuration */
+#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
+/* The real hardware Versatile express uses SMSC9118 */
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_32_BIT 1
+#define CONFIG_SMC911X_BASE (0x018000000)
+#else
+/* The Vexpress64 simulators use SMSC91C111 */
#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE (0x01A000000)
+#endif
/* PL011 Serial Configuration */
#define CONFIG_PL011_SERIAL
@@ -175,7 +173,6 @@
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PXE
#define CONFIG_CMD_ENV
-#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_MEMORY
@@ -237,7 +234,7 @@
"fdt_addr_r=0x83000000\0" \
"fdt_high=0xa0000000\0"
-#define CONFIG_BOOTARGS "console=ttyAMA0 root=/dev/ram0"
+#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 root=/dev/ram0"
#define CONFIG_BOOTCOMMAND "bootm $kernel_addr_r " \
"$initrd_addr_r:$initrd_size $fdt_addr_r"
#define CONFIG_BOOTDELAY -1
@@ -258,4 +255,27 @@
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_MAXARGS 64 /* max command args */
+/* Flash memory is available on the Juno board only */
+#ifndef CONFIG_TARGET_VEXPRESS64_JUNO
+#define CONFIG_SYS_NO_FLASH
+#else
+#define CONFIG_CMD_FLASH
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_BASE 0x08000000
+#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MiB */
+#define CONFIG_SYS_MAX_FLASH_BANKS 2
+
+/* Timeout values in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */
+#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */
+
+/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
+#define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
+#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
+
+#endif
+
#endif /* __VEXPRESS_AEMV8A_H */
diff --git a/include/configs/x600.h b/include/configs/x600.h
index 04187c0a31..241bf65f30 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -16,6 +16,7 @@
*/
#define CONFIG_SPEAR600 /* SPEAr600 SoC */
#define CONFIG_X600 /* on X600 board */
+#define CONFIG_SYS_GENERIC_BOARD
#include <asm/arch/hardware.h>
diff --git a/include/e500.h b/include/e500.h
index 5884a224d2..255f46bf1e 100644
--- a/include/e500.h
+++ b/include/e500.h
@@ -11,6 +11,9 @@
typedef struct
{
unsigned long freq_processor[CONFIG_MAX_CPUS];
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+ unsigned long freq_processor_dsp[CONFIG_MAX_DSP_CPUS];
+#endif
unsigned long freq_systembus;
unsigned long freq_ddrbus;
unsigned long freq_localbus;
@@ -24,6 +27,14 @@ typedef struct
#ifdef CONFIG_SYS_DPAA_PME
unsigned long freq_pme;
#endif
+#ifdef CONFIG_SYS_CPRI
+ unsigned long freq_cpri;
+#endif
+#ifdef CONFIG_SYS_MAPLE
+ unsigned long freq_maple;
+ unsigned long freq_maple_ulb;
+ unsigned long freq_maple_etvpe;
+#endif
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
unsigned char diff_sysclk;
#endif
diff --git a/include/fsl_sec_mon.h b/include/fsl_sec_mon.h
new file mode 100644
index 0000000000..b6794cefcc
--- /dev/null
+++ b/include/fsl_sec_mon.h
@@ -0,0 +1,58 @@
+/*
+ * Common internal memory map for some Freescale SoCs
+ *
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_SEC_MON_H
+#define __FSL_SEC_MON_H
+
+#include <common.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_SYS_FSL_SEC_MON_LE
+#define sec_mon_in32(a) in_le32(a)
+#define sec_mon_out32(a, v) out_le32(a, v)
+#define sec_mon_in16(a) in_le16(a)
+#define sec_mon_clrbits32 clrbits_le32
+#define sec_mon_setbits32 setbits_le32
+#elif defined(CONFIG_SYS_FSL_SEC_MON_BE)
+#define sec_mon_in32(a) in_be32(a)
+#define sec_mon_out32(a, v) out_be32(a, v)
+#define sec_mon_in16(a) in_be16(a)
+#define sec_mon_clrbits32 clrbits_be32
+#define sec_mon_setbits32 setbits_be32
+#else
+#error Neither CONFIG_SYS_FSL_SEC_MON_LE nor CONFIG_SYS_FSL_SEC_MON_BE defined
+#endif
+
+struct ccsr_sec_mon_regs {
+ u8 reserved0[0x04];
+ u32 hp_com; /* 0x04 SEC_MON_HP Command Register */
+ u8 reserved2[0x0c];
+ u32 hp_stat; /* 0x08 SEC_MON_HP Status Register */
+};
+
+#define HPCOMR_SW_SV 0x100 /* Security Violation bit */
+#define HPCOMR_SW_FSV 0x200 /* Fatal Security Violation bit */
+#define HPCOMR_SSM_ST 0x1 /* SSM_ST field in SEC_MON command */
+#define HPSR_SSM_ST_CHECK 0x900 /* SEC_MON is in check state */
+#define HPSR_SSM_ST_NON_SECURE 0xb00 /* SEC_MON is in non secure state */
+#define HPSR_SSM_ST_TRUST 0xd00 /* SEC_MON is in trusted state */
+#define HPSR_SSM_ST_SOFT_FAIL 0x300 /* SEC_MON is in soft fail state */
+#define HPSR_SSM_ST_MASK 0xf00 /* Mask for SSM_ST field */
+
+/*
+ * SEC_MON read. This specifies the possible reads
+ * from the SEC_MON
+ */
+enum {
+ SEC_MON_SSM_ST,
+ SEC_MON_SW_FSV,
+ SEC_MON_SW_SV,
+};
+
+int change_sec_mon_state(uint32_t initial_state, uint32_t final_state);
+
+#endif /* __FSL_SEC_MON_H */
diff --git a/include/fsl_secboot_err.h b/include/fsl_secboot_err.h
new file mode 100644
index 0000000000..afc50a80ca
--- /dev/null
+++ b/include/fsl_secboot_err.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _FSL_SECBOOT_ERR_H
+#define _FSL_SECBOOT_ERR_H
+
+#define ERROR_ESBC_PAMU_INIT 0x100000
+#define ERROR_ESBC_SEC_RESET 0x200000
+#define ERROR_ESBC_SEC_INIT 0x400000
+#define ERROR_ESBC_SEC_DEQ 0x800000
+#define ERROR_ESBC_SEC_DEQ_TO 0x1000000
+#define ERROR_ESBC_SEC_ENQ 0x2000000
+#define ERROR_ESBC_SEC_JOBQ_STATUS 0x4000000
+#define ERROR_ESBC_CLIENT_CPUID_NO_MATCH 0x1
+#define ERROR_ESBC_CLIENT_HDR_LOC 0x2
+#define ERROR_ESBC_CLIENT_HEADER_BARKER 0x4
+#define ERROR_ESBC_CLIENT_HEADER_KEY_LEN 0x8
+#define ERROR_ESBC_CLIENT_HEADER_SIG_LEN 0x10
+#define ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED 0x11
+#define ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY 0x12
+#define ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM 0x13
+#define ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN 0x14
+#define ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED 0x15
+#define ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY 0x16
+#define ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM 0x17
+#define ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN 0x18
+#define ERROR_IE_TABLE_NOT_FOUND 0x19
+#define ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN 0x20
+#define ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1 0x40
+#define ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2 0x80
+#define ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD 0x100
+#define ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP 0x200
+#define ERROR_ESBC_CLIENT_HASH_COMPARE_KEY 0x400
+#define ERROR_ESBC_CLIENT_HASH_COMPARE_EM 0x800
+#define ERROR_ESBC_CLIENT_SSM_TRUSTSTS 0x1000
+#define ERROR_ESBC_CLIENT_BAD_ADDRESS 0x2000
+#define ERROR_ESBC_CLIENT_MISC 0x4000
+#define ERROR_ESBC_CLIENT_HEADER_SG_ENTIRES_BAD 0x8000
+#define ERROR_ESBC_CLIENT_HEADER_SG 0x10000
+#define ERROR_ESBC_CLIENT_HEADER_IMG_SIZE 0x20000
+#define ERROR_ESBC_WRONG_CMD 0x40000
+#define ERROR_ESBC_MISSING_BOOTM 0x80000
+#define ERROR_ESBC_CLIENT_MAX 0x0
+
+struct fsl_secboot_errcode {
+ int errcode;
+ const char *name;
+};
+
+static const struct fsl_secboot_errcode fsl_secboot_errcodes[] = {
+ { ERROR_ESBC_PAMU_INIT,
+ "Error in initializing PAMU"},
+ { ERROR_ESBC_SEC_RESET,
+ "Error in resetting Job ring of SEC"},
+ { ERROR_ESBC_SEC_INIT,
+ "Error in initializing SEC"},
+ { ERROR_ESBC_SEC_ENQ,
+ "Error in enqueue operation by SEC"},
+ { ERROR_ESBC_SEC_DEQ_TO,
+ "Dequeue operation by SEC is timed out"},
+ { ERROR_ESBC_SEC_DEQ,
+ "Error in dequeue operation by SEC"},
+ { ERROR_ESBC_SEC_JOBQ_STATUS,
+ "Error in status of the job submitted to SEC"},
+ { ERROR_ESBC_CLIENT_CPUID_NO_MATCH,
+ "Current core is not boot core i.e core0" },
+ { ERROR_ESBC_CLIENT_HDR_LOC,
+ "Header address not in allowed memory range" },
+ { ERROR_ESBC_CLIENT_HEADER_BARKER,
+ "Wrong barker code in header" },
+ { ERROR_ESBC_CLIENT_HEADER_KEY_LEN,
+ "Wrong public key length in header" },
+ { ERROR_ESBC_CLIENT_HEADER_SIG_LEN,
+ "Wrong signature length in header" },
+ { ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN,
+ "Public key length not twice of signature length" },
+ { ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1,
+ "Public key Modulus most significant bit not set" },
+ { ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2,
+ "Public key Modulus in header not odd" },
+ { ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD,
+ "Signature not less than modulus" },
+ { ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP,
+ "Entry point not in allowed space or one of the SG entries" },
+ { ERROR_ESBC_CLIENT_HASH_COMPARE_KEY,
+ "Public key hash comparison failed" },
+ { ERROR_ESBC_CLIENT_HASH_COMPARE_EM,
+ "RSA verification failed" },
+ { ERROR_ESBC_CLIENT_SSM_TRUSTSTS,
+ "SNVS not in TRUSTED state" },
+ { ERROR_ESBC_CLIENT_BAD_ADDRESS,
+ "Bad address error" },
+ { ERROR_ESBC_CLIENT_MISC,
+ "Miscallaneous error" },
+ { ERROR_ESBC_CLIENT_HEADER_SG,
+ "No SG support" },
+ { ERROR_ESBC_CLIENT_HEADER_IMG_SIZE,
+ "Invalid Image size" },
+ { ERROR_ESBC_WRONG_CMD,
+ "Unknown cmd/Wrong arguments. Core in infinite loop"},
+ { ERROR_ESBC_MISSING_BOOTM,
+ "Bootm command missing from bootscript" },
+ { ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED,
+ "Selected key is revoked" },
+ { ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY,
+ "Wrong key entry" },
+ { ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM,
+ "Wrong key is selected" },
+ { ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN,
+ "Wrong srk public key len in header" },
+ { ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED,
+ "Selected IE key is revoked" },
+ { ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY,
+ "Wrong key entry in IE Table" },
+ { ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM,
+ "Wrong IE key is selected" },
+ { ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN,
+ "Wrong IE public key len in header" },
+ { ERROR_IE_TABLE_NOT_FOUND,
+ "Information about IE Table missing" },
+ { ERROR_ESBC_CLIENT_MAX, "NULL" }
+};
+
+void fsl_secboot_handle_error(int error);
+#endif
diff --git a/include/fsl_sfp.h b/include/fsl_sfp.h
new file mode 100644
index 0000000000..353a123ee5
--- /dev/null
+++ b/include/fsl_sfp.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _FSL_SFP_SNVS_
+#define _FSL_SFP_SNVS_
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_SYS_FSL_SRK_LE
+#define srk_in32(a) in_le32(a)
+#else
+#define srk_in32(a) in_be32(a)
+#endif
+
+#ifdef CONFIG_SYS_FSL_SFP_LE
+#define sfp_in32(a) in_le32(a)
+#define sfp_out32(a, v) out_le32(a, v)
+#define sfp_in16(a) in_le16(a)
+#elif defined(CONFIG_SYS_FSL_SFP_BE)
+#define sfp_in32(a) in_be32(a)
+#define sfp_out32(a, v) out_be32(a, v)
+#define sfp_in16(a) in_be16(a)
+#else
+#error Neither CONFIG_SYS_FSL_SFP_LE nor CONFIG_SYS_FSL_SFP_BE is defined
+#endif
+
+/* Number of SRKH registers */
+#define NUM_SRKH_REGS 8
+
+#ifdef CONFIG_SYS_FSL_SFP_VER_3_2
+struct ccsr_sfp_regs {
+ u32 ospr; /* 0x200 */
+ u32 ospr1; /* 0x204 */
+ u32 reserved1[4];
+ u32 fswpr; /* 0x218 FSL Section Write Protect */
+ u32 fsl_uid; /* 0x21c FSL UID 0 */
+ u32 fsl_uid_1; /* 0x220 FSL UID 0 */
+ u32 reserved2[12];
+ u32 srk_hash[8]; /* 0x254 Super Root Key Hash */
+ u32 oem_uid; /* 0x274 OEM UID 0*/
+ u32 oem_uid_1; /* 0x278 OEM UID 1*/
+ u32 oem_uid_2; /* 0x27c OEM UID 2*/
+ u32 oem_uid_3; /* 0x280 OEM UID 3*/
+ u32 oem_uid_4; /* 0x284 OEM UID 4*/
+ u32 reserved3[8];
+};
+#elif defined(CONFIG_SYS_FSL_SFP_VER_3_0)
+struct ccsr_sfp_regs {
+ u32 ospr; /* 0x200 */
+ u32 reserved0[14];
+ u32 srk_hash[NUM_SRKH_REGS]; /* 0x23c Super Root Key Hash */
+ u32 oem_uid; /* 0x9c OEM Unique ID */
+ u8 reserved2[0x04];
+ u32 ovpr; /* 0xA4 Intent To Secure */
+ u8 reserved4[0x08];
+ u32 fsl_uid; /* 0xB0 FSL Unique ID */
+ u8 reserved5[0x04];
+ u32 fsl_spfr0; /* Scratch Pad Fuse Register 0 */
+ u32 fsl_spfr1; /* Scratch Pad Fuse Register 1 */
+
+};
+#else
+struct ccsr_sfp_regs {
+ u8 reserved0[0x40];
+ u32 ospr; /* 0x40 OEM Security Policy Register */
+ u8 reserved2[0x38];
+ u32 srk_hash[8]; /* 0x7c Super Root Key Hash */
+ u32 oem_uid; /* 0x9c OEM Unique ID */
+ u8 reserved4[0x4];
+ u32 ovpr; /* 0xA4 OEM Validation Policy Register */
+ u8 reserved8[0x8];
+ u32 fsl_uid; /* 0xB0 FSL Unique ID */
+};
+#endif
+#define ITS_MASK 0x00000004
+#define ITS_BIT 2
+#define OSPR_KEY_REVOC_SHIFT 13
+#define OSPR_KEY_REVOC_MASK 0x0000e000
+
+#endif
diff --git a/include/fsl_validate.h b/include/fsl_validate.h
new file mode 100644
index 0000000000..c4605349a6
--- /dev/null
+++ b/include/fsl_validate.h
@@ -0,0 +1,199 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _FSL_VALIDATE_H_
+#define _FSL_VALIDATE_H_
+
+#include <fsl_sec.h>
+#include <fsl_sec_mon.h>
+#include <command.h>
+#include <linux/types.h>
+
+#define WORD_SIZE 4
+
+/* Minimum and maximum size of RSA signature length in bits */
+#define KEY_SIZE 4096
+#define KEY_SIZE_BYTES (KEY_SIZE/8)
+#define KEY_SIZE_WORDS (KEY_SIZE_BYTES/(WORD_SIZE))
+
+extern struct jobring jr;
+
+#ifdef CONFIG_KEY_REVOCATION
+/* Srk table and key revocation check */
+#define SRK_FLAG 0x01
+#define UNREVOCABLE_KEY 4
+#define ALIGN_REVOC_KEY 3
+#define MAX_KEY_ENTRIES 4
+#endif
+
+/* Barker code size in bytes */
+#define ESBC_BARKER_LEN 4 /* barker code length in ESBC uboot client */
+ /* header */
+
+/* No-error return values */
+#define ESBC_VALID_HDR 0 /* header is valid */
+
+/* Maximum number of SG entries allowed */
+#define MAX_SG_ENTRIES 8
+
+/*
+ * ESBC uboot client header structure.
+ * The struct contain the following fields
+ * barker code
+ * public key offset
+ * pub key length
+ * signature offset
+ * length of the signature
+ * ptr to SG table
+ * no of entries in SG table
+ * esbc ptr
+ * size of esbc
+ * esbc entry point
+ * Scatter gather flag
+ * UID flag
+ * FSL UID
+ * OEM UID
+ * Here, pub key is modulus concatenated with exponent
+ * of equal length
+ */
+struct fsl_secboot_img_hdr {
+ u8 barker[ESBC_BARKER_LEN]; /* barker code */
+ union {
+ u32 pkey; /* public key offset */
+#ifdef CONFIG_KEY_REVOCATION
+ u32 srk_tbl_off;
+#endif
+ };
+
+ union {
+ u32 key_len; /* pub key length in bytes */
+#ifdef CONFIG_KEY_REVOCATION
+ struct {
+ u32 srk_table_flag:8;
+ u32 srk_sel:8;
+ u32 num_srk:16;
+ } len_kr;
+#endif
+ };
+
+ u32 psign; /* signature offset */
+ u32 sign_len; /* length of the signature in bytes */
+ union {
+ struct fsl_secboot_sg_table *psgtable; /* ptr to SG table */
+ u8 *pimg; /* ptr to ESBC client image */
+ };
+ union {
+ u32 sg_entries; /* no of entries in SG table */
+ u32 img_size; /* ESBC client image size in bytes */
+ };
+ ulong img_start; /* ESBC client entry point */
+ u32 sg_flag; /* Scatter gather flag */
+ u32 uid_flag;
+ u32 fsl_uid_0;
+ u32 oem_uid_0;
+ u32 reserved1[2];
+ u32 fsl_uid_1;
+ u32 oem_uid_1;
+ u32 reserved2[2];
+ u32 ie_flag;
+ u32 ie_key_sel;
+};
+
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+struct ie_key_table {
+ u32 key_len;
+ u8 pkey[2 * KEY_SIZE_BYTES];
+};
+
+struct ie_key_info {
+ uint32_t key_revok;
+ uint32_t num_keys;
+ struct ie_key_table ie_key_tbl[32];
+};
+#endif
+
+#ifdef CONFIG_KEY_REVOCATION
+struct srk_table {
+ u32 key_len;
+ u8 pkey[2 * KEY_SIZE_BYTES];
+};
+#endif
+
+/*
+ * SG table.
+ */
+#if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET)
+/*
+ * This struct contains the following fields
+ * length of the segment
+ * source address
+ */
+struct fsl_secboot_sg_table {
+ u32 len; /* length of the segment in bytes */
+ ulong src_addr; /* ptr to the data segment */
+};
+#else
+/*
+ * This struct contains the following fields
+ * length of the segment
+ * Destination Target ID
+ * source address
+ * destination address
+ */
+struct fsl_secboot_sg_table {
+ u32 len;
+ u32 trgt_id;
+ ulong src_addr;
+ ulong dst_addr;
+};
+#endif
+
+/*
+ * ESBC private structure.
+ * Private structure used by ESBC to store following fields
+ * ESBC client key
+ * ESBC client key hash
+ * ESBC client Signature
+ * Encoded hash recovered from signature
+ * Encoded hash of ESBC client header plus ESBC client image
+ */
+struct fsl_secboot_img_priv {
+ uint32_t hdr_location;
+ ulong ie_addr;
+ u32 key_len;
+ struct fsl_secboot_img_hdr hdr;
+
+ u8 img_key[2 * KEY_SIZE_BYTES]; /* ESBC client key */
+ u8 img_key_hash[32]; /* ESBC client key hash */
+
+#ifdef CONFIG_KEY_REVOCATION
+ struct srk_table srk_tbl[MAX_KEY_ENTRIES];
+#endif
+ u8 img_sign[KEY_SIZE_BYTES]; /* ESBC client signature */
+
+ u8 img_encoded_hash[KEY_SIZE_BYTES]; /* EM wrt RSA PKCSv1.5 */
+ /* Includes hash recovered after
+ * signature verification
+ */
+
+ u8 img_encoded_hash_second[KEY_SIZE_BYTES];/* EM' wrt RSA PKCSv1.5 */
+ /* Includes hash of
+ * ESBC client header plus
+ * ESBC client image
+ */
+
+ struct fsl_secboot_sg_table sgtbl[MAX_SG_ENTRIES]; /* SG table */
+ u32 ehdrloc; /* ESBC client location */
+};
+
+int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[]);
+int fsl_secboot_blob_encap(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[]);
+int fsl_secboot_blob_decap(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[]);
+
+#endif
diff --git a/include/linux/linkage.h b/include/linux/linkage.h
index 5797498adc..efb04eeed4 100644
--- a/include/linux/linkage.h
+++ b/include/linux/linkage.h
@@ -11,6 +11,11 @@
#include <asm/linkage.h>
+/* Some toolchains use other characters (e.g. '`') to mark new line in macro */
+#ifndef ASM_NL
+#define ASM_NL ;
+#endif
+
#ifdef __cplusplus
#define CPP_ASMLINKAGE extern "C"
#else
@@ -43,15 +48,15 @@
#define ALIGN_STR __ALIGN_STR
#define LENTRY(name) \
- ALIGN; \
+ ALIGN ASM_NL \
SYMBOL_NAME_LABEL(name)
#define ENTRY(name) \
- .globl SYMBOL_NAME(name); \
+ .globl SYMBOL_NAME(name) ASM_NL \
LENTRY(name)
#define WEAK(name) \
- .weak SYMBOL_NAME(name); \
+ .weak SYMBOL_NAME(name) ASM_NL \
LENTRY(name)
#ifndef END
@@ -61,7 +66,7 @@
#ifndef ENDPROC
#define ENDPROC(name) \
- .type name STT_FUNC; \
+ .type name STT_FUNC ASM_NL \
END(name)
#endif
diff --git a/include/power/tps65217.h b/include/power/tps65217.h
index 297c4cbd99..93cbe36c47 100644
--- a/include/power/tps65217.h
+++ b/include/power/tps65217.h
@@ -73,6 +73,7 @@ enum {
#define TPS65217_LDO_VOLTAGE_OUT_1_8 0x06
#define TPS65217_LDO_VOLTAGE_OUT_3_3 0x1F
+#define TPS65217_PWR_OFF 0x80
#define TPS65217_PWR_SRC_USB_BITMASK 0x4
#define TPS65217_PWR_SRC_AC_BITMASK 0x8
diff --git a/include/stdio_dev.h b/include/stdio_dev.h
index 24da23fe50..95d6246f59 100644
--- a/include/stdio_dev.h
+++ b/include/stdio_dev.h
@@ -23,7 +23,7 @@
struct stdio_dev {
int flags; /* Device flags: input/output/system */
int ext; /* Supported extensions */
- char name[16]; /* Device name */
+ char name[32]; /* Device name */
/* GENERAL functions */
generated by cgit (git 2.34.1) at 2025-02-11 21:23:21 +0000