diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/common.h | 5 | ||||
| -rw-r--r-- | include/configs/calimain.h | 3 | ||||
| -rw-r--r-- | include/configs/edb93xx.h | 292 | ||||
| -rw-r--r-- | include/configs/h2200.h | 1 | ||||
| -rw-r--r-- | include/configs/integrator-common.h | 1 | ||||
| -rw-r--r-- | include/configs/ls2085a_common.h | 226 | ||||
| -rw-r--r-- | include/configs/ls2085a_emu.h | 19 | ||||
| -rw-r--r-- | include/configs/ls2085a_simu.h | 16 | ||||
| -rw-r--r-- | include/configs/rpi_b.h | 1 | ||||
| -rw-r--r-- | include/configs/socfpga_cyclone5.h | 15 | ||||
| -rw-r--r-- | include/configs/vexpress_aemv8a.h | 63 | ||||
| -rw-r--r-- | include/fdt_support.h | 14 | ||||
| -rw-r--r-- | include/fsl_mc.h | 59 |
13 files changed, 701 insertions, 14 deletions
diff --git a/include/common.h b/include/common.h index cc74633df5..2e5a6d3d2f 100644 --- a/include/common.h +++ b/include/common.h @@ -687,9 +687,6 @@ ulong get_PERCLK3(void); ulong get_bus_freq (ulong); int get_serial_clock(void); -#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) -ulong get_ddr_freq(ulong); -#endif #if defined(CONFIG_MPC85xx) typedef MPC85xx_SYS_INFO sys_info_t; void get_sys_info ( sys_info_t * ); @@ -705,6 +702,8 @@ static inline ulong get_ddr_freq(ulong dummy) { return get_bus_freq(dummy); } +#else +ulong get_ddr_freq(ulong); #endif #if defined(CONFIG_4xx) diff --git a/include/configs/calimain.h b/include/configs/calimain.h index febee45b3b..b27f973896 100644 --- a/include/configs/calimain.h +++ b/include/configs/calimain.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 OMICRON electronics GmbH + * Copyright (C) 2011-2014 OMICRON electronics GmbH * * Based on da850evm.h. Original Copyrights follow: * @@ -18,6 +18,7 @@ #define CONFIG_DRIVER_TI_EMAC #define MACH_TYPE_CALIMAIN 3528 #define CONFIG_MACH_TYPE MACH_TYPE_CALIMAIN +#define CONFIG_SYS_GENERIC_BOARD /* * SoC Configuration diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h new file mode 100644 index 0000000000..37bdcc0f33 --- /dev/null +++ b/include/configs/edb93xx.h @@ -0,0 +1,292 @@ +/* + * U-boot - Configuration file for Cirrus Logic EDB93xx boards + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#ifdef CONFIG_MK_edb9301 +#define CONFIG_EDB9301 +#elif defined(CONFIG_MK_edb9302) +#define CONFIG_EDB9302 +#elif defined(CONFIG_MK_edb9302a) +#define CONFIG_EDB9302A +#elif defined(CONFIG_MK_edb9307) +#define CONFIG_EDB9307 +#elif defined(CONFIG_MK_edb9307a) +#define CONFIG_EDB9307A +#elif defined(CONFIG_MK_edb9312) +#define CONFIG_EDB9312 +#elif defined(CONFIG_MK_edb9315) +#define CONFIG_EDB9315 +#elif defined(CONFIG_MK_edb9315a) +#define CONFIG_EDB9315A +#else +#error "no board defined" +#endif + +/* Initial environment and monitor configuration options. */ +#define CONFIG_BOOTDELAY 2 +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_BOOTARGS "root=/dev/nfs console=ttyAM0,115200 ip=dhcp" +#define CONFIG_BOOTFILE "edb93xx.img" + +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + + +#define CONFIG_SYS_LDSCRIPT "board/cirrus/edb93xx/u-boot.lds" + + +#ifdef CONFIG_EDB9301 +#define CONFIG_EP9301 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9301 +#define CONFIG_SYS_PROMPT "EDB9301> " +#define CONFIG_ENV_SECT_SIZE 0x00020000 +#elif defined(CONFIG_EDB9302) +#define CONFIG_EP9302 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302 +#define CONFIG_SYS_PROMPT "EDB9302> " +#define CONFIG_ENV_SECT_SIZE 0x00020000 +#elif defined(CONFIG_EDB9302A) +#define CONFIG_EP9302 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302A +#define CONFIG_SYS_PROMPT "EDB9302A> " +#define CONFIG_ENV_SECT_SIZE 0x00020000 +#elif defined(CONFIG_EDB9307) +#define CONFIG_EP9307 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307 +#define CONFIG_SYS_PROMPT "EDB9307> " +#define CONFIG_ENV_SECT_SIZE 0x00040000 +#elif defined(CONFIG_EDB9307A) +#define CONFIG_EP9307 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307A +#define CONFIG_SYS_PROMPT "EDB9307A> " +#define CONFIG_ENV_SECT_SIZE 0x00020000 +#elif defined(CONFIG_EDB9312) +#define CONFIG_EP9312 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9312 +#define CONFIG_SYS_PROMPT "EDB9312> " +#define CONFIG_ENV_SECT_SIZE 0x00040000 +#elif defined(CONFIG_EDB9315) +#define CONFIG_EP9315 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315 +#define CONFIG_SYS_PROMPT "EDB9315> " +#define CONFIG_ENV_SECT_SIZE 0x00040000 +#elif defined(CONFIG_EDB9315A) +#define CONFIG_EP9315 +#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315A +#define CONFIG_SYS_PROMPT "EDB9315A> " +#define CONFIG_ENV_SECT_SIZE 0x00020000 +#else +#error "no board defined" +#endif + +/* High-level configuration options */ +#define CONFIG_ARM920T 1 /* This is an ARM920T core... */ +#define CONFIG_EP93XX 1 /* in a Cirrus Logic 93xx SoC */ + +#define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */ +#define CONFIG_SYS_HZ 1000 /* decr freq: 1 ms ticks */ +#undef CONFIG_USE_IRQ /* Don't need IRQ/FIQ */ + +/* Monitor configuration */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG + +#undef CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_JFFS2 + +#define CONFIG_SYS_LONGHELP /* Enable "long" help in mon */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +/* Print buffer size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +/* Boot argument buffer size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ + +/* Serial port hardware configuration */ +#define CONFIG_PL010_SERIAL +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, \ + 115200, 230400} +#define CONFIG_SYS_SERIAL0 0x808C0000 +#define CONFIG_SYS_SERIAL1 0x808D0000 +/*#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1} */ + +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0} + +/* Status LED */ +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED 1 +#define STATUS_LED_GREEN 0 +#define STATUS_LED_RED 1 +/* Green */ +#define STATUS_LED_BIT STATUS_LED_GREEN +#define STATUS_LED_STATE STATUS_LED_ON +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) +/* Red */ +#define STATUS_LED_BIT1 STATUS_LED_RED +#define STATUS_LED_STATE1 STATUS_LED_OFF +#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) +/* Optional value */ +#define STATUS_LED_BOOT STATUS_LED_BIT + +/* Network hardware configuration */ +#define CONFIG_DRIVER_EP93XX_MAC +#define CONFIG_MII_SUPPRESS_PREAMBLE +#define CONFIG_MII +#define CONFIG_PHY_ADDR 1 +#define CONFIG_NET_MULTI +#undef CONFIG_NETCONSOLE + +/* SDRAM configuration */ +#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \ + defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || \ + defined(CONFIG_EDB9315) +/* + * EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75 + * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set + * the SROMLL bit on the processor, resulting in this non-contiguous memory map. + * + * The EDB9307, EDB9312, and EDB9315 have 2 banks of SDRAM consisting of + * 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of + * 64 MB of SDRAM. + */ + +#define CONFIG_EDB93XX_SDCS3 + +#elif defined(CONFIG_EDB9302A) || \ + defined(CONFIG_EDB9307A) || defined(CONFIG_EDB9315A) +/* + * EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75 + * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set + * the SROMLL bit on the processor, resulting in this non-contiguous memory map. + * + * The EDB9307A and EDB9315A have 2 banks of SDRAM consisting of 2x Samsung + * K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of SDRAM. + */ +#define CONFIG_EDB93XX_SDCS0 + +#else +#error "no SDCS configuration for this board" +#endif + + +#if defined(CONFIG_EDB93XX_SDCS3) +#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* Default load address */ +#define PHYS_SDRAM_1 0x00000000 +#elif defined(CONFIG_EDB93XX_SDCS0) +#define CONFIG_SYS_LOAD_ADDR 0xc1000000 /* Default load address */ +#define PHYS_SDRAM_1 0xc0000000 +#endif + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_NR_DRAM_BANKS 8 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 32*1024 - GENERATED_GBL_DATA_SIZE) + + +/* Must match kernel config */ +#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) + +/* Run-time memory allocatons */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_STACKSIZE (128 * 1024) + +#if defined(CONFIG_USE_IRQ) +#define CONFIG_STACKSIZE_IRQ (4 * 1024) +#define CONFIG_STACKSIZE_FIQ (4 * 1024) +#endif + +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) + +/* ----------------------------------------------------------------------------- + * FLASH and environment organization + * + * The EDB9301, EDB9302(a), EDB9307a, EDB9315a have 1 bank of flash memory at + * 0x60000000 consisting of 1x Intel TE28F128J3C-150 128 Mbit flash on a 16-bit + * data bus, for a total of 16 MB of CFI-compatible flash. + * + * The EDB9307, EDB9312, and EDB9315 have 1 bank of flash memory at + * 0x60000000 consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a 32-bit + * data bus, for a total of 32 MB of CFI-compatible flash. + * + * + * EDB9301/02(a)7a/15a EDB9307/12/15 + * 0x60000000 - 0x0003FFFF u-boot u-boot + * 0x60040000 - 0x0005FFFF environment #1 environment #1 + * 0x60060000 - 0x0007FFFF environment #2 environment #1 (continued) + * 0x60080000 - 0x0009FFFF unused environment #2 + * 0x600A0000 - 0x000BFFFF unused environment #2 (continued) + * 0x600C0000 - 0x00FFFFFF unused unused + * 0x61000000 - 0x01FFFFFF not present unused + */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + + +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT (256+8) + +#define CONFIG_SYS_TEXT_BASE 0x60000000 +#define PHYS_FLASH_1 CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) + +#define CONFIG_ENV_OVERWRITE /* Vendor params unprotected */ +#define CONFIG_ENV_IS_IN_FLASH + +#define CONFIG_ENV_ADDR 0x60040000 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) + +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +/* Define to enable MMC on SPI support */ +/* #define CONFIG_EP93XX_SPI_MMC */ + +#ifdef CONFIG_EP93XX_SPI_MMC +#define CONFIG_EP93XX_SPI +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC_SPI +#define CONFIG_CMD_MMC +#define CONFIG_MMC_SPI_NPOWER_EGPIO 9 +#endif + +#define CONFIG_USB_STORAGE +#define CONFIG_USB_OHCI_NEW +#define CONFIG_USB_OHCI_EP93XX +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ep93xx-ohci" +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80020000 + +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_USB + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_CMD_BOOTZ + +/* Define to disable flash configuration*/ +/* #define CONFIG_EP93XX_NO_FLASH_CFG */ + +/* Define this for indusrial rated chips */ +/* #define CONFIG_EDB93XX_INDUSTRIAL */ + +#endif /* !defined (__CONFIG_H) */ diff --git a/include/configs/h2200.h b/include/configs/h2200.h index d02648420f..5d0b85e431 100644 --- a/include/configs/h2200.h +++ b/include/configs/h2200.h @@ -12,6 +12,7 @@ #define MACH_TYPE_H2200 341 #define CONFIG_MACH_TYPE MACH_TYPE_H2200 +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_CPU_PXA25X 1 #define CONFIG_BOARD_H2200 diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h index 267a92b2d0..eac517aeeb 100644 --- a/include/configs/integrator-common.h +++ b/include/configs/integrator-common.h @@ -26,6 +26,7 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_OF_LIBFDT /* enable passing a Device Tree */ #define CONFIG_MISC_INIT_R /* call misc_init_r during start up */ +#define CONFIG_SYS_GENERIC_BOARD /* * There are various dependencies on the core module (CM) fitted diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h new file mode 100644 index 0000000000..2bd5a472b3 --- /dev/null +++ b/include/configs/ls2085a_common.h @@ -0,0 +1,226 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS2_COMMON_H +#define __LS2_COMMON_H + +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_REMAKE_ELF +#define CONFIG_FSL_LSCH3 +#define CONFIG_LS2085A +#define CONFIG_GICV3 + +/* Link Definitions */ +#define CONFIG_SYS_TEXT_BASE 0x30000000 + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SUPPORT_RAW_INITRD + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F 1 + +#define CONFIG_IDENT_STRING " LS2085A-EMU" +#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-EMU" + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#ifndef CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ +#define CONFIG_SYS_DDR_RAW_TIMING +#endif +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ + +/* SMP Definitions */ +#define CPU_RELEASE_ADDR CONFIG_SYS_INIT_SP_ADDR + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 12000000 /* 12MHz */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) + +/* I2C */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_MXC_I2C1_SPEED 40000000 +#define CONFIG_SYS_MXC_I2C2_SPEED 40000000 + +/* Serial Port */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* IFC */ +#define CONFIG_FSL_IFC +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +/* + * During booting, CS0 needs to be at the region of 0x30000000, i.e. the IFC + * address 0. But this region is limited to 256MB. To accommodate bigger NOR + * flash and other devices, we will map CS0 to 0x580000000 after relocation. + * CONFIG_SYS_FLASH_BASE has the final address (core view) + * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) + * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address + * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting + */ +#define CONFIG_SYS_FLASH_BASE 0x580000000ULL +#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 +#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 + +/* + * NOR Flash Timing Params + */ +#define CONFIG_SYS_NOR0_CSPR \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR0_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ + FTIM0_NOR_TEADC(0x1) | \ + FTIM0_NOR_TEAHC(0x1)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ + FTIM1_NOR_TRAD_NOR(0x1)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ + FTIM2_NOR_TCH(0x0) | \ + FTIM2_NOR_TWP(0x1)) +#define CONFIG_SYS_NOR_FTIM3 0x04000000 +#define CONFIG_SYS_IFC_CCR 0x01000000 + +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY +#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 + +/* MC firmware */ +#define CONFIG_FSL_MC_ENET +#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) +#define CONFIG_SYS_LS_MC_FW_IN_NOR +#define CONFIG_SYS_LS_MC_FW_ADDR 0x580200000ULL +/* TODO Actual FW length needs to be determined at runtime from FW header */ +#define CONFIG_SYS_LS_MC_FW_LENGTH (4U * 1024 * 1024) +#define CONFIG_SYS_LS_MC_DPL_IN_NOR +#define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL +/* TODO Actual DPL max length needs to be confirmed with the MC FW team */ +#define CONFIG_SYS_LS_MC_DPL_LENGTH 4096 +#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0xe00000 + +/* Carve the MC private DRAM block from the end of DRAM */ +#ifdef CONFIG_FSL_MC_ENET +#define CONFIG_SYS_MEM_TOP_HIDE mc_get_dram_block_size() +#endif + +/* Command line configuration */ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_BDI +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_IMI +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_RUN +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_SOURCE +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) + +/* Physical Memory Map */ +/* fixme: these need to be checked against the board */ +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#define CONFIG_SYS_CLK_FREQ 133333333 + + +#define CONFIG_NR_DRAM_BANKS 2 + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 128 + +#define CONFIG_DISPLAY_CPUINFO + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x581200000\0" \ + "kernel_load=0x806f0000\0" \ + "kernel_size=0x1000000\0" \ + "console=ttyAMA0,38400n8\0" + +#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ + "earlyprintk=uart8250-8bit,0x21c0600" +#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ + "$kernel_size && bootm $kernel_load" +#define CONFIG_BOOTDELAY 1 + +/* Store environment at top of flash */ +#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_SIZE 0x1000 + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PROMPT "> " +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#ifndef __ASSEMBLY__ +unsigned long mc_get_dram_block_size(void); +#endif + +#endif /* __LS2_COMMON_H */ diff --git a/include/configs/ls2085a_emu.h b/include/configs/ls2085a_emu.h new file mode 100644 index 0000000000..a5cea63b33 --- /dev/null +++ b/include/configs/ls2085a_emu.h @@ -0,0 +1,19 @@ +/* + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS2_EMU_H +#define __LS2_EMU_H + +#include "ls2085a_common.h" + +#define CONFIG_DDR_SPD +#define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */ +#define SPD_EEPROM_ADDRESS1 0x51 +#define SPD_EEPROM_ADDRESS2 0x52 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 +#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */ + +#endif /* __LS2_EMU_H */ diff --git a/include/configs/ls2085a_simu.h b/include/configs/ls2085a_simu.h new file mode 100644 index 0000000000..46d47b06e4 --- /dev/null +++ b/include/configs/ls2085a_simu.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS2_SIMU_H +#define __LS2_SIMU_H + +#include "ls2085a_common.h" + +/* SMSC 91C111 ethernet configuration */ +#define CONFIG_SMC91111 +#define CONFIG_SMC91111_BASE (0x2210000) + +#endif /* __LS2_SIMU_H */ diff --git a/include/configs/rpi_b.h b/include/configs/rpi_b.h index ed8b4dfb51..ff48598dd5 100644 --- a/include/configs/rpi_b.h +++ b/include/configs/rpi_b.h @@ -20,6 +20,7 @@ #include <linux/sizes.h> /* Architecture, CPU, etc.*/ +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_ARM1176 #define CONFIG_BCM2835 #define CONFIG_ARCH_CPU_INIT diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 0254249751..7646a857c3 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -8,6 +8,7 @@ #include <asm/arch/socfpga_base_addrs.h> #include "../../board/altera/socfpga/pinmux_config.h" +#include "../../board/altera/socfpga/iocsr_config.h" #include "../../board/altera/socfpga/pll_config.h" /* @@ -206,6 +207,17 @@ #define CONFIG_ENV_IS_NOWHERE /* + * L4 Watchdog + */ +#define CONFIG_HW_WATCHDOG +#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000 +#define CONFIG_DESIGNWARE_WATCHDOG +#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS +/* Clocks source frequency to watchdog timer */ +#define CONFIG_DW_WDT_CLOCK_KHZ 25000 + + +/* * SPL "Second Program Loader" aka Initial Software */ @@ -237,4 +249,7 @@ /* Support for lib/libgeneric.o in SPL binary */ #define CONFIG_SPL_LIBGENERIC_SUPPORT +/* Support for watchdog */ +#define CONFIG_SPL_WATCHDOG_SUPPORT + #endif /* __CONFIG_H */ diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index dff6adcc7c..1905d133e2 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -10,9 +10,20 @@ #define DEBUG +#ifdef CONFIG_BASE_FVP +#ifndef CONFIG_SEMIHOSTING +#error CONFIG_BASE_FVP requires CONFIG_SEMIHOSTING +#endif +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_ARMV8_SWITCH_TO_EL1 +#endif + #define CONFIG_REMAKE_ELF +#ifndef CONFIG_BASE_FVP +/* Base FVP not using GICv3 yet */ #define CONFIG_GICV3 +#endif /*#define CONFIG_ARMV8_SWITCH_TO_EL1*/ @@ -30,8 +41,14 @@ #define CONFIG_BOOTP_VCI_STRING "U-boot.armv8.vexpress_aemv8a" /* Link Definitions */ +#ifdef CONFIG_BASE_FVP +/* ATF loads u-boot here for BASE_FVP model */ +#define CONFIG_SYS_TEXT_BASE 0x88000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) +#else #define CONFIG_SYS_TEXT_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) +#endif /* Flat Device Tree Definitions */ #define CONFIG_OF_LIBFDT @@ -39,7 +56,11 @@ #define CONFIG_DEFAULT_DEVICE_TREE vexpress64 /* SMP Spin Table Definitions */ +#ifdef CONFIG_BASE_FVP +#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) +#else #define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) +#endif /* CS register bases for the original memory map. */ #define V2M_PA_CS0 0x00000000 @@ -99,9 +120,15 @@ #define GICD_BASE (0x2f000000) #define GICR_BASE (0x2f100000) #else + +#ifdef CONFIG_BASE_FVP +#define GICD_BASE (0x2f000000) +#define GICC_BASE (0x2c000000) +#else #define GICD_BASE (0x2C001000) #define GICC_BASE (0x2C002000) #endif +#endif #define CONFIG_SYS_MEMTEST_START V2M_BASE #define CONFIG_SYS_MEMTEST_END (V2M_BASE + 0x80000000) @@ -121,7 +148,6 @@ #define CONFIG_CONS_INDEX 0 #define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CONFIG_SYS_SERIAL0 V2M_UART0 #define CONFIG_SYS_SERIAL1 V2M_UART1 @@ -165,17 +191,41 @@ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Initial environment variables */ +#ifdef CONFIG_BASE_FVP +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_name=uImage\0" \ + "kernel_addr_r=0x80000000\0" \ + "initrd_name=ramdisk.img\0" \ + "initrd_addr_r=0x88000000\0" \ + "fdt_name=devtree.dtb\0" \ + "fdt_addr_r=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" + +#define CONFIG_BOOTARGS "console=ttyAMA0 earlyprintk=pl011,"\ + "0x1c090000 debug user_debug=31 "\ + "loglevel=9" + +#define CONFIG_BOOTCOMMAND "fdt addr $fdt_addr_r; fdt resize; " \ + "fdt chosen $initrd_addr_r $initrd_end; " \ + "bootm $kernel_addr_r - $fdt_addr_r" + +#define CONFIG_BOOTDELAY 1 + +#else + #define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr=0x200000\0" \ - "initrd_addr=0xa00000\0" \ + "kernel_addr_r=0x200000\0" \ + "initrd_addr_r=0xa00000\0" \ "initrd_size=0x2000000\0" \ - "fdt_addr=0x100000\0" \ + "fdt_addr_r=0x100000\0" \ "fdt_high=0xa0000000\0" #define CONFIG_BOOTARGS "console=ttyAMA0 root=/dev/ram0" -#define CONFIG_BOOTCOMMAND "bootm $kernel_addr " \ - "$initrd_addr:$initrd_size $fdt_addr" +#define CONFIG_BOOTCOMMAND "bootm $kernel_addr_r " \ + "$initrd_addr_r:$initrd_size $fdt_addr_r" #define CONFIG_BOOTDELAY -1 +#endif /* Do not preserve environment */ #define CONFIG_ENV_IS_NOWHERE 1 @@ -187,7 +237,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_LONGHELP #define CONFIG_CMDLINE_EDITING 1 diff --git a/include/fdt_support.h b/include/fdt_support.h index 21d7b44453..fd44d7e2f6 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -113,17 +113,25 @@ static inline int fdt_status_disabled(void *fdt, int nodeoffset) { return fdt_set_node_status(fdt, nodeoffset, FDT_STATUS_DISABLED, 0); } +static inline int fdt_status_fail(void *fdt, int nodeoffset) +{ + return fdt_set_node_status(fdt, nodeoffset, FDT_STATUS_FAIL, 0); +} -int fdt_set_status_by_alias(void *fdt, const char* alias, +int fdt_set_status_by_alias(void *fdt, const char *alias, enum fdt_status status, unsigned int error_code); -static inline int fdt_status_okay_by_alias(void *fdt, const char* alias) +static inline int fdt_status_okay_by_alias(void *fdt, const char *alias) { return fdt_set_status_by_alias(fdt, alias, FDT_STATUS_OKAY, 0); } -static inline int fdt_status_disabled_by_alias(void *fdt, const char* alias) +static inline int fdt_status_disabled_by_alias(void *fdt, const char *alias) { return fdt_set_status_by_alias(fdt, alias, FDT_STATUS_DISABLED, 0); } +static inline int fdt_status_fail_by_alias(void *fdt, const char *alias) +{ + return fdt_set_status_by_alias(fdt, alias, FDT_STATUS_FAIL, 0); +} #endif /* ifdef CONFIG_OF_LIBFDT */ diff --git a/include/fsl_mc.h b/include/fsl_mc.h new file mode 100644 index 0000000000..b9f089e5f3 --- /dev/null +++ b/include/fsl_mc.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_MC_H__ +#define __FSL_MC_H__ + +#include <common.h> + +#define MC_CCSR_BASE_ADDR \ + ((struct mc_ccsr_registers __iomem *)0x8340000) + +#define BIT(x) (1 << (x)) +#define GCR1_P1_STOP BIT(31) +#define GCR1_P2_STOP BIT(30) +#define GCR1_P1_DE_RST BIT(23) +#define GCR1_P2_DE_RST BIT(22) +#define GCR1_M1_DE_RST BIT(15) +#define GCR1_M2_DE_RST BIT(14) +#define GCR1_M_ALL_DE_RST (GCR1_M1_DE_RST | GCR1_M2_DE_RST) +#define GSR_FS_MASK 0x3fffffff +#define MCFAPR_PL_MASK (0x1 << 18) +#define MCFAPR_BMT_MASK (0x1 << 17) +#define MCFAPR_BYPASS_ICID_MASK \ + (MCFAPR_PL_MASK | MCFAPR_BMT_MASK) + +#define SOC_MC_PORTALS_BASE_ADDR ((void __iomem *)0x00080C000000) +#define SOC_MC_PORTAL_STRIDE 0x10000 + +#define SOC_MC_PORTAL_ADDR(_portal_id) \ + ((void __iomem *)((uintptr_t)SOC_MC_PORTALS_BASE_ADDR + \ + (_portal_id) * SOC_MC_PORTAL_STRIDE)) + +struct mc_ccsr_registers { + u32 reg_gcr1; + u32 reserved1; + u32 reg_gsr; + u32 reserved2; + u32 reg_sicbalr; + u32 reg_sicbahr; + u32 reg_sicapr; + u32 reserved3; + u32 reg_mcfbalr; + u32 reg_mcfbahr; + u32 reg_mcfapr; + u32 reserved4[0x2f1]; + u32 reg_psr; + u32 reserved5; + u32 reg_brr[2]; + u32 reserved6[0x80]; + u32 reg_error[]; +}; + +int mc_init(bd_t *bis); + +int get_mc_boot_status(void); +#endif |