diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/chromebox_panther.h | 2 | ||||
| -rw-r--r-- | include/configs/crownbay.h | 1 | ||||
| -rw-r--r-- | include/configs/efi-x86.h | 4 | ||||
| -rw-r--r-- | include/configs/x86-common.h | 2 | ||||
| -rw-r--r-- | include/pch.h | 64 | ||||
| -rw-r--r-- | include/pci.h | 16 |
6 files changed, 48 insertions, 41 deletions
diff --git a/include/configs/chromebox_panther.h b/include/configs/chromebox_panther.h index 00fe26da29..d5b33902cc 100644 --- a/include/configs/chromebox_panther.h +++ b/include/configs/chromebox_panther.h @@ -11,7 +11,5 @@ #include <configs/x86-chromebook.h> #define CONFIG_RTL8169 -/* Avoid a warning in the Realtek Ethernet driver */ -#define CONFIG_SYS_CACHELINE_SIZE 16 #endif /* __CONFIG_H */ diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index ffd65d5439..fc1a8baf89 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -16,7 +16,6 @@ #define CONFIG_SYS_MONITOR_LEN (1 << 20) #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_ARCH_EARLY_INIT_R -#define CONFIG_ARCH_MISC_INIT #define CONFIG_SMSC_LPC47M diff --git a/include/configs/efi-x86.h b/include/configs/efi-x86.h index 258a83f9de..6dd0b32dae 100644 --- a/include/configs/efi-x86.h +++ b/include/configs/efi-x86.h @@ -13,9 +13,6 @@ #undef CONFIG_TPM_TIS_BASE_ADDRESS -#undef CONFIG_CMD_IMLS - -#undef CONFIG_X86_SERIAL #undef CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_IS_NOWHERE #undef CONFIG_VIDEO @@ -23,6 +20,7 @@ #undef CONFIG_SCSI_AHCI #undef CONFIG_CMD_SCSI #undef CONFIG_INTEL_ICH6_GPIO +#undef CONFIG_USB_EHCI_PCI #define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ "stdout=vga,serial\0" \ diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index dc7b227d25..3ae4366bfa 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -236,4 +236,6 @@ "tftpboot $loadaddr $bootfile;" \ "zboot $loadaddr" +#define CONFIG_BOOTDELAY 2 + #endif /* __CONFIG_H */ diff --git a/include/pch.h b/include/pch.h index 79f49bd5f6..222e9081c3 100644 --- a/include/pch.h +++ b/include/pch.h @@ -8,12 +8,6 @@ #ifndef __pch_h #define __pch_h -enum pch_version { - PCHV_UNKNOWN, - PCHV_7, - PCHV_9, -}; - #define PCH_RCBA 0xf0 #define BIOS_CTRL_BIOSWE BIT(0) @@ -21,20 +15,13 @@ enum pch_version { /* Operations for the Platform Controller Hub */ struct pch_ops { /** - * get_sbase() - get the address of SPI base + * get_spi_base() - get the address of SPI base * * @dev: PCH device to check * @sbasep: Returns address of SPI base if available, else 0 * @return 0 if OK, -ve on error (e.g. there is no SPI base) */ - int (*get_sbase)(struct udevice *dev, ulong *sbasep); - - /** - * get_version() - get the PCH version - * - * @return version, or -ENOSYS if unknown - */ - enum pch_version (*get_version)(struct udevice *dev); + int (*get_spi_base)(struct udevice *dev, ulong *sbasep); /** * set_spi_protect() - set whether SPI flash is protected or not @@ -45,25 +32,36 @@ struct pch_ops { * @return 0 on success, -ENOSYS if not implemented */ int (*set_spi_protect)(struct udevice *dev, bool protect); + + /** + * get_gpio_base() - get the address of GPIO base + * + * @dev: PCH device to check + * @gbasep: Returns address of GPIO base if available, else 0 + * @return 0 if OK, -ve on error (e.g. there is no GPIO base) + */ + int (*get_gpio_base)(struct udevice *dev, u32 *gbasep); + + /** + * get_io_base() - get the address of IO base + * + * @dev: PCH device to check + * @iobasep: Returns address of IO base if available, else 0 + * @return 0 if OK, -ve on error (e.g. there is no IO base) + */ + int (*get_io_base)(struct udevice *dev, u32 *iobasep); }; #define pch_get_ops(dev) ((struct pch_ops *)(dev)->driver->ops) /** - * pch_get_sbase() - get the address of SPI base + * pch_get_spi_base() - get the address of SPI base * * @dev: PCH device to check * @sbasep: Returns address of SPI base if available, else 0 * @return 0 if OK, -ve on error (e.g. there is no SPI base) */ -int pch_get_sbase(struct udevice *dev, ulong *sbasep); - -/** - * pch_get_version() - get the PCH version - * - * @return version, or -ENOSYS if unknown - */ -enum pch_version pch_get_version(struct udevice *dev); +int pch_get_spi_base(struct udevice *dev, ulong *sbasep); /** * set_spi_protect() - set whether SPI flash is protected or not @@ -75,4 +73,22 @@ enum pch_version pch_get_version(struct udevice *dev); */ int pch_set_spi_protect(struct udevice *dev, bool protect); +/** + * pch_get_gpio_base() - get the address of GPIO base + * + * @dev: PCH device to check + * @gbasep: Returns address of GPIO base if available, else 0 + * @return 0 if OK, -ve on error (e.g. there is no GPIO base) + */ +int pch_get_gpio_base(struct udevice *dev, u32 *gbasep); + +/** + * pch_get_io_base() - get the address of IO base + * + * @dev: PCH device to check + * @iobasep: Returns address of IO base if available, else 0 + * @return 0 if OK, -ve on error (e.g. there is no IO base) + */ +int pch_get_io_base(struct udevice *dev, u32 *iobasep); + #endif diff --git a/include/pci.h b/include/pci.h index d0d152c00b..68548b00d9 100644 --- a/include/pci.h +++ b/include/pci.h @@ -1050,6 +1050,11 @@ int dm_pci_write_config32(struct udevice *dev, int offset, u32 value); * functions, rather than byte/word/dword. But both are supported. */ int pci_write_config32(pci_dev_t pcidev, int offset, u32 value); +int pci_write_config16(pci_dev_t pcidev, int offset, u16 value); +int pci_write_config8(pci_dev_t pcidev, int offset, u8 value); +int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep); +int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep); +int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep); #ifdef CONFIG_DM_PCI_COMPAT /* Compatibility with old naming */ @@ -1059,8 +1064,6 @@ static inline int pci_write_config_dword(pci_dev_t pcidev, int offset, return pci_write_config32(pcidev, offset, value); } -int pci_write_config16(pci_dev_t pcidev, int offset, u16 value); - /* Compatibility with old naming */ static inline int pci_write_config_word(pci_dev_t pcidev, int offset, u16 value) @@ -1068,8 +1071,6 @@ static inline int pci_write_config_word(pci_dev_t pcidev, int offset, return pci_write_config16(pcidev, offset, value); } -int pci_write_config8(pci_dev_t pcidev, int offset, u8 value); - /* Compatibility with old naming */ static inline int pci_write_config_byte(pci_dev_t pcidev, int offset, u8 value) @@ -1077,8 +1078,6 @@ static inline int pci_write_config_byte(pci_dev_t pcidev, int offset, return pci_write_config8(pcidev, offset, value); } -int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep); - /* Compatibility with old naming */ static inline int pci_read_config_dword(pci_dev_t pcidev, int offset, u32 *valuep) @@ -1086,8 +1085,6 @@ static inline int pci_read_config_dword(pci_dev_t pcidev, int offset, return pci_read_config32(pcidev, offset, valuep); } -int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep); - /* Compatibility with old naming */ static inline int pci_read_config_word(pci_dev_t pcidev, int offset, u16 *valuep) @@ -1095,15 +1092,12 @@ static inline int pci_read_config_word(pci_dev_t pcidev, int offset, return pci_read_config16(pcidev, offset, valuep); } -int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep); - /* Compatibility with old naming */ static inline int pci_read_config_byte(pci_dev_t pcidev, int offset, u8 *valuep) { return pci_read_config8(pcidev, offset, valuep); } - #endif /* CONFIG_DM_PCI_COMPAT */ /** |