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-rw-r--r--include/configs/ls1012a_common.h1
-rw-r--r--include/configs/ls1043a_common.h11
-rw-r--r--include/configs/ls1046a_common.h1
-rw-r--r--include/configs/ls1088a_common.h1
-rw-r--r--include/configs/ls2080a_common.h2
-rw-r--r--include/configs/lx2160a_common.h289
-rw-r--r--include/configs/lx2160aqds.h140
-rw-r--r--include/configs/lx2160ardb.h109
-rw-r--r--include/dt-bindings/sound/azalia.h44
-rw-r--r--include/hda_codec.h103
-rw-r--r--include/log.h9
-rw-r--r--include/pch.h51
-rw-r--r--include/pci.h8
-rw-r--r--include/pci_ids.h5
-rw-r--r--include/sound.h46
15 files changed, 802 insertions, 18 deletions
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 324dba2b7e..9bbf34883e 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -6,7 +6,6 @@
#ifndef __LS1012A_COMMON_H
#define __LS1012A_COMMON_H
-#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_GICV2
#include <asm/arch/config.h>
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 49b014181e..662b573ed9 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -26,7 +26,6 @@
#endif
#define CONFIG_REMAKE_ELF
-#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_GICV2
#include <asm/arch/stream_id_lsch2.h>
@@ -209,7 +208,7 @@
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
-#define CONFIG_SYS_QE_FW_ADDR (512 * 0x4a08)
+#define CONFIG_SYS_QE_FW_ADDR (512 * 0x4A00)
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
@@ -255,6 +254,8 @@
"fdtheader_addr_r=0x80100000\0" \
"kernelheader_addr_r=0x80200000\0" \
"kernel_addr_r=0x81000000\0" \
+ "kernel_start=0x1000000\0" \
+ "kernelheader_start=0x800000\0" \
"fdt_addr_r=0x90000000\0" \
"load_addr=0xa0000000\0" \
"kernelheader_addr=0x60800000\0" \
@@ -306,6 +307,12 @@
"&& cp.b $kernelheader_addr $kernelheader_addr_r " \
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
"bootm $load_addr#$board\0" \
+ "nand_bootcmd=echo Trying load from NAND..;" \
+ "nand info; nand read $load_addr " \
+ "$kernel_start $kernel_size; env exists secureboot " \
+ "&& nand read $kernelheader_addr_r $kernelheader_start " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
+ "bootm $load_addr#$board\0" \
"sd_bootcmd=echo Trying load from SD ..;" \
"mmcinfo; mmc read $load_addr " \
"$kernel_addr_sd $kernel_size_sd && " \
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
index 6e36c9339b..0266681c52 100644
--- a/include/configs/ls1046a_common.h
+++ b/include/configs/ls1046a_common.h
@@ -26,7 +26,6 @@
#endif
#define CONFIG_REMAKE_ELF
-#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_GICV2
#include <asm/arch/config.h>
diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index 95e6786e6c..b663937d8c 100644
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h
@@ -21,7 +21,6 @@
#endif
#define CONFIG_REMAKE_ELF
-#define CONFIG_FSL_LAYERSCAPE
#include <asm/arch/stream_id_lsch3.h>
#include <asm/arch/config.h>
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 235a757f75..0a6c90dc8b 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -8,9 +8,7 @@
#define __LS2_COMMON_H
#define CONFIG_REMAKE_ELF
-#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_GICV3
-#define CONFIG_FSL_TZPC_BP147
#include <asm/arch/stream_id_lsch3.h>
#include <asm/arch/config.h>
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
new file mode 100644
index 0000000000..4b5608b5a3
--- /dev/null
+++ b/include/configs/lx2160a_common.h
@@ -0,0 +1,289 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __LX2_COMMON_H
+#define __LX2_COMMON_H
+
+#include <asm/arch/stream_id_lsch3.h>
+#include <asm/arch/config.h>
+#include <asm/arch/soc.h>
+
+#define CONFIG_REMAKE_ELF
+#define CONFIG_FSL_LAYERSCAPE
+#define CONFIG_GICV3
+#define CONFIG_FSL_TZPC_BP147
+#define CONFIG_FSL_MEMAC
+
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_FLASH_BASE 0x20000000
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F 1
+
+/* DDR */
+#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
+#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
+#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL
+#define CONFIG_DDR_SPD
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#define SPD_EEPROM_ADDRESS1 0x51
+#define SPD_EEPROM_ADDRESS2 0x52
+#define SPD_EEPROM_ADDRESS3 0x53
+#define SPD_EEPROM_ADDRESS4 0x54
+#define SPD_EEPROM_ADDRESS5 0x55
+#define SPD_EEPROM_ADDRESS6 0x56
+#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
+#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
+#define CONFIG_DIMM_SLOTS_PER_CTLR 2
+#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
+#define CONFIG_SYS_MONITOR_LEN (936 * 1024)
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Generic Timer Definitions */
+/*
+ * This is not an accurate number. It is used in start.S. The frequency
+ * will be udpated later when get_bus_freq(0) is available.
+ */
+
+#define COUNTER_FREQUENCY 25000000 /* 25MHz */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
+
+/* Serial Port */
+#define CONFIG_PL01X_SERIAL
+#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4)
+#define CONFIG_SYS_SERIAL0 0x21c0000
+#define CONFIG_SYS_SERIAL1 0x21d0000
+#define CONFIG_SYS_SERIAL2 0x21e0000
+#define CONFIG_SYS_SERIAL3 0x21f0000
+/*below might needs to be removed*/
+#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
+ (void *)CONFIG_SYS_SERIAL1, \
+ (void *)CONFIG_SYS_SERIAL2, \
+ (void *)CONFIG_SYS_SERIAL3 }
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/* MC firmware */
+#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
+#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
+#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
+#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+
+/* Define phy_reset function to boot the MC based on mcinitcmd.
+ * This happens late enough to properly fixup u-boot env MAC addresses.
+ */
+#define CONFIG_RESET_PHY_R
+
+/*
+ * Carve out a DDR region which will not be used by u-boot/Linux
+ *
+ * It will be used by MC and Debug Server. The MC region must be
+ * 512MB aligned, so the min size to hide is 512MB.
+ */
+#ifdef CONFIG_FSL_MC_ENET
+#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
+#endif
+
+/* I2C bus multiplexer */
+#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
+#define I2C_MUX_CH_DEFAULT 0x8
+
+/* RTC */
+#define RTC
+#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/* Qixis */
+#define CONFIG_FSL_QIXIS
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+
+/* PCI */
+#ifdef CONFIG_PCI
+#define CONFIG_SYS_PCI_64BIT
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+/* MMC */
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+
+/* SATA */
+
+#ifdef CONFIG_SCSI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
+#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+#endif
+
+/* USB */
+#ifdef CONFIG_USB
+#define CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
+/* FlexSPI */
+#ifdef CONFIG_NXP_FSPI
+#define NXP_FSPI_FLASH_SIZE SZ_64M
+#define NXP_FSPI_FLASH_NUM 1
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
+#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE 128
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_OFFSET 0x500000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_ENV_OFFSET)
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_SYS_MAXARGS 64 /* max command args */
+
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+/* Initial environment variables */
+#define XSPI_MC_INIT_CMD \
+ "env exists secureboot && " \
+ "esbc_validate 0x20700000 && " \
+ "esbc_validate 0x20740000 ;" \
+ "fsl_mc start mc 0x20a00000 0x20e00000\0"
+
+#define SD_MC_INIT_CMD \
+ "mmc read 0x80000000 0x5000 0x800;" \
+ "mmc read 0x80100000 0x7000 0x800;" \
+ "env exists secureboot && " \
+ "mmc read 0x80700000 0x3800 0x10 && " \
+ "mmc read 0x80740000 0x3A00 0x10 && " \
+ "esbc_validate 0x80700000 && " \
+ "esbc_validate 0x80740000 ;" \
+ "fsl_mc start mc 0x80000000 0x80100000\0"
+
+#define EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
+ "ramdisk_addr=0x800000\0" \
+ "ramdisk_size=0x2000000\0" \
+ "fdt_high=0xa0000000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "fdt_addr=0x64f00000\0" \
+ "kernel_start=0x1000000\0" \
+ "kernelheader_start=0x7C0000\0" \
+ "scriptaddr=0x80000000\0" \
+ "scripthdraddr=0x80080000\0" \
+ "fdtheader_addr_r=0x80100000\0" \
+ "kernelheader_addr_r=0x80200000\0" \
+ "kernel_addr_r=0x81000000\0" \
+ "kernelheader_size=0x40000\0" \
+ "fdt_addr_r=0x90000000\0" \
+ "load_addr=0xa0000000\0" \
+ "kernel_size=0x2800000\0" \
+ "kernel_addr_sd=0x8000\0" \
+ "kernelhdr_addr_sd=0x3E00\0" \
+ "kernel_size_sd=0x1d000\0" \
+ "kernelhdr_size_sd=0x10\0" \
+ "console=ttyAMA0,38400n8\0" \
+ BOOTENV \
+ "mcmemsize=0x70000000\0" \
+ XSPI_MC_INIT_CMD \
+ "boot_scripts=lx2160ardb_boot.scr\0" \
+ "boot_script_hdr=hdr_lx2160ardb_bs.out\0" \
+ "scan_dev_for_boot_part=" \
+ "part list ${devtype} ${devnum} devplist; " \
+ "env exists devplist || setenv devplist 1; " \
+ "for distro_bootpart in ${devplist}; do " \
+ "if fstype ${devtype} " \
+ "${devnum}:${distro_bootpart} " \
+ "bootfstype; then " \
+ "run scan_dev_for_boot; " \
+ "fi; " \
+ "done\0" \
+ "scan_dev_for_boot=" \
+ "echo Scanning ${devtype} " \
+ "${devnum}:${distro_bootpart}...; " \
+ "for prefix in ${boot_prefixes}; do " \
+ "run scan_dev_for_scripts; " \
+ "done;\0" \
+ "boot_a_script=" \
+ "load ${devtype} ${devnum}:${distro_bootpart} " \
+ "${scriptaddr} ${prefix}${script}; " \
+ "env exists secureboot && load ${devtype} " \
+ "${devnum}:${distro_bootpart} " \
+ "${scripthdraddr} ${prefix}${boot_script_hdr} " \
+ "&& esbc_validate ${scripthdraddr};" \
+ "source ${scriptaddr}\0"
+
+#define XSPI_NOR_BOOTCOMMAND \
+ "env exists mcinitcmd && env exists secureboot "\
+ "&& esbc_validate 0x20780000; " \
+ "env exists mcinitcmd && " \
+ "fsl_mc lazyapply dpl 0x20d00000; " \
+ "run distro_bootcmd;run xspi_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
+
+#define SD_BOOTCOMMAND \
+ "env exists mcinitcmd && mmcinfo; " \
+ "mmc read 0x80001000 0x6800 0x800; " \
+ "env exists mcinitcmd && env exists secureboot " \
+ " && mmc read 0x80780000 0x3C00 0x10 " \
+ "&& esbc_validate 0x80780000;env exists mcinitcmd " \
+ "&& fsl_mc lazyapply dpl 0x80001000;" \
+ "run distro_bootcmd;run sd_bootcmd;" \
+ "env exists secureboot && esbc_halt;"
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(USB, usb, 0) \
+ func(MMC, mmc, 0) \
+ func(SCSI, scsi, 0)
+#include <config_distro_bootcmd.h>
+
+#endif /* __LX2_COMMON_H */
diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h
new file mode 100644
index 0000000000..662e601f0f
--- /dev/null
+++ b/include/configs/lx2160aqds.h
@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#ifndef __LX2_QDS_H
+#define __LX2_QDS_H
+
+#include "lx2160a_common.h"
+
+/* Qixis */
+#define QIXIS_XMAP_MASK 0x07
+#define QIXIS_XMAP_SHIFT 5
+#define QIXIS_RST_CTL_RESET_EN 0x30
+#define QIXIS_LBMAP_DFLTBANK 0x00
+#define QIXIS_LBMAP_ALTBANK 0x20
+#define QIXIS_LBMAP_QSPI 0x00
+#define QIXIS_RCW_SRC_QSPI 0xff
+#define QIXIS_RST_CTL_RESET 0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+#define QIXIS_LBMAP_MASK 0x0f
+#define QIXIS_LBMAP_SD
+#define QIXIS_RCW_SRC_SD 0x08
+#define NON_EXTENDED_DUTCFG
+#define QIXIS_SDID_MASK 0x07
+#define QIXIS_ESDHC_NO_ADAPTER 0x7
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_100 0x0
+#define QIXIS_SYSCLK_125 0x1
+#define QIXIS_SYSCLK_133 0x2
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_100 0x0
+#define QIXIS_DDRCLK_125 0x1
+#define QIXIS_DDRCLK_133 0x2
+
+#define BRDCFG4_EMI1SEL_MASK 0xF8
+#define BRDCFG4_EMI1SEL_SHIFT 3
+#define BRDCFG4_EMI2SEL_MASK 0x07
+#define BRDCFG4_EMI2SEL_SHIFT 0
+
+/* VID */
+
+#define I2C_MUX_CH_VOL_MONITOR 0xA
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR 0x63
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+#define CONFIG_VID_FLS_ENV "lx2160aqds_vdd_mv"
+#define CONFIG_VID
+
+/* The lowest and highest voltage allowed*/
+#define VDD_MV_MIN 775
+#define VDD_MV_MAX 925
+
+/* PM Bus commands code for LTC3882*/
+#define PMBUS_CMD_PAGE 0x0
+#define PMBUS_CMD_READ_VOUT 0x8B
+#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
+#define PMBUS_CMD_VOUT_COMMAND 0x21
+#define PWM_CHANNEL0 0x0
+
+#define CONFIG_VOL_MONITOR_LTC3882_SET
+#define CONFIG_VOL_MONITOR_LTC3882_READ
+
+/* RTC */
+#define CONFIG_SYS_RTC_BUS_NUM 0
+#define I2C_MUX_CH_RTC 0xB
+
+/*
+ * MMC
+ */
+#ifdef CONFIG_MMC
+#ifndef __ASSEMBLY__
+u8 qixis_esdhc_detect_quirk(void);
+#endif
+#define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk()
+#endif
+
+/* MAC/PHY configuration */
+#if defined(CONFIG_FSL_MC_ENET)
+#define CONFIG_MII
+#define CONFIG_ETHPRIME "DPMAC17@rgmii-id"
+
+#define AQ_PHY_ADDR1 0x00
+#define AQ_PHY_ADDR2 0x01
+#define AQ_PHY_ADDR3 0x02
+#define AQ_PHY_ADDR4 0x03
+
+#define CORTINA_NO_FW_UPLOAD
+#define CORTINA_PHY_ADDR1 0x0
+
+#define INPHI_PHY_ADDR1 0x0
+#define INPHI_PHY_ADDR2 0x1
+
+#define RGMII_PHY_ADDR1 0x01
+#define RGMII_PHY_ADDR2 0x02
+
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ EXTRA_ENV_SETTINGS \
+ "lx2160aqds_vdd_mv=800\0" \
+ "BOARD=lx2160aqds\0" \
+ "xspi_bootcmd=echo Trying load from flexspi..;" \
+ "sf probe 0:0 && sf read $load_addr " \
+ "$kernel_start $kernel_size ; env exists secureboot &&" \
+ "sf read $kernelheader_addr_r $kernelheader_start " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+ " bootm $load_addr#$BOARD\0" \
+ "sd_bootcmd=echo Trying load from sd card..;" \
+ "mmcinfo; mmc read $load_addr " \
+ "$kernel_addr_sd $kernel_size_sd ;" \
+ "env exists secureboot && mmc read $kernelheader_addr_r "\
+ "$kernelhdr_addr_sd $kernelhdr_size_sd " \
+ " && esbc_validate ${kernelheader_addr_r};" \
+ "bootm $load_addr#$BOARD\0"
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LX2_QDS_H */
diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h
new file mode 100644
index 0000000000..972bb5e102
--- /dev/null
+++ b/include/configs/lx2160ardb.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __LX2_RDB_H
+#define __LX2_RDB_H
+
+#include "lx2160a_common.h"
+
+/* Qixis */
+#define QIXIS_XMAP_MASK 0x07
+#define QIXIS_XMAP_SHIFT 5
+#define QIXIS_RST_CTL_RESET_EN 0x30
+#define QIXIS_LBMAP_DFLTBANK 0x00
+#define QIXIS_LBMAP_ALTBANK 0x20
+#define QIXIS_LBMAP_QSPI 0x00
+#define QIXIS_RCW_SRC_QSPI 0xff
+#define QIXIS_RST_CTL_RESET 0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+#define QIXIS_LBMAP_MASK 0x0f
+#define QIXIS_LBMAP_SD
+#define QIXIS_RCW_SRC_SD 0x08
+#define NON_EXTENDED_DUTCFG
+
+/* VID */
+
+#define I2C_MUX_CH_VOL_MONITOR 0xA
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR 0x63
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+#define CONFIG_VID_FLS_ENV "lx2160ardb_vdd_mv"
+#define CONFIG_VID
+
+/* The lowest and highest voltage allowed*/
+#define VDD_MV_MIN 775
+#define VDD_MV_MAX 855
+
+/* PM Bus commands code for LTC3882*/
+#define PMBUS_CMD_PAGE 0x0
+#define PMBUS_CMD_READ_VOUT 0x8B
+#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
+#define PMBUS_CMD_VOUT_COMMAND 0x21
+#define PWM_CHANNEL0 0x0
+
+#define CONFIG_VOL_MONITOR_LTC3882_SET
+#define CONFIG_VOL_MONITOR_LTC3882_READ
+
+/* RTC */
+#define CONFIG_SYS_RTC_BUS_NUM 4
+
+/* MAC/PHY configuration */
+#if defined(CONFIG_FSL_MC_ENET)
+#define CONFIG_MII
+#define CONFIG_ETHPRIME "DPMAC1@xgmii"
+
+#define AQR107_PHY_ADDR1 0x04
+#define AQR107_PHY_ADDR2 0x05
+
+#define CORTINA_NO_FW_UPLOAD
+#define CORTINA_PHY_ADDR1 0x0
+#define INPHI_PHY_ADDR1 0x0
+
+#define RGMII_PHY_ADDR1 0x01
+#define RGMII_PHY_ADDR2 0x02
+
+#endif
+
+/* EMC2305 */
+#define I2C_MUX_CH_EMC2305 0x09
+#define I2C_EMC2305_ADDR 0x4D
+#define I2C_EMC2305_CMD 0x40
+#define I2C_EMC2305_PWM 0x80
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ EXTRA_ENV_SETTINGS \
+ "lx2160ardb_vdd_mv=800\0" \
+ "BOARD=lx2160ardb\0" \
+ "xspi_bootcmd=echo Trying load from flexspi..;" \
+ "sf probe 0:0 && sf read $load_addr " \
+ "$kernel_start $kernel_size ; env exists secureboot &&" \
+ "sf read $kernelheader_addr_r $kernelheader_start " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+ " bootm $load_addr#$BOARD\0" \
+ "sd_bootcmd=echo Trying load from sd card..;" \
+ "mmcinfo; mmc read $load_addr " \
+ "$kernel_addr_sd $kernel_size_sd ;" \
+ "env exists secureboot && mmc read $kernelheader_addr_r "\
+ "$kernelhdr_addr_sd $kernelhdr_size_sd " \
+ " && esbc_validate ${kernelheader_addr_r};" \
+ "bootm $load_addr#$BOARD\0"
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LX2_RDB_H */
diff --git a/include/dt-bindings/sound/azalia.h b/include/dt-bindings/sound/azalia.h
new file mode 100644
index 0000000000..10ace3ef56
--- /dev/null
+++ b/include/dt-bindings/sound/azalia.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Intel HDA audio codec config. This is a mechanicm to configure codecs when
+ * using Intel HDA audio.
+ *
+ * Copyright 2018 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __AZALIA_H
+#define __AZALIA_H
+
+#define AZALIA_CODEC_SHIFT 28
+#define AZALIA_NID_SHIFT 20
+#define AZALIA_VERB_SHIFT 8
+
+/* Supported opcodes */
+#define AZALIA_OPCODE_CONFIG_DEFAULT 0x71c
+#define AZALIA_OPCODE_IMPL_ID 0x720
+#define AZALIA_OPCODE_READ_PARAM 0xf00
+
+#define AZALIA_PARAM_VENDOR_ID 0
+
+/* Generate the register value to write a particular byte of a 32-bit value */
+#define AZALIA_SET_BYTE(codec, nid, opcode, val, byte) \
+ ((codec) << AZALIA_CODEC_SHIFT | \
+ (nid) << AZALIA_NID_SHIFT | \
+ ((opcode) + (byte)) << AZALIA_VERB_SHIFT | \
+ (((val) >> ((byte) * 8)) & 0xff))
+
+/* Generate the register value to write all bytes of a 32-bit value */
+#define AZALIA_WORD(codec, nid, opcode, val) \
+ (AZALIA_SET_BYTE(codec, nid, opcode, val, 0) | \
+ AZALIA_SET_BYTE(codec, nid, opcode, val, 1) | \
+ AZALIA_SET_BYTE(codec, nid, opcode, val, 2) | \
+ AZALIA_SET_BYTE(codec, nid, opcode, val, 3))
+
+#define AZALIA_PIN_CFG(codec, nid, val) \
+ AZALIA_WORD(codec, nid, AZALIA_OPCODE_CONFIG_DEFAULT, val)
+
+#define AZALIA_SUBVENDOR(codec, val) \
+ AZALIA_WORD(codec, 1, AZALIA_OPCODE_IMPL_ID, val)
+
+#endif /* __AZALIA_H */
diff --git a/include/hda_codec.h b/include/hda_codec.h
new file mode 100644
index 0000000000..56de571f0f
--- /dev/null
+++ b/include/hda_codec.h
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Support for Intel High-Definition Audio codec
+ *
+ * Copyright 2018 Google LLC
+ *
+ * Taken from coreboot file of the same name
+ */
+
+#ifndef __HDA_CODEC_H_
+#define __HDA_CODEC_H_
+
+struct hda_regs;
+
+/**
+ * struct hda_codec_priv - Private data required by the HDA codec
+ *
+ * @regs: HDA registers
+ * @beep_nid: Node ID of beep node (>0)
+ */
+struct hda_codec_priv {
+ struct hda_regs *regs;
+ uint beep_nid;
+};
+
+/**
+ * hda_wait_for_ready() - Wait for the codec to indicate it is ready
+ *
+ * @regs: HDA registers
+ * @return 0 if OK -ETIMEDOUT if codec did not respond in time
+ */
+int hda_wait_for_ready(struct hda_regs *regs);
+
+/**
+ * hda_wait_for_valid() - Wait for the codec to accept the last command
+ *
+ * @regs: HDA registers
+ * @return 0 if OK -ETIMEDOUT if codec did not respond in time
+ */
+int hda_wait_for_valid(struct hda_regs *regs);
+
+/**
+ * hda_codec_detect() - Detect which codecs are present
+ *
+ * @regs: HDA registers
+ * @return bit mask of active codecs (0 if none)
+ * @return 0 if OK, -ve on error
+ */
+int hda_codec_detect(struct hda_regs *regs);
+
+/**
+ * hda_codecs_init() - Init all codecs
+ *
+ * @dev: Sound device
+ * @regs: HDA registers
+ * @codec_mask: Mask of codecs to init (bits 3:0)
+ * @return 0 if OK, -ve on error
+ */
+int hda_codecs_init(struct udevice *dev, struct hda_regs *regs, u32 codec_mask);
+
+/**
+ * hda_codec_start_beep() - Start beeping
+ *
+ * This tells the sound hardware to start a beep. It will continue until stopped
+ * by sound_stop_beep().
+ *
+ * @dev: Sound device
+ * @frequency_hz: Beep frequency in hertz
+ * @return if OK, -ve on error
+ */
+int hda_codec_start_beep(struct udevice *dev, int frequency_hz);
+
+/**
+ * hda_codec_stop_beep() - Stop beeping
+ *
+ * This tells the sound hardware to stop a previously started beep.
+ *
+ * @dev: Sound device
+ * @return if OK, -ve on error
+ */
+int hda_codec_stop_beep(struct udevice *dev);
+
+/**
+ * hda_codec_init() - Set up the HDA codec base address
+ *
+ * This should be called at the start of the probe() method.
+ *
+ * @dev: Sound device
+ * @return 0 if OK, -ve on error
+ */
+int hda_codec_init(struct udevice *dev);
+
+/**
+ * hda_codec_finish_init() - Finish setting up the HDA codec base address
+ *
+ * This should be called at the end of the probe() method.
+ *
+ * @dev: Sound device
+ * @return 0 if OK, -ve on error
+ */
+int hda_codec_finish_init(struct udevice *dev);
+
+#endif /* __HDA_CODEC_H_ */
diff --git a/include/log.h b/include/log.h
index d7f6471006..7566ba7f2d 100644
--- a/include/log.h
+++ b/include/log.h
@@ -14,7 +14,7 @@
/** Log levels supported, ranging from most to least important */
enum log_level_t {
- LOGL_EMERG = 0, /*U-Boot is unstable */
+ LOGL_EMERG = 0, /* U-Boot is unstable */
LOGL_ALERT, /* Action must be taken immediately */
LOGL_CRIT, /* Critical conditions */
LOGL_ERR, /* Error that prevents something from working */
@@ -111,11 +111,16 @@ int _log(enum log_category_t cat, enum log_level_t level, const char *file,
#endif
#if CONFIG_IS_ENABLED(LOG)
+#ifdef LOG_DEBUG
+#define _LOG_DEBUG 1
+#else
+#define _LOG_DEBUG 0
+#endif
/* Emit a log record if the level is less that the maximum */
#define log(_cat, _level, _fmt, _args...) ({ \
int _l = _level; \
- if (CONFIG_IS_ENABLED(LOG) && _l <= _LOG_MAX_LEVEL) \
+ if (CONFIG_IS_ENABLED(LOG) && (_l <= _LOG_MAX_LEVEL || _LOG_DEBUG)) \
_log((enum log_category_t)(_cat), _l, __FILE__, __LINE__, \
__func__, \
pr_fmt(_fmt), ##_args); \
diff --git a/include/pch.h b/include/pch.h
index 73994b8343..046a5fde3a 100644
--- a/include/pch.h
+++ b/include/pch.h
@@ -11,7 +11,23 @@
#define BIOS_CTRL_BIOSWE BIT(0)
-/* Operations for the Platform Controller Hub */
+/* All the supported PCH ioctls */
+enum pch_req_t {
+ /* Returns HDA config info if Azalia V1CTL enabled, -ENOENT if not */
+ PCH_REQ_HDA_CONFIG,
+
+ PCH_REQ_TEST1, /* Test requests for sandbox driver */
+ PCH_REQ_TEST2,
+ PCH_REQ_TEST3,
+
+ PCH_REQ_COUNT, /* Number of ioctrls supported */
+};
+
+/**
+ * struct pch_ops - Operations for the Platform Controller Hub
+ *
+ * Consider using ioctl() to add rarely used or driver-specific operations.
+ */
struct pch_ops {
/**
* get_spi_base() - get the address of SPI base
@@ -49,6 +65,23 @@ struct pch_ops {
* @return 0 if OK, -ve on error (e.g. there is no IO base)
*/
int (*get_io_base)(struct udevice *dev, u32 *iobasep);
+
+ /**
+ * ioctl() - perform misc read/write operations
+ *
+ * This is a catch-all operation intended to avoid adding lots of
+ * methods to this uclass, of which few are commonly used. Uncommon
+ * operations that pertain only to a few devices in this uclass should
+ * use this method instead of adding new methods.
+ *
+ * @dev: PCH device to check
+ * @req: PCH request ID
+ * @data: Input/output data
+ * @size: Size of input data (and maximum size of output data)
+ * @return size of output data on sucesss, -ve on error
+ */
+ int (*ioctl)(struct udevice *dev, enum pch_req_t req, void *data,
+ int size);
};
#define pch_get_ops(dev) ((struct pch_ops *)(dev)->driver->ops)
@@ -90,4 +123,20 @@ int pch_get_gpio_base(struct udevice *dev, u32 *gbasep);
*/
int pch_get_io_base(struct udevice *dev, u32 *iobasep);
+/**
+ * pch_ioctl() - perform misc read/write operations
+ *
+ * This is a catch-all operation intended to avoid adding lots of
+ * methods to this uclass, of which few are commonly used. Uncommon
+ * operations that pertain only to a few devices in this uclass should
+ * use this method instead of adding new methods.
+ *
+ * @dev: PCH device to check
+ * @req: PCH request ID
+ * @data: Input/output data
+ * @size: Size of input data (and maximum size of output data)
+ * @return size of output data on sucesss, -ve on error
+ */
+int pch_ioctl(struct udevice *dev, ulong req, void *data, int size);
+
#endif
diff --git a/include/pci.h b/include/pci.h
index 041f8e3747..936cfe975c 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -735,12 +735,6 @@ extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int
extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
pci_dev_t pci_find_class(unsigned int find_class, int index);
-extern int pci_hose_config_device(struct pci_controller *hose,
- pci_dev_t dev,
- unsigned long io,
- pci_addr_t mem,
- unsigned long command);
-
extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
int cap);
extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
@@ -828,7 +822,7 @@ struct udevice;
*
* Every device on a PCI bus has this per-child data.
*
- * It can be accessed using dev_get_parent_priv(dev) if dev->parent is a
+ * It can be accessed using dev_get_parent_platdata(dev) if dev->parent is a
* PCI bus (i.e. UCLASS_PCI)
*
* @devfn: Encoded device and function index - see PCI_DEVFN()
diff --git a/include/pci_ids.h b/include/pci_ids.h
index fdda679cc0..bd59578ccb 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -41,6 +41,7 @@
#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400
#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401
#define PCI_CLASS_MULTIMEDIA_PHONE 0x0402
+#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480
#define PCI_BASE_CLASS_MEMORY 0x05
@@ -1363,6 +1364,7 @@
#define PCI_DEVICE_ID_CREATIVE_EMU10K1 0x0002
#define PCI_DEVICE_ID_CREATIVE_20K1 0x0005
#define PCI_DEVICE_ID_CREATIVE_20K2 0x000b
+#define PCI_DEVICE_ID_CREATIVE_CA01322 0x0011
#define PCI_SUBDEVICE_ID_CREATIVE_SB0760 0x0024
#define PCI_SUBDEVICE_ID_CREATIVE_SB08801 0x0041
#define PCI_SUBDEVICE_ID_CREATIVE_SB08802 0x0042
@@ -2827,6 +2829,7 @@
#define PCI_DEVICE_ID_INTEL_ICH7_19 0x27dd
#define PCI_DEVICE_ID_INTEL_ICH7_20 0x27de
#define PCI_DEVICE_ID_INTEL_ICH7_21 0x27df
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_HDMI 0x2806
#define PCI_DEVICE_ID_INTEL_ICH8_0 0x2810
#define PCI_DEVICE_ID_INTEL_ICH8_1 0x2811
#define PCI_DEVICE_ID_INTEL_ICH8_2 0x2812
@@ -3025,6 +3028,8 @@
#define PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI 0x9c03
#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC 0x9c45
#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_AHCI 0x9c83
+#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_HDA 0x9ca0
+#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_ADSP 0x9cb6
#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LPC 0x9cc3
#define PCI_DEVICE_ID_INTEL_S21152BB 0xb152
diff --git a/include/sound.h b/include/sound.h
index b7959cc260..47de9fa3ed 100644
--- a/include/sound.h
+++ b/include/sound.h
@@ -54,7 +54,7 @@ void sound_create_square_wave(uint sample_rate, unsigned short *data, int size,
/* Operations for sound */
struct sound_ops {
/**
- * setup() - Set up to play a sound
+ * setup() - Set up to play a sound (optional)
*/
int (*setup)(struct udevice *dev);
@@ -67,6 +67,28 @@ struct sound_ops {
* @return 0 if OK, -ve on error
*/
int (*play)(struct udevice *dev, void *data, uint data_size);
+
+ /**
+ * start_beep() - Start beeping (optional)
+ *
+ * This tells the sound hardware to start a beep. It will continue until
+ * stopped by sound_stop_beep().
+ *
+ * @dev: Sound device
+ * @frequency_hz: Beep frequency in hertz
+ * @return if OK, -ENOSYS if not supported, -ve on error
+ */
+ int (*start_beep)(struct udevice *dev, int frequency_hz);
+
+ /**
+ * stop_beep() - Stop beeping (optional)
+ *
+ * This tells the sound hardware to stop a previously started beep.
+ *
+ * @dev: Sound device
+ * @return if OK, -ve on error
+ */
+ int (*stop_beep)(struct udevice *dev);
};
#define sound_get_ops(dev) ((struct sound_ops *)(dev)->driver->ops)
@@ -87,6 +109,28 @@ int sound_setup(struct udevice *dev);
int sound_beep(struct udevice *dev, int msecs, int frequency_hz);
/**
+ * sound_start_beep() - Start beeping
+ *
+ * This tells the sound hardware to start a beep. It will continue until stopped
+ * by sound_stop_beep().
+ *
+ * @dev: Sound device
+ * @frequency_hz: Beep frequency in hertz
+ * @return if OK, -ve on error
+ */
+int sound_start_beep(struct udevice *dev, int frequency_hz);
+
+/**
+ * sound_stop_beep() - Stop beeping
+ *
+ * This tells the sound hardware to stop a previously started beep.
+ *
+ * @dev: Sound device
+ * @return if OK, -ve on error
+ */
+int sound_stop_beep(struct udevice *dev);
+
+/**
* sound_find_codec_i2s() - Called by sound drivers to locate codec and i2s
*
* This finds the audio codec and i2s devices and puts them in the uclass's
generated by cgit (git 2.34.1) at 2025-01-24 01:01:37 +0000