diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-ppc/interrupt.h | 36 | ||||
| -rw-r--r-- | include/asm-ppc/ppc4xx-ebc.h | 156 | ||||
| -rw-r--r-- | include/asm-ppc/ppc4xx-intvec.h | 474 | ||||
| -rw-r--r-- | include/asm-ppc/ppc4xx-sdram.h | 326 | ||||
| -rw-r--r-- | include/asm-ppc/ppc4xx-uic.h | 316 | ||||
| -rw-r--r-- | include/asm-ppc/processor.h | 6 | ||||
| -rw-r--r-- | include/asm-ppc/xilinx_irq.h | 36 | ||||
| -rw-r--r-- | include/configs/HH405.h | 2 | ||||
| -rw-r--r-- | include/configs/katmai.h | 1 | ||||
| -rw-r--r-- | include/configs/kilauea.h | 146 | ||||
| -rw-r--r-- | include/configs/makalu.h | 1 | ||||
| -rw-r--r-- | include/configs/ml507.h | 122 | ||||
| -rw-r--r-- | include/configs/redwood.h | 186 | ||||
| -rw-r--r-- | include/ppc405.h | 397 | ||||
| -rw-r--r-- | include/ppc440.h | 1112 | ||||
| -rw-r--r-- | include/ppc4xx.h | 7 | ||||
| -rw-r--r-- | include/ppc4xx_enet.h | 16 |
17 files changed, 1324 insertions, 2016 deletions
diff --git a/include/asm-ppc/interrupt.h b/include/asm-ppc/interrupt.h new file mode 100644 index 0000000000..792836b229 --- /dev/null +++ b/include/asm-ppc/interrupt.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ +#ifndef INTERRUPT_H +#define INTERRUPT_H + +#if defined(CONFIG_XILINX_440) +#include <asm/xilinx_irq.h> +#else +#include <asm/ppc4xx-uic.h> +#endif + +void pic_enable(void); +void pic_irq_enable(unsigned int irq); +void pic_irq_disable(unsigned int irq); +void pic_irq_ack(unsigned int irq); +void external_interrupt(struct pt_regs *regs); +void interrupt_run_handler(int vec); + +#endif diff --git a/include/asm-ppc/ppc4xx-ebc.h b/include/asm-ppc/ppc4xx-ebc.h new file mode 100644 index 0000000000..d180e045fc --- /dev/null +++ b/include/asm-ppc/ppc4xx-ebc.h @@ -0,0 +1,156 @@ +/* + * (C) Copyright 2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PPC4xx_EBC_H_ +#define _PPC4xx_EBC_H_ + +/* + * Currently there are two register layout versions for the + * IBM EBC core used on 4xx PPC's: + */ +#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \ + defined(CONFIG_405EP) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#define CONFIG_EBC_PPC4xx_IBM_VER1 +#endif + +/* Bank Configuration Register */ +#define EBC_BXCR_BAS_MASK PPC_REG_VAL(11, 0xFFF) +#define EBC_BXCR_BAS_ENCODE(n) (((static_cast(u32, n)) & EBC_BXCR_BAS_MASK)) +#define EBC_BXCR_BS_MASK PPC_REG_VAL(14, 0x7) +#define EBC_BXCR_BS_1MB PPC_REG_VAL(14, 0x0) +#define EBC_BXCR_BS_2MB PPC_REG_VAL(14, 0x1) +#define EBC_BXCR_BS_4MB PPC_REG_VAL(14, 0x2) +#define EBC_BXCR_BS_8MB PPC_REG_VAL(14, 0x3) +#define EBC_BXCR_BS_16MB PPC_REG_VAL(14, 0x4) +#define EBC_BXCR_BS_32MB PPC_REG_VAL(14, 0x5) +#define EBC_BXCR_BS_64MB PPC_REG_VAL(14, 0x6) +#define EBC_BXCR_BS_128MB PPC_REG_VAL(14, 0x7) +#define EBC_BXCR_BU_MASK PPC_REG_VAL(16, 0x3) +#define EBC_BXCR_BU_NONE PPC_REG_VAL(16, 0x0) +#define EBC_BXCR_BU_R PPC_REG_VAL(16, 0x1) +#define EBC_BXCR_BU_W PPC_REG_VAL(16, 0x2) +#define EBC_BXCR_BU_RW PPC_REG_VAL(16, 0x3) +#define EBC_BXCR_BW_MASK PPC_REG_VAL(18, 0x3) +#define EBC_BXCR_BW_8BIT PPC_REG_VAL(18, 0x0) +#define EBC_BXCR_BW_16BIT PPC_REG_VAL(18, 0x1) +#if defined(CONFIG_EBC_PPC4xx_IBM_VER1) +#define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x2) +#else +#define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x3) +#endif + +/* Bank Access Parameter Register */ +#define EBC_BXAP_BME_ENABLED PPC_REG_VAL(0, 0x1) +#define EBC_BXAP_BME_DISABLED PPC_REG_VAL(0, 0x0) +#define EBC_BXAP_TWT_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0xFF) +#define EBC_BXAP_FWT_ENCODE(n) PPC_REG_VAL(5, (static_cast(u32, n)) & 0x1F) +#define EBC_BXAP_BWT_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0x7) +#define EBC_BXAP_BCE_DISABLE PPC_REG_VAL(9, 0x0) +#define EBC_BXAP_BCE_ENABLE PPC_REG_VAL(9, 0x1) +#define EBC_BXAP_BCT_MASK PPC_REG_VAL(11, 0x3) +#define EBC_BXAP_BCT_2TRANS PPC_REG_VAL(11, 0x0) +#define EBC_BXAP_BCT_4TRANS PPC_REG_VAL(11, 0x1) +#define EBC_BXAP_BCT_8TRANS PPC_REG_VAL(11, 0x2) +#define EBC_BXAP_BCT_16TRANS PPC_REG_VAL(11, 0x3) +#define EBC_BXAP_CSN_ENCODE(n) PPC_REG_VAL(13, (static_cast(u32, n)) & 0x3) +#define EBC_BXAP_OEN_ENCODE(n) PPC_REG_VAL(15, (static_cast(u32, n)) & 0x3) +#define EBC_BXAP_WBN_ENCODE(n) PPC_REG_VAL(17, (static_cast(u32, n)) & 0x3) +#define EBC_BXAP_WBF_ENCODE(n) PPC_REG_VAL(19, (static_cast(u32, n)) & 0x3) +#define EBC_BXAP_TH_ENCODE(n) PPC_REG_VAL(22, (static_cast(u32, n)) & 0x7) +#define EBC_BXAP_RE_ENABLED PPC_REG_VAL(23, 0x1) +#define EBC_BXAP_RE_DISABLED PPC_REG_VAL(23, 0x0) +#define EBC_BXAP_SOR_DELAYED PPC_REG_VAL(24, 0x0) +#define EBC_BXAP_SOR_NONDELAYED PPC_REG_VAL(24, 0x1) +#define EBC_BXAP_BEM_WRITEONLY PPC_REG_VAL(25, 0x0) +#define EBC_BXAP_BEM_RW PPC_REG_VAL(25, 0x1) +#define EBC_BXAP_PEN_DISABLED PPC_REG_VAL(26, 0x0) +#define EBC_BXAP_PEN_ENABLED PPC_REG_VAL(26, 0x1) + +/* Common fields in EBC0_CFG register */ +#define EBC_CFG_PTD_MASK PPC_REG_VAL(1, 0x1) +#define EBC_CFG_PTD_ENABLE PPC_REG_VAL(1, 0x0) +#define EBC_CFG_PTD_DISABLE PPC_REG_VAL(1, 0x1) +#define EBC_CFG_RTC_MASK PPC_REG_VAL(4, 0x7) +#define EBC_CFG_RTC_16PERCLK PPC_REG_VAL(4, 0x0) +#define EBC_CFG_RTC_32PERCLK PPC_REG_VAL(4, 0x1) +#define EBC_CFG_RTC_64PERCLK PPC_REG_VAL(4, 0x2) +#define EBC_CFG_RTC_128PERCLK PPC_REG_VAL(4, 0x3) +#define EBC_CFG_RTC_256PERCLK PPC_REG_VAL(4, 0x4) +#define EBC_CFG_RTC_512PERCLK PPC_REG_VAL(4, 0x5) +#define EBC_CFG_RTC_1024PERCLK PPC_REG_VAL(4, 0x6) +#define EBC_CFG_RTC_2048PERCLK PPC_REG_VAL(4, 0x7) +#define EBC_CFG_PME_MASK PPC_REG_VAL(14, 0x1) +#define EBC_CFG_PME_DISABLE PPC_REG_VAL(14, 0x0) +#define EBC_CFG_PME_ENABLE PPC_REG_VAL(14, 0x1) +#define EBC_CFG_PMT_MASK PPC_REG_VAL(19, 0x1F) +#define EBC_CFG_PMT_ENCODE(n) PPC_REG_VAL(19, (static_cast(u32, n)) & 0x1F) + +/* Now the two versions of the other bits */ +#if defined(CONFIG_EBC_PPC4xx_IBM_VER1) +#define EBC_CFG_EBTC_MASK PPC_REG_VAL(0, 0x1) +#define EBC_CFG_EBTC_HI PPC_REG_VAL(0, 0x0) +#define EBC_CFG_EBTC_DRIVEN PPC_REG_VAL(0, 0x1) +#define EBC_CFG_EMPH_MASK PPC_REG_VAL(6, 0x3) +#define EBC_CFG_EMPH_ENCODE(n) PPC_REG_VAL(6, (static_cast(u32, n)) & 0x3) +#define EBC_CFG_EMPL_MASK PPC_REG_VAL(8, 0x3) +#define EBC_CFG_EMPL_ENCODE(n) PPC_REG_VAL(8, (static_cast(u32, n)) & 0x3) +#define EBC_CFG_CSTC_MASK PPC_REG_VAL(9, 0x1) +#define EBC_CFG_CSTC_HI PPC_REG_VAL(9, 0x0) +#define EBC_CFG_CSTC_DRIVEN PPC_REG_VAL(9, 0x1) +#define EBC_CFG_BPR_MASK PPC_REG_VAL(11, 0x3) +#define EBC_CFG_BPR_1DW PPC_REG_VAL(11, 0x0) +#define EBC_CFG_BPR_2DW PPC_REG_VAL(11, 0x1) +#define EBC_CFG_BPR_4DW PPC_REG_VAL(11, 0x2) +#define EBC_CFG_EMS_MASK PPC_REG_VAL(13, 0x3) +#define EBC_CFG_EMS_8BIT PPC_REG_VAL(13, 0x0) +#define EBC_CFG_EMS_16BIT PPC_REG_VAL(13, 0x1) +#define EBC_CFG_EMS_32BIT PPC_REG_VAL(13, 0x2) +#else +#define EBC_CFG_LE_MASK PPC_REG_VAL(0, 0x1) +#define EBC_CFG_LE_UNLOCK PPC_REG_VAL(0, 0x0) +#define EBC_CFG_LE_LOCK PPC_REG_VAL(0, 0x1) +#define EBC_CFG_ATC_MASK PPC_REG_VAL(5, 0x1) +#define EBC_CFG_ATC_HI PPC_REG_VAL(5, 0x0) +#define EBC_CFG_ATC_PREVIOUS PPC_REG_VAL(5, 0x1) +#define EBC_CFG_DTC_MASK PPC_REG_VAL(6, 0x1) +#define EBC_CFG_DTC_HI PPC_REG_VAL(6, 0x0) +#define EBC_CFG_DTC_PREVIOUS PPC_REG_VAL(6, 0x1) +#define EBC_CFG_CTC_MASK PPC_REG_VAL(7, 0x1) +#define EBC_CFG_CTC_HI PPC_REG_VAL(7, 0x0) +#define EBC_CFG_CTC_PREVIOUS PPC_REG_VAL(7, 0x1) +#define EBC_CFG_OEO_MASK PPC_REG_VAL(8, 0x1) +#define EBC_CFG_OEO_HI PPC_REG_VAL(8, 0x0) +#define EBC_CFG_OEO_PREVIOUS PPC_REG_VAL(8, 0x1) +#define EBC_CFG_EMC_MASK PPC_REG_VAL(9, 0x1) +#define EBC_CFG_EMC_NONDEFAULT PPC_REG_VAL(9, 0x0) +#define EBC_CFG_EMC_DEFAULT PPC_REG_VAL(9, 0x1) +#define EBC_CFG_PR_MASK PPC_REG_VAL(21, 0x3) +#define EBC_CFG_PR_16 PPC_REG_VAL(21, 0x0) +#define EBC_CFG_PR_32 PPC_REG_VAL(21, 0x1) +#define EBC_CFG_PR_64 PPC_REG_VAL(21, 0x2) +#define EBC_CFG_PR_128 PPC_REG_VAL(21, 0x3) +#endif + +#endif /* _PPC4xx_EBC_H_ */ diff --git a/include/asm-ppc/ppc4xx-intvec.h b/include/asm-ppc/ppc4xx-intvec.h deleted file mode 100644 index 5b45de4335..0000000000 --- a/include/asm-ppc/ppc4xx-intvec.h +++ /dev/null @@ -1,474 +0,0 @@ -/* -* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ - -/* - * Interrupt vector number definitions to ease the - * 405 -- 440 porting pain ;-) - * - * NOTE: They're not all here yet ... update as needed. - * - */ - -#ifndef _VECNUMS_H_ -#define _VECNUMS_H_ - -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - -/* UIC 0 */ -#define VECNUM_U0 0 /* UART 0 */ -#define VECNUM_U1 1 /* UART 1 */ -#define VECNUM_IIC0 2 /* IIC */ -#define VECNUM_KRD 3 /* Kasumi Ready for data */ -#define VECNUM_KDA 4 /* Kasumi Data Available */ -#define VECNUM_PCRW 5 /* PCI command register write */ -#define VECNUM_PPM 6 /* PCI power management */ -#define VECNUM_IIC1 7 /* IIC */ -#define VECNUM_SPI 8 /* SPI */ -#define VECNUM_EPCISER 9 /* External PCI SERR */ -#define VECNUM_MTE 10 /* MAL TXEOB */ -#define VECNUM_MRE 11 /* MAL RXEOB */ -#define VECNUM_D0 12 /* DMA channel 0 */ -#define VECNUM_D1 13 /* DMA channel 1 */ -#define VECNUM_D2 14 /* DMA channel 2 */ -#define VECNUM_D3 15 /* DMA channel 3 */ -#define VECNUM_UD0 16 /* UDMA irq 0 */ -#define VECNUM_UD1 17 /* UDMA irq 1 */ -#define VECNUM_UD2 18 /* UDMA irq 2 */ -#define VECNUM_UD3 19 /* UDMA irq 3 */ -#define VECNUM_HSB2D 20 /* USB2.0 Device */ -#define VECNUM_USBDEV 20 /* USB 1.1/USB 2.0 Device */ -#define VECNUM_OHCI1 21 /* USB2.0 Host OHCI irq 1 */ -#define VECNUM_OHCI2 22 /* USB2.0 Host OHCI irq 2 */ -#define VECNUM_EIP94 23 /* Security EIP94 */ -#define VECNUM_ETH0 24 /* Emac 0 */ -#define VECNUM_ETH1 25 /* Emac 1 */ -#define VECNUM_EHCI 26 /* USB2.0 Host EHCI */ -#define VECNUM_EIR4 27 /* External interrupt 4 */ -#define VECNUM_UIC2NC 28 /* UIC2 non-critical interrupt */ -#define VECNUM_UIC2C 29 /* UIC2 critical interrupt */ -#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ -#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ - -/* UIC 1 */ -#define VECNUM_MS (32 + 0) /* MAL SERR */ -#define VECNUM_MTDE (32 + 1) /* MAL TXDE */ -#define VECNUM_MRDE (32 + 2) /* MAL RXDE */ -#define VECNUM_U2 (32 + 3) /* UART 2 */ -#define VECNUM_U3 (32 + 4) /* UART 3 */ -#define VECNUM_EBCO (32 + 5) /* EBCO interrupt status */ -#define VECNUM_NDFC (32 + 6) /* NDFC */ -#define VECNUM_KSLE (32 + 7) /* KASUMI slave error */ -#define VECNUM_CT5 (32 + 8) /* GPT compare timer 5 */ -#define VECNUM_CT6 (32 + 9) /* GPT compare timer 6 */ -#define VECNUM_PLB34I0 (32 + 10) /* PLB3X4X MIRQ0 */ -#define VECNUM_PLB34I1 (32 + 11) /* PLB3X4X MIRQ1 */ -#define VECNUM_PLB34I2 (32 + 12) /* PLB3X4X MIRQ2 */ -#define VECNUM_PLB34I3 (32 + 13) /* PLB3X4X MIRQ3 */ -#define VECNUM_PLB34I4 (32 + 14) /* PLB3X4X MIRQ4 */ -#define VECNUM_PLB34I5 (32 + 15) /* PLB3X4X MIRQ5 */ -#define VECNUM_CT0 (32 + 16) /* GPT compare timer 0 */ -#define VECNUM_CT1 (32 + 17) /* GPT compare timer 1 */ -#define VECNUM_EIR7 (32 + 18) /* External interrupt 7 */ -#define VECNUM_EIR8 (32 + 19) /* External interrupt 8 */ -#define VECNUM_EIR9 (32 + 20) /* External interrupt 9 */ -#define VECNUM_CT2 (32 + 21) /* GPT compare timer 2 */ -#define VECNUM_CT3 (32 + 22) /* GPT compare timer 3 */ -#define VECNUM_CT4 (32 + 23) /* GPT compare timer 4 */ -#define VECNUM_SRE (32 + 24) /* Serial ROM error */ -#define VECNUM_GPTDC (32 + 25) /* GPT decrementer pulse */ -#define VECNUM_RSVD0 (32 + 26) /* Reserved */ -#define VECNUM_EPCIPER (32 + 27) /* External PCI PERR */ -#define VECNUM_EIR0 (32 + 28) /* External interrupt 0 */ -#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */ -#define VECNUM_EIR1 (32 + 30) /* External interrupt 1 */ -#define VECNUM_EWU1 (32 + 31) /* Ethernet 1 wakeup */ - -#define VECNUM_TXDE VECNUM_MTDE -#define VECNUM_RXDE VECNUM_MRDE - -/* UIC 2 */ -#define VECNUM_EIR5 (64 + 0) /* External interrupt 5 */ -#define VECNUM_EIR6 (64 + 1) /* External interrupt 6 */ -#define VECNUM_OPB (64 + 2) /* OPB to PLB bridge int stat */ -#define VECNUM_EIR2 (64 + 3) /* External interrupt 2 */ -#define VECNUM_EIR3 (64 + 4) /* External interrupt 3 */ -#define VECNUM_DDR2 (64 + 5) /* DDR2 sdram */ -#define VECNUM_MCTX0 (64 + 6) /* MAl intp coalescence TX0 */ -#define VECNUM_MCTX1 (64 + 7) /* MAl intp coalescence TX1 */ -#define VECNUM_MCTR0 (64 + 8) /* MAl intp coalescence TR0 */ -#define VECNUM_MCTR1 (64 + 9) /* MAl intp coalescence TR1 */ - -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) - -/* UIC 0 */ -#define VECNUM_U1 1 /* UART1 */ -#define VECNUM_IIC0 2 /* IIC0 */ -#define VECNUM_IIC1 3 /* IIC1 */ -#define VECNUM_PIM 4 /* PCI inbound message */ -#define VECNUM_PCRW 5 /* PCI command reg write */ -#define VECNUM_PPM 6 /* PCI power management */ -#define VECNUM_MSI0 8 /* PCI MSI level 0 */ -#define VECNUM_EIR0 9 /* External interrupt 0 */ -#define VECNUM_UIC2NC 10 /* UIC2 non-critical interrupt */ -#define VECNUM_UIC2C 11 /* UIC2 critical interrupt */ -#define VECNUM_D0 12 /* DMA channel 0 */ -#define VECNUM_D1 13 /* DMA channel 1 */ -#define VECNUM_D2 14 /* DMA channel 2 */ -#define VECNUM_D3 15 /* DMA channel 3 */ -#define VECNUM_UIC3NC 16 /* UIC3 non-critical interrupt */ -#define VECNUM_UIC3C 17 /* UIC3 critical interrupt */ -#define VECNUM_EIR1 9 /* External interrupt 1 */ -#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ -#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ - -/* UIC 1 */ -#define VECNUM_EIR2 (32 + 0) /* External interrupt 0 */ -#define VECNUM_U0 (32 + 1) /* UART0 */ -#define VECNUM_EIR3 (32 + 20) /* External interrupt 3 */ -#define VECNUM_EIR4 (32 + 21) /* External interrupt 4 */ -#define VECNUM_EIR5 (32 + 26) /* External interrupt 5 */ -#define VECNUM_EIR6 (32 + 27) /* External interrupt 6 */ -#define VECNUM_U2 (32 + 28) /* UART2 */ -#define VECNUM_U3 (32 + 29) /* UART3 */ -#define VECNUM_EIR7 (32 + 30) /* External interrupt 7 */ -#define VECNUM_EIR8 (32 + 31) /* External interrupt 8 */ - -/* UIC 2 */ -#define VECNUM_EIR9 (64 + 2) /* External interrupt 9 */ -#define VECNUM_MS (64 + 3) /* MAL SERR */ -#define VECNUM_TXDE (64 + 4) /* MAL TXDE */ -#define VECNUM_RXDE (64 + 5) /* MAL RXDE */ -#define VECNUM_MTE (64 + 6) /* MAL TXEOB */ -#define VECNUM_MRE (64 + 7) /* MAL RXEOB */ -#define VECNUM_ETH0 (64 + 16) /* Ethernet 0 */ -#define VECNUM_ETH1 (64 + 17) /* Ethernet 1 */ -#define VECNUM_ETH2 (64 + 18) /* Ethernet 2 */ -#define VECNUM_ETH3 (64 + 19) /* Ethernet 3 */ -#define VECNUM_EWU0 (64 + 20) /* Emac 0 wakeup */ -#define VECNUM_EWU1 (64 + 21) /* Emac 1 wakeup */ -#define VECNUM_EWU2 (64 + 22) /* Emac 2 wakeup */ -#define VECNUM_EWU3 (64 + 23) /* Emac 3 wakeup */ -#define VECNUM_EIR10 (64 + 24) /* External interrupt 10 */ -#define VECNUM_EIR11 (64 + 25) /* External interrupt 11 */ - -/* UIC 3 */ -#define VECNUM_EIR12 (96 + 20) /* External interrupt 20 */ -#define VECNUM_EIR13 (96 + 21) /* External interrupt 21 */ -#define VECNUM_EIR14 (96 + 22) /* External interrupt 22 */ -#define VECNUM_EIR15 (96 + 23) /* External interrupt 23 */ -#define VECNUM_PCIEMSI0 (96 + 24) /* PCI Express MSI level 0 */ -#define VECNUM_PCIEMSI1 (96 + 25) /* PCI Express MSI level 1 */ -#define VECNUM_PCIEMSI2 (96 + 26) /* PCI Express MSI level 2 */ -#define VECNUM_PCIEMSI3 (96 + 27) /* PCI Express MSI level 3 */ -#define VECNUM_PCIEMSI4 (96 + 28) /* PCI Express MSI level 4 */ -#define VECNUM_PCIEMSI5 (96 + 29) /* PCI Express MSI level 5 */ -#define VECNUM_PCIEMSI6 (96 + 30) /* PCI Express MSI level 6 */ -#define VECNUM_PCIEMSI7 (96 + 31) /* PCI Express MSI level 7 */ - -#elif defined(CONFIG_440SPE) - -/* UIC 0 */ -#define VECNUM_U0 0 /* UART0 */ -#define VECNUM_U1 1 /* UART1 */ -#define VECNUM_IIC0 2 /* IIC0 */ -#define VECNUM_IIC1 3 /* IIC1 */ -#define VECNUM_PIM 4 /* PCI inbound message */ -#define VECNUM_PCRW 5 /* PCI command reg write */ -#define VECNUM_PPM 6 /* PCI power management */ -#define VECNUM_MSI0 7 /* PCI MSI level 0 */ -#define VECNUM_MSI1 8 /* PCI MSI level 0 */ -#define VECNUM_MSI2 9 /* PCI MSI level 0 */ -#define VECNUM_UIC2NC 10 /* UIC2 non-critical interrupt */ -#define VECNUM_UIC2C 11 /* UIC2 critical interrupt */ -#define VECNUM_D0 12 /* DMA channel 0 */ -#define VECNUM_D1 13 /* DMA channel 1 */ -#define VECNUM_D2 14 /* DMA channel 2 */ -#define VECNUM_D3 15 /* DMA channel 3 */ -#define VECNUM_UIC3NC 16 /* UIC3 non-critical interrupt */ -#define VECNUM_UIC3C 17 /* UIC3 critical interrupt */ -#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ -#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ - -/* UIC 1 */ -#define VECNUM_MS (32 + 1 ) /* MAL SERR */ -#define VECNUM_TXDE (32 + 2 ) /* MAL TXDE */ -#define VECNUM_RXDE (32 + 3 ) /* MAL RXDE */ -#define VECNUM_MTE (32 + 6 ) /* MAL Tx EOB */ -#define VECNUM_MRE (32 + 7 ) /* MAL Rx EOB */ -#define VECNUM_CT0 (32 + 12 ) /* GPT compare timer 0 */ -#define VECNUM_CT1 (32 + 13 ) /* GPT compare timer 1 */ -#define VECNUM_CT2 (32 + 14 ) /* GPT compare timer 2 */ -#define VECNUM_CT3 (32 + 15 ) /* GPT compare timer 3 */ -#define VECNUM_CT4 (32 + 16 ) /* GPT compare timer 4 */ -#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */ -#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */ - -/* UIC 2 */ -#define VECNUM_EIR5 (64 + 24) /* External interrupt 5 */ -#define VECNUM_EIR4 (64 + 25) /* External interrupt 4 */ -#define VECNUM_EIR3 (64 + 26) /* External interrupt 3 */ -#define VECNUM_EIR2 (64 + 27) /* External interrupt 2 */ -#define VECNUM_EIR1 (64 + 28) /* External interrupt 1 */ -#define VECNUM_EIR0 (64 + 29) /* External interrupt 0 */ - -#elif defined(CONFIG_440SP) - -/* UIC 0 */ -#define VECNUM_U0 0 /* UART0 */ -#define VECNUM_U1 1 /* UART1 */ -#define VECNUM_IIC0 2 /* IIC0 */ -#define VECNUM_IIC1 3 /* IIC1 */ -#define VECNUM_PIM 4 /* PCI inbound message */ -#define VECNUM_PCRW 5 /* PCI command reg write */ -#define VECNUM_PPM 6 /* PCI power management */ -#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ -#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ - -/* UIC 1 */ -#define VECNUM_EIR0 (32 + 0) /* External interrupt 0 */ -#define VECNUM_MS (32 + 1) /* MAL SERR */ -#define VECNUM_TXDE (32 + 2) /* MAL TXDE */ -#define VECNUM_RXDE (32 + 3) /* MAL RXDE */ -#define VECNUM_MTE (32 + 6) /* MAL Tx EOB */ -#define VECNUM_MRE (32 + 7) /* MAL Rx EOB */ -#define VECNUM_CT0 (32 + 12) /* GPT compare timer 0 */ -#define VECNUM_CT1 (32 + 13) /* GPT compare timer 1 */ -#define VECNUM_CT2 (32 + 14) /* GPT compare timer 2 */ -#define VECNUM_CT3 (32 + 15) /* GPT compare timer 3 */ -#define VECNUM_CT4 (32 + 16) /* GPT compare timer 4 */ -#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */ -#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */ - -#elif defined(CONFIG_440) - -/* UIC 0 */ -#define VECNUM_U0 0 /* UART0 */ -#define VECNUM_U1 1 /* UART1 */ -#define VECNUM_IIC0 2 /* IIC0 */ -#define VECNUM_IIC1 3 /* IIC1 */ -#define VECNUM_PIM 4 /* PCI inbound message */ -#define VECNUM_PCRW 5 /* PCI command reg write */ -#define VECNUM_PPM 6 /* PCI power management */ -#define VECNUM_MSI0 7 /* PCI MSI level 0 */ -#define VECNUM_MSI1 8 /* PCI MSI level 0 */ -#define VECNUM_MSI2 9 /* PCI MSI level 0 */ -#define VECNUM_MTE 10 /* MAL TXEOB */ -#define VECNUM_MRE 11 /* MAL RXEOB */ -#define VECNUM_D0 12 /* DMA channel 0 */ -#define VECNUM_D1 13 /* DMA channel 1 */ -#define VECNUM_D2 14 /* DMA channel 2 */ -#define VECNUM_D3 15 /* DMA channel 3 */ -#define VECNUM_CT0 18 /* GPT compare timer 0 */ -#define VECNUM_CT1 19 /* GPT compare timer 1 */ -#define VECNUM_CT2 20 /* GPT compare timer 2 */ -#define VECNUM_CT3 21 /* GPT compare timer 3 */ -#define VECNUM_CT4 22 /* GPT compare timer 4 */ -#define VECNUM_EIR0 23 /* External interrupt 0 */ -#define VECNUM_EIR1 24 /* External interrupt 1 */ -#define VECNUM_EIR2 25 /* External interrupt 2 */ -#define VECNUM_EIR3 26 /* External interrupt 3 */ -#define VECNUM_EIR4 27 /* External interrupt 4 */ -#define VECNUM_EIR5 28 /* External interrupt 5 */ -#define VECNUM_EIR6 29 /* External interrupt 6 */ -#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ -#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ - -/* UIC 1 */ -#define VECNUM_MS (32 + 0 ) /* MAL SERR */ -#define VECNUM_TXDE (32 + 1 ) /* MAL TXDE */ -#define VECNUM_RXDE (32 + 2 ) /* MAL RXDE */ -#define VECNUM_USBDEV (32 + 23) /* USB 1.1/USB 2.0 Device */ -#define VECNUM_ETH0 (32 + 28) /* Ethernet 0 interrupt status */ -#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */ - -#else /* !defined(CONFIG_440) */ - -#if defined(CONFIG_405EZ) -#define VECNUM_D0 0 /* DMA channel 0 */ -#define VECNUM_D1 1 /* DMA channel 1 */ -#define VECNUM_D2 2 /* DMA channel 2 */ -#define VECNUM_D3 3 /* DMA channel 3 */ -#define VECNUM_1588 4 /* IEEE 1588 network synchronization */ -#define VECNUM_U0 5 /* UART0 */ -#define VECNUM_U1 6 /* UART1 */ -#define VECNUM_CAN0 7 /* CAN 0 */ -#define VECNUM_CAN1 8 /* CAN 1 */ -#define VECNUM_SPI 9 /* SPI */ -#define VECNUM_IIC0 10 /* I2C */ -#define VECNUM_CHT0 11 /* Chameleon timer high pri interrupt */ -#define VECNUM_CHT1 12 /* Chameleon timer high pri interrupt */ -#define VECNUM_USBH1 13 /* USB Host 1 */ -#define VECNUM_USBH2 14 /* USB Host 2 */ -#define VECNUM_USBDEV 15 /* USB Device */ -#define VECNUM_ETH0 16 /* 10/100 Ethernet interrupt status */ -#define VECNUM_EWU0 17 /* Ethernet wakeup sequence detected */ - -#define VECNUM_MADMAL 18 /* Logical OR of following MadMAL int */ -#define VECNUM_MS 18 /* MAL_SERR_INT */ -#define VECNUM_TXDE 18 /* MAL_TXDE_INT */ -#define VECNUM_RXDE 18 /* MAL_RXDE_INT */ - -#define VECNUM_MTE 19 /* MAL TXEOB */ -#define VECNUM_MTE1 20 /* MAL TXEOB1 */ -#define VECNUM_MRE 21 /* MAL RXEOB */ -#define VECNUM_NAND 22 /* NAND Flash controller */ -#define VECNUM_ADC 23 /* ADC */ -#define VECNUM_DAC 24 /* DAC */ -#define VECNUM_OPB2PLB 25 /* OPB to PLB bridge interrupt */ -#define VECNUM_RESERVED0 26 /* Reserved */ -#define VECNUM_EIR0 27 /* External interrupt 0 */ -#define VECNUM_EIR1 28 /* External interrupt 1 */ -#define VECNUM_EIR2 29 /* External interrupt 2 */ -#define VECNUM_EIR3 30 /* External interrupt 3 */ -#define VECNUM_EIR4 31 /* External interrupt 4 */ - -#elif defined(CONFIG_405EX) - -/* UIC 0 */ -#define VECNUM_U0 00 -#define VECNUM_U1 01 -#define VECNUM_IIC0 02 -#define VECNUM_PKA 03 -#define VECNUM_TRNG 04 -#define VECNUM_EBM 05 -#define VECNUM_BGI 06 -#define VECNUM_IIC1 07 -#define VECNUM_SPI 08 -#define VECNUM_EIR0 09 -#define VECNUM_MTE 10 /* MAL Tx EOB */ -#define VECNUM_MRE 11 /* MAL Rx EOB */ -#define VECNUM_DMA0 12 -#define VECNUM_DMA1 13 -#define VECNUM_DMA2 14 -#define VECNUM_DMA3 15 -#define VECNUM_PCIE0AL 16 -#define VECNUM_PCIE0VPD 17 -#define VECNUM_RPCIE0HRST 18 -#define VECNUM_FPCIE0HRST 19 -#define VECNUM_PCIE0TCR 20 -#define VECNUM_PCIEMSI0 21 -#define VECNUM_PCIEMSI1 22 -#define VECNUM_SECURITY 23 -#define VECNUM_ETH0 24 -#define VECNUM_ETH1 25 -#define VECNUM_PCIEMSI2 26 -#define VECNUM_EIR4 27 -#define VECNUM_UIC2NC 28 -#define VECNUM_UIC2C 29 -#define VECNUM_UIC1NC 30 -#define VECNUM_UIC1C 31 - -/* UIC 1 */ -#define VECNUM_MS (32 + 00) /* MAL SERR */ -#define VECNUM_TXDE (32 + 01) /* MAL TXDE */ -#define VECNUM_RXDE (32 + 02) /* MAL RXDE */ -#define VECNUM_PCIE0BMVC0 (32 + 03) -#define VECNUM_PCIE0DCRERR (32 + 04) -#define VECNUM_EBC (32 + 05) -#define VECNUM_NDFC (32 + 06) -#define VECNUM_PCEI1DCRERR (32 + 07) -#define VECNUM_CT8 (32 + 08) -#define VECNUM_CT9 (32 + 09) -#define VECNUM_PCIE1AL (32 + 10) -#define VECNUM_PCIE1VPD (32 + 11) -#define VECNUM_RPCE1HRST (32 + 12) -#define VECNUM_FPCE1HRST (32 + 13) -#define VECNUM_PCIE1TCR (32 + 14) -#define VECNUM_PCIE1VC0 (32 + 15) -#define VECNUM_CT3 (32 + 16) -#define VECNUM_CT4 (32 + 17) -#define VECNUM_EIR7 (32 + 18) -#define VECNUM_EIR8 (32 + 19) -#define VECNUM_EIR9 (32 + 20) -#define VECNUM_CT5 (32 + 21) -#define VECNUM_CT6 (32 + 22) -#define VECNUM_CT7 (32 + 23) -#define VECNUM_SROM (32 + 24) /* SERIAL ROM */ -#define VECNUM_GPTDECPULS (32 + 25) /* GPT Decrement pulse */ -#define VECNUM_EIR2 (32 + 26) -#define VECNUM_EIR5 (32 + 27) -#define VECNUM_EIR6 (32 + 28) -#define VECNUM_EMAC0WAKE (32 + 29) -#define VECNUM_EIR1 (32 + 30) -#define VECNUM_EMAC1WAKE (32 + 31) - -/* UIC 2 */ -#define VECNUM_PCIE0INTA (64 + 00) /* PCIE0 INTA */ -#define VECNUM_PCIE0INTB (64 + 01) /* PCIE0 INTB */ -#define VECNUM_PCIE0INTC (64 + 02) /* PCIE0 INTC */ -#define VECNUM_PCIE0INTD (64 + 03) /* PCIE0 INTD */ -#define VECNUM_EIR3 (64 + 04) /* External IRQ 3 */ -#define VECNUM_DDRMCUE (64 + 05) -#define VECNUM_DDRMCCE (64 + 06) -#define VECNUM_MALINTCOATX0 (64 + 07) /* Interrupt coalecence TX0 */ -#define VECNUM_MALINTCOATX1 (64 + 08) /* Interrupt coalecence TX1 */ -#define VECNUM_MALINTCOARX0 (64 + 09) /* Interrupt coalecence RX0 */ -#define VECNUM_MALINTCOARX1 (64 + 10) /* Interrupt coalecence RX1 */ -#define VECNUM_PCIE1INTA (64 + 11) /* PCIE0 INTA */ -#define VECNUM_PCIE1INTB (64 + 12) /* PCIE0 INTB */ -#define VECNUM_PCIE1INTC (64 + 13) /* PCIE0 INTC */ -#define VECNUM_PCIE1INTD (64 + 14) /* PCIE0 INTD */ -#define VECNUM_RPCIEMSI2 (64 + 15) /* MSI level 2 */ -#define VECNUM_PCIEMSI3 (64 + 16) /* MSI level 2 */ -#define VECNUM_PCIEMSI4 (64 + 17) /* MSI level 2 */ -#define VECNUM_PCIEMSI5 (64 + 18) /* MSI level 2 */ -#define VECNUM_PCIEMSI6 (64 + 19) /* MSI level 2 */ -#define VECNUM_PCIEMSI7 (64 + 20) /* MSI level 2 */ -#define VECNUM_PCIEMSI8 (64 + 21) /* MSI level 2 */ -#define VECNUM_PCIEMSI9 (64 + 22) /* MSI level 2 */ -#define VECNUM_PCIEMSI10 (64 + 23) /* MSI level 2 */ -#define VECNUM_PCIEMSI11 (64 + 24) /* MSI level 2 */ -#define VECNUM_PCIEMSI12 (64 + 25) /* MSI level 2 */ -#define VECNUM_PCIEMSI13 (64 + 26) /* MSI level 2 */ -#define VECNUM_PCIEMSI14 (64 + 27) /* MSI level 2 */ -#define VECNUM_PCIEMSI15 (64 + 28) /* MSI level 2 */ -#define VECNUM_PLB4XAHB (64 + 29) /* PLBxAHB bridge */ -#define VECNUM_USBWAKE (64 + 30) /* USB wakup */ -#define VECNUM_USBOTG (64 + 31) /* USB OTG */ - -#else /* !CONFIG_405EZ */ - -#define VECNUM_U0 0 /* UART0 */ -#define VECNUM_U1 1 /* UART1 */ -#define VECNUM_D0 5 /* DMA channel 0 */ -#define VECNUM_D1 6 /* DMA channel 1 */ -#define VECNUM_D2 7 /* DMA channel 2 */ -#define VECNUM_D3 8 /* DMA channel 3 */ -#define VECNUM_EWU0 9 /* Ethernet wakeup */ -#define VECNUM_MS 10 /* MAL SERR */ -#define VECNUM_MTE 11 /* MAL TXEOB */ -#define VECNUM_MRE 12 /* MAL RXEOB */ -#define VECNUM_TXDE 13 /* MAL TXDE */ -#define VECNUM_RXDE 14 /* MAL RXDE */ -#define VECNUM_ETH0 15 /* Ethernet interrupt status */ -#define VECNUM_EIR0 25 /* External interrupt 0 */ -#define VECNUM_EIR1 26 /* External interrupt 1 */ -#define VECNUM_EIR2 27 /* External interrupt 2 */ -#define VECNUM_EIR3 28 /* External interrupt 3 */ -#define VECNUM_EIR4 29 /* External interrupt 4 */ -#define VECNUM_EIR5 30 /* External interrupt 5 */ -#define VECNUM_EIR6 31 /* External interrupt 6 */ -#endif /* defined(CONFIG_405EZ) */ - -#endif /* defined(CONFIG_440) */ - -#endif /* _VECNUMS_H_ */ diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index e151f0c113..df787b3d4c 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -282,7 +282,8 @@ * Memory Bank 0-7 configuration */ #if defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) #define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */ #define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000)) #define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2) @@ -353,7 +354,19 @@ /* * Memory controller registers */ +#define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */ +#define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */ +#define SDRAM_BEARL 0x02 /* PLB bus error address low */ +#define SDRAM_BEARH 0x03 /* PLB bus error address high */ +#define SDRAM_WMIRQ 0x06 /* PLB write master interrupt (read/clear) */ +#define SDRAM_WMIRQT 0x07 /* PLB write master interrupt (test/set) */ +#define SDRAM_PLBOPT 0x08 /* PLB slave options */ +#define SDRAM_PUABA 0x09 /* PLB upper address base */ +#ifndef CONFIG_405EX #define SDRAM_MCSTAT 0x14 /* memory controller status */ +#else +#define SDRAM_MCSTAT 0x1F /* memory controller status */ +#endif #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ #define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ #define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ @@ -398,9 +411,35 @@ #define SDRAM_MMODE 0x88 /* memory mode */ #define SDRAM_MEMODE 0x89 /* memory extended mode */ #define SDRAM_ECCCR 0x98 /* ECC error status */ +#define SDRAM_ECCES SDRAM_ECCCR #define SDRAM_CID 0xA4 /* core ID */ +#ifndef CONFIG_405EX #define SDRAM_RID 0xA8 /* revision ID */ +#endif +#define SDRAM_FCSR 0xB0 /* feedback calibration status */ #define SDRAM_RTSR 0xB1 /* run time status tracking */ +#ifdef CONFIG_405EX +#define SDRAM_RID 0xF8 /* revision ID */ +#endif + +/* + * Memory Controller Bus Error Status + */ +#define SDRAM_BESR_MASK PPC_REG_VAL(7, 0xFF) +#define SDRAM_BESR_M0ID_MASK PPC_REG_VAL(3, 0xF) +#define SDRAM_BESR_M0ID_ICU PPC_REG_VAL(3, 0x0) +#define SDRAM_BESR_M0ID_PCIE0 PPC_REG_VAL(3, 0x1) +#define SDRAM_BESR_M0ID_PCIE1 PPC_REG_VAL(3, 0x2) +#define SDRAM_BESR_M0ID_DMA PPC_REG_VAL(3, 0x3) +#define SDRAM_BESR_M0ID_DCU PPC_REG_VAL(3, 0x4) +#define SDRAM_BESR_M0ID_OPB PPC_REG_VAL(3, 0x5) +#define SDRAM_BESR_M0ID_MAL PPC_REG_VAL(3, 0x6) +#define SDRAM_BESR_M0ID_SEC PPC_REG_VAL(3, 0x7) +#define SDRAM_BESR_M0ET_MASK PPC_REG_VAL(6, 0x7) +#define SDRAM_BESR_M0ET_NONE PPC_REG_VAL(6, 0x0) +#define SDRAM_BESR_M0ET_ECC PPC_REG_VAL(6, 0x1) +#define SDRAM_BESR_M0RW_WRITE PPC_REG_VAL(7, 0) +#define SDRAM_BESR_M0RW_READ PPC_REG_VAL(8, 1) /* * Memory Controller Status @@ -523,7 +562,7 @@ * SDRAM Delay Line Calibration Register */ #define SDRAM_DLCR_DCLM_MASK 0x80000000 -#define SDRAM_DLCR_DCLM_MANUEL 0x80000000 +#define SDRAM_DLCR_DCLM_MANUAL 0x80000000 #define SDRAM_DLCR_DCLM_AUTO 0x00000000 #define SDRAM_DLCR_DLCR_MASK 0x08000000 #define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000 @@ -539,59 +578,234 @@ #define SDRAM_DLCR_DLCV_DECODE(n) ((((u32)(n))>>0)&0x1FF) /* + * SDRAM Memory On Die Terimination Control Register + */ +#define SDRAM_MODT_ODTON_DISABLE PPC_REG_VAL(0, 0) +#define SDRAM_MODT_ODTON_ENABLE PPC_REG_VAL(0, 1) +#define SDRAM_MODT_EB1W_DISABLE PPC_REG_VAL(1, 0) +#define SDRAM_MODT_EB1W_ENABLE PPC_REG_VAL(1, 1) +#define SDRAM_MODT_EB1R_DISABLE PPC_REG_VAL(2, 0) +#define SDRAM_MODT_EB1R_ENABLE PPC_REG_VAL(2, 1) +#define SDRAM_MODT_EB0W_DISABLE PPC_REG_VAL(7, 0) +#define SDRAM_MODT_EB0W_ENABLE PPC_REG_VAL(7, 1) +#define SDRAM_MODT_EB0R_DISABLE PPC_REG_VAL(8, 0) +#define SDRAM_MODT_EB0R_ENABLE PPC_REG_VAL(8, 1) + +/* * SDRAM Controller On Die Termination Register */ -#define SDRAM_CODT_ODT_ON 0x80000000 -#define SDRAM_CODT_ODT_OFF 0x00000000 -#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020 -#define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000 -#define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020 -#define SDRAM_CODT_DQS_MASK 0x00000010 -#define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000 -#define SDRAM_CODT_DQS_SINGLE_END 0x00000010 -#define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000 -#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008 -#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004 -#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002 -#define SDRAM_CODT_IO_HIZ 0x00000000 -#define SDRAM_CODT_IO_NMODE 0x00000001 +#define SDRAM_CODT_ODT_ON PPC_REG_VAL(0, 1) +#define SDRAM_CODT_ODT_OFF PPC_REG_VAL(0, 0) +#define SDRAM_CODT_RK1W_ON PPC_REG_VAL(1, 1) +#define SDRAM_CODT_RK1W_OFF PPC_REG_VAL(1, 0) +#define SDRAM_CODT_RK1R_ON PPC_REG_VAL(2, 1) +#define SDRAM_CODT_RK1R_OFF PPC_REG_VAL(2, 0) +#define SDRAM_CODT_RK0W_ON PPC_REG_VAL(7, 1) +#define SDRAM_CODT_RK0W_OFF PPC_REG_VAL(7, 0) +#define SDRAM_CODT_RK0R_ON PPC_REG_VAL(8, 1) +#define SDRAM_CODT_RK0R_OFF PPC_REG_VAL(8, 0) +#define SDRAM_CODT_ODTSH_NORMAL PPC_REG_VAL(10, 0) +#define SDRAM_CODT_ODTSH_REMOVE_ONE_AT_END PPC_REG_VAL(10, 1) +#define SDRAM_CODT_ODTSH_ADD_ONE_AT_START PPC_REG_VAL(10, 2) +#define SDRAM_CODT_ODTSH_SHIFT_ONE_EARLIER PPC_REG_VAL(10, 3) +#define SDRAM_CODT_CODTZ_75OHM PPC_REG_VAL(11, 0) +#define SDRAM_CODT_CKEG_ON PPC_REG_VAL(12, 1) +#define SDRAM_CODT_CKEG_OFF PPC_REG_VAL(12, 0) +#define SDRAM_CODT_CTLG_ON PPC_REG_VAL(13, 1) +#define SDRAM_CODT_CTLG_OFF PPC_REG_VAL(13, 0) +#define SDRAM_CODT_FBDG_ON PPC_REG_VAL(14, 1) +#define SDRAM_CODT_FBDG_OFF PPC_REG_VAL(14, 0) +#define SDRAM_CODT_FBRG_ON PPC_REG_VAL(15, 1) +#define SDRAM_CODT_FBRG_OFF PPC_REG_VAL(15, 0) +#define SDRAM_CODT_CKLZ_36OHM PPC_REG_VAL(18, 1) +#define SDRAM_CODT_CKLZ_18OHM PPC_REG_VAL(18, 0) +#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK PPC_REG_VAL(26, 1) +#define SDRAM_CODT_DQS_2_5_V_DDR1 PPC_REG_VAL(26, 0) +#define SDRAM_CODT_DQS_1_8_V_DDR2 PPC_REG_VAL(26, 1) +#define SDRAM_CODT_DQS_MASK PPC_REG_VAL(27, 1) +#define SDRAM_CODT_DQS_DIFFERENTIAL PPC_REG_VAL(27, 0) +#define SDRAM_CODT_DQS_SINGLE_END PPC_REG_VAL(27, 1) +#define SDRAM_CODT_CKSE_DIFFERENTIAL PPC_REG_VAL(28, 0) +#define SDRAM_CODT_CKSE_SINGLE_END PPC_REG_VAL(28, 1) +#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END PPC_REG_VAL(29, 1) +#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END PPC_REG_VAL(30, 1) +#define SDRAM_CODT_IO_HIZ PPC_REG_VAL(31, 0) +#define SDRAM_CODT_IO_NMODE PPC_REG_VAL(31, 1) /* - * SDRAM Mode Register + * SDRAM Initialization Preload Register */ -#define SDRAM_MMODE_WR_MASK 0x00000E00 -#define SDRAM_MMODE_WR_DDR1 0x00000000 -#define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400 -#define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600 -#define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800 -#define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00 -#define SDRAM_MMODE_DCL_MASK 0x00000070 -#define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020 -#define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060 -#define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030 -#define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020 -#define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030 -#define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040 -#define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050 -#define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060 -#define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070 +#define SDRAM_INITPLR_ENABLE PPC_REG_VAL(0, 1) +#define SDRAM_INITPLR_DISABLE PPC_REG_VAL(0, 0) +#define SDRAM_INITPLR_IMWT_MASK PPC_REG_VAL(8, 0xFF) +#define SDRAM_INITPLR_IMWT_ENCODE(n) PPC_REG_VAL(8, \ + (static_cast(u32, \ + n)) \ + & 0xFF) +#define SDRAM_INITPLR_ICMD_MASK PPC_REG_VAL(12, 0x7) +#define SDRAM_INITPLR_ICMD_ENCODE(n) PPC_REG_VAL(12, \ + (static_cast(u32, \ + n)) \ + & 0x7) +#define SDRAM_INITPLR_IBA_MASK PPC_REG_VAL(15, 0x7) +#define SDRAM_INITPLR_IBA_ENCODE(n) PPC_REG_VAL(15, \ + (static_cast(u32, \ + n)) \ + & 0x7) +#define SDRAM_INITPLR_IMA_MASK PPC_REG_VAL(31, 0x7FFF) +#define SDRAM_INITPLR_IMA_ENCODE(n) PPC_REG_VAL(31, \ + (static_cast(u32, \ + n)) \ + & 0x7FFF) /* - * SDRAM Extended Mode Register + * JEDEC DDR Initialization Commands */ -#define SDRAM_MEMODE_DIC_MASK 0x00000002 -#define SDRAM_MEMODE_DIC_NORMAL 0x00000000 -#define SDRAM_MEMODE_DIC_WEAK 0x00000002 -#define SDRAM_MEMODE_DLL_MASK 0x00000001 -#define SDRAM_MEMODE_DLL_DISABLE 0x00000001 -#define SDRAM_MEMODE_DLL_ENABLE 0x00000000 -#define SDRAM_MEMODE_RTT_MASK 0x00000044 -#define SDRAM_MEMODE_RTT_DISABLED 0x00000000 -#define SDRAM_MEMODE_RTT_75OHM 0x00000004 -#define SDRAM_MEMODE_RTT_150OHM 0x00000040 -#define SDRAM_MEMODE_DQS_MASK 0x00000400 -#define SDRAM_MEMODE_DQS_DISABLE 0x00000400 -#define SDRAM_MEMODE_DQS_ENABLE 0x00000000 +#define JEDEC_CMD_NOP 7 +#define JEDEC_CMD_PRECHARGE 2 +#define JEDEC_CMD_REFRESH 1 +#define JEDEC_CMD_EMR 0 +#define JEDEC_CMD_READ 5 +#define JEDEC_CMD_WRITE 4 + +/* + * JEDEC Precharge Command Memory Address Arguments + */ +#define JEDEC_MA_PRECHARGE_ONE (0 << 10) +#define JEDEC_MA_PRECHARGE_ALL (1 << 10) + +/* + * JEDEC DDR EMR Command Bank Address Arguments + */ +#define JEDEC_BA_MR 0 +#define JEDEC_BA_EMR 1 +#define JEDEC_BA_EMR2 2 +#define JEDEC_BA_EMR3 3 + +/* + * JEDEC DDR Mode Register + */ +#define JEDEC_MA_MR_PDMODE_FAST_EXIT (0 << 12) +#define JEDEC_MA_MR_PDMODE_SLOW_EXIT (1 << 12) +#define JEDEC_MA_MR_WR_MASK (0x7 << 9) +#define JEDEC_MA_MR_WR_DDR1 (0x0 << 9) +#define JEDEC_MA_MR_WR_DDR2_2_CYC (0x1 << 9) +#define JEDEC_MA_MR_WR_DDR2_3_CYC (0x2 << 9) +#define JEDEC_MA_MR_WR_DDR2_4_CYC (0x3 << 9) +#define JEDEC_MA_MR_WR_DDR2_5_CYC (0x4 << 9) +#define JEDEC_MA_MR_WR_DDR2_6_CYC (0x5 << 9) +#define JEDEC_MA_MR_DLL_RESET (1 << 8) +#define JEDEC_MA_MR_MODE_NORMAL (0 << 8) +#define JEDEC_MA_MR_MODE_TEST (1 << 8) +#define JEDEC_MA_MR_CL_MASK (0x7 << 4) +#define JEDEC_MA_MR_CL_DDR1_2_0_CLK (0x2 << 4) +#define JEDEC_MA_MR_CL_DDR1_2_5_CLK (0x6 << 4) +#define JEDEC_MA_MR_CL_DDR1_3_0_CLK (0x3 << 4) +#define JEDEC_MA_MR_CL_DDR2_2_0_CLK (0x2 << 4) +#define JEDEC_MA_MR_CL_DDR2_3_0_CLK (0x3 << 4) +#define JEDEC_MA_MR_CL_DDR2_4_0_CLK (0x4 << 4) +#define JEDEC_MA_MR_CL_DDR2_5_0_CLK (0x5 << 4) +#define JEDEC_MA_MR_CL_DDR2_6_0_CLK (0x6 << 4) +#define JEDEC_MA_MR_CL_DDR2_7_0_CLK (0x7 << 4) +#define JEDEC_MA_MR_BTYP_SEQUENTIAL (0 << 3) +#define JEDEC_MA_MR_BTYP_INTERLEAVED (1 << 3) +#define JEDEC_MA_MR_BLEN_MASK (0x7 << 0) +#define JEDEC_MA_MR_BLEN_4 (2 << 0) +#define JEDEC_MA_MR_BLEN_8 (3 << 0) + +/* + * JEDEC DDR Extended Mode Register + */ +#define JEDEC_MA_EMR_OUTPUT_MASK (1 << 12) +#define JEDEC_MA_EMR_OUTPUT_ENABLE (0 << 12) +#define JEDEC_MA_EMR_OUTPUT_DISABLE (1 << 12) +#define JEDEC_MA_EMR_RQDS_MASK (1 << 11) +#define JEDEC_MA_EMR_RDQS_DISABLE (0 << 11) +#define JEDEC_MA_EMR_RDQS_ENABLE (1 << 11) +#define JEDEC_MA_EMR_DQS_MASK (1 << 10) +#define JEDEC_MA_EMR_DQS_DISABLE (1 << 10) +#define JEDEC_MA_EMR_DQS_ENABLE (0 << 10) +#define JEDEC_MA_EMR_OCD_MASK (0x7 << 7) +#define JEDEC_MA_EMR_OCD_EXIT (0 << 7) +#define JEDEC_MA_EMR_OCD_ENTER (7 << 7) +#define JEDEC_MA_EMR_AL_DDR1_0_CYC (0 << 3) +#define JEDEC_MA_EMR_AL_DDR2_1_CYC (1 << 3) +#define JEDEC_MA_EMR_AL_DDR2_2_CYC (2 << 3) +#define JEDEC_MA_EMR_AL_DDR2_3_CYC (3 << 3) +#define JEDEC_MA_EMR_AL_DDR2_4_CYC (4 << 3) +#define JEDEC_MA_EMR_RTT_MASK (0x11 << 2) +#define JEDEC_MA_EMR_RTT_DISABLED (0x00 << 2) +#define JEDEC_MA_EMR_RTT_75OHM (0x01 << 2) +#define JEDEC_MA_EMR_RTT_150OHM (0x10 << 2) +#define JEDEC_MA_EMR_RTT_50OHM (0x11 << 2) +#define JEDEC_MA_EMR_ODS_MASK (1 << 1) +#define JEDEC_MA_EMR_ODS_NORMAL (0 << 1) +#define JEDEC_MA_EMR_ODS_WEAK (1 << 1) +#define JEDEC_MA_EMR_DLL_MASK (1 << 0) +#define JEDEC_MA_EMR_DLL_ENABLE (0 << 0) +#define JEDEC_MA_EMR_DLL_DISABLE (1 << 0) + +/* + * JEDEC DDR Extended Mode Register 2 + */ +#define JEDEC_MA_EMR2_TEMP_COMMERCIAL (0 << 7) +#define JEDEC_MA_EMR2_TEMP_INDUSTRIAL (1 << 7) + +/* + * SDRAM Mode Register (Corresponds 1:1 w/ JEDEC Mode Register) + */ +#define SDRAM_MMODE_WR_MASK JEDEC_MA_MR_WR_MASK +#define SDRAM_MMODE_WR_DDR1 JEDEC_MA_MR_WR_DDR1 +#define SDRAM_MMODE_WR_DDR2_2_CYC JEDEC_MA_MR_WR_DDR2_2_CYC +#define SDRAM_MMODE_WR_DDR2_3_CYC JEDEC_MA_MR_WR_DDR2_3_CYC +#define SDRAM_MMODE_WR_DDR2_4_CYC JEDEC_MA_MR_WR_DDR2_4_CYC +#define SDRAM_MMODE_WR_DDR2_5_CYC JEDEC_MA_MR_WR_DDR2_5_CYC +#define SDRAM_MMODE_WR_DDR2_6_CYC JEDEC_MA_MR_WR_DDR2_6_CYC +#define SDRAM_MMODE_DCL_MASK JEDEC_MA_MR_CL_MASK +#define SDRAM_MMODE_DCL_DDR1_2_0_CLK JEDEC_MA_MR_CL_DDR1_2_0_CLK +#define SDRAM_MMODE_DCL_DDR1_2_5_CLK JEDEC_MA_MR_CL_DDR1_2_5_CLK +#define SDRAM_MMODE_DCL_DDR1_3_0_CLK JEDEC_MA_MR_CL_DDR1_3_0_CLK +#define SDRAM_MMODE_DCL_DDR2_2_0_CLK JEDEC_MA_MR_CL_DDR2_2_0_CLK +#define SDRAM_MMODE_DCL_DDR2_3_0_CLK JEDEC_MA_MR_CL_DDR2_3_0_CLK +#define SDRAM_MMODE_DCL_DDR2_4_0_CLK JEDEC_MA_MR_CL_DDR2_4_0_CLK +#define SDRAM_MMODE_DCL_DDR2_5_0_CLK JEDEC_MA_MR_CL_DDR2_5_0_CLK +#define SDRAM_MMODE_DCL_DDR2_6_0_CLK JEDEC_MA_MR_CL_DDR2_6_0_CLK +#define SDRAM_MMODE_DCL_DDR2_7_0_CLK JEDEC_MA_MR_CL_DDR2_7_0_CLK +#define SDRAM_MMODE_BTYP_SEQUENTIAL JEDEC_MA_MR_BTYP_SEQUENTIAL +#define SDRAM_MMODE_BTYP_INTERLEAVED JEDEC_MA_MR_BTYP_INTERLEAVED +#define SDRAM_MMODE_BLEN_MASK JEDEC_MA_MR_BLEN_MASK +#define SDRAM_MMODE_BLEN_4 JEDEC_MA_MR_BLEN_4 +#define SDRAM_MMODE_BLEN_8 JEDEC_MA_MR_BLEN_8 + +/* + * SDRAM Extended Mode Register (Corresponds 1:1 w/ JEDEC Extended + * Mode Register) + */ +#define SDRAM_MEMODE_QOFF_MASK JEDEC_MA_EMR_OUTPUT_MASK +#define SDRAM_MEMODE_QOFF_DISABLE JEDEC_MA_EMR_OUTPUT_DISABLE +#define SDRAM_MEMODE_QOFF_ENABLE JEDEC_MA_EMR_OUTPUT_ENABLE +#define SDRAM_MEMODE_RDQS_MASK JEDEC_MA_EMR_RQDS_MASK +#define SDRAM_MEMODE_RDQS_DISABLE JEDEC_MA_EMR_RDQS_DISABLE +#define SDRAM_MEMODE_RDQS_ENABLE JEDEC_MA_EMR_RDQS_ENABLE +#define SDRAM_MEMODE_DQS_MASK JEDEC_MA_EMR_DQS_MASK +#define SDRAM_MEMODE_DQS_DISABLE JEDEC_MA_EMR_DQS_DISABLE +#define SDRAM_MEMODE_DQS_ENABLE JEDEC_MA_EMR_DQS_ENABLE +#define SDRAM_MEMODE_AL_DDR1_0_CYC JEDEC_MA_EMR_AL_DDR1_0_CYC +#define SDRAM_MEMODE_AL_DDR2_1_CYC JEDEC_MA_EMR_AL_DDR2_1_CYC +#define SDRAM_MEMODE_AL_DDR2_2_CYC JEDEC_MA_EMR_AL_DDR2_2_CYC +#define SDRAM_MEMODE_AL_DDR2_3_CYC JEDEC_MA_EMR_AL_DDR2_3_CYC +#define SDRAM_MEMODE_AL_DDR2_4_CYC JEDEC_MA_EMR_AL_DDR2_4_CYC +#define SDRAM_MEMODE_RTT_MASK JEDEC_MA_EMR_RTT_MASK +#define SDRAM_MEMODE_RTT_DISABLED JEDEC_MA_EMR_RTT_DISABLED +#define SDRAM_MEMODE_RTT_75OHM JEDEC_MA_EMR_RTT_75OHM +#define SDRAM_MEMODE_RTT_150OHM JEDEC_MA_EMR_RTT_150OHM +#define SDRAM_MEMODE_RTT_50OHM JEDEC_MA_EMR_RTT_50OHM +#define SDRAM_MEMODE_DIC_MASK JEDEC_MA_EMR_ODS_MASK +#define SDRAM_MEMODE_DIC_NORMAL JEDEC_MA_EMR_ODS_NORMAL +#define SDRAM_MEMODE_DIC_WEAK JEDEC_MA_EMR_ODS_WEAK +#define SDRAM_MEMODE_DLL_MASK JEDEC_MA_EMR_DLL_MASK +#define SDRAM_MEMODE_DLL_DISABLE JEDEC_MA_EMR_DLL_DISABLE +#define SDRAM_MEMODE_DLL_ENABLE JEDEC_MA_EMR_DLL_ENABLE /* * SDRAM Clock Timing Register @@ -684,6 +898,24 @@ #define SDRAM_SDTR3_RFC_ENCODE(n) ((((u32)(n))&0x3F)<<0) /* + * ECC Error Status + */ +#define SDRAM_ECCES_MASK PPC_REG_VAL(21, 0x3FFFFF) +#define SDRAM_ECCES_BNCE_MASK PPC_REG_VAL(15, 0xFFFF) +#define SDRAM_ECCES_BNCE_ENCODE(lane) PPC_REG_VAL(((lane) & 0xF), 1) +#define SDRAM_ECCES_CKBER_MASK PPC_REG_VAL(17, 0x3) +#define SDRAM_ECCES_CKBER_NONE PPC_REG_VAL(17, 0) +#define SDRAM_ECCES_CKBER_16_ECC_0_3 PPC_REG_VAL(17, 2) +#define SDRAM_ECCES_CKBER_32_ECC_0_3 PPC_REG_VAL(17, 1) +#define SDRAM_ECCES_CKBER_32_ECC_4_8 PPC_REG_VAL(17, 2) +#define SDRAM_ECCES_CKBER_32_ECC_0_8 PPC_REG_VAL(17, 3) +#define SDRAM_ECCES_CE PPC_REG_VAL(18, 1) +#define SDRAM_ECCES_UE PPC_REG_VAL(19, 1) +#define SDRAM_ECCES_BKNER_MASK PPC_REG_VAL(21, 0x3) +#define SDRAM_ECCES_BK0ER PPC_REG_VAL(20, 1) +#define SDRAM_ECCES_BK1ER PPC_REG_VAL(21, 1) + +/* * Memory Bank 0-1 configuration */ #define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */ diff --git a/include/asm-ppc/ppc4xx-uic.h b/include/asm-ppc/ppc4xx-uic.h new file mode 100644 index 0000000000..c908d42452 --- /dev/null +++ b/include/asm-ppc/ppc4xx-uic.h @@ -0,0 +1,316 @@ +/* + * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> + * + * (C) Copyright 2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PPC4xx_UIC_H_ +#define _PPC4xx_UIC_H_ + +/* + * Define the number of UIC's + */ +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) +#define UIC_MAX 4 +#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) +#define UIC_MAX 3 +#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) +#define UIC_MAX 2 +#else +#define UIC_MAX 1 +#endif + +#define IRQ_MAX UIC_MAX * 32 + +/* + * UIC register + */ +#define UIC_SR 0x0 /* UIC status */ +#define UIC_ER 0x2 /* UIC enable */ +#define UIC_CR 0x3 /* UIC critical */ +#define UIC_PR 0x4 /* UIC polarity */ +#define UIC_TR 0x5 /* UIC triggering */ +#define UIC_MSR 0x6 /* UIC masked status */ +#define UIC_VR 0x7 /* UIC vector */ +#define UIC_VCR 0x8 /* UIC vector configuration */ + +/* + * On 440GX we use the UICB0 as UIC0. Its the root UIC where all other UIC's + * are cascaded on. With this trick we can use the common UIC code for 440GX + * too. + */ +#if defined(CONFIG_440GX) +#define UIC0_DCR_BASE 0x200 +#define UIC1_DCR_BASE 0xc0 +#define UIC2_DCR_BASE 0xd0 +#define UIC3_DCR_BASE 0x210 +#else +#define UIC0_DCR_BASE 0xc0 +#define UIC1_DCR_BASE 0xd0 +#define UIC2_DCR_BASE 0xe0 +#define UIC3_DCR_BASE 0xf0 +#endif + +#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */ +#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */ +#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */ +#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ +#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ +#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ +#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */ +#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ + +#define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */ +#define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */ +#define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */ +#define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */ +#define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */ +#define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */ +#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */ +#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */ + +#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */ +#define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */ +#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */ +#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */ +#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */ +#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */ +#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */ +#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */ +#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */ + +#define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */ +#define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */ +#define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */ +#define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */ +#define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */ +#define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */ +#define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */ +#define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */ +#define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */ + +/* The following is for compatibility with 405 code */ +#define uicsr uic0sr +#define uicer uic0er +#define uiccr uic0cr +#define uicpr uic0pr +#define uictr uic0tr +#define uicmsr uic0msr +#define uicvr uic0vr +#define uicvcr uic0vcr + +/* + * Now the interrupt vector definitions. They are different for most of + * the 4xx variants, so we need some more #ifdef's here. No mask + * definitions anymore here. For this please use the UIC_MASK macro below. + * + * Note: Please only define the interrupts really used in U-Boot here. + * Those are the cascading and EMAC/MAL related interrupt. + */ + +#if defined(CONFIG_405EP) || defined(CONFIG_405GP) +#define VECNUM_MAL_SERR 10 +#define VECNUM_MAL_TXEOB 11 +#define VECNUM_MAL_RXEOB 12 +#define VECNUM_MAL_TXDE 13 +#define VECNUM_MAL_RXDE 14 +#define VECNUM_ETH0 15 +#define VECNUM_ETH1_OFFS 2 +#define VECNUM_EIRQ6 29 +#endif /* defined(CONFIG_405EP) */ + +#if defined(CONFIG_405EZ) +#define VECNUM_USBDEV 15 +#define VECNUM_ETH0 16 +#define VECNUM_MAL_SERR 18 +#define VECNUM_MAL_TXDE 18 +#define VECNUM_MAL_RXDE 18 +#define VECNUM_MAL_TXEOB 19 +#define VECNUM_MAL_RXEOB 21 +#endif /* CONFIG_405EX */ + +#if defined(CONFIG_405EX) +/* UIC 0 */ +#define VECNUM_MAL_TXEOB 10 +#define VECNUM_MAL_RXEOB 11 +#define VECNUM_ETH0 24 +#define VECNUM_ETH1_OFFS 1 +#define VECNUM_UIC2NCI 28 +#define VECNUM_UIC2CI 29 +#define VECNUM_UIC1NCI 30 +#define VECNUM_UIC1CI 31 + +/* UIC 1 */ +#define VECNUM_MAL_SERR (32 + 0) +#define VECNUM_MAL_TXDE (32 + 1) +#define VECNUM_MAL_RXDE (32 + 2) +#endif /* CONFIG_405EX */ + +#if defined(CONFIG_440GP) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) +/* UIC 0 */ +#define VECNUM_MAL_TXEOB 10 +#define VECNUM_MAL_RXEOB 11 +#define VECNUM_UIC1NCI 30 +#define VECNUM_UIC1CI 31 + +/* UIC 1 */ +#define VECNUM_MAL_SERR (32 + 0) +#define VECNUM_MAL_TXDE (32 + 1) +#define VECNUM_MAL_RXDE (32 + 2) +#define VECNUM_USBDEV (32 + 23) +#define VECNUM_ETH0 (32 + 28) +#define VECNUM_ETH1_OFFS 2 +#endif /* CONFIG_440GP */ + +#if defined(CONFIG_440GX) +/* UICB 0 (440GX only) */ +/* + * All those defines below are off-by-one, so that the common UIC code + * can be used. So VECNUM_UIC1CI refers to VECNUM_UIC0CI etc. + */ +#define VECNUM_UIC1CI 0 +#define VECNUM_UIC1NCI 1 +#define VECNUM_UIC2CI 2 +#define VECNUM_UIC2NCI 3 +#define VECNUM_UIC3CI 4 +#define VECNUM_UIC3NCI 5 + +/* UIC 0, used as UIC1 on 440GX because of UICB0 */ +#define VECNUM_MAL_TXEOB (32 + 10) +#define VECNUM_MAL_RXEOB (32 + 11) + +/* UIC 1, used as UIC2 on 440GX because of UICB0 */ +#define VECNUM_MAL_SERR (64 + 0) +#define VECNUM_MAL_TXDE (64 + 1) +#define VECNUM_MAL_RXDE (64 + 2) +#define VECNUM_ETH0 (64 + 28) +#define VECNUM_ETH1_OFFS 2 +#endif /* CONFIG_440GX */ + +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +/* UIC 0 */ +#define VECNUM_MAL_TXEOB 10 +#define VECNUM_MAL_RXEOB 11 +#define VECNUM_USBDEV 20 +#define VECNUM_ETH0 24 +#define VECNUM_ETH1_OFFS 1 +#define VECNUM_UIC2NCI 28 +#define VECNUM_UIC2CI 29 +#define VECNUM_UIC1NCI 30 +#define VECNUM_UIC1CI 31 + +/* UIC 1 */ +#define VECNUM_MAL_SERR (32 + 0) +#define VECNUM_MAL_TXDE (32 + 1) +#define VECNUM_MAL_RXDE (32 + 2) + +/* UIC 2 */ +#define VECNUM_EIRQ2 (64 + 3) +#endif /* CONFIG_440EPX */ + +#if defined(CONFIG_440SP) +/* UIC 0 */ +#define VECNUM_UIC1NCI 30 +#define VECNUM_UIC1CI 31 + +/* UIC 1 */ +#define VECNUM_MAL_SERR (32 + 1) +#define VECNUM_MAL_TXDE (32 + 2) +#define VECNUM_MAL_RXDE (32 + 3) +#define VECNUM_MAL_TXEOB (32 + 6) +#define VECNUM_MAL_RXEOB (32 + 7) +#define VECNUM_ETH0 (32 + 28) +#endif /* CONFIG_440SP */ + +#if defined(CONFIG_440SPE) +/* UIC 0 */ +#define VECNUM_UIC2NCI 10 +#define VECNUM_UIC2CI 11 +#define VECNUM_UIC3NCI 16 +#define VECNUM_UIC3CI 17 +#define VECNUM_UIC1NCI 30 +#define VECNUM_UIC1CI 31 + +/* UIC 1 */ +#define VECNUM_MAL_SERR (32 + 1) +#define VECNUM_MAL_TXDE (32 + 2) +#define VECNUM_MAL_RXDE (32 + 3) +#define VECNUM_MAL_TXEOB (32 + 6) +#define VECNUM_MAL_RXEOB (32 + 7) +#define VECNUM_ETH0 (32 + 28) +#endif /* CONFIG_440SPE */ + +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +/* UIC 0 */ +#define VECNUM_UIC2NCI 10 +#define VECNUM_UIC2CI 11 +#define VECNUM_UIC3NCI 16 +#define VECNUM_UIC3CI 17 +#define VECNUM_UIC1NCI 30 +#define VECNUM_UIC1CI 31 + +/* UIC 2 */ +#define VECNUM_MAL_SERR (64 + 3) +#define VECNUM_MAL_TXDE (64 + 4) +#define VECNUM_MAL_RXDE (64 + 5) +#define VECNUM_MAL_TXEOB (64 + 6) +#define VECNUM_MAL_RXEOB (64 + 7) +#define VECNUM_ETH0 (64 + 16) +#define VECNUM_ETH1_OFFS 1 +#endif /* CONFIG_460EX */ + +#if defined(CONFIG_460SX) +/* UIC 0 */ +#define VECNUM_UIC2NCI 10 +#define VECNUM_UIC2CI 11 +#define VECNUM_UIC3NCI 16 +#define VECNUM_UIC3CI 17 +#define VECNUM_ETH0 19 +#define VECNUM_ETH1_OFFS 1 +#define VECNUM_UIC1NCI 30 +#define VECNUM_UIC1CI 31 + +/* UIC 1 */ +#define VECNUM_MAL_SERR (32 + 1) +#define VECNUM_MAL_TXDE (32 + 2) +#define VECNUM_MAL_RXDE (32 + 3) +#define VECNUM_MAL_TXEOB (32 + 6) +#define VECNUM_MAL_RXEOB (32 + 7) +#endif /* CONFIG_460EX */ + +#if !defined(VECNUM_ETH1_OFFS) +#define VECNUM_ETH1_OFFS 1 +#endif + +/* + * Mask definitions (used for example in 4xx_enet.c) + */ +#define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f)) +/* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */ +#define UIC_NR(vec) ((vec) >> 5) + +#endif /* _PPC4xx_UIC_H_ */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index e617868091..dce4717f42 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -830,6 +830,10 @@ #define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */ #define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */ #define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */ +#define PVR_460SX_RA 0x13541800 /* 460SX rev A */ +#define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */ +#define PVR_460GX_RA 0x13541802 /* 460GX rev A */ +#define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */ #define PVR_601 0x00010000 #define PVR_602 0x00050000 #define PVR_603 0x00030000 @@ -855,6 +859,8 @@ #define PVR_86xx 0x80040000 #define PVR_86xx_REV1 (PVR_86xx | 0x0010) +#define PVR_VIRTEX5 0x7ff21912 + /* * For the 8xx processors, all of them report the same PVR family for * the PowerPC core. The various versions of these processors must be diff --git a/include/asm-ppc/xilinx_irq.h b/include/asm-ppc/xilinx_irq.h new file mode 100644 index 0000000000..61171c21ff --- /dev/null +++ b/include/asm-ppc/xilinx_irq.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ +#ifndef XILINX_IRQ_H +#define XILINX_IRQ_H + +#define intc XPAR_INTC_0_BASEADDR +#define ISR (intc + (0 * 4)) /* Interrupt Status Register */ +#define IPR (intc + (1 * 4)) /* Interrupt Pending Register */ +#define IER (intc + (2 * 4)) /* Interrupt Enable Register */ +#define IAR (intc + (3 * 4)) /* Interrupt Acknowledge Register */ +#define SIE (intc + (4 * 4)) /* Set Interrupt Enable bits */ +#define CIE (intc + (5 * 4)) /* Clear Interrupt Enable bits */ +#define IVR (intc + (6 * 4)) /* Interrupt Vector Register */ +#define MER (intc + (7 * 4)) /* Master Enable Register */ + +#define IRQ_MASK(irq) (1 << (irq & 0x1f)) + +#define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS + +#endif diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 8ea1ac37d1..9bcbfe3b7d 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -407,7 +407,7 @@ /* * define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high */ -#define CFG_UIC0_POLARITY (0xFFFFFF80 | UIC_EXT6) +#define CFG_UIC0_POLARITY (0xFFFFFF80 | UIC_MASK(VECNUM_EIRQ6)) /*----------------------------------------------------------------------- * FPGA stuff diff --git a/include/configs/katmai.h b/include/configs/katmai.h index f07e470683..047ec9ede3 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -54,7 +54,6 @@ #include "amcc-common.h" #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ #undef CONFIG_SHOW_BOOT_PROGRESS /*----------------------------------------------------------------------- diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 9c1a3a4c1e..dc246fd23e 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -233,39 +233,124 @@ #define CFG_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE #define CFG_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE #define CFG_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE -#define CFG_SDRAM0_MCOPT1 0x04322000 +#define CFG_SDRAM0_MCOPT1 (SDRAM_MCOPT1_PMU_OPEN | \ + SDRAM_MCOPT1_8_BANKS | \ + SDRAM_MCOPT1_DDR2_TYPE | \ + SDRAM_MCOPT1_QDEP | \ + SDRAM_MCOPT1_DCOO_DISABLED) #define CFG_SDRAM0_MCOPT2 0x00000000 -#define CFG_SDRAM0_MODT0 0x01800000 +#define CFG_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \ + SDRAM_MODT_EB0R_ENABLE) #define CFG_SDRAM0_MODT1 0x00000000 -#define CFG_SDRAM0_CODT 0x0080f837 -#define CFG_SDRAM0_RTR 0x06180000 -#define CFG_SDRAM0_INITPLR0 0xa8380000 -#define CFG_SDRAM0_INITPLR1 0x81900400 -#define CFG_SDRAM0_INITPLR2 0x81020000 -#define CFG_SDRAM0_INITPLR3 0x81030000 -#define CFG_SDRAM0_INITPLR4 0x81010404 -#define CFG_SDRAM0_INITPLR5 0x81000542 -#define CFG_SDRAM0_INITPLR6 0x81900400 -#define CFG_SDRAM0_INITPLR7 0x8D080000 -#define CFG_SDRAM0_INITPLR8 0x8D080000 -#define CFG_SDRAM0_INITPLR9 0x8D080000 -#define CFG_SDRAM0_INITPLR10 0x8D080000 -#define CFG_SDRAM0_INITPLR11 0x81000442 -#define CFG_SDRAM0_INITPLR12 0x81010780 -#define CFG_SDRAM0_INITPLR13 0x81010400 -#define CFG_SDRAM0_INITPLR14 0x00000000 -#define CFG_SDRAM0_INITPLR15 0x00000000 -#define CFG_SDRAM0_RQDC 0x80000038 -#define CFG_SDRAM0_RFDC 0x00000209 -#define CFG_SDRAM0_RDCC 0x40000000 -#define CFG_SDRAM0_DLCR 0x030000a5 -#define CFG_SDRAM0_CLKTR 0x80000000 +#define CFG_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \ + SDRAM_CODT_CKLZ_36OHM | \ + SDRAM_CODT_DQS_1_8_V_DDR2 | \ + SDRAM_CODT_IO_NMODE) +#define CFG_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560) +#define CFG_SDRAM0_INITPLR0 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(80) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP)) +#define CFG_SDRAM0_INITPLR1 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(3) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL)) +#define CFG_SDRAM0_INITPLR2 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL)) +#define CFG_SDRAM0_INITPLR3 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \ + SDRAM_INITPLR_IMA_ENCODE(0)) +#define CFG_SDRAM0_INITPLR4 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \ + JEDEC_MA_EMR_RTT_75OHM)) +#define CFG_SDRAM0_INITPLR5 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \ + JEDEC_MA_MR_CL_DDR2_4_0_CLK | \ + JEDEC_MA_MR_BLEN_4 | \ + JEDEC_MA_MR_DLL_RESET)) +#define CFG_SDRAM0_INITPLR6 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(3) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \ + SDRAM_INITPLR_IBA_ENCODE(0x0) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL)) +#define CFG_SDRAM0_INITPLR7 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CFG_SDRAM0_INITPLR8 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CFG_SDRAM0_INITPLR9 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CFG_SDRAM0_INITPLR10 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(26) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) +#define CFG_SDRAM0_INITPLR11 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \ + JEDEC_MA_MR_CL_DDR2_4_0_CLK | \ + JEDEC_MA_MR_BLEN_4)) +#define CFG_SDRAM0_INITPLR12 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \ + JEDEC_MA_EMR_RDQS_DISABLE | \ + JEDEC_MA_EMR_DQS_DISABLE | \ + JEDEC_MA_EMR_RTT_DISABLED | \ + JEDEC_MA_EMR_ODS_NORMAL)) +#define CFG_SDRAM0_INITPLR13 (SDRAM_INITPLR_ENABLE | \ + SDRAM_INITPLR_IMWT_ENCODE(2) | \ + SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ + SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ + SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \ + JEDEC_MA_EMR_RDQS_DISABLE | \ + JEDEC_MA_EMR_DQS_DISABLE | \ + JEDEC_MA_EMR_RTT_DISABLED | \ + JEDEC_MA_EMR_ODS_NORMAL)) +#define CFG_SDRAM0_INITPLR14 (SDRAM_INITPLR_DISABLE) +#define CFG_SDRAM0_INITPLR15 (SDRAM_INITPLR_DISABLE) +#define CFG_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \ + SDRAM_RQDC_RQFD_ENCODE(56)) +#define CFG_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(521) +#define CFG_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2) +#define CFG_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \ + SDRAM_DLCR_DLCS_CONT_DONE | \ + SDRAM_DLCR_DLCV_ENCODE(165)) +#define CFG_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV) #define CFG_SDRAM0_WRDTR 0x00000000 -#define CFG_SDRAM0_SDTR1 0x80201000 -#define CFG_SDRAM0_SDTR2 0x32204232 -#define CFG_SDRAM0_SDTR3 0x080b0d1a -#define CFG_SDRAM0_MMODE 0x00000442 -#define CFG_SDRAM0_MEMODE 0x00000404 +#define CFG_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \ + SDRAM_SDTR1_RTW_2_CLK | \ + SDRAM_SDTR1_RTRO_1_CLK) +#define CFG_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \ + SDRAM_SDTR2_WTR_2_CLK | \ + SDRAM_SDTR2_XSNR_32_CLK | \ + SDRAM_SDTR2_WPC_4_CLK | \ + SDRAM_SDTR2_RPC_2_CLK | \ + SDRAM_SDTR2_RP_3_CLK | \ + SDRAM_SDTR2_RRD_2_CLK) +#define CFG_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8) | \ + SDRAM_SDTR3_RC_ENCODE(11) | \ + SDRAM_SDTR3_XCS | \ + SDRAM_SDTR3_RFC_ENCODE(26)) +#define CFG_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \ + SDRAM_MMODE_DCL_DDR2_4_0_CLK | \ + SDRAM_MMODE_BLEN_4) +#define CFG_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_DISABLE | \ + SDRAM_MEMODE_RTT_75OHM) /*----------------------------------------------------------------------- * I2C @@ -290,6 +375,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_M88E1111_PHY 1 #define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ diff --git a/include/configs/makalu.h b/include/configs/makalu.h index 65b240e0f1..ab92ae488d 100644 --- a/include/configs/makalu.h +++ b/include/configs/makalu.h @@ -223,6 +223,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_M88E1111_PHY 1 #define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII #define CONFIG_PHY_ADDR 6 /* PHY address, See schematics */ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ diff --git a/include/configs/ml507.h b/include/configs/ml507.h new file mode 100644 index 0000000000..c653a5105c --- /dev/null +++ b/include/configs/ml507.h @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef __CONFIG_H +#define __CONFIG_H +/* +#define DEBUG +#define ET_DEBUG +*/ + /*CPU*/ +#define CONFIG_XILINX_ML507 1 +#define CONFIG_XILINX_440 1 +#define CONFIG_440 1 +#define CONFIG_4xx 1 +#include "../board/xilinx/ml507/xparameters.h" + +/*Mem Map*/ +#define CFG_SDRAM_BASE 0x0 +#define CFG_SDRAM_SIZE_MB 256 +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN ( 192 * 1024 ) +#define CFG_MALLOC_LEN ( CFG_ENV_SIZE + 128 * 1024 ) + +/*Uart*/ +#define CONFIG_XILINX_UARTLITE +#define CONFIG_BAUDRATE XPAR_UARTLITE_0_BAUDRATE +#define CFG_BAUDRATE_TABLE { XPAR_UARTLITE_0_BAUDRATE } +#define CONFIG_SERIAL_BASE XPAR_UARTLITE_0_BASEADDR + +/*Cmd*/ +#include <config_cmd_default.h> +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_ELF +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_JFFS2 +#define CONFIG_JFFS2_CMDLINE +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_DTT +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_PING +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_IMLS + +/*Env*/ +#define CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SIZE 0x20000 +#define CFG_ENV_SECT_SIZE 0x20000 +#define CFG_ENV_OFFSET 0x340000 +#define CFG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CFG_ENV_OFFSET) + +/*Misc*/ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "board:/# " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE ( CFG_CBSIZE + sizeof( CFG_PROMPT ) + 16 ) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ +#define CFG_LOAD_ADDR 0x00400000 /* default load address */ +#define CFG_EXTBDINFO 1 /* Extended board_into (bd_t) */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_CMDLINE_EDITING /* add command line history */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_LOOPW /* enable loopw command */ +#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE /* include version env variable */ +#define CFG_CONSOLE_INFO_QUIET /* don't print console @ startup */ +#define CFG_HUSH_PARSER /* Use the HUSH parser */ +#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ +#define CFG_BOOTMAPSZ ( 8 << 20 ) /* Initial Memory map for Linux */ +#define CONFIG_PREBOOT "echo U-Boot is up and runnining;" + +/*Stack*/ +#define CFG_INIT_RAM_ADDR 0x800000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET ( CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE ) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +/*Speed*/ +#define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ + +/*Flash*/ +#define CFG_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR +#define CFG_FLASH_SIZE (32*1024*1024) +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#define CFG_FLASH_EMPTY_INFO 1 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 259 +#define CFG_FLASH_PROTECTION +#define MTDIDS_DEFAULT "nor0=ml507-flash" +#define MTDPARTS_DEFAULT "mtdparts=ml507-flash:-(user)" + + +#endif /* __CONFIG_H */ diff --git a/include/configs/redwood.h b/include/configs/redwood.h new file mode 100644 index 0000000000..32ed5746c5 --- /dev/null +++ b/include/configs/redwood.h @@ -0,0 +1,186 @@ +/* + * Configuration for AMCC 460SX Ref (redwood) + * + * (C) Copyright 2008 + * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_440 1 /* ... PPC460 family */ +#define CONFIG_460SX 1 /* ... PPC460 family */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +/*----------------------------------------------------------------------- + * Include common defines/options for all AMCC boards + *----------------------------------------------------------------------*/ +#define CONFIG_HOSTNAME redwood + +#include "amcc-common.h" + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */ +#define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ +#define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */ + +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ + +#define CFG_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */ +#define CFG_PCIE0_MEMBASE 0x90000000 /* mapped PCIe memory */ +#define CFG_PCIE1_MEMBASE 0xa0000000 /* mapped PCIe memory */ +#define CFG_PCIE_MEMSIZE 0x01000000 + +#define CFG_PCIE0_XCFGBASE 0xb0000000 +#define CFG_PCIE1_XCFGBASE 0xb2000000 +#define CFG_PCIE2_XCFGBASE 0xb4000000 +#define CFG_PCIE0_CFGBASE 0xb6000000 +#define CFG_PCIE1_CFGBASE 0xb8000000 +#define CFG_PCIE2_CFGBASE 0xba000000 + +/* PCIe mapped UTL registers */ +#define CFG_PCIE0_REGBASE 0xd0000000 +#define CFG_PCIE1_REGBASE 0xd0010000 +#define CFG_PCIE2_REGBASE 0xd0020000 + +/* System RAM mapped to PCI space */ +#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) + +#define CFG_FPGA_BASE 0xe2000000 /* epld */ +#define CFG_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */ + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in internal SRAM) + *----------------------------------------------------------------------*/ +#define CFG_TEMP_STACK_OCM 1 +#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE +#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ + +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ +#define CONFIG_DDR_ECC 1 /* with ECC support */ + +#define CFG_SPD_MAX_DIMMS 2 + +/* SPD i2c spd addresses */ +#define SPD_EEPROM_ADDRESS {IIC0_DIMM0_ADDR, IIC0_DIMM1_ADDR} +#define IIC0_DIMM0_ADDR 0x53 +#define IIC0_DIMM1_ADDR 0x52 + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CFG_I2C_SPEED 400000 /* I2C speed */ + +#define IIC0_BOOTPROM_ADDR 0x50 +#define IIC0_ALT_BOOTPROM_ADDR 0x54 + +/* Don't probe these addrs */ +#define CFG_I2C_NOPROBES {0x50, 0x52, 0x53, 0x54} + +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#undef CFG_ENV_IS_IN_NVRAM /* ... not in NVRAM */ +#define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ +#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + CONFIG_AMCC_DEF_ENV_NAND_UPD \ + "kernel_addr=fc000000\0" \ + "fdt_addr=fc1e0000\0" \ + "ramdisk_addr=fc200000\0" \ + "" + +/*----------------------------------------------------------------------------+ +| Commands in addition to amcc-common.h ++----------------------------------------------------------------------------*/ +#define CONFIG_CMD_SDRAM + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_RESET_DELAY 1000 +#define CONFIG_M88E1141_PHY 1 /* Enable phy */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ +#define CONFIG_PHY1_ADDR 1 /* PHY address, See schematics */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */ + +#define CFG_MAX_FLASH_BANKS 3 /* number of banks */ +#define CFG_MAX_FLASH_SECT 256 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR 0xfffa0000 +#define CFG_ENV_SIZE 0x10000 /* Size of Environment vars */ +#endif /* CFG_ENV_IS_IN_FLASH */ + +/*---------------------------------------------------------------------------*/ + +#endif /* __CONFIG_H */ diff --git a/include/ppc405.h b/include/ppc405.h index 2231a5fbb4..f19b67f1bb 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -119,367 +119,6 @@ #define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ #define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */ -/****************************************************************************** - * Universal interrupt controller - ******************************************************************************/ -#define UIC_SR 0x0 /* UIC status */ -#define UIC_ER 0x2 /* UIC enable */ -#define UIC_CR 0x3 /* UIC critical */ -#define UIC_PR 0x4 /* UIC polarity */ -#define UIC_TR 0x5 /* UIC triggering */ -#define UIC_MSR 0x6 /* UIC masked status */ -#define UIC_VR 0x7 /* UIC vector */ -#define UIC_VCR 0x8 /* UIC vector configuration */ - -#define UIC_DCR_BASE 0xc0 -#define UIC0_DCR_BASE UIC_DCR_BASE -#define uicsr (UIC_DCR_BASE+0x0) /* UIC status */ -#define uicsrs (UIC_DCR_BASE+0x1) /* UIC status set */ -#define uicer (UIC_DCR_BASE+0x2) /* UIC enable */ -#define uiccr (UIC_DCR_BASE+0x3) /* UIC critical */ -#define uicpr (UIC_DCR_BASE+0x4) /* UIC polarity */ -#define uictr (UIC_DCR_BASE+0x5) /* UIC triggering */ -#define uicmsr (UIC_DCR_BASE+0x6) /* UIC masked status */ -#define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */ -#define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */ - -#if defined(CONFIG_405EX) -#define uic0sr uicsr /* UIC status */ -#define uic0srs uicsrs /* UIC status set */ -#define uic0er uicer /* UIC enable */ -#define uic0cr uiccr /* UIC critical */ -#define uic0pr uicpr /* UIC polarity */ -#define uic0tr uictr /* UIC triggering */ -#define uic0msr uicmsr /* UIC masked status */ -#define uic0vr uicvr /* UIC vector */ -#define uic0vcr uicvcr /* UIC vector configuration*/ - -#define UIC_DCR_BASE1 0xd0 -#define UIC1_DCR_BASE 0xd0 -#define uic1sr (UIC_DCR_BASE1+0x0) /* UIC status */ -#define uic1srs (UIC_DCR_BASE1+0x1) /* UIC status set */ -#define uic1er (UIC_DCR_BASE1+0x2) /* UIC enable */ -#define uic1cr (UIC_DCR_BASE1+0x3) /* UIC critical */ -#define uic1pr (UIC_DCR_BASE1+0x4) /* UIC polarity */ -#define uic1tr (UIC_DCR_BASE1+0x5) /* UIC triggering */ -#define uic1msr (UIC_DCR_BASE1+0x6) /* UIC masked status */ -#define uic1vr (UIC_DCR_BASE1+0x7) /* UIC vector */ -#define uic1vcr (UIC_DCR_BASE1+0x8) /* UIC vector configuration*/ - -#define UIC_DCR_BASE2 0xe0 -#define UIC2_DCR_BASE 0xe0 -#define uic2sr (UIC_DCR_BASE2+0x0) /* UIC status */ -#define uic2srs (UIC_DCR_BASE2+0x1) /* UIC status set */ -#define uic2er (UIC_DCR_BASE2+0x2) /* UIC enable */ -#define uic2cr (UIC_DCR_BASE2+0x3) /* UIC critical */ -#define uic2pr (UIC_DCR_BASE2+0x4) /* UIC polarity */ -#define uic2tr (UIC_DCR_BASE2+0x5) /* UIC triggering */ -#define uic2msr (UIC_DCR_BASE2+0x6) /* UIC masked status */ -#define uic2vr (UIC_DCR_BASE2+0x7) /* UIC vector */ -#define uic2vcr (UIC_DCR_BASE2+0x8) /* UIC vector configuration*/ -#endif - -/*-----------------------------------------------------------------------------+ -| Universal interrupt controller interrupts -+-----------------------------------------------------------------------------*/ -#if defined(CONFIG_405EZ) -#define UIC_DMA0 0x80000000 /* DMA chan. 0 */ -#define UIC_DMA1 0x40000000 /* DMA chan. 1 */ -#define UIC_DMA2 0x20000000 /* DMA chan. 2 */ -#define UIC_DMA3 0x10000000 /* DMA chan. 3 */ -#define UIC_1588 0x08000000 /* IEEE 1588 network synchronization */ -#define UIC_UART0 0x04000000 /* UART 0 */ -#define UIC_UART1 0x02000000 /* UART 1 */ -#define UIC_CAN0 0x01000000 /* CAN 0 */ -#define UIC_CAN1 0x00800000 /* CAN 1 */ -#define UIC_SPI 0x00400000 /* SPI */ -#define UIC_IIC 0x00200000 /* IIC */ -#define UIC_CHT0 0x00100000 /* Chameleon timer high pri interrupt */ -#define UIC_CHT1 0x00080000 /* Chameleon timer high pri interrupt */ -#define UIC_USBH1 0x00040000 /* USB Host 1 */ -#define UIC_USBH2 0x00020000 /* USB Host 2 */ -#define UIC_USBDEV 0x00010000 /* USB Device */ -#define UIC_ENET 0x00008000 /* Ethernet interrupt status */ -#define UIC_ENET1 0x00008000 /* dummy define */ -#define UIC_EMAC_WAKE 0x00004000 /* EMAC wake up */ - -#define UIC_MADMAL 0x00002000 /* Logical OR of following MadMAL int */ -#define UIC_MAL_SERR 0x00002000 /* MAL SERR */ -#define UIC_MAL_TXDE 0x00002000 /* MAL TXDE */ -#define UIC_MAL_RXDE 0x00002000 /* MAL RXDE */ - -#define UIC_MAL_TXEOB 0x00001000 /* MAL TXEOB */ -#define UIC_MAL_TXEOB1 0x00000800 /* MAL TXEOB1 */ -#define UIC_MAL_RXEOB 0x00000400 /* MAL RXEOB */ -#define UIC_NAND 0x00000200 /* NAND Flash controller */ -#define UIC_ADC 0x00000100 /* ADC */ -#define UIC_DAC 0x00000080 /* DAC */ -#define UIC_OPB2PLB 0x00000040 /* OPB to PLB bridge interrupt */ -#define UIC_RESERVED0 0x00000020 /* Reserved */ -#define UIC_EXT0 0x00000010 /* External interrupt 0 */ -#define UIC_EXT1 0x00000008 /* External interrupt 1 */ -#define UIC_EXT2 0x00000004 /* External interrupt 2 */ -#define UIC_EXT3 0x00000002 /* External interrupt 3 */ -#define UIC_EXT4 0x00000001 /* External interrupt 4 */ - -#elif defined(CONFIG_405EX) - -/* UIC 0 */ -#define UIC_U0 0x80000000 /* */ -#define UIC_U1 0x40000000 /* */ -#define UIC_IIC0 0x20000000 /* */ -#define UIC_PKA 0x10000000 /* */ -#define UIC_TRNG 0x08000000 /* */ -#define UIC_EBM 0x04000000 /* */ -#define UIC_BGI 0x02000000 /* */ -#define UIC_IIC1 0x01000000 /* */ -#define UIC_SPI 0x00800000 /* */ -#define UIC_EIRQ0 0x00400000 /**/ -#define UIC_MTE 0x00200000 /*MAL Tx EOB */ -#define UIC_MRE 0x00100000 /*MAL Rx EOB */ -#define UIC_DMA0 0x00080000 /* */ -#define UIC_DMA1 0x00040000 /* */ -#define UIC_DMA2 0x00020000 /* */ -#define UIC_DMA3 0x00010000 /* */ -#define UIC_PCIE0AL 0x00008000 /* */ -#define UIC_PCIE0VPD 0x00004000 /* */ -#define UIC_RPCIE0HRST 0x00002000 /* */ -#define UIC_FPCIE0HRST 0x00001000 /* */ -#define UIC_PCIE0TCR 0x00000800 /* */ -#define UIC_PCIEMSI0 0x00000400 /* */ -#define UIC_PCIEMSI1 0x00000200 /* */ -#define UIC_SECURITY 0x00000100 /* */ -#define UIC_ENET 0x00000080 /* */ -#define UIC_ENET1 0x00000040 /* */ -#define UIC_PCIEMSI2 0x00000020 /* */ -#define UIC_EIRQ4 0x00000010 /**/ -#define UICB0_UIC2NCI 0x00000008 /* */ -#define UICB0_UIC2CI 0x00000004 /* */ -#define UICB0_UIC1NCI 0x00000002 /* */ -#define UICB0_UIC1CI 0x00000001 /* */ - -#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | \ - UICB0_UIC1CI | UICB0_UIC2NCI) - -#define UIC_MAL_TXEOB UIC_MTE/* MAL TXEOB */ -#define UIC_MAL_RXEOB UIC_MRE/* MAL RXEOB */ -/* UIC 1 */ -#define UIC_MS 0x80000000 /* MAL SERR */ -#define UIC_MTDE 0x40000000 /* MAL TXDE */ -#define UIC_MRDE 0x20000000 /* MAL RXDE */ -#define UIC_PCIE0BMVC0 0x10000000 /* */ -#define UIC_PCIE0DCRERR 0x08000000 /* */ -#define UIC_EBC 0x04000000 /* */ -#define UIC_NDFC 0x02000000 /* */ -#define UIC_PCEI1DCRERR 0x01000000 /* */ -#define UIC_GPTCMPT8 0x00800000 /* */ -#define UIC_GPTCMPT9 0x00400000 /* */ -#define UIC_PCIE1AL 0x00200000 /* */ -#define UIC_PCIE1VPD 0x00100000 /* */ -#define UIC_RPCE1HRST 0x00080000 /* */ -#define UIC_FPCE1HRST 0x00040000 /* */ -#define UIC_PCIE1TCR 0x00020000 /* */ -#define UIC_PCIE1VC0 0x00010000 /* */ -#define UIC_GPTCMPT3 0x00008000 /* */ -#define UIC_GPTCMPT4 0x00004000 /* */ -#define UIC_EIRQ7 0x00002000 /* */ -#define UIC_EIRQ8 0x00001000 /* */ -#define UIC_EIRQ9 0x00000800 /* */ -#define UIC_GPTCMP5 0x00000400 /* */ -#define UIC_GPTCMP6 0x00000200 /* */ -#define UIC_GPTCMP7 0x00000100 /* */ -#define UIC_SROM 0x00000080 /* SERIAL ROM*/ -#define UIC_GPTDECPULS 0x00000040 /* GPT Decrement pulse*/ -#define UIC_EIRQ2 0x00000020 /* */ -#define UIC_EIRQ5 0x00000010 /* */ -#define UIC_EIRQ6 0x00000008 /* */ -#define UIC_EMAC0WAKE 0x00000004 /* */ -#define UIC_EIRQ1 0x00000002 /* */ -#define UIC_EMAC1WAKE 0x00000001 /* */ -#define UIC_MAL_SERR UIC_MS /* MAL SERR */ -#define UIC_MAL_TXDE UIC_MTDE /* MAL TXDE */ -#define UIC_MAL_RXDE UIC_MRDE /* MAL RXDE */ -/* UIC 2 */ -#define UIC_PCIE0INTA 0x80000000 /* PCIE0 INTA*/ -#define UIC_PCIE0INTB 0x40000000 /* PCIE0 INTB*/ -#define UIC_PCIE0INTC 0x20000000 /* PCIE0 INTC*/ -#define UIC_PCIE0INTD 0x10000000 /* PCIE0 INTD*/ -#define UIC_EIRQ3 0x08000000 /* External IRQ 3*/ -#define UIC_DDRMCUE 0x04000000 /* */ -#define UIC_DDRMCCE 0x02000000 /* */ -#define UIC_MALINTCOATX0 0x01000000 /* Interrupt coalecence TX0*/ -#define UIC_MALINTCOATX1 0x00800000 /* Interrupt coalecence TX1*/ -#define UIC_MALINTCOARX0 0x00400000 /* Interrupt coalecence RX0*/ -#define UIC_MALINTCOARX1 0x00200000 /* Interrupt coalecence RX1*/ -#define UIC_PCIE1INTA 0x00100000 /* PCIE0 INTA*/ -#define UIC_PCIE1INTB 0x00080000 /* PCIE0 INTB*/ -#define UIC_PCIE1INTC 0x00040000 /* PCIE0 INTC*/ -#define UIC_PCIE1INTD 0x00020000 /* PCIE0 INTD*/ -#define UIC_RPCIEMSI2 0x00010000 /* MSI level 2 Note this looks same as uic0-26*/ -#define UIC_PCIEMSI3 0x00008000 /* MSI level 2*/ -#define UIC_PCIEMSI4 0x00004000 /* MSI level 2*/ -#define UIC_PCIEMSI5 0x00002000 /* MSI level 2*/ -#define UIC_PCIEMSI6 0x00001000 /* MSI level 2*/ -#define UIC_PCIEMSI7 0x00000800 /* MSI level 2*/ -#define UIC_PCIEMSI8 0x00000400 /* MSI level 2*/ -#define UIC_PCIEMSI9 0x00000200 /* MSI level 2*/ -#define UIC_PCIEMSI10 0x00000100 /* MSI level 2*/ -#define UIC_PCIEMSI11 0x00000080 /* MSI level 2*/ -#define UIC_PCIEMSI12 0x00000040 /* MSI level 2*/ -#define UIC_PCIEMSI13 0x00000020 /* MSI level 2*/ -#define UIC_PCIEMSI14 0x00000010 /* MSI level 2*/ -#define UIC_PCIEMSI15 0x00000008 /* MSI level 2*/ -#define UIC_PLB4XAHB 0x00000004 /* PLBxAHB bridge*/ -#define UIC_USBWAKE 0x00000002 /* USB wakup*/ -#define UIC_USBOTG 0x00000001 /* USB OTG*/ -#define UIC_ETH0 UIC_ENET -#define UIC_ETH1 UIC_ENET1 - -#else /* !defined(CONFIG_405EZ) */ - -#define UIC_UART0 0x80000000 /* UART 0 */ -#define UIC_UART1 0x40000000 /* UART 1 */ -#define UIC_IIC 0x20000000 /* IIC */ -#define UIC_EXT_MAST 0x10000000 /* External Master */ -#define UIC_PCI 0x08000000 /* PCI write to command reg */ -#define UIC_DMA0 0x04000000 /* DMA chan. 0 */ -#define UIC_DMA1 0x02000000 /* DMA chan. 1 */ -#define UIC_DMA2 0x01000000 /* DMA chan. 2 */ -#define UIC_DMA3 0x00800000 /* DMA chan. 3 */ -#define UIC_EMAC_WAKE 0x00400000 /* EMAC wake up */ -#define UIC_MAL_SERR 0x00200000 /* MAL SERR */ -#define UIC_MAL_TXEOB 0x00100000 /* MAL TXEOB */ -#define UIC_MAL_RXEOB 0x00080000 /* MAL RXEOB */ -#define UIC_MAL_TXDE 0x00040000 /* MAL TXDE */ -#define UIC_MAL_RXDE 0x00020000 /* MAL RXDE */ -#define UIC_ENET 0x00010000 /* Ethernet0 */ -#define UIC_ENET1 0x00004000 /* Ethernet1 on 405EP */ -#define UIC_ECC_CE 0x00004000 /* ECC Correctable Error on 405GP */ -#define UIC_EXT_PCI_SERR 0x00008000 /* External PCI SERR# */ -#define UIC_PCI_PM 0x00002000 /* PCI Power Management */ -#define UIC_EXT0 0x00000040 /* External interrupt 0 */ -#define UIC_EXT1 0x00000020 /* External interrupt 1 */ -#define UIC_EXT2 0x00000010 /* External interrupt 2 */ -#define UIC_EXT3 0x00000008 /* External interrupt 3 */ -#define UIC_EXT4 0x00000004 /* External interrupt 4 */ -#define UIC_EXT5 0x00000002 /* External interrupt 5 */ -#define UIC_EXT6 0x00000001 /* External interrupt 6 */ -#endif /* defined(CONFIG_405EZ) */ - -/****************************************************************************** - * External Bus Controller (EBC) - *****************************************************************************/ - -/* Bank Configuration Register */ -#define EBC_BXCR_BAS_MASK PPC_REG_VAL(11, 0xFFF) -#define EBC_BXCR_BAS_ENCODE(n) (((static_cast(unsigned long, n)) & \ - EBC_BXCR_BAS_MASK) << 0) -#define EBC_BXCR_BS_MASK PPC_REG_VAL(14, 0x7) -#define EBC_BXCR_BS_1MB PPC_REG_VAL(14, 0x0) -#define EBC_BXCR_BS_2MB PPC_REG_VAL(14, 0x1) -#define EBC_BXCR_BS_4MB PPC_REG_VAL(14, 0x2) -#define EBC_BXCR_BS_8MB PPC_REG_VAL(14, 0x3) -#define EBC_BXCR_BS_16MB PPC_REG_VAL(14, 0x4) -#define EBC_BXCR_BS_32MB PPC_REG_VAL(14, 0x5) -#define EBC_BXCR_BS_64MB PPC_REG_VAL(14, 0x6) -#define EBC_BXCR_BS_128MB PPC_REG_VAL(14, 0x7) -#define EBC_BXCR_BU_MASK PPC_REG_VAL(16, 0x3) -#define EBC_BXCR_BU_NONE PPC_REG_VAL(16, 0x0) -#define EBC_BXCR_BU_R PPC_REG_VAL(16, 0x1) -#define EBC_BXCR_BU_W PPC_REG_VAL(16, 0x2) -#define EBC_BXCR_BU_RW PPC_REG_VAL(16, 0x3) -#define EBC_BXCR_BW_MASK PPC_REG_VAL(18, 0x3) -#define EBC_BXCR_BW_8BIT PPC_REG_VAL(18, 0x0) -#define EBC_BXCR_BW_16BIT PPC_REG_VAL(18, 0x1) -#define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x3) - -/* Bank Access Parameter Register */ -#define EBC_BXAP_BME_ENABLED PPC_REG_VAL(0, 0x1) -#define EBC_BXAP_BME_DISABLED PPC_REG_VAL(0, 0x0) -#define EBC_BXAP_TWT_ENCODE(n) PPC_REG_VAL(8, \ - (static_cast(unsigned long, n)) \ - & 0xFF) -#define EBC_BXAP_FWT_ENCODE(n) PPC_REG_VAL(5, \ - (static_cast(unsigned long, n)) \ - & 0x1F) -#define EBC_BXAP_BWT_ENCODE(n) PPC_REG_VAL(8, \ - (static_cast(unsigned long, n)) \ - & 0x7) -#define EBC_BXAP_BCE_DISABLE PPC_REG_VAL(9, 0x0) -#define EBC_BXAP_BCE_ENABLE PPC_REG_VAL(9, 0x1) -#define EBC_BXAP_BCT_MASK PPC_REG_VAL(11, 0x3) -#define EBC_BXAP_BCT_2TRANS PPC_REG_VAL(11, 0x0) -#define EBC_BXAP_BCT_4TRANS PPC_REG_VAL(11, 0x1) -#define EBC_BXAP_BCT_8TRANS PPC_REG_VAL(11, 0x2) -#define EBC_BXAP_BCT_16TRANS PPC_REG_VAL(11, 0x3) -#define EBC_BXAP_CSN_ENCODE(n) PPC_REG_VAL(13, \ - (static_cast(unsigned long, n)) \ - & 0x3) -#define EBC_BXAP_OEN_ENCODE(n) PPC_REG_VAL(15, \ - (static_cast(unsigned long, n)) \ - & 0x3) -#define EBC_BXAP_WBN_ENCODE(n) PPC_REG_VAL(17, \ - (static_cast(unsigned long, n)) \ - & 0x3) -#define EBC_BXAP_WBF_ENCODE(n) PPC_REG_VAL(19, \ - (static_cast(unsigned long, n)) \ - & 0x3) -#define EBC_BXAP_TH_ENCODE(n) PPC_REG_VAL(22, \ - (static_cast(unsigned long, n)) \ - & 0x7) -#define EBC_BXAP_RE_ENABLED PPC_REG_VAL(23, 0x1) -#define EBC_BXAP_RE_DISABLED PPC_REG_VAL(23, 0x0) -#define EBC_BXAP_SOR_DELAYED PPC_REG_VAL(24, 0x0) -#define EBC_BXAP_SOR_NONDELAYED PPC_REG_VAL(24, 0x1) -#define EBC_BXAP_BEM_WRITEONLY PPC_REG_VAL(25, 0x0) -#define EBC_BXAP_BEM_RW PPC_REG_VAL(25, 0x1) -#define EBC_BXAP_PEN_DISABLED PPC_REG_VAL(26, 0x0) -#define EBC_BXAP_PEN_ENABLED PPC_REG_VAL(26, 0x1) - -/* Configuration Register */ -#define EBC_CFG_LE_MASK PPC_REG_VAL(0, 0x1) -#define EBC_CFG_LE_UNLOCK PPC_REG_VAL(0, 0x0) -#define EBC_CFG_LE_LOCK PPC_REG_VAL(0, 0x1) -#define EBC_CFG_PTD_MASK PPC_REG_VAL(1, 0x1) -#define EBC_CFG_PTD_ENABLE PPC_REG_VAL(1, 0x0) -#define EBC_CFG_PTD_DISABLE PPC_REG_VAL(1, 0x1) -#define EBC_CFG_RTC_MASK PPC_REG_VAL(4, 0x7) -#define EBC_CFG_RTC_16PERCLK PPC_REG_VAL(4, 0x0) -#define EBC_CFG_RTC_32PERCLK PPC_REG_VAL(4, 0x1) -#define EBC_CFG_RTC_64PERCLK PPC_REG_VAL(4, 0x2) -#define EBC_CFG_RTC_128PERCLK PPC_REG_VAL(4, 0x3) -#define EBC_CFG_RTC_256PERCLK PPC_REG_VAL(4, 0x4) -#define EBC_CFG_RTC_512PERCLK PPC_REG_VAL(4, 0x5) -#define EBC_CFG_RTC_1024PERCLK PPC_REG_VAL(4, 0x6) -#define EBC_CFG_RTC_2048PERCLK PPC_REG_VAL(4, 0x7) -#define EBC_CFG_ATC_MASK PPC_REG_VAL(5, 0x1) -#define EBC_CFG_ATC_HI PPC_REG_VAL(5, 0x0) -#define EBC_CFG_ATC_PREVIOUS PPC_REG_VAL(5, 0x1) -#define EBC_CFG_DTC_MASK PPC_REG_VAL(6, 0x1) -#define EBC_CFG_DTC_HI PPC_REG_VAL(6, 0x0) -#define EBC_CFG_DTC_PREVIOUS PPC_REG_VAL(6, 0x1) -#define EBC_CFG_CTC_MASK PPC_REG_VAL(7, 0x1) -#define EBC_CFG_CTC_HI PPC_REG_VAL(7, 0x0) -#define EBC_CFG_CTC_PREVIOUS PPC_REG_VAL(7, 0x1) -#define EBC_CFG_OEO_MASK PPC_REG_VAL(8, 0x1) -#define EBC_CFG_OEO_DISABLE PPC_REG_VAL(8, 0x0) -#define EBC_CFG_OEO_ENABLE PPC_REG_VAL(8, 0x1) -#define EBC_CFG_EMC_MASK PPC_REG_VAL(9, 0x1) -#define EBC_CFG_EMC_NONDEFAULT PPC_REG_VAL(9, 0x0) -#define EBC_CFG_EMC_DEFAULT PPC_REG_VAL(9, 0x1) -#define EBC_CFG_PME_MASK PPC_REG_VAL(14, 0x1) -#define EBC_CFG_PME_DISABLE PPC_REG_VAL(14, 0x0) -#define EBC_CFG_PME_ENABLE PPC_REG_VAL(14, 0x1) -#define EBC_CFG_PMT_MASK PPC_REG_VAL(19, 0x1F) -#define EBC_CFG_PMT_ENCODE(n) PPC_REG_VAL(19, \ - (static_cast(unsigned long, n)) \ - & 0x1F) -#define EBC_CFG_PR_MASK PPC_REG_VAL(21, 0x3) -#define EBC_CFG_PR_16 PPC_REG_VAL(21, 0x0) -#define EBC_CFG_PR_32 PPC_REG_VAL(21, 0x1) -#define EBC_CFG_PR_64 PPC_REG_VAL(21, 0x2) -#define EBC_CFG_PR_128 PPC_REG_VAL(21, 0x3) - #ifndef CONFIG_405EP /****************************************************************************** * Decompression Controller @@ -1254,6 +893,42 @@ #if defined(CONFIG_405EX) #define SDR0_SRST 0x0200 +/* + * Software Reset Register + */ +#define SDR0_SRST_BGO PPC_REG_VAL(0, 1) +#define SDR0_SRST_PLB4 PPC_REG_VAL(1, 1) +#define SDR0_SRST_EBC PPC_REG_VAL(2, 1) +#define SDR0_SRST_OPB PPC_REG_VAL(3, 1) +#define SDR0_SRST_UART0 PPC_REG_VAL(4, 1) +#define SDR0_SRST_UART1 PPC_REG_VAL(5, 1) +#define SDR0_SRST_IIC0 PPC_REG_VAL(6, 1) +#define SDR0_SRST_BGI PPC_REG_VAL(7, 1) +#define SDR0_SRST_GPIO PPC_REG_VAL(8, 1) +#define SDR0_SRST_GPT PPC_REG_VAL(9, 1) +#define SDR0_SRST_DMC PPC_REG_VAL(10, 1) +#define SDR0_SRST_RGMII PPC_REG_VAL(11, 1) +#define SDR0_SRST_EMAC0 PPC_REG_VAL(12, 1) +#define SDR0_SRST_EMAC1 PPC_REG_VAL(13, 1) +#define SDR0_SRST_CPM PPC_REG_VAL(14, 1) +#define SDR0_SRST_EPLL PPC_REG_VAL(15, 1) +#define SDR0_SRST_UIC PPC_REG_VAL(16, 1) +#define SDR0_SRST_UPRST PPC_REG_VAL(17, 1) +#define SDR0_SRST_IIC1 PPC_REG_VAL(18, 1) +#define SDR0_SRST_SCP PPC_REG_VAL(19, 1) +#define SDR0_SRST_UHRST PPC_REG_VAL(20, 1) +#define SDR0_SRST_DMA PPC_REG_VAL(21, 1) +#define SDR0_SRST_DMAC PPC_REG_VAL(22, 1) +#define SDR0_SRST_MAL PPC_REG_VAL(23, 1) +#define SDR0_SRST_EBM PPC_REG_VAL(24, 1) +#define SDR0_SRST_GPTR PPC_REG_VAL(25, 1) +#define SDR0_SRST_PE0 PPC_REG_VAL(26, 1) +#define SDR0_SRST_PE1 PPC_REG_VAL(27, 1) +#define SDR0_SRST_CRYP PPC_REG_VAL(28, 1) +#define SDR0_SRST_PKP PPC_REG_VAL(29, 1) +#define SDR0_SRST_AHB PPC_REG_VAL(30, 1) +#define SDR0_SRST_NDFC PPC_REG_VAL(31, 1) + #define sdr_uart0 0x0120 /* UART0 Config */ #define sdr_uart1 0x0121 /* UART1 Config */ #define sdr_mfr 0x4300 /* SDR0_MFR reg */ diff --git a/include/ppc440.h b/include/ppc440.h index c581f1b468..92db15f312 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -77,7 +77,6 @@ #define tbl 0x11c /* time base lower (supervisor)*/ #define tbu 0x11d /* time base upper (supervisor)*/ #define pir 0x11e /* processor id register */ -/*#define pvr 0x11f processor version register */ #define dbsr 0x130 /* debug status register */ #define dbcr0 0x134 /* debug control register 0 */ #define dbcr1 0x135 /* debug control register 1 */ @@ -268,86 +267,6 @@ #define sdr_sdstp6 0x4005 #define sdr_sdstp7 0x4007 -/****************************************************************************** - * PCI express defines - ******************************************************************************/ -#define SDR0_PE0UTLSET1 0x00000300 /* PE0 Upper transaction layer conf setting */ -#define SDR0_PE0UTLSET2 0x00000301 /* PE0 Upper transaction layer conf setting 2 */ -#define SDR0_PE0DLPSET 0x00000302 /* PE0 Data link & logical physical configuration */ -#define SDR0_PE0LOOP 0x00000303 /* PE0 Loopback interface status */ -#define SDR0_PE0RCSSET 0x00000304 /* PE0 Reset, clock & shutdown setting */ -#define SDR0_PE0RCSSTS 0x00000305 /* PE0 Reset, clock & shutdown status */ -#define SDR0_PE0HSSSET1L0 0x00000306 /* PE0 HSS Control Setting 1: Lane 0 */ -#define SDR0_PE0HSSSET2L0 0x00000307 /* PE0 HSS Control Setting 2: Lane 0 */ -#define SDR0_PE0HSSSTSL0 0x00000308 /* PE0 HSS Control Status : Lane 0 */ -#define SDR0_PE0HSSSET1L1 0x00000309 /* PE0 HSS Control Setting 1: Lane 1 */ -#define SDR0_PE0HSSSET2L1 0x0000030A /* PE0 HSS Control Setting 2: Lane 1 */ -#define SDR0_PE0HSSSTSL1 0x0000030B /* PE0 HSS Control Status : Lane 1 */ -#define SDR0_PE0HSSSET1L2 0x0000030C /* PE0 HSS Control Setting 1: Lane 2 */ -#define SDR0_PE0HSSSET2L2 0x0000030D /* PE0 HSS Control Setting 2: Lane 2 */ -#define SDR0_PE0HSSSTSL2 0x0000030E /* PE0 HSS Control Status : Lane 2 */ -#define SDR0_PE0HSSSET1L3 0x0000030F /* PE0 HSS Control Setting 1: Lane 3 */ -#define SDR0_PE0HSSSET2L3 0x00000310 /* PE0 HSS Control Setting 2: Lane 3 */ -#define SDR0_PE0HSSSTSL3 0x00000311 /* PE0 HSS Control Status : Lane 3 */ -#define SDR0_PE0HSSSET1L4 0x00000312 /* PE0 HSS Control Setting 1: Lane 4 */ -#define SDR0_PE0HSSSET2L4 0x00000313 /* PE0 HSS Control Setting 2: Lane 4 */ -#define SDR0_PE0HSSSTSL4 0x00000314 /* PE0 HSS Control Status : Lane 4 */ -#define SDR0_PE0HSSSET1L5 0x00000315 /* PE0 HSS Control Setting 1: Lane 5 */ -#define SDR0_PE0HSSSET2L5 0x00000316 /* PE0 HSS Control Setting 2: Lane 5 */ -#define SDR0_PE0HSSSTSL5 0x00000317 /* PE0 HSS Control Status : Lane 5 */ -#define SDR0_PE0HSSSET1L6 0x00000318 /* PE0 HSS Control Setting 1: Lane 6 */ -#define SDR0_PE0HSSSET2L6 0x00000319 /* PE0 HSS Control Setting 2: Lane 6 */ -#define SDR0_PE0HSSSTSL6 0x0000031A /* PE0 HSS Control Status : Lane 6 */ -#define SDR0_PE0HSSSET1L7 0x0000031B /* PE0 HSS Control Setting 1: Lane 7 */ -#define SDR0_PE0HSSSET2L7 0x0000031C /* PE0 HSS Control Setting 2: Lane 7 */ -#define SDR0_PE0HSSSTSL7 0x0000031D /* PE0 HSS Control Status : Lane 7 */ -#define SDR0_PE0HSSSEREN 0x0000031E /* PE0 Serdes Transmitter Enable */ -#define SDR0_PE0LANEABCD 0x0000031F /* PE0 Lanes ABCD affectation */ -#define SDR0_PE0LANEEFGH 0x00000320 /* PE0 Lanes EFGH affectation */ - -#define SDR0_PE1UTLSET1 0x00000340 /* PE1 Upper transaction layer conf setting */ -#define SDR0_PE1UTLSET2 0x00000341 /* PE1 Upper transaction layer conf setting 2 */ -#define SDR0_PE1DLPSET 0x00000342 /* PE1 Data link & logical physical configuration */ -#define SDR0_PE1LOOP 0x00000343 /* PE1 Loopback interface status */ -#define SDR0_PE1RCSSET 0x00000344 /* PE1 Reset, clock & shutdown setting */ -#define SDR0_PE1RCSSTS 0x00000345 /* PE1 Reset, clock & shutdown status */ -#define SDR0_PE1HSSSET1L0 0x00000346 /* PE1 HSS Control Setting 1: Lane 0 */ -#define SDR0_PE1HSSSET2L0 0x00000347 /* PE1 HSS Control Setting 2: Lane 0 */ -#define SDR0_PE1HSSSTSL0 0x00000348 /* PE1 HSS Control Status : Lane 0 */ -#define SDR0_PE1HSSSET1L1 0x00000349 /* PE1 HSS Control Setting 1: Lane 1 */ -#define SDR0_PE1HSSSET2L1 0x0000034A /* PE1 HSS Control Setting 2: Lane 1 */ -#define SDR0_PE1HSSSTSL1 0x0000034B /* PE1 HSS Control Status : Lane 1 */ -#define SDR0_PE1HSSSET1L2 0x0000034C /* PE1 HSS Control Setting 1: Lane 2 */ -#define SDR0_PE1HSSSET2L2 0x0000034D /* PE1 HSS Control Setting 2: Lane 2 */ -#define SDR0_PE1HSSSTSL2 0x0000034E /* PE1 HSS Control Status : Lane 2 */ -#define SDR0_PE1HSSSET1L3 0x0000034F /* PE1 HSS Control Setting 1: Lane 3 */ -#define SDR0_PE1HSSSET2L3 0x00000350 /* PE1 HSS Control Setting 2: Lane 3 */ -#define SDR0_PE1HSSSTSL3 0x00000351 /* PE1 HSS Control Status : Lane 3 */ -#define SDR0_PE1HSSSEREN 0x00000352 /* PE1 Serdes Transmitter Enable */ -#define SDR0_PE1LANEABCD 0x00000353 /* PE1 Lanes ABCD affectation */ -#define SDR0_PE2UTLSET1 0x00000370 /* PE2 Upper transaction layer conf setting */ -#define SDR0_PE2UTLSET2 0x00000371 /* PE2 Upper transaction layer conf setting 2 */ -#define SDR0_PE2DLPSET 0x00000372 /* PE2 Data link & logical physical configuration */ -#define SDR0_PE2LOOP 0x00000373 /* PE2 Loopback interface status */ -#define SDR0_PE2RCSSET 0x00000374 /* PE2 Reset, clock & shutdown setting */ -#define SDR0_PE2RCSSTS 0x00000375 /* PE2 Reset, clock & shutdown status */ -#define SDR0_PE2HSSSET1L0 0x00000376 /* PE2 HSS Control Setting 1: Lane 0 */ -#define SDR0_PE2HSSSET2L0 0x00000377 /* PE2 HSS Control Setting 2: Lane 0 */ -#define SDR0_PE2HSSSTSL0 0x00000378 /* PE2 HSS Control Status : Lane 0 */ -#define SDR0_PE2HSSSET1L1 0x00000379 /* PE2 HSS Control Setting 1: Lane 1 */ -#define SDR0_PE2HSSSET2L1 0x0000037A /* PE2 HSS Control Setting 2: Lane 1 */ -#define SDR0_PE2HSSSTSL1 0x0000037B /* PE2 HSS Control Status : Lane 1 */ -#define SDR0_PE2HSSSET1L2 0x0000037C /* PE2 HSS Control Setting 1: Lane 2 */ -#define SDR0_PE2HSSSET2L2 0x0000037D /* PE2 HSS Control Setting 2: Lane 2 */ -#define SDR0_PE2HSSSTSL2 0x0000037E /* PE2 HSS Control Status : Lane 2 */ -#define SDR0_PE2HSSSET1L3 0x0000037F /* PE2 HSS Control Setting 1: Lane 3 */ -#define SDR0_PE2HSSSET2L3 0x00000380 /* PE2 HSS Control Setting 2: Lane 3 */ -#define SDR0_PE2HSSSTSL3 0x00000381 /* PE2 HSS Control Status : Lane 3 */ -#define SDR0_PE2HSSSEREN 0x00000382 /* PE2 Serdes Transmitter Enable */ -#define SDR0_PE2LANEABCD 0x00000383 /* PE2 Lanes ABCD affectation */ -#define SDR0_PEGPLLSET1 0x000003A0 /* PE Pll LC Tank Setting1 */ -#define SDR0_PEGPLLSET2 0x000003A1 /* PE Pll LC Tank Setting2 */ -#define SDR0_PEGPLLSTS 0x000003A2 /* PE Pll LC Tank Status */ #endif /* CONFIG_440SPE */ /*----------------------------------------------------------------------------- @@ -749,7 +668,8 @@ +----------------------------------------------------------------------------*/ #if defined (CONFIG_440GX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) #define L2_CACHE_BASE 0x030 #define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */ #define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */ @@ -837,7 +757,8 @@ /*----------------------------------------------------------------------------- | Clocking, Power Management and Chip Control +----------------------------------------------------------------------------*/ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) #define CNTRL_DCR_BASE 0x160 #else #define CNTRL_DCR_BASE 0x0b0 @@ -863,193 +784,6 @@ #define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */ /*----------------------------------------------------------------------------- - | Universal interrupt controller - +----------------------------------------------------------------------------*/ -#define UIC_SR 0x0 /* UIC status */ -#define UIC_ER 0x2 /* UIC enable */ -#define UIC_CR 0x3 /* UIC critical */ -#define UIC_PR 0x4 /* UIC polarity */ -#define UIC_TR 0x5 /* UIC triggering */ -#define UIC_MSR 0x6 /* UIC masked status */ -#define UIC_VR 0x7 /* UIC vector */ -#define UIC_VCR 0x8 /* UIC vector configuration */ - -#define UIC0_DCR_BASE 0xc0 -#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */ -#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */ -#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */ -#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ -#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ -#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ -#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */ -#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ - -#define UIC1_DCR_BASE 0xd0 -#define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */ -#define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */ -#define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */ -#define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */ -#define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */ -#define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */ -#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */ -#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */ - -#if defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define UIC2_DCR_BASE 0xe0 -#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */ -#define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */ -#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */ -#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */ -#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */ -#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */ -#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */ -#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */ -#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */ - -#define UIC3_DCR_BASE 0xf0 -#define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */ -#define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */ -#define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */ -#define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */ -#define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */ -#define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */ -#define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */ -#define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */ -#define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */ -#endif /* CONFIG_440SPE */ - -#if defined(CONFIG_440GX) -#define UIC2_DCR_BASE 0x210 -#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status */ -#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */ -#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */ -#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */ -#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */ -#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */ -#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */ -#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */ - - -#define UIC_DCR_BASE 0x200 -#define uicb0sr (UIC_DCR_BASE+0x0) /* UIC Base Status Register */ -#define uicb0er (UIC_DCR_BASE+0x2) /* UIC Base enable */ -#define uicb0cr (UIC_DCR_BASE+0x3) /* UIC Base critical */ -#define uicb0pr (UIC_DCR_BASE+0x4) /* UIC Base polarity */ -#define uicb0tr (UIC_DCR_BASE+0x5) /* UIC Base triggering */ -#define uicb0msr (UIC_DCR_BASE+0x6) /* UIC Base masked status */ -#define uicb0vr (UIC_DCR_BASE+0x7) /* UIC Base vector */ -#define uicb0vcr (UIC_DCR_BASE+0x8) /* UIC Base vector configuration */ -#endif /* CONFIG_440GX */ - -/* The following is for compatibility with 405 code */ -#define uicsr uic0sr -#define uicer uic0er -#define uiccr uic0cr -#define uicpr uic0pr -#define uictr uic0tr -#define uicmsr uic0msr -#define uicvr uic0vr -#define uicvcr uic0vcr - -#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) -/*----------------------------------------------------------------------------+ -| Clock / Power-on-reset DCR's. -+----------------------------------------------------------------------------*/ -#define CPR0_CLKUPD 0x20 -#define CPR0_CLKUPD_BSY_MASK 0x80000000 -#define CPR0_CLKUPD_BSY_COMPLETED 0x00000000 -#define CPR0_CLKUPD_BSY_BUSY 0x80000000 -#define CPR0_CLKUPD_CUI_MASK 0x80000000 -#define CPR0_CLKUPD_CUI_DISABLE 0x00000000 -#define CPR0_CLKUPD_CUI_ENABLE 0x80000000 -#define CPR0_CLKUPD_CUD_MASK 0x40000000 -#define CPR0_CLKUPD_CUD_DISABLE 0x00000000 -#define CPR0_CLKUPD_CUD_ENABLE 0x40000000 - -#define CPR0_PLLC 0x40 -#define CPR0_PLLC_RST_MASK 0x80000000 -#define CPR0_PLLC_RST_PLLLOCKED 0x00000000 -#define CPR0_PLLC_RST_PLLRESET 0x80000000 -#define CPR0_PLLC_ENG_MASK 0x40000000 -#define CPR0_PLLC_ENG_DISABLE 0x00000000 -#define CPR0_PLLC_ENG_ENABLE 0x40000000 -#define CPR0_PLLC_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) -#define CPR0_PLLC_ENG_DECODE(n) ((((unsigned long)(n))>>30)&0x01) -#define CPR0_PLLC_SRC_MASK 0x20000000 -#define CPR0_PLLC_SRC_PLLOUTA 0x00000000 -#define CPR0_PLLC_SRC_PLLOUTB 0x20000000 -#define CPR0_PLLC_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) -#define CPR0_PLLC_SRC_DECODE(n) ((((unsigned long)(n))>>29)&0x01) -#define CPR0_PLLC_SEL_MASK 0x07000000 -#define CPR0_PLLC_SEL_PLLOUT 0x00000000 -#define CPR0_PLLC_SEL_CPU 0x01000000 -#define CPR0_PLLC_SEL_EBC 0x05000000 -#define CPR0_PLLC_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) -#define CPR0_PLLC_SEL_DECODE(n) ((((unsigned long)(n))>>24)&0x07) -#define CPR0_PLLC_TUNE_MASK 0x000003FF -#define CPR0_PLLC_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) -#define CPR0_PLLC_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) - -#define CPR0_PLLD 0x60 -#define CPR0_PLLD_FBDV_MASK 0x1F000000 -#define CPR0_PLLD_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define CPR0_PLLD_FBDV_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x1F)+1) -#define CPR0_PLLD_FWDVA_MASK 0x000F0000 -#define CPR0_PLLD_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<16) -#define CPR0_PLLD_FWDVA_DECODE(n) ((((((unsigned long)(n))>>16)-1)&0x0F)+1) -#define CPR0_PLLD_FWDVB_MASK 0x00000700 -#define CPR0_PLLD_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<8) -#define CPR0_PLLD_FWDVB_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x07)+1) -#define CPR0_PLLD_LFBDV_MASK 0x0000003F -#define CPR0_PLLD_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0) -#define CPR0_PLLD_LFBDV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1) - -#define CPR0_PRIMAD 0x80 -#define CPR0_PRIMAD_PRADV0_MASK 0x07000000 -#define CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) -#define CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1) - -#define CPR0_PRIMBD 0xA0 -#define CPR0_PRIMBD_PRBDV0_MASK 0x07000000 -#define CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) -#define CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1) - -#define CPR0_OPBD 0xC0 -#define CPR0_OPBD_OPBDV0_MASK 0x03000000 -#define CPR0_OPBD_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) -#define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) - -#define CPR0_PERD 0xE0 -#if !defined(CONFIG_440EPX) -#define CPR0_PERD_PERDV0_MASK 0x03000000 -#define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) -#define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) -#endif - -#define CPR0_MALD 0x100 -#define CPR0_MALD_MALDV0_MASK 0x03000000 -#define CPR0_MALD_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) -#define CPR0_MALD_MALDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) - -#define CPR0_ICFG 0x140 -#define CPR0_ICFG_RLI_MASK 0x80000000 -#define CPR0_ICFG_RLI_RESETCPR 0x00000000 -#define CPR0_ICFG_RLI_PRESERVECPR 0x80000000 -#define CPR0_ICFG_ICS_MASK 0x00000007 -#define CPR0_ICFG_ICS_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0) -#define CPR0_ICFG_ICS_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1) - -/************************/ -/* IIC defines */ -/************************/ -#define IIC0_MMIO_BASE 0xA0000400 -#define IIC1_MMIO_BASE 0xA0000500 - -#endif /* CONFIG_440SP */ - -/*----------------------------------------------------------------------------- | DMA +----------------------------------------------------------------------------*/ #if defined(CONFIG_460EX) || defined(CONFIG_460GT) @@ -1136,708 +870,6 @@ #define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */ #endif /* CONFIG_440GX */ - -/*---------------------------------------------------------------------------+ -| Universal interrupt controller 0 interrupts (UIC0) -+---------------------------------------------------------------------------*/ -#if defined(CONFIG_440SP) -#define UIC_U0 0x80000000 /* UART 0 */ -#define UIC_U1 0x40000000 /* UART 1 */ -#define UIC_IIC0 0x20000000 /* IIC */ -#define UIC_IIC1 0x10000000 /* IIC */ -#define UIC_PIM 0x08000000 /* PCI0 inbound message */ -#define UIC_PCRW 0x04000000 /* PCI0 command write register */ -#define UIC_PPM 0x02000000 /* PCI0 power management */ -#define UIC_PVPD 0x01000000 /* PCI0 VPD Access */ -#define UIC_MSI0 0x00800000 /* PCI0 MSI level 0 */ -#define UIC_P1IM 0x00400000 /* PCI1 Inbound Message */ -#define UIC_P1CRW 0x00200000 /* PCI1 command write register */ -#define UIC_P1PM 0x00100000 /* PCI1 power management */ -#define UIC_P1VPD 0x00080000 /* PCI1 VPD Access */ -#define UIC_P1MSI0 0x00040000 /* PCI1 MSI level 0 */ -#define UIC_P2IM 0x00020000 /* PCI2 inbound message */ -#define UIC_P2CRW 0x00010000 /* PCI2 command register write */ -#define UIC_P2PM 0x00008000 /* PCI2 power management */ -#define UIC_P2VPD 0x00004000 /* PCI2 VPD access */ -#define UIC_P2MSI0 0x00002000 /* PCI2 MSI level 0 */ -#define UIC_D0CPF 0x00001000 /* DMA0 command pointer */ -#define UIC_D0CSF 0x00000800 /* DMA0 command status */ -#define UIC_D1CPF 0x00000400 /* DMA1 command pointer */ -#define UIC_D1CSF 0x00000200 /* DMA1 command status */ -#define UIC_I2OID 0x00000100 /* I2O inbound doorbell */ -#define UIC_I2OPLF 0x00000080 /* I2O inbound post list */ -#define UIC_I2O0LL 0x00000040 /* I2O0 low latency PLB write */ -#define UIC_I2O1LL 0x00000020 /* I2O1 low latency PLB write */ -#define UIC_I2O0HB 0x00000010 /* I2O0 high bandwidth PLB write */ -#define UIC_I2O1HB 0x00000008 /* I2O1 high bandwidth PLB write */ -#define UIC_GPTCT 0x00000004 /* GPT count timer */ -#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ -#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ -#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) -#define UIC_U0 0x80000000 /* UART 0 */ -#define UIC_U1 0x40000000 /* UART 1 */ -#define UIC_IIC0 0x20000000 /* IIC */ -#define UIC_IIC1 0x10000000 /* IIC */ -#define UIC_PIM 0x08000000 /* PCI inbound message */ -#define UIC_PCRW 0x04000000 /* PCI command register write */ -#define UIC_PPM 0x02000000 /* PCI power management */ -#define UIC_MSI0 0x01000000 /* PCI MSI level 0 */ -#define UIC_MSI1 0x00800000 /* PCI MSI level 1 */ -#define UIC_MSI2 0x00400000 /* PCI MSI level 2 */ -#define UIC_MTE 0x00200000 /* MAL TXEOB */ -#define UIC_MRE 0x00100000 /* MAL RXEOB */ -#define UIC_D0 0x00080000 /* DMA channel 0 */ -#define UIC_D1 0x00040000 /* DMA channel 1 */ -#define UIC_D2 0x00020000 /* DMA channel 2 */ -#define UIC_D3 0x00010000 /* DMA channel 3 */ -#define UIC_RSVD0 0x00008000 /* Reserved */ -#define UIC_RSVD1 0x00004000 /* Reserved */ -#define UIC_CT0 0x00002000 /* GPT compare timer 0 */ -#define UIC_CT1 0x00001000 /* GPT compare timer 1 */ -#define UIC_CT2 0x00000800 /* GPT compare timer 2 */ -#define UIC_CT3 0x00000400 /* GPT compare timer 3 */ -#define UIC_CT4 0x00000200 /* GPT compare timer 4 */ -#define UIC_EIR0 0x00000100 /* External interrupt 0 */ -#define UIC_EIR1 0x00000080 /* External interrupt 1 */ -#define UIC_EIR2 0x00000040 /* External interrupt 2 */ -#define UIC_EIR3 0x00000020 /* External interrupt 3 */ -#define UIC_EIR4 0x00000010 /* External interrupt 4 */ -#define UIC_EIR5 0x00000008 /* External interrupt 5 */ -#define UIC_EIR6 0x00000004 /* External interrupt 6 */ -#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ -#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ - -#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - -#define UIC_U0 0x80000000 /* UART 0 */ -#define UIC_U1 0x40000000 /* UART 1 */ -#define UIC_IIC0 0x20000000 /* IIC */ -#define UIC_KRD 0x10000000 /* Kasumi Ready for data */ -#define UIC_KDA 0x08000000 /* Kasumi Data Available */ -#define UIC_PCRW 0x04000000 /* PCI command register write */ -#define UIC_PPM 0x02000000 /* PCI power management */ -#define UIC_IIC1 0x01000000 /* IIC */ -#define UIC_SPI 0x00800000 /* SPI */ -#define UIC_EPCISER 0x00400000 /* External PCI SERR */ -#define UIC_MTE 0x00200000 /* MAL TXEOB */ -#define UIC_MRE 0x00100000 /* MAL RXEOB */ -#define UIC_D0 0x00080000 /* DMA channel 0 */ -#define UIC_D1 0x00040000 /* DMA channel 1 */ -#define UIC_D2 0x00020000 /* DMA channel 2 */ -#define UIC_D3 0x00010000 /* DMA channel 3 */ -#define UIC_UD0 0x00008000 /* UDMA irq 0 */ -#define UIC_UD1 0x00004000 /* UDMA irq 1 */ -#define UIC_UD2 0x00002000 /* UDMA irq 2 */ -#define UIC_UD3 0x00001000 /* UDMA irq 3 */ -#define UIC_HSB2D 0x00000800 /* USB2.0 Device */ -#define UIC_OHCI1 0x00000400 /* USB2.0 Host OHCI irq 1 */ -#define UIC_OHCI2 0x00000200 /* USB2.0 Host OHCI irq 2 */ -#define UIC_EIP94 0x00000100 /* Security EIP94 */ -#define UIC_ETH0 0x00000080 /* Emac 0 */ -#define UIC_ETH1 0x00000040 /* Emac 1 */ -#define UIC_EHCI 0x00000020 /* USB2.0 Host EHCI */ -#define UIC_EIR4 0x00000010 /* External interrupt 4 */ -#define UIC_UIC2NC 0x00000008 /* UIC2 non-critical interrupt */ -#define UIC_UIC2C 0x00000004 /* UIC2 critical interrupt */ -#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ -#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ - -/* For compatibility with 405 code */ -#define UIC_MAL_TXEOB UIC_MTE -#define UIC_MAL_RXEOB UIC_MRE - -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) - -#define UIC_RSVD0 0x80000000 /* N/A - unused */ -#define UIC_U1 0x40000000 /* UART 1 */ -#define UIC_IIC0 0x20000000 /* IIC */ -#define UIC_IIC1 0x10000000 /* IIC */ -#define UIC_PIM 0x08000000 /* PCI inbound message */ -#define UIC_PCRW 0x04000000 /* PCI command register write */ -#define UIC_PPM 0x02000000 /* PCI power management */ -#define UIC_PCIVPD 0x01000000 /* PCI VPD */ -#define UIC_MSI0 0x00800000 /* PCI MSI level 0 */ -#define UIC_EIR0 0x00400000 /* External interrupt 0 */ -#define UIC_UIC2NC 0x00200000 /* UIC2 non-critical interrupt */ -#define UIC_UIC2C 0x00100000 /* UIC2 critical interrupt */ -#define UIC_D0 0x00080000 /* DMA channel 0 */ -#define UIC_D1 0x00040000 /* DMA channel 1 */ -#define UIC_D2 0x00020000 /* DMA channel 2 */ -#define UIC_D3 0x00010000 /* DMA channel 3 */ -#define UIC_UIC3NC 0x00008000 /* UIC3 non-critical interrupt */ -#define UIC_UIC3C 0x00004000 /* UIC3 critical interrupt */ -#define UIC_EIR1 0x00002000 /* External interrupt 1 */ -#define UIC_TRNGDA 0x00001000 /* TRNG data available */ -#define UIC_PKAR1 0x00000800 /* PKA ready (PKA[1]) */ -#define UIC_D1CPFF 0x00000400 /* DMA1 cp fifo full */ -#define UIC_D1CSNS 0x00000200 /* DMA1 cs fifo needs service */ -#define UIC_I2OID 0x00000100 /* I2O inbound door bell */ -#define UIC_I2OLNE 0x00000080 /* I2O Inbound Post List FIFO Not Empty */ -#define UIC_I20R0LL 0x00000040 /* I2O Region 0 Low Latency PLB Write */ -#define UIC_I2OR1LL 0x00000020 /* I2O Region 1 Low Latency PLB Write */ -#define UIC_I20R0HB 0x00000010 /* I2O Region 0 High Bandwidth PLB Write */ -#define UIC_I2OR1HB 0x00000008 /* I2O Region 1 High Bandwidth PLB Write */ -#define UIC_EIP94 0x00000004 /* Security EIP94 */ -#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ -#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ - -#elif !defined(CONFIG_440SPE) -#define UIC_U0 0x80000000 /* UART 0 */ -#define UIC_U1 0x40000000 /* UART 1 */ -#define UIC_IIC0 0x20000000 /* IIC */ -#define UIC_IIC1 0x10000000 /* IIC */ -#define UIC_PIM 0x08000000 /* PCI inbound message */ -#define UIC_PCRW 0x04000000 /* PCI command register write */ -#define UIC_PPM 0x02000000 /* PCI power management */ -#define UIC_MSI0 0x01000000 /* PCI MSI level 0 */ -#define UIC_MSI1 0x00800000 /* PCI MSI level 1 */ -#define UIC_MSI2 0x00400000 /* PCI MSI level 2 */ -#define UIC_MTE 0x00200000 /* MAL TXEOB */ -#define UIC_MRE 0x00100000 /* MAL RXEOB */ -#define UIC_D0 0x00080000 /* DMA channel 0 */ -#define UIC_D1 0x00040000 /* DMA channel 1 */ -#define UIC_D2 0x00020000 /* DMA channel 2 */ -#define UIC_D3 0x00010000 /* DMA channel 3 */ -#define UIC_RSVD0 0x00008000 /* Reserved */ -#define UIC_RSVD1 0x00004000 /* Reserved */ -#define UIC_CT0 0x00002000 /* GPT compare timer 0 */ -#define UIC_CT1 0x00001000 /* GPT compare timer 1 */ -#define UIC_CT2 0x00000800 /* GPT compare timer 2 */ -#define UIC_CT3 0x00000400 /* GPT compare timer 3 */ -#define UIC_CT4 0x00000200 /* GPT compare timer 4 */ -#define UIC_EIR0 0x00000100 /* External interrupt 0 */ -#define UIC_EIR1 0x00000080 /* External interrupt 1 */ -#define UIC_EIR2 0x00000040 /* External interrupt 2 */ -#define UIC_EIR3 0x00000020 /* External interrupt 3 */ -#define UIC_EIR4 0x00000010 /* External interrupt 4 */ -#define UIC_EIR5 0x00000008 /* External interrupt 5 */ -#define UIC_EIR6 0x00000004 /* External interrupt 6 */ -#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */ -#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */ -#endif /* CONFIG_440GX */ - -/* For compatibility with 405 code */ -#define UIC_MAL_TXEOB UIC_MTE -#define UIC_MAL_RXEOB UIC_MRE - -/*---------------------------------------------------------------------------+ -| Universal interrupt controller 1 interrupts (UIC1) -+---------------------------------------------------------------------------*/ -#if defined(CONFIG_440SP) -#define UIC_EIR0 0x80000000 /* External interrupt 0 */ -#define UIC_MS 0x40000000 /* MAL SERR */ -#define UIC_MTDE 0x20000000 /* MAL TXDE */ -#define UIC_MRDE 0x10000000 /* MAL RXDE */ -#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */ -#define UIC_EBCO 0x04000000 /* EBCO interrupt status */ -#define UIC_MTE 0x02000000 /* MAL TXEOB */ -#define UIC_MRE 0x01000000 /* MAL RXEOB */ -#define UIC_P0MSI1 0x00800000 /* PCI0 MSI level 1 */ -#define UIC_P1MSI1 0x00400000 /* PCI1 MSI level 1 */ -#define UIC_P2MSI1 0x00200000 /* PCI2 MSI level 1 */ -#define UIC_L2C 0x00100000 /* L2 cache */ -#define UIC_CT0 0x00080000 /* GPT compare timer 0 */ -#define UIC_CT1 0x00040000 /* GPT compare timer 1 */ -#define UIC_CT2 0x00020000 /* GPT compare timer 2 */ -#define UIC_CT3 0x00010000 /* GPT compare timer 3 */ -#define UIC_CT4 0x00008000 /* GPT compare timer 4 */ -#define UIC_EIR1 0x00004000 /* External interrupt 1 */ -#define UIC_EIR2 0x00002000 /* External interrupt 2 */ -#define UIC_EIR3 0x00001000 /* External interrupt 3 */ -#define UIC_EIR4 0x00000800 /* External interrupt 4 */ -#define UIC_EIR5 0x00000400 /* External interrupt 5 */ -#define UIC_DMAE 0x00000200 /* DMA error */ -#define UIC_I2OE 0x00000100 /* I2O error */ -#define UIC_SRE 0x00000080 /* Serial ROM error */ -#define UIC_P0AE 0x00000040 /* PCI0 asynchronous error */ -#define UIC_P1AE 0x00000020 /* PCI1 asynchronous error */ -#define UIC_P2AE 0x00000010 /* PCI2 asynchronous error */ -#define UIC_ETH0 0x00000008 /* Ethernet 0 */ -#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ -#define UIC_ETH1 0x00000002 /* Reserved */ -#define UIC_XOR 0x00000001 /* XOR */ -#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) -#define UIC_MS 0x80000000 /* MAL SERR */ -#define UIC_MTDE 0x40000000 /* MAL TXDE */ -#define UIC_MRDE 0x20000000 /* MAL RXDE */ -#define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/ -#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */ -#define UIC_EBCO 0x04000000 /* EBCO interrupt status */ -#define UIC_EBMI 0x02000000 /* EBMI interrupt status */ -#define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */ -#define UIC_MSI3 0x00800000 /* PCI MSI level 3 */ -#define UIC_MSI4 0x00400000 /* PCI MSI level 4 */ -#define UIC_MSI5 0x00200000 /* PCI MSI level 5 */ -#define UIC_MSI6 0x00100000 /* PCI MSI level 6 */ -#define UIC_MSI7 0x00080000 /* PCI MSI level 7 */ -#define UIC_MSI8 0x00040000 /* PCI MSI level 8 */ -#define UIC_MSI9 0x00020000 /* PCI MSI level 9 */ -#define UIC_MSI10 0x00010000 /* PCI MSI level 10 */ -#define UIC_MSI11 0x00008000 /* PCI MSI level 11 */ -#define UIC_PPMI 0x00004000 /* PPM interrupt status */ -#define UIC_EIR7 0x00002000 /* External interrupt 7 */ -#define UIC_EIR8 0x00001000 /* External interrupt 8 */ -#define UIC_EIR9 0x00000800 /* External interrupt 9 */ -#define UIC_EIR10 0x00000400 /* External interrupt 10 */ -#define UIC_EIR11 0x00000200 /* External interrupt 11 */ -#define UIC_EIR12 0x00000100 /* External interrupt 12 */ -#define UIC_SRE 0x00000080 /* Serial ROM error */ -#define UIC_RSVD2 0x00000040 /* Reserved */ -#define UIC_RSVD3 0x00000020 /* Reserved */ -#define UIC_PAE 0x00000010 /* PCI asynchronous error */ -#define UIC_ETH0 0x00000008 /* Ethernet 0 */ -#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ -#define UIC_ETH1 0x00000002 /* Ethernet 1 */ -#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */ - -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) - -#define UIC_EIR2 0x80000000 /* External interrupt 2 */ -#define UIC_U0 0x40000000 /* UART 0 */ -#define UIC_SPI 0x20000000 /* SPI */ -#define UIC_TRNGAL 0x10000000 /* TRNG alarm */ -#define UIC_DEUE 0x08000000 /* DDR SDRAM ECC correct/uncorrectable error */ -#define UIC_EBCO 0x04000000 /* EBCO interrupt status */ -#define UIC_NDFC 0x02000000 /* NDFC */ -#define UIC_EIPPKPSE 0x01000000 /* EIPPKP slave error */ -#define UIC_P0MSI1 0x00800000 /* PCI0 MSI level 1 */ -#define UIC_P0MSI2 0x00400000 /* PCI0 MSI level 2 */ -#define UIC_P0MSI3 0x00200000 /* PCI0 MSI level 3 */ -#define UIC_L2C 0x00100000 /* L2 cache */ -#define UIC_CT0 0x00080000 /* GPT compare timer 0 */ -#define UIC_CT1 0x00040000 /* GPT compare timer 1 */ -#define UIC_CT2 0x00020000 /* GPT compare timer 2 */ -#define UIC_CT3 0x00010000 /* GPT compare timer 3 */ -#define UIC_CT4 0x00008000 /* GPT compare timer 4 */ -#define UIC_CT5 0x00004000 /* GPT compare timer 5 */ -#define UIC_CT6 0x00002000 /* GPT compare timer 6 */ -#define UIC_GPTDC 0x00001000 /* GPT decrementer pulse */ -#define UIC_EIR3 0x00000800 /* External interrupt 3 */ -#define UIC_EIR4 0x00000400 /* External interrupt 4 */ -#define UIC_DMAE 0x00000200 /* DMA error */ -#define UIC_I2OE 0x00000100 /* I2O error */ -#define UIC_SRE 0x00000080 /* Serial ROM error */ -#define UIC_P0AE 0x00000040 /* PCI0 asynchronous error */ -#define UIC_EIR5 0x00000020 /* External interrupt 5 */ -#define UIC_EIR6 0x00000010 /* External interrupt 6 */ -#define UIC_U2 0x00000008 /* UART 2 */ -#define UIC_U3 0x00000004 /* UART 3 */ -#define UIC_EIR7 0x00000002 /* External interrupt 7 */ -#define UIC_EIR8 0x00000001 /* External interrupt 8 */ - -#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - -#define UIC_MS 0x80000000 /* MAL SERR */ -#define UIC_MTDE 0x40000000 /* MAL TXDE */ -#define UIC_MRDE 0x20000000 /* MAL RXDE */ -#define UIC_U2 0x10000000 /* UART 2 */ -#define UIC_U3 0x08000000 /* UART 3 */ -#define UIC_EBCO 0x04000000 /* EBCO interrupt status */ -#define UIC_NDFC 0x02000000 /* NDFC */ -#define UIC_KSLE 0x01000000 /* KASUMI slave error */ -#define UIC_CT5 0x00800000 /* GPT compare timer 5 */ -#define UIC_CT6 0x00400000 /* GPT compare timer 6 */ -#define UIC_PLB34I0 0x00200000 /* PLB3X4X MIRQ0 */ -#define UIC_PLB34I1 0x00100000 /* PLB3X4X MIRQ1 */ -#define UIC_PLB34I2 0x00080000 /* PLB3X4X MIRQ2 */ -#define UIC_PLB34I3 0x00040000 /* PLB3X4X MIRQ3 */ -#define UIC_PLB34I4 0x00020000 /* PLB3X4X MIRQ4 */ -#define UIC_PLB34I5 0x00010000 /* PLB3X4X MIRQ5 */ -#define UIC_CT0 0x00008000 /* GPT compare timer 0 */ -#define UIC_CT1 0x00004000 /* GPT compare timer 1 */ -#define UIC_EIR7 0x00002000 /* External interrupt 7 */ -#define UIC_EIR8 0x00001000 /* External interrupt 8 */ -#define UIC_EIR9 0x00000800 /* External interrupt 9 */ -#define UIC_CT2 0x00000400 /* GPT compare timer 2 */ -#define UIC_CT3 0x00000200 /* GPT compare timer 3 */ -#define UIC_CT4 0x00000100 /* GPT compare timer 4 */ -#define UIC_SRE 0x00000080 /* Serial ROM error */ -#define UIC_GPTDC 0x00000040 /* GPT decrementer pulse */ -#define UIC_RSVD0 0x00000020 /* Reserved */ -#define UIC_EPCIPER 0x00000010 /* External PCI PERR */ -#define UIC_EIR0 0x00000008 /* External interrupt 0 */ -#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ -#define UIC_EIR1 0x00000002 /* External interrupt 1 */ -#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */ - -/* For compatibility with 405 code */ -#define UIC_MAL_SERR UIC_MS -#define UIC_MAL_TXDE UIC_MTDE -#define UIC_MAL_RXDE UIC_MRDE -#define UIC_ENET UIC_ETH0 - -#elif !defined(CONFIG_440SPE) -#define UIC_MS 0x80000000 /* MAL SERR */ -#define UIC_MTDE 0x40000000 /* MAL TXDE */ -#define UIC_MRDE 0x20000000 /* MAL RXDE */ -#define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/ -#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */ -#define UIC_EBCO 0x04000000 /* EBCO interrupt status */ -#define UIC_EBMI 0x02000000 /* EBMI interrupt status */ -#define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */ -#define UIC_MSI3 0x00800000 /* PCI MSI level 3 */ -#define UIC_MSI4 0x00400000 /* PCI MSI level 4 */ -#define UIC_MSI5 0x00200000 /* PCI MSI level 5 */ -#define UIC_MSI6 0x00100000 /* PCI MSI level 6 */ -#define UIC_MSI7 0x00080000 /* PCI MSI level 7 */ -#define UIC_MSI8 0x00040000 /* PCI MSI level 8 */ -#define UIC_MSI9 0x00020000 /* PCI MSI level 9 */ -#define UIC_MSI10 0x00010000 /* PCI MSI level 10 */ -#define UIC_MSI11 0x00008000 /* PCI MSI level 11 */ -#define UIC_PPMI 0x00004000 /* PPM interrupt status */ -#define UIC_EIR7 0x00002000 /* External interrupt 7 */ -#define UIC_EIR8 0x00001000 /* External interrupt 8 */ -#define UIC_EIR9 0x00000800 /* External interrupt 9 */ -#define UIC_EIR10 0x00000400 /* External interrupt 10 */ -#define UIC_EIR11 0x00000200 /* External interrupt 11 */ -#define UIC_EIR12 0x00000100 /* External interrupt 12 */ -#define UIC_SRE 0x00000080 /* Serial ROM error */ -#define UIC_RSVD2 0x00000040 /* Reserved */ -#define UIC_RSVD3 0x00000020 /* Reserved */ -#define UIC_PAE 0x00000010 /* PCI asynchronous error */ -#define UIC_ETH0 0x00000008 /* Ethernet 0 */ -#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ -#define UIC_ETH1 0x00000002 /* Ethernet 1 */ -#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */ -#endif /* CONFIG_440SP */ - -/* For compatibility with 405 code */ -#define UIC_MAL_SERR UIC_MS -#define UIC_MAL_TXDE UIC_MTDE -#define UIC_MAL_RXDE UIC_MRDE -#define UIC_ENET UIC_ETH0 - -/*---------------------------------------------------------------------------+ -| Universal interrupt controller 2 interrupts (UIC2) -+---------------------------------------------------------------------------*/ -#if defined(CONFIG_440GX) -#define UIC_ETH2 0x80000000 /* Ethernet 2 */ -#define UIC_EWU2 0x40000000 /* Ethernet 2 wakeup */ -#define UIC_ETH3 0x20000000 /* Ethernet 3 */ -#define UIC_EWU3 0x10000000 /* Ethernet 3 wakeup */ -#define UIC_TAH0 0x08000000 /* TAH 0 */ -#define UIC_TAH1 0x04000000 /* TAH 1 */ -#define UIC_IMUOBFQ 0x02000000 /* IMU outbound free queue */ -#define UIC_IMUIBPQ 0x01000000 /* IMU inbound post queue */ -#define UIC_IMUIRQDB 0x00800000 /* IMU irq doorbell */ -#define UIC_IMUIBDB 0x00400000 /* IMU inbound doorbell */ -#define UIC_IMUMSG0 0x00200000 /* IMU inbound message 0 */ -#define UIC_IMUMSG1 0x00100000 /* IMU inbound message 1 */ -#define UIC_IMUTO 0x00080000 /* IMU timeout */ -#define UIC_MSI12 0x00040000 /* PCI MSI level 12 */ -#define UIC_MSI13 0x00020000 /* PCI MSI level 13 */ -#define UIC_MSI14 0x00010000 /* PCI MSI level 14 */ -#define UIC_MSI15 0x00008000 /* PCI MSI level 15 */ -#define UIC_EIR13 0x00004000 /* External interrupt 13 */ -#define UIC_EIR14 0x00002000 /* External interrupt 14 */ -#define UIC_EIR15 0x00001000 /* External interrupt 15 */ -#define UIC_EIR16 0x00000800 /* External interrupt 16 */ -#define UIC_EIR17 0x00000400 /* External interrupt 17 */ -#define UIC_PCIVPD 0x00000200 /* PCI VPD */ -#define UIC_L2C 0x00000100 /* L2 Cache */ -#define UIC_ETH2PCS 0x00000080 /* Ethernet 2 PCS */ -#define UIC_ETH3PCS 0x00000040 /* Ethernet 3 PCS */ -#define UIC_RSVD26 0x00000020 /* Reserved */ -#define UIC_RSVD27 0x00000010 /* Reserved */ -#define UIC_RSVD28 0x00000008 /* Reserved */ -#define UIC_RSVD29 0x00000004 /* Reserved */ -#define UIC_RSVD30 0x00000002 /* Reserved */ -#define UIC_RSVD31 0x00000001 /* Reserved */ - -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) - -#define UIC_TAH0 0x80000000 /* TAHOE 0 */ -#define UIC_TAH1 0x40000000 /* TAHOE 1 */ -#define UIC_EIR9 0x20000000 /* External interrupt 9 */ -#define UIC_MS 0x10000000 /* MAL SERR */ -#define UIC_MTDE 0x08000000 /* MAL TXDE */ -#define UIC_MRDE 0x04000000 /* MAL RXDE */ -#define UIC_MTE 0x02000000 /* MAL TXEOB */ -#define UIC_MRE 0x01000000 /* MAL RXEOB */ -#define UIC_MCTX0 0x00800000 /* MAL interrupt coalescence TX0 */ -#define UIC_MCTX1 0x00400000 /* MAL interrupt coalescence TX1 */ -#define UIC_MCTX2 0x00200000 /* MAL interrupt coalescence TX2 */ -#define UIC_MCTX3 0x00100000 /* MAL interrupt coalescence TX3 */ -#define UIC_MCTR0 0x00080000 /* MAL interrupt coalescence TR0 */ -#define UIC_MCTR1 0x00040000 /* MAL interrupt coalescence TR1 */ -#define UIC_MCTR2 0x00020000 /* MAL interrupt coalescence TR2 */ -#define UIC_MCTR3 0x00010000 /* MAL interrupt coalescence TR3 */ -#define UIC_ETH0 0x00008000 /* Ethernet 0 */ -#define UIC_ETH1 0x00004000 /* Ethernet 1 */ -#define UIC_ETH2 0x00002000 /* Ethernet 2 */ -#define UIC_ETH3 0x00001000 /* Ethernet 3 */ -#define UIC_EWU0 0x00000800 /* Ethernet 0 wakeup */ -#define UIC_EWU1 0x00000400 /* Ethernet 1 wakeup */ -#define UIC_EWU2 0x00000200 /* Ethernet 2 wakeup */ -#define UIC_EWU3 0x00000100 /* Ethernet 3 wakeup */ -#define UIC_EIR10 0x00000080 /* External interrupt 10 */ -#define UIC_EIR11 0x00000040 /* External interrupt 11 */ -#define UIC_RSVD2 0x00000020 /* Reserved */ -#define UIC_PLB4XAHB 0x00000010 /* PLB4XAHB / AHBARB error */ -#define UIC_OTG 0x00000008 /* USB2.0 OTG */ -#define UIC_EHCI 0x00000004 /* USB2.0 Host EHCI */ -#define UIC_OHCI 0x00000002 /* USB2.0 Host OHCI */ -#define UIC_OHCISMI 0x00000001 /* USB2.0 Host OHCI SMI */ - -#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* UIC2 */ - -#define UIC_EIR5 0x80000000 /* External interrupt 5 */ -#define UIC_EIR6 0x40000000 /* External interrupt 6 */ -#define UIC_OPB 0x20000000 /* OPB to PLB bridge interrupt stat */ -#define UIC_EIR2 0x10000000 /* External interrupt 2 */ -#define UIC_EIR3 0x08000000 /* External interrupt 3 */ -#define UIC_DDR2 0x04000000 /* DDR2 sdram */ -#define UIC_MCTX0 0x02000000 /* MAl intp coalescence TX0 */ -#define UIC_MCTX1 0x01000000 /* MAl intp coalescence TX1 */ -#define UIC_MCTR0 0x00800000 /* MAl intp coalescence TR0 */ -#define UIC_MCTR1 0x00400000 /* MAl intp coalescence TR1 */ - -#endif /* CONFIG_440GX */ - -/*---------------------------------------------------------------------------+ -| Universal interrupt controller Base 0 interrupts (UICB0) -+---------------------------------------------------------------------------*/ -#if defined(CONFIG_440GX) -#define UICB0_UIC0CI 0x80000000 /* UIC0 Critical Interrupt */ -#define UICB0_UIC0NCI 0x40000000 /* UIC0 Noncritical Interrupt */ -#define UICB0_UIC1CI 0x20000000 /* UIC1 Critical Interrupt */ -#define UICB0_UIC1NCI 0x10000000 /* UIC1 Noncritical Interrupt */ -#define UICB0_UIC2CI 0x08000000 /* UIC2 Critical Interrupt */ -#define UICB0_UIC2NCI 0x04000000 /* UIC2 Noncritical Interrupt */ - -#define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \ - UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI) - -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) - -#define UICB0_UIC1NCI 0x00000002 /* UIC1 Noncritical Interrupt */ -#define UICB0_UIC1CI 0x00000001 /* UIC1 Critical Interrupt */ -#define UICB0_UIC2NCI 0x00200000 /* UIC2 Noncritical Interrupt */ -#define UICB0_UIC2CI 0x00100000 /* UIC2 Critical Interrupt */ -#define UICB0_UIC3NCI 0x00008000 /* UIC3 Noncritical Interrupt */ -#define UICB0_UIC3CI 0x00004000 /* UIC3 Critical Interrupt */ - -#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \ - UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI) - -#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - -#define UICB0_UIC1CI 0x00000001 /* UIC1 Critical Interrupt */ -#define UICB0_UIC1NCI 0x00000002 /* UIC1 Noncritical Interrupt */ -#define UICB0_UIC2CI 0x00000004 /* UIC2 Critical Interrupt */ -#define UICB0_UIC2NCI 0x00000008 /* UIC2 Noncritical Interrupt */ - -#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | \ - UICB0_UIC1CI | UICB0_UIC2NCI) - -#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \ - defined(CONFIG_440EP) || defined(CONFIG_440GR) - -#define UICB0_UIC1CI 0x00000001 /* UIC1 Critical Interrupt */ -#define UICB0_UIC1NCI 0x00000002 /* UIC1 Noncritical Interrupt */ - -#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI) - -#endif /* CONFIG_440GX */ -/*---------------------------------------------------------------------------+ -| Universal interrupt controller interrupts -+---------------------------------------------------------------------------*/ -#if defined(CONFIG_440SPE) -/*#define UICB0_UIC0CI 0x80000000*/ /* UIC0 Critical Interrupt */ -/*#define UICB0_UIC0NCI 0x40000000*/ /* UIC0 Noncritical Interrupt */ -#define UICB0_UIC1CI 0x00000002 /* UIC1 Critical Interrupt */ -#define UICB0_UIC1NCI 0x00000001 /* UIC1 Noncritical Interrupt */ -#define UICB0_UIC2CI 0x00200000 /* UIC2 Critical Interrupt */ -#define UICB0_UIC2NCI 0x00100000 /* UIC2 Noncritical Interrupt */ -#define UICB0_UIC3CI 0x00008000 /* UIC3 Critical Interrupt */ -#define UICB0_UIC3NCI 0x00004000 /* UIC3 Noncritical Interrupt */ - -#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \ - UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI) -/*---------------------------------------------------------------------------+ -| Universal interrupt controller 0 interrupts (UIC0) -+---------------------------------------------------------------------------*/ -#define UIC_U0 0x80000000 /* UART 0 */ -#define UIC_U1 0x40000000 /* UART 1 */ -#define UIC_IIC0 0x20000000 /* IIC */ -#define UIC_IIC1 0x10000000 /* IIC */ -#define UIC_PIM 0x08000000 /* PCI inbound message */ -#define UIC_PCRW 0x04000000 /* PCI command register write */ -#define UIC_PPM 0x02000000 /* PCI power management */ -#define UIC_PVPDA 0x01000000 /* PCIx 0 vpd access */ -#define UIC_MSI0 0x00800000 /* PCIx MSI level 0 */ -#define UIC_EIR15 0x00400000 /* External intp 15 */ -#define UIC_PEMSI0 0x00080000 /* PCIe MSI level 0 */ -#define UIC_PEMSI1 0x00040000 /* PCIe MSI level 1 */ -#define UIC_PEMSI2 0x00020000 /* PCIe MSI level 2 */ -#define UIC_PEMSI3 0x00010000 /* PCIe MSI level 3 */ -#define UIC_EIR14 0x00002000 /* External interrupt 14 */ -#define UIC_D0CPFF 0x00001000 /* DMA0 cp fifo full */ -#define UIC_D0CSNS 0x00000800 /* DMA0 cs fifo needs service */ -#define UIC_D1CPFF 0x00000400 /* DMA1 cp fifo full */ -#define UIC_D1CSNS 0x00000200 /* DMA1 cs fifo needs service */ -#define UIC_I2OID 0x00000100 /* I2O inbound door bell */ -#define UIC_I2OLNE 0x00000080 /* I2O Inbound Post List FIFO Not Empty */ -#define UIC_I20R0LL 0x00000040 /* I2O Region 0 Low Latency PLB Write */ -#define UIC_I2OR1LL 0x00000020 /* I2O Region 1 Low Latency PLB Write */ -#define UIC_I20R0HB 0x00000010 /* I2O Region 0 High Bandwidth PLB Write */ -#define UIC_I2OR1HB 0x00000008 /* I2O Region 1 High Bandwidth PLB Write */ -#define UIC_CPTCNT 0x00000004 /* GPT Count Timer */ -/*---------------------------------------------------------------------------+ -| Universal interrupt controller 1 interrupts (UIC1) -+---------------------------------------------------------------------------*/ -#define UIC_EIR13 0x80000000 /* externei intp 13 */ -#define UIC_MS 0x40000000 /* MAL SERR */ -#define UIC_MTDE 0x20000000 /* MAL TXDE */ -#define UIC_MRDE 0x10000000 /* MAL RXDE */ -#define UIC_DEUE 0x08000000 /* DDR SDRAM ECC correct/uncorrectable error */ -#define UIC_EBCO 0x04000000 /* EBCO interrupt status */ -#define UIC_MTE 0x02000000 /* MAL TXEOB */ -#define UIC_MRE 0x01000000 /* MAL RXEOB */ -#define UIC_MSI1 0x00800000 /* PCI MSI level 1 */ -#define UIC_MSI2 0x00400000 /* PCI MSI level 2 */ -#define UIC_MSI3 0x00200000 /* PCI MSI level 3 */ -#define UIC_L2C 0x00100000 /* L2 cache */ -#define UIC_CT0 0x00080000 /* GPT compare timer 0 */ -#define UIC_CT1 0x00040000 /* GPT compare timer 1 */ -#define UIC_CT2 0x00020000 /* GPT compare timer 2 */ -#define UIC_CT3 0x00010000 /* GPT compare timer 3 */ -#define UIC_CT4 0x00008000 /* GPT compare timer 4 */ -#define UIC_EIR12 0x00004000 /* External interrupt 12 */ -#define UIC_EIR11 0x00002000 /* External interrupt 11 */ -#define UIC_EIR10 0x00001000 /* External interrupt 10 */ -#define UIC_EIR9 0x00000800 /* External interrupt 9 */ -#define UIC_EIR8 0x00000400 /* External interrupt 8 */ -#define UIC_DMAE 0x00000200 /* dma error */ -#define UIC_I2OE 0x00000100 /* i2o error */ -#define UIC_SRE 0x00000080 /* Serial ROM error */ -#define UIC_PCIXAE 0x00000040 /* Pcix0 async error */ -#define UIC_EIR7 0x00000020 /* External interrupt 7 */ -#define UIC_EIR6 0x00000010 /* External interrupt 6 */ -#define UIC_ETH0 0x00000008 /* Ethernet 0 */ -#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */ -#define UIC_ETH1 0x00000002 /* reserved */ -#define UIC_XOR 0x00000001 /* xor */ - -/*---------------------------------------------------------------------------+ -| Universal interrupt controller 2 interrupts (UIC2) -+---------------------------------------------------------------------------*/ -#define UIC_PEOAL 0x80000000 /* PE0 AL */ -#define UIC_PEOVA 0x40000000 /* PE0 VPD access */ -#define UIC_PEOHRR 0x20000000 /* PE0 Host reset request rising */ -#define UIC_PE0HRF 0x10000000 /* PE0 Host reset request falling */ -#define UIC_PE0TCR 0x08000000 /* PE0 TCR */ -#define UIC_PE0BVCO 0x04000000 /* PE0 Busmaster VCO */ -#define UIC_PE0DCRE 0x02000000 /* PE0 DCR error */ -#define UIC_PE1AL 0x00800000 /* PE1 AL */ -#define UIC_PE1VA 0x00400000 /* PE1 VPD access */ -#define UIC_PE1HRR 0x00200000 /* PE1 Host reset request rising */ -#define UIC_PE1HRF 0x00100000 /* PE1 Host reset request falling */ -#define UIC_PE1TCR 0x00080000 /* PE1 TCR */ -#define UIC_PE1BVCO 0x00040000 /* PE1 Busmaster VCO */ -#define UIC_PE1DCRE 0x00020000 /* PE1 DCR error */ -#define UIC_PE2AL 0x00008000 /* PE2 AL */ -#define UIC_PE2VA 0x00004000 /* PE2 VPD access */ -#define UIC_PE2HRR 0x00002000 /* PE2 Host reset request rising */ -#define UIC_PE2HRF 0x00001000 /* PE2 Host reset request falling */ -#define UIC_PE2TCR 0x00000800 /* PE2 TCR */ -#define UIC_PE2BVCO 0x00000400 /* PE2 Busmaster VCO */ -#define UIC_PE2DCRE 0x00000200 /* PE2 DCR error */ -#define UIC_EIR5 0x00000080 /* External interrupt 5 */ -#define UIC_EIR4 0x00000040 /* External interrupt 4 */ -#define UIC_EIR3 0x00000020 /* External interrupt 3 */ -#define UIC_EIR2 0x00000010 /* External interrupt 2 */ -#define UIC_EIR1 0x00000008 /* External interrupt 1 */ -#define UIC_EIR0 0x00000004 /* External interrupt 0 */ -#endif /* CONFIG_440SPE */ - -/*-----------------------------------------------------------------------------+ -| External Bus Controller Bit Settings -+-----------------------------------------------------------------------------*/ -#define EBC_CFGADDR_MASK 0x0000003F - -#define EBC_BXCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0) -#define EBC_BXCR_BS_MASK 0x000E0000 -#define EBC_BXCR_BS_1MB 0x00000000 -#define EBC_BXCR_BS_2MB 0x00020000 -#define EBC_BXCR_BS_4MB 0x00040000 -#define EBC_BXCR_BS_8MB 0x00060000 -#define EBC_BXCR_BS_16MB 0x00080000 -#define EBC_BXCR_BS_32MB 0x000A0000 -#define EBC_BXCR_BS_64MB 0x000C0000 -#define EBC_BXCR_BS_128MB 0x000E0000 -#define EBC_BXCR_BU_MASK 0x00018000 -#define EBC_BXCR_BU_R 0x00008000 -#define EBC_BXCR_BU_W 0x00010000 -#define EBC_BXCR_BU_RW 0x00018000 -#define EBC_BXCR_BW_MASK 0x00006000 -#define EBC_BXCR_BW_8BIT 0x00000000 -#define EBC_BXCR_BW_16BIT 0x00002000 -#define EBC_BXCR_BW_32BIT 0x00006000 -#define EBC_BXAP_BME_ENABLED 0x80000000 -#define EBC_BXAP_BME_DISABLED 0x00000000 -#define EBC_BXAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) -#define EBC_BXAP_BCE_DISABLE 0x00000000 -#define EBC_BXAP_BCE_ENABLE 0x00400000 -#define EBC_BXAP_BCT_MASK 0x00300000 -#define EBC_BXAP_BCT_2TRANS 0x00000000 -#define EBC_BXAP_BCT_4TRANS 0x00100000 -#define EBC_BXAP_BCT_8TRANS 0x00200000 -#define EBC_BXAP_BCT_16TRANS 0x00300000 -#define EBC_BXAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) -#define EBC_BXAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) -#define EBC_BXAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) -#define EBC_BXAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) -#define EBC_BXAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) -#define EBC_BXAP_RE_ENABLED 0x00000100 -#define EBC_BXAP_RE_DISABLED 0x00000000 -#define EBC_BXAP_SOR_DELAYED 0x00000000 -#define EBC_BXAP_SOR_NONDELAYED 0x00000080 -#define EBC_BXAP_BEM_WRITEONLY 0x00000000 -#define EBC_BXAP_BEM_RW 0x00000040 -#define EBC_BXAP_PEN_DISABLED 0x00000000 - -#define EBC_CFG_LE_MASK 0x80000000 -#define EBC_CFG_LE_UNLOCK 0x00000000 -#define EBC_CFG_LE_LOCK 0x80000000 -#define EBC_CFG_PTD_MASK 0x40000000 -#define EBC_CFG_PTD_ENABLE 0x00000000 -#define EBC_CFG_PTD_DISABLE 0x40000000 -#define EBC_CFG_RTC_MASK 0x38000000 -#define EBC_CFG_RTC_16PERCLK 0x00000000 -#define EBC_CFG_RTC_32PERCLK 0x08000000 -#define EBC_CFG_RTC_64PERCLK 0x10000000 -#define EBC_CFG_RTC_128PERCLK 0x18000000 -#define EBC_CFG_RTC_256PERCLK 0x20000000 -#define EBC_CFG_RTC_512PERCLK 0x28000000 -#define EBC_CFG_RTC_1024PERCLK 0x30000000 -#define EBC_CFG_RTC_2048PERCLK 0x38000000 -#define EBC_CFG_ATC_MASK 0x04000000 -#define EBC_CFG_ATC_HI 0x00000000 -#define EBC_CFG_ATC_PREVIOUS 0x04000000 -#define EBC_CFG_DTC_MASK 0x02000000 -#define EBC_CFG_DTC_HI 0x00000000 -#define EBC_CFG_DTC_PREVIOUS 0x02000000 -#define EBC_CFG_CTC_MASK 0x01000000 -#define EBC_CFG_CTC_HI 0x00000000 -#define EBC_CFG_CTC_PREVIOUS 0x01000000 -#define EBC_CFG_OEO_MASK 0x00800000 -#define EBC_CFG_OEO_HI 0x00000000 -#define EBC_CFG_OEO_PREVIOUS 0x00800000 -#define EBC_CFG_EMC_MASK 0x00400000 -#define EBC_CFG_EMC_NONDEFAULT 0x00000000 -#define EBC_CFG_EMC_DEFAULT 0x00400000 -#define EBC_CFG_PME_MASK 0x00200000 -#define EBC_CFG_PME_DISABLE 0x00000000 -#define EBC_CFG_PME_ENABLE 0x00200000 -#define EBC_CFG_PMT_MASK 0x001F0000 -#define EBC_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12) -#define EBC_CFG_PR_MASK 0x0000C000 -#define EBC_CFG_PR_16 0x00000000 -#define EBC_CFG_PR_32 0x00004000 -#define EBC_CFG_PR_64 0x00008000 -#define EBC_CFG_PR_128 0x0000C000 - /*-----------------------------------------------------------------------------+ | SDR0 Bit Settings +-----------------------------------------------------------------------------*/ @@ -1855,7 +887,7 @@ #define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF) #endif -#if defined(CONFIG_440SPE) +#if defined(CONFIG_440SPE) || defined(CONFIG_460SX) #define SDR0_CP440 0x0180 #define SDR0_CP440_ERPN_MASK 0x30000000 #define SDR0_CP440_ERPN_MASK_HI 0x3000 @@ -2793,7 +1825,8 @@ /*-----------------------------------------------------------------------------+ | Clocking +-----------------------------------------------------------------------------*/ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) #define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */ #define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */ #define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */ @@ -2873,118 +1906,10 @@ #endif /* CONFIG_440GX */ #if defined (CONFIG_440EPX) || defined (CONFIG_440GRX) -/*--------------------------------------*/ -#define CPR0_PLLC 0x40 -#define CPR0_PLLC_RST_MASK 0x80000000 -#define CPR0_PLLC_RST_PLLLOCKED 0x00000000 -#define CPR0_PLLC_RST_PLLRESET 0x80000000 -#define CPR0_PLLC_ENG_MASK 0x40000000 -#define CPR0_PLLC_ENG_DISABLE 0x00000000 -#define CPR0_PLLC_ENG_ENABLE 0x40000000 -#define CPR0_PLLC_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) -#define CPR0_PLLC_ENG_DECODE(n) ((((unsigned long)(n))>>30)&0x01) -#define CPR0_PLLC_SRC_MASK 0x20000000 -#define CPR0_PLLC_SRC_PLLOUTA 0x00000000 -#define CPR0_PLLC_SRC_PLLOUTB 0x20000000 -#define CPR0_PLLC_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) -#define CPR0_PLLC_SRC_DECODE(n) ((((unsigned long)(n))>>29)&0x01) -#define CPR0_PLLC_SEL_MASK 0x07000000 -#define CPR0_PLLC_SEL_PLL 0x00000000 -#define CPR0_PLLC_SEL_CPU 0x01000000 -#define CPR0_PLLC_SEL_PER 0x05000000 -#define CPR0_PLLC_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) -#define CPR0_PLLC_SEL_DECODE(n) ((((unsigned long)(n))>>24)&0x07) -#define CPR0_PLLC_TUNE_MASK 0x000003FF -#define CPR0_PLLC_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) -#define CPR0_PLLC_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) -/*--------------------------------------*/ -#define CPR0_PLLD 0x60 -#define CPR0_PLLD_FBDV_MASK 0x1F000000 -#define CPR0_PLLD_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) -#define CPR0_PLLD_FBDV_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x1F)+1) -#define CPR0_PLLD_FWDVA_MASK 0x000F0000 -#define CPR0_PLLD_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<16) -#define CPR0_PLLD_FWDVA_DECODE(n) ((((((unsigned long)(n))>>16)-1)&0x0F)+1) -#define CPR0_PLLD_FWDVB_MASK 0x00000700 -#define CPR0_PLLD_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<8) -#define CPR0_PLLD_FWDVB_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x07)+1) -#define CPR0_PLLD_LFBDV_MASK 0x0000003F -#define CPR0_PLLD_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0) -#define CPR0_PLLD_LFBDV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1) -/*--------------------------------------*/ -#define CPR0_PRIMAD 0x80 -#define CPR0_PRIMAD_PRADV0_MASK 0x07000000 -#define CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) -#define CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1) -/*--------------------------------------*/ -#define CPR0_PRIMBD 0xA0 -#define CPR0_PRIMBD_PRBDV0_MASK 0x07000000 -#define CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) -#define CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1) -/*--------------------------------------*/ -#if 0 -#define CPR0_CPM0_ER 0xB0 /* CPM Enable Register */ -#define CPR0_CPM0_FR 0xB1 /* CPM Force Register */ -#define CPR0_CPM0_SR 0xB2 /* CPM Status Register */ -#define CPR0_CPM0_IIC0 0x80000000 /* Inter-Intergrated Circuit0 */ -#define CPR0_CPM0_IIC1 0x40000000 /* Inter-Intergrated Circuit1 */ -#define CPR0_CPM0_PCI 0x20000000 /* Peripheral Component Interconnect */ -#define CPR0_CPM0_USB1H 0x08000000 /* USB1.1 Host */ -#define CPR0_CPM0_FPU 0x04000000 /* PPC440 FPU */ -#define CPR0_CPM0_CPU 0x02000000 /* PPC440x5 Processor Core */ -#define CPR0_CPM0_DMA 0x01000000 /* Direct Memory Access Controller */ -#define CPR0_CPM0_BGO 0x00800000 /* PLB to OPB Bridge */ -#define CPR0_CPM0_BGI 0x00400000 /* OPB to PLB Bridge */ -#define CPR0_CPM0_EBC 0x00200000 /* External Bus Controller */ -#define CPR0_CPM0_NDFC 0x00100000 /* Nand Flash Controller */ -#define CPR0_CPM0_MADMAL 0x00080000 /* DDR SDRAM Controller or MADMAL ??? */ -#define CPR0_CPM0_DMC 0x00080000 /* DDR SDRAM Controller or MADMAL ??? */ -#define CPR0_CPM0_PLB4 0x00040000 /* PLB4 Arbiter */ -#define CPR0_CPM0_PLB4x3x 0x00020000 /* PLB4 to PLB3 */ -#define CPR0_CPM0_PLB3x4x 0x00010000 /* PLB3 to PLB4 */ -#define CPR0_CPM0_PLB3 0x00008000 /* PLB3 Arbiter */ -#define CPR0_CPM0_PPM 0x00002000 /* PLB Performance Monitor */ -#define CPR0_CPM0_UIC1 0x00001000 /* Universal Interrupt Controller 1 */ -#define CPR0_CPM0_GPIO 0x00000800 /* General Purpose IO */ -#define CPR0_CPM0_GPT 0x00000400 /* General Purpose Timer */ -#define CPR0_CPM0_UART0 0x00000200 /* Universal Asynchronous Rcver/Xmitter 0 */ -#define CPR0_CPM0_UART1 0x00000100 /* Universal Asynchronous Rcver/Xmitter 1 */ -#define CPR0_CPM0_UIC0 0x00000080 /* Universal Interrupt Controller 0 */ -#define CPR0_CPM0_TMRCLK 0x00000040 /* CPU Timer */ -#define CPR0_CPM0_EMC0 0x00000020 /* Ethernet 0 */ -#define CPR0_CPM0_EMC1 0x00000010 /* Ethernet 1 */ -#define CPR0_CPM0_UART2 0x00000008 /* Universal Asynchronous Rcver/Xmitter 2 */ -#define CPR0_CPM0_UART3 0x00000004 /* Universal Asynchronous Rcver/Xmitter 3 */ -#define CPR0_CPM0_USB2D 0x00000002 /* USB2.0 Device */ -#define CPR0_CPM0_USB2H 0x00000001 /* USB2.0 Host */ +#define CPR0_ICFG_RLI_MASK 0x80000000 +#define CPR0_SPCID_SPCIDV0_MASK 0x03000000 +#define CPR0_PERD_PERDV0_MASK 0x07000000 #endif -/*--------------------------------------*/ -#define CPR0_OPBD 0xC0 -#define CPR0_OPBD_OPBDV0_MASK 0x03000000 -#define CPR0_OPBD_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) -#define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) -/*--------------------------------------*/ -#define CPR0_PERD 0xE0 -#define CPR0_PERD_PERDV0_MASK 0x07000000 -#define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24) -#define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1) -/*--------------------------------------*/ -#define CPR0_MALD 0x100 -#define CPR0_MALD_MALDV0_MASK 0x03000000 -#define CPR0_MALD_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) -#define CPR0_MALD_MALDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) -/*--------------------------------------*/ -#define CPR0_SPCID 0x120 -#define CPR0_SPCID_SPCIDV0_MASK 0x03000000 -#define CPR0_SPCID_SPCIDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) -#define CPR0_SPCID_SPCIDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) -/*--------------------------------------*/ -#define CPR0_ICFG 0x140 -#define CPR0_ICFG_RLI_MASK 0x80000000 -#define CPR0_ICFG_RLI_RESETCPR 0x00000000 -#define CPR0_ICFG_RLI_PRESERVECPR 0x80000000 -#define CPR0_ICFG_ICS_MASK 0x00000007 -#endif /* defined (CONFIG_440EPX) || defined (CONFIG_440GRX) */ /*----------------------------------------------------------------------------- | IIC Register Offsets @@ -3006,20 +1931,6 @@ #define IICDIRECTCNTL 0x10 /*----------------------------------------------------------------------------- -| UART Register Offsets -'----------------------------------------------------------------------------*/ -#define DATA_REG 0x00 -#define DL_LSB 0x00 -#define DL_MSB 0x01 -#define INT_ENABLE 0x01 -#define FIFO_CONTROL 0x02 -#define LINE_CONTROL 0x03 -#define MODEM_CONTROL 0x04 -#define LINE_STATUS 0x05 -#define MODEM_STATUS 0x06 -#define SCRATCH 0x07 - -/*----------------------------------------------------------------------------- | PCI Internal Registers et. al. (accessed via plb) +----------------------------------------------------------------------------*/ #define PCIX0_CFGADR (CFG_PCI_BASE + 0x0ec00000) @@ -3145,7 +2056,8 @@ * GPIO macro register defines ******************************************************************************/ #if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460SX) #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700) #define GPIO0_OR (GPIO0_BASE+0x0) diff --git a/include/ppc4xx.h b/include/ppc4xx.h index 1d06da8779..c71da60844 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -41,7 +41,8 @@ #if defined(CONFIG_405EX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) #define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ #endif @@ -58,6 +59,10 @@ #endif #include <asm/ppc4xx-sdram.h> +#include <asm/ppc4xx-ebc.h> +#if !defined(CONFIG_XILINX_440) +#include <asm/ppc4xx-uic.h> +#endif /* * Macro for generating register field mnemonics diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h index 4c97b36c05..b74c6fcafd 100644 --- a/include/ppc4xx_enet.h +++ b/include/ppc4xx_enet.h @@ -153,6 +153,20 @@ typedef struct emac_4xx_hw_st { #define SDR0_PFC1_EM_1000 (0x00200000) #endif +/* + * XMII bridge configurations for those systems (e.g. 405EX(r)) that do + * not have a pin function control (PFC) register to otherwise determine + * the bridge configuration. + */ +#define EMAC_PHY_MODE_NONE 0 +#define EMAC_PHY_MODE_NONE_RGMII 1 +#define EMAC_PHY_MODE_RGMII_NONE 2 +#define EMAC_PHY_MODE_RGMII_RGMII 3 +#define EMAC_PHY_MODE_NONE_GMII 4 +#define EMAC_PHY_MODE_GMII_NONE 5 +#define EMAC_PHY_MODE_NONE_MII 6 +#define EMAC_PHY_MODE_MII_NONE 7 + /* ZMII Bridge Register addresses */ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ @@ -218,12 +232,12 @@ typedef struct emac_4xx_hw_st { #endif /* RGMII Function Enable (FER) Register Bit Definitions */ -/* Note: for EMAC 2 and 3 only, 440GX only */ #define RGMII_FER_DIS (0x00) #define RGMII_FER_RTBI (0x04) #define RGMII_FER_RGMII (0x05) #define RGMII_FER_TBI (0x06) #define RGMII_FER_GMII (0x07) +#define RGMII_FER_MII (RGMII_FER_GMII) #define RGMII_FER_V(__x) ((__x - 2) * 4) |