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-rw-r--r--include/configs/CATcenter.h19
-rw-r--r--include/configs/CPU86.h2
-rw-r--r--include/configs/IDS8247.h1
-rw-r--r--include/configs/NC650.h2
-rw-r--r--include/configs/NETTA.h1
-rw-r--r--include/configs/RBC823.h2
-rw-r--r--include/configs/VCMA9.h1
-rw-r--r--include/configs/delta.h3
-rw-r--r--include/configs/omap2420h4.h1
-rw-r--r--include/configs/stxxtc.h1
-rw-r--r--include/linux/mtd/doc2000.h65
11 files changed, 84 insertions, 14 deletions
diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h
index ffe89cb78f..7ec4599ebb 100644
--- a/include/configs/CATcenter.h
+++ b/include/configs/CATcenter.h
@@ -193,6 +193,8 @@
*/
#define CFG_NAND0_BASE 0xFF400000
#define CFG_NAND1_BASE 0xFF000000
+#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }
+#define NAND_BIG_DELAY_US 25
/* For CATcenter there is only NAND on the module */
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
@@ -218,9 +220,9 @@
#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
-#define NAND_DISABLE_CE(nand) do \
+#define MACRO_NAND_DISABLE_CE(nandptr) do \
{ \
- switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
+ switch((unsigned long)nandptr) \
{ \
case CFG_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
@@ -231,9 +233,9 @@
} \
} while(0)
-#define NAND_ENABLE_CE(nand) do \
+#define MACRO_NAND_ENABLE_CE(nandptr) do \
{ \
- switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
+ switch((unsigned long)nandptr) \
{ \
case CFG_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
@@ -244,8 +246,7 @@
} \
} while(0)
-
-#define NAND_CTL_CLRALE(nandptr) do \
+#define MACRO_NAND_CTL_CLRALE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
{ \
@@ -258,7 +259,7 @@
} \
} while(0)
-#define NAND_CTL_SETALE(nandptr) do \
+#define MACRO_NAND_CTL_SETALE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
{ \
@@ -271,7 +272,7 @@
} \
} while(0)
-#define NAND_CTL_CLRCLE(nandptr) do \
+#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
{ \
@@ -284,7 +285,7 @@
} \
} while(0)
-#define NAND_CTL_SETCLE(nandptr) do { \
+#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
switch((unsigned long)nandptr) { \
case CFG_NAND0_BASE: \
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h
index 1e9a99eed3..16a9ea5dd7 100644
--- a/include/configs/CPU86.h
+++ b/include/configs/CPU86.h
@@ -178,8 +178,6 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
-#define CFG_NAND_LEGACY
-
/*
* Miscellaneous configurable options
*/
diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h
index aaa44c5398..29eb874dbf 100644
--- a/include/configs/IDS8247.h
+++ b/include/configs/IDS8247.h
@@ -236,6 +236,7 @@
*/
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CFG_NAND_LEGACY
#define CFG_NAND0_BASE 0xE1000000
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
diff --git a/include/configs/NC650.h b/include/configs/NC650.h
index 371ea17edd..3c59df4f45 100644
--- a/include/configs/NC650.h
+++ b/include/configs/NC650.h
@@ -217,6 +217,8 @@
/*
* NAND flash support
*/
+#define CFG_NAND_LEGACY
+
#define CFG_MAX_NAND_DEVICE 1
#define NAND_ChipID_UNKNOWN 0x00
#define SECTORSIZE 512
diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h
index 1bcd88d208..25b63457c7 100644
--- a/include/configs/NETTA.h
+++ b/include/configs/NETTA.h
@@ -609,6 +609,7 @@
/****************************************************************/
/* NAND */
+#define CFG_NAND_LEGACY
#define CFG_NAND_BASE NAND_BASE
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_MTD_NAND_UNSAFE
diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h
index 21945a343c..242c837a3b 100644
--- a/include/configs/RBC823.h
+++ b/include/configs/RBC823.h
@@ -326,8 +326,6 @@
/************************************************************
* Disk-On-Chip configuration
************************************************************/
-#define CFG_NAND_LEGACY
-
#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
#define CFG_DOC_SHORT_TIMEOUT
#define CFG_DOC_SUPPORT_2000
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index 3f29190e43..5f48a70938 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -248,6 +248,7 @@
*/
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#define CFG_NAND_LEGACY
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
diff --git a/include/configs/delta.h b/include/configs/delta.h
index 5edea95a4f..e4c8ccab11 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -178,7 +178,8 @@
* NAND Flash
*/
/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
-#define CONFIG_NEW_NAND_CODE
+#undef CFG_NAND_LEGACY
+
#define CFG_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */
#undef CFG_NAND1_BASE
diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h
index 12252ac129..58374616a1 100644
--- a/include/configs/omap2420h4.h
+++ b/include/configs/omap2420h4.h
@@ -132,6 +132,7 @@
/*
* Board NAND Info.
*/
+#define CFG_NAND_LEGACY
#define CFG_NAND_ADDR 0x04000000 /* physical address to access nand at CS0*/
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h
index be6c36cac9..614a046105 100644
--- a/include/configs/stxxtc.h
+++ b/include/configs/stxxtc.h
@@ -436,6 +436,7 @@
/****************************************************************/
/* NAND */
+#define CFG_NAND_LEGACY
#define CFG_NAND_BASE NAND_BASE
#define CONFIG_MTD_NAND_ECC_JFFS2
#define CONFIG_MTD_NAND_VERIFY_WRITE
diff --git a/include/linux/mtd/doc2000.h b/include/linux/mtd/doc2000.h
index ebf9a76924..eeb1d7e98e 100644
--- a/include/linux/mtd/doc2000.h
+++ b/include/linux/mtd/doc2000.h
@@ -91,6 +91,13 @@ struct DiskOnChip;
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
+struct Nand {
+ char floor, chip;
+ unsigned long curadr;
+ unsigned char curmode;
+ /* Also some erase/write/pipeline info when we get that far */
+};
+
struct DiskOnChip {
unsigned long physadr;
unsigned long virtadr;
@@ -148,4 +155,62 @@ void doc_probe(unsigned long physadr);
void doc_print(struct DiskOnChip*);
+/*
+ * Standard NAND flash commands
+ */
+#define NAND_CMD_READ0 0
+#define NAND_CMD_READ1 1
+#define NAND_CMD_PAGEPROG 0x10
+#define NAND_CMD_READOOB 0x50
+#define NAND_CMD_ERASE1 0x60
+#define NAND_CMD_STATUS 0x70
+#define NAND_CMD_SEQIN 0x80
+#define NAND_CMD_READID 0x90
+#define NAND_CMD_ERASE2 0xd0
+#define NAND_CMD_RESET 0xff
+
+/*
+ * NAND Flash Manufacturer ID Codes
+ */
+#define NAND_MFR_TOSHIBA 0x98
+#define NAND_MFR_SAMSUNG 0xec
+
+/*
+ * NAND Flash Device ID Structure
+ *
+ * Structure overview:
+ *
+ * name - Complete name of device
+ *
+ * manufacture_id - manufacturer ID code of device.
+ *
+ * model_id - model ID code of device.
+ *
+ * chipshift - total number of address bits for the device which
+ * is used to calculate address offsets and the total
+ * number of bytes the device is capable of.
+ *
+ * page256 - denotes if flash device has 256 byte pages or not.
+ *
+ * pageadrlen - number of bytes minus one needed to hold the
+ * complete address into the flash array. Keep in
+ * mind that when a read or write is done to a
+ * specific address, the address is input serially
+ * 8 bits at a time. This structure member is used
+ * by the read/write routines as a loop index for
+ * shifting the address out 8 bits at a time.
+ *
+ * erasesize - size of an erase block in the flash device.
+ */
+struct nand_flash_dev {
+ char * name;
+ int manufacture_id;
+ int model_id;
+ int chipshift;
+ char page256;
+ char pageadrlen;
+ unsigned long erasesize;
+ int bus16;
+};
+
#endif /* __MTD_DOC2000_H__ */
generated by cgit (git 2.34.1) at 2024-12-27 19:40:49 +0000